WO2022000843A1 - U形铁电场效应晶体管存储单元串、存储器及制备方法 - Google Patents

U形铁电场效应晶体管存储单元串、存储器及制备方法 Download PDF

Info

Publication number
WO2022000843A1
WO2022000843A1 PCT/CN2020/119410 CN2020119410W WO2022000843A1 WO 2022000843 A1 WO2022000843 A1 WO 2022000843A1 CN 2020119410 W CN2020119410 W CN 2020119410W WO 2022000843 A1 WO2022000843 A1 WO 2022000843A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
shaped
memory cell
field effect
effect transistor
Prior art date
Application number
PCT/CN2020/119410
Other languages
English (en)
French (fr)
Inventor
曾斌建
周益春
廖敏
Original Assignee
湘潭大学
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 湘潭大学 filed Critical 湘潭大学
Publication of WO2022000843A1 publication Critical patent/WO2022000843A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6684—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a ferroelectric gate insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/20—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels

Definitions

  • the invention relates to the field of memory, in particular to a U-shaped ferroelectric field effect transistor memory cell string, a memory and a preparation method.
  • Ferroelectric field effect transistor replaces the gate dielectric layer in field effect transistor (MOSFET) with ferroelectric thin film material. By changing the polarization direction of the ferroelectric thin film material, the on and off of the channel current is controlled to realize the information of storage.
  • FeFET memory has the advantages of non-volatility, low power consumption, fast read and write speed, simple cell structure and high theoretical storage density. In particular, FeFETs can achieve three-dimensional integration and are considered to be one of the most promising new types of high-density memories.
  • the shortcomings of the existing three-dimensional FeFET memory after research are: the uniformity and electrical performance of the existing ferroelectric thin film layer and its devices are poor, that is, the performance of the two memories prepared by the same method is quite different; Second, in the process of preparation, there are many interface defects between the ferroelectric thin film layer and the channel layer, resulting in poor fatigue performance of the device, and the threshold voltage and subthreshold swing between devices are greatly different, resulting in memory failure. The reliability is poor. Third, in the preparation process of the existing memory, the dielectric layer or the ferroelectric thin film layer needs to be etched, which is easy to damage the dielectric layer and the ferroelectric thin film layer, which affects the device performance and affects the reliability of the memory.
  • the object of the present invention is to provide a U-shaped ferroelectric field effect transistor memory cell string, a memory and a manufacturing method.
  • the memory cell string includes a U-shaped body formed by connecting two first columnar structures through a second columnar structure.
  • the shape is obtained by the deposition method, which can avoid the etching of the ferroelectric thin film layer during the preparation process, and improve the reliability of the memory; in addition, by setting the first dielectric layer and the second dielectric layer, the ferroelectric thin film is not directly connected to the gate electrode.
  • the contact between the ferroelectric film layer and the channel layer avoids the diffusion of elements in the ferroelectric thin film and its interface reaction with the gate electrode and the channel layer, which further ensures the quality and performance of the ferroelectric thin film layer and the memory cell, and reduces the interference between the memory cells. difference and improve the reliability of the memory.
  • a first aspect of the present invention provides a U-shaped ferroelectric field effect transistor memory cell string, which includes a U-shaped body formed by connecting two first columnar structures through a second columnar structure, a separation layer, and a spaced U-shaped body.
  • each layer of gate electrode is used to surround the U-shaped body; a separation layer runs through the multi-layer gate electrode and is located in the opening of the U-shaped body, and is used for isolating the two first columnar structures of the U-shaped body, So that the number of memory cells in the memory cell string is twice the number of gate electrode layers in the memory cell string; the columnar structures are arranged in order from the outer layer to the inner layer: the first dielectric layer, the ferroelectric layer A thin film layer, a second dielectric layer and a channel layer; the first dielectric layer and the second dielectric layer are used to isolate the ferroelectric thin film layer to avoid the ferroelectric thin film layer and the channel layer and the channel layer.
  • the gate electrode is in direct contact, and the first dielectric layer and the second dielectric layer are both used as a seed layer or a stress regulation layer for the growth of the ferroelectric thin film layer, so as to promote the generation of the ferroelectric phase in the ferroelectric thin film layer, So that the ferroelectric thin film layer in the U-shaped ferroelectric field effect transistor memory cell string realizes the memory function.
  • a filling layer disposed in the channel layer, for filling the center of the columnar structure.
  • the thickness of the channel layer is not greater than the thickness of the depletion layer of the channel layer.
  • an isolation layer is provided between the adjacent gate electrodes.
  • the first dielectric layer is silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), One or more of zirconium oxide (ZrO 2 ), titanium oxide (TiO 2 ), lanthanum oxide (La 2 O 3 ), hafnium silicon oxynitride (HfSiON), germanium oxide (GeO 2 ); the second medium The layer 9 is made of silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), One or more of titanium oxide (TiO 2 ), lanthanum oxide (La 2 O 3 ), hafnium silicon oxynitride (HfSiON), germanium oxide (
  • the ferroelectric thin film layer is one of hafnium oxide (HfO 2 ), doped HfO 2 , zirconium oxide (ZrO 2 ) or doped ZrO 2 ; wherein, the doped HfO 2 is doped in
  • the elements include silicon (Si), aluminum (Al), zirconium (Zr), lanthanum (La), cerium (Ce), strontium (Sr), lutetium (Lu), gadolinium (Gd), scandium (Sc), neodymium ( One or more of Nd), germanium (Ge), nitrogen (N), and the like.
  • the channel layer is polycrystalline silicon (Si), polycrystalline germanium (Ge), polycrystalline silicon germanium (SiGe), or doped polycrystalline silicon (Si), doped polycrystalline germanium (Ge), doped polycrystalline silicon Germanium (SiGe), the doping element is one or more of boron (B), phosphorus (P) and arsenic (As).
  • a U-shaped ferroelectric field effect transistor memory comprising: a substrate, a conductive layer and a plurality of U-shaped ferroelectric field effect transistor memory cell strings provided in the first aspect of the present invention;
  • the conductive layer is arranged on the surface of the substrate;
  • the second column structure in the U-shaped ferroelectric field effect transistor memory cell string is embedded in the conductive layer, and the U-shaped ferroelectric field effect transistor memory cell string is
  • Two first columnar structures are located outside the conductive layer and are arranged perpendicular to the conductive layer; the separation layer is arranged on the side of the conductive layer away from the substrate, and is located between the two first columnar structures space for isolating the two first columnar structures.
  • the multi-layered gate electrodes are arranged on the surface of the conductive layer, and an isolation layer is arranged between the adjacent gate electrodes; in the multi-layered gate electrodes, the gate electrode close to the conductive layer is The isolation layer is provided between the electrode and the conductive layer.
  • the isolation layer is SiO 2 or is formed of an insulating material whose dielectric constant is smaller than that of SiO 2 ;
  • the gate electrode is heavily doped polysilicon, nitride metal electrode and tungsten (W) either.
  • an electronic device comprising one or more of the U-shaped ferroelectric field effect transistor memories provided in the second aspect.
  • a method for preparing a U-shaped ferroelectric field effect transistor memory comprising: S1: forming a conductive layer on the substrate 1; S2: forming at least one trench in the conductive layer, and depositing a medium to fill the trenches; S3: sequentially overlapping and depositing an isolation layer and a gate electrode on the surface of the conductive layer to obtain a stacked layer, and the number of layers of the gate electrode is a preset number of layers; S4: in each Two through holes are formed above the trenches, the through holes penetrate through the stacked layers and reach the top of the trenches; S5: remove the filled medium in the trenches, so that the two through holes are The hole 13 forms a U-shaped through hole; S6: sequentially deposit a first dielectric layer, a ferroelectric thin film layer, a second dielectric layer and a channel layer on the inner wall of the U-shaped through hole; S7: on the inner wall of the U-shaped through hole
  • the method further includes: depositing a filling layer on the inner wall of the channel layer to fill the through hole.
  • the step S2 includes: using a wet process or an etching process to form a trench in the conductive layer; using thermal oxidation, chemical vapor deposition (CVD), sputtering, atomic layer deposition (ALD) to deposit a dielectric to fill the trenches; the deposited dielectric is one or more of SiO 2 , SiON and Si 3 N 4 .
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • step S7 includes: using a dry or wet etching process to etch the middle of the U-shaped through hole to form a separation hole.
  • the method further includes: depositing an insulating material into the separation hole to fill the separation hole.
  • the ferroelectric film is not directly in contact with the gate electrode layer and the channel layer, so as to avoid the diffusion of elements in the ferroelectric film and its connection with the gate electrode and the channel layer.
  • the interface reaction of the ferroelectric film further ensures the quality and performance of the ferroelectric thin film layer and the memory cell, reduces the difference between the memory cells, and improves the reliability of the memory; in addition, the first dielectric layer and the second dielectric layer are used as the ferroelectric thin film. layer growth seed layer or stress regulation layer, thereby improving the performance of the ferroelectric thin film layer, and can also effectively reduce the leakage current and improve the retention performance of the FeFET memory.
  • a filling layer is added to the channel layer, which is equivalent to reducing the volume of the polycrystalline channel layer in the device, which can reduce defects in the polycrystalline channel layer. Helps to improve device fatigue performance and improve device-to-device variability.
  • the deposition method is used to form the first dielectric layer, the ferroelectric thin film layer and the second dielectric layer. Since the memory cell strings are U-shaped, the first dielectric layer, the ferroelectric thin film layer and the second dielectric layer are avoided. The etching of the second dielectric layer can increase the reliability of the memory.
  • FIG. 1 is a schematic structural diagram of a ferroelectric field effect transistor memory cell according to a first embodiment of the present invention.
  • FIG. 2a is a schematic structural diagram of a U-shaped ferroelectric field effect transistor memory cell string according to a second embodiment of the present invention
  • FIG. 2b is a top view of a U-shaped ferroelectric field effect transistor memory cell string according to a second embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a U-shaped ferroelectric field effect transistor memory provided by a third embodiment of the present invention.
  • FIG. 4 is a schematic flowchart of a method for preparing a U-shaped ferroelectric field effect transistor memory according to a fourth embodiment of the present invention.
  • FIG. 4a is a schematic diagram of forming a conductive layer on a substrate according to a fourth embodiment of the present invention.
  • 4b is a schematic diagram of forming a trench on the conductive layer according to the fourth embodiment of the present invention.
  • 4c is a schematic diagram of forming a stacked layer on the conductive layer according to the fourth embodiment of the present invention.
  • 4d is a schematic diagram of forming a through hole on a stacked layer according to a fourth embodiment of the present invention.
  • FIG. 4e is a schematic diagram of removing the medium in the channel 12a according to the fourth embodiment of the present invention.
  • 4f is a schematic diagram of depositing a filling layer in a U-shaped through hole according to a fourth embodiment of the present invention.
  • FIG. 4g is a schematic diagram of forming a separation layer according to a fourth embodiment of the present invention.
  • FIG. 1 A schematic diagram of a layer structure according to an embodiment of the present invention is shown in the accompanying drawings.
  • the figures are not to scale, some details are exaggerated for clarity, and some details may have been omitted.
  • the shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships are only exemplary, and in practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art should Regions/layers with different shapes, sizes, relative positions can be additionally designed as desired.
  • the inventor of the present invention found that the gate electrode and the ferroelectric thin film layer are in direct contact with the existing transistor during the preparation process, and the interface layer is easily formed on the contact surface, and it is difficult to control the quality of the interface layer, resulting in The uniformity and electrical performance of the ferroelectric thin film layer and its devices are poor, that is, the performance of the two memories prepared by the same method is quite different.
  • FIG. 1 is a schematic structural diagram of a ferroelectric field effect transistor memory cell according to a first embodiment of the present invention.
  • the memory cell includes: a gate electrode layer 4 ; a columnar structure is embedded in the thickness direction of the gate electrode layer 4 . From the outer layer of the columnar structure to the direction close to the axis, the first dielectric layer 7 , the ferroelectric thin film layer 8 , the second dielectric layer 9 and the channel layer 10 are sequentially covered.
  • the first dielectric layer 7 and the second dielectric layer 9 are both insulating materials, which are used to prevent the ferroelectric thin film layer 8 from contacting the gate electrode layer 4 and the channel layer 10, and also make the first dielectric layer 7 and the channel layer 10 contact.
  • the second dielectric layer 9 serves as a seed layer or a stress regulating layer for the growth of the ferroelectric thin film layer 8 , and promotes the formation of a ferroelectric phase in the ferroelectric thin film layer 8 , so that the ferroelectric thin film layer 8 has excellent ferroelectric properties.
  • the electrical performance ensures the storage function of the storage unit.
  • the ferroelectric thin film layer 8 serves as a storage medium.
  • the principle of the above memory cell is that the direction of polarization of the ferroelectric thin film layer 8 is changed by the direction of the voltage applied to the gate electrode layer 4 , so that the channel layer 10 is turned on and off to realize the memory function.
  • each layer of gate electrodes and corresponding columnar structures corresponds to one ferroelectric field effect transistor memory cell.
  • a filling layer 11 is further included, which is disposed in the channel layer 10 and is used to fill the center of the columnar structure.
  • a filling layer is added to the channel layer, which is equivalent to reducing the volume of the channel layer in the device, which can reduce defects in the channel layer, help to improve the fatigue performance of the device and improve the inter-device relationship. difference.
  • FIG. 2a is a schematic structural diagram of a U-shaped ferroelectric field effect transistor memory cell string according to a second embodiment of the present invention.
  • Figure 2a shows a front view of a U-shaped ferroelectric field effect transistor memory cell string.
  • 2b is a top view of a U-shaped ferroelectric field effect transistor memory cell string according to a second embodiment of the present invention.
  • the U-shaped ferroelectric field effect transistor memory cell string includes a U-shaped body formed by connecting two first columnar structures through a second columnar structure, a separation layer 6, and a plurality of layers arranged at intervals. gate electrode 4 .
  • the U-shaped body may be integrally formed, for example, by bending two ends of a columnar structure toward one side of the columnar structure.
  • the U-shaped body may also be formed by connecting the ends of two first columnar structures (two vertically arranged columnar structures in FIG. 2 ) through a second columnar structure (in FIG. 2 , a horizontally arranged columnar structure).
  • the U-shaped body can be formed by extending the end of a first columnar structure in a direction perpendicular to its length direction to form a second columnar structure, and then connecting the second columnar structure with the end of another first columnar structure.
  • the U-shaped body of the present invention can be formed in many ways, and the present invention is not limited thereto.
  • each layer of the gate electrode 4 is used to surround the U-shaped body.
  • the separation layer 6 runs through the multi-layer gate electrode 4 and is located in the opening of the U-shaped body, and is used to separate the two first columnar structures of the U-shaped body, so that the memory cells in the memory cell string 5 are separated.
  • the number of cells is twice the number of layers of gate electrodes 4 in the memory cell string 5 . That is, the role of the separation layer is to isolate the two first columnar structures of the U-shaped body, so that each first columnar structure and the multi-layer gate electrode 4 are used as a column-shaped memory cell string.
  • the two columnar structures of the U-shaped body are connected, so that under the action of the separation layer, the two columnar structures of the U-shaped body are connected in series, so that the number of memory cells in the U-shaped memory cell string 5 is the number of layers of gate electrodes 4 in the memory cell string 5 twice.
  • the separation layer 6 is a hole, such as a trapezoidal hole or a square hole, or the separation layer 6 is a layer of insulating material.
  • the above-mentioned columnar structure can be cylindrical or square, and certainly can also be prism, and the present invention is not limited to this.
  • the first columnar structure and the second columnar structure are both multi-layer structures. Specifically, each columnar structure is sequentially provided with a first dielectric layer 7, a ferroelectric thin film layer 8, and a second dielectric layer from the outer layer to the inner layer. layer 9 and channel layer 10; the first dielectric layer 7 and the second dielectric layer 9 are used to isolate the ferroelectric thin film layer 8 to avoid the ferroelectric thin film layer 8 and the channel layer 10 In direct contact with the gate electrode 4, the first dielectric layer 7 and the second dielectric layer 9 are both used as the seed layer or stress regulation layer for the growth of the ferroelectric thin film layer 8, which promotes the growth of the ferroelectric thin film layer 8. The formation of the ferroelectric phase ensures that the ferroelectric thin film layer 8 has excellent ferroelectric properties, so that the ferroelectric thin film layer 8 in the U-shaped memory cell string can realize the storage function.
  • a filling layer 11 is further included, which is disposed in the channel layer 10 and is used to fill the center of the columnar structure.
  • the filling layer 11 is added to the channel layer 10, which is equivalent to reducing the volume of the channel layer 10 in the device, which can reduce the defects in the channel layer 10, and help to improve the fatigue performance of the device. Improve device-to-device variability.
  • a conventional memory cell string is elongated, the source electrode and its selection transistor are arranged at the upper end of the memory cell string, and the drain electrode and its selection transistor are arranged at the lower end of the memory cell string.
  • This will affect the metal wiring in the subsequent process, resulting in a complicated assembly process.
  • the source electrode and the drain electrode are respectively located at the top of the two first column structures of the U-shaped memory cell string, so that more compact wiring can be obtained and higher density can be achieved Integration makes the assembly process simple and easy to use.
  • the thickness of the channel layer 10 is not greater than the thickness of the depletion layer of the channel layer 10 .
  • an isolation layer 3 is provided between adjacent gate electrodes 4 .
  • the isolation layer 3 is made of insulating material and is used to isolate the adjacent gate electrodes 4 .
  • the material of the isolation layer 3 is SiO 2 or an insulating material whose dielectric constant is smaller than that of SiO 2 .
  • the first dielectric layer 7 is silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ) ), one or more of zirconium oxide (ZrO 2 ), titanium oxide (TiO 2 ), lanthanum oxide (La 2 O 3 ), hafnium silicon oxynitride (HfSiON), germanium oxide (GeO 2 ); the first The second dielectric layer 9 is silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ) ), one or more of titanium oxide (TiO 2 ), lanthanum oxide (La 2 O 3 ), silicon hafnium oxynitride (HfSiON),
  • the channel layer 10 is polycrystalline silicon (Si), polycrystalline germanium (Ge), polycrystalline silicon germanium (SiGe), or doped polycrystalline silicon (Si), doped polycrystalline germanium (Ge), doped
  • the polycrystalline silicon germanium (SiGe) is doped with one or more of boron (B), phosphorus (P) and arsenic (As).
  • FIG. 3 is a schematic structural diagram of a U-shaped ferroelectric field effect transistor memory according to a third embodiment of the present invention.
  • the memory includes: a substrate 1, a conductive layer 2 and a plurality of U-shaped ferroelectric field effect transistor memory cell strings 5 provided in the second embodiment; the conductive layer 2 is disposed on the substrate 1; The second columnar structures of the U-shaped ferroelectric field effect transistor memory cell strings 5 are embedded in the conductive layer 2, and the two first columnar structures of the U-shaped ferroelectric field effect transistor memory cell strings 5 are located in the conductive layer 2 outside and perpendicular to the conductive layer 2 ; the separation layer 6 is disposed on the conductive layer 2 and is located between the two columnar structures for isolating the two structures.
  • the multi-layered gate electrodes 4 are arranged on the surface of the conductive layer 2, an isolation layer 3 is arranged between the adjacent gate electrodes 4, and between the conductive layer 2 and the gate electrodes 4 The isolation layer 3 is provided.
  • the substrate 1 is a semiconductor substrate, including but not limited to silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs) and the like.
  • the conductive layer 2 includes but is not limited to forming a pn junction with the substrate 1.
  • the substrate 1 is a p-type semiconductor
  • the conductive layer 2 is a heavily doped n-type semiconductor.
  • the conductive layer 2 can also be a metal electrode, and is isolated from the substrate 1 by providing an insulating material.
  • the ferroelectric thin film layer 8 may be hafnium oxide (HfO 2 ) or doped HfO 2
  • the doping elements include silicon (Si), aluminum (Al), zirconium (Zr), lanthanum (La), cerium (Ce) ), one or more of strontium (Sr), lutetium (Lu), gadolinium (Gd), scandium (Sc), neodymium (Nd), germanium (Ge), nitrogen (N), etc., and can also be zirconia (ZrO 2 ) and doped ZrO 2 .
  • the first dielectric layer 7 is silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), oxide One or more of zirconium (ZrO 2 ), titanium oxide (TiO 2 ), lanthanum oxide (La 2 O 3 ), hafnium silicon oxynitride (HfSiON), and germanium oxide (GeO 2 ).
  • the second dielectric layer 9 is that the first dielectric layer is silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), oxide One or more of hafnium (HfO 2 ), zirconium oxide (ZrO 2 ), titanium oxide (TiO 2 ), lanthanum oxide (La 2 O 3 ), hafnium oxynitride (HfSiON), germanium oxide (GeO 2 ) .
  • the channel layer 10 is polycrystalline silicon (Si), polycrystalline germanium (Ge), polycrystalline silicon germanium (SiGe), or doped polycrystalline silicon (Si), doped polycrystalline germanium (Ge), doped polycrystalline silicon (Si), doped polycrystalline germanium (Ge), doped polycrystalline silicon (Si), doped polycrystalline germanium (Ge).
  • Polycrystalline silicon germanium (SiGe), the doping element is one of boron (B), phosphorus (P) and arsenic (As).
  • the thickness of the channel layer 10 is not greater than the thickness of the depletion layer.
  • the filling layer 11 includes but is not limited to SiO 2 , SiON and Si 3 N 4 .
  • the isolation layer 3 is SiO 2 or an insulating material with a lower dielectric constant than SiO 2 .
  • the gate electrode 4 is any one of heavily doped polysilicon, nitride metal electrode and tungsten (W).
  • FIG. 4 is a schematic flowchart of a method for preparing a memory according to a fourth embodiment of the present invention.
  • steps S1-S7 are included.
  • S1 a conductive layer 2 is formed on the substrate 1, see FIG. 4a.
  • ions can be implanted into the surface of the substrate 1 by using an ion implantation process to form a pn junction between the conductive layer 2 and the substrate 1 , and the implanted ions are determined according to the substrate 1 .
  • At least one trench 12a is formed in the conductive layer 2, and a dielectric is deposited to fill the trench 12a, see FIG. 4b.
  • the trenches 12a may be formed in the conductive layer by a wet or dry etching process, and the number of the trenches 12a to be formed is determined according to requirements.
  • the contour of each trench 12a corresponds to the contour of the second column structure of the U-shaped ferroelectric field effect transistor memory cell string of the U-shaped ferroelectric field effect transistor memory.
  • the deposited medium is one or more of SiO 2 , SiON and Si 3 N 4 , and the deposition method is thermal oxidation, chemical vapor deposition (CVD), sputtering, atomic layer deposition (ALD) ) any one or more of them.
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • An isolation layer 3 and a gate electrode 4 are sequentially overlapped and deposited on the surface of the conductive layer 2 to obtain a stacked layer, and the number of layers of the gate electrode 4 is a preset number of layers.
  • the isolation layer 3 deposited in S3 is SiO 2 or an insulating material with a smaller dielectric constant than SiO 2 , and the deposition method is chemical vapor deposition (CVD), sputtering, atomic layer deposition. (ALD) any of.
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • the deposited control gate electrode layer 4 is any one of heavily doped polysilicon, nitride metal electrode, tungsten (W), and the deposition method is chemical vapor deposition (CVD), sputtering , any of atomic layer deposition (ALD) and metal organic vapor deposition (MOCVD).
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • MOCVD metal organic vapor deposition
  • the through hole 13 is formed by a wet or dry etching process.
  • the method for removing the filling medium is a wet etching process.
  • the deposited ferroelectric thin film layer 8 may be hafnium oxide (HfO 2 ) or doped HfO 2 , and the doping elements include silicon (Si), aluminum (Al), zirconium (Zr), lanthanum (La), One or more of cerium (Ce), strontium (Sr), lutetium (Lu), gadolinium (Gd), scandium (Sc), neodymium (Nd), germanium (Ge), nitrogen (N), etc.
  • the deposition method is chemical vapor deposition (CVD) or atomic layer deposition (ALD).
  • the deposited first dielectric layer 7 is silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), HfO 2 , ZrO 2
  • the deposition method is chemical vapor deposition (CVD) or Atomic Layer Deposition (ALD).
  • the deposited second dielectric layer 9 is silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ) ), one or more of zirconium oxide (ZrO 2 ), titanium oxide (TiO 2 ), lanthanum oxide (La 2 O 3 ), hafnium silicon oxynitride (HfSiON), germanium oxide (GeO 2 ), etc., deposition method For chemical vapor deposition (CVD) or atomic layer deposition (ALD).
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • the deposited channel layer 10 is polycrystalline silicon (Si), polycrystalline germanium (Ge), polycrystalline silicon germanium (SiGe), or doped polycrystalline silicon (Si), doped polycrystalline germanium (Ge), doped polycrystalline silicon (Si), doped polycrystalline germanium (Ge), doped polycrystalline silicon (Si), doped polycrystalline germanium (Ge).
  • the polycrystalline silicon germanium (SiGe) is doped with one of boron (B), phosphorus (P) and arsenic (As), and the deposition method is chemical vapor deposition (CVD) or atomic layer deposition (ALD).
  • the deposited filling layer 11 includes but is not limited to SiO 2 , SiON and Si 3 N 4 , and the deposition method is chemical vapor deposition (CVD) or atomic layer deposition (ALD).
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • a separation layer 6 is formed in the middle of the U-shaped through hole, and the separation layer 6 penetrates at least the gate electrode 4 in the stacked structure to form the U-shaped ferroelectric field effect transistor memory.
  • the separation layer 6 is, for example, a hole, or the hole is formed first, and then the insulating material is deposited.
  • a dry or wet etching process is used to etch the middle of the U-shaped through hole to form the separation hole, which is the separation layer.
  • a separation layer is obtained by depositing an insulating material to fill the separation hole.
  • step S6 after the step S6, before the step S7, it further includes:
  • a filling layer 11 is deposited on the inner wall of the channel layer 10 to fill the through hole 13 .
  • the deposited filling layer 11 includes but is not limited to SiO 2 , SiON and Si 3 N 4 , and the deposition method is chemical vapor deposition (CVD) or atomic layer deposition (ALD).
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • the U-shaped memory cell string provided by the embodiment of the present invention can obtain more compact wiring and achieve higher density integration.
  • the memory cell string is provided with the first dielectric layer 7 and the second dielectric layer 9 so that the ferroelectric thin film 8 is not in direct contact with the gate electrode layer 4 and the channel layer 10, so as to avoid the diffusion of elements in the ferroelectric thin film 8 and its interaction with the ferroelectric thin film 8.
  • the interface reaction between the gate electrode and the channel layer further ensures the quality and performance of the ferroelectric thin film layer 8 and the memory cell, reduces the difference between the memory cells, and improves the reliability of the memory.
  • first dielectric layer 7 and The second dielectric layer 9 serves as a seed layer or stress regulating layer for the growth of the ferroelectric thin film layer 8 , thereby improving the performance of the ferroelectric thin film layer 8 , and can also effectively reduce leakage current and improve the retention performance of the FeFET memory.
  • the filling layer 11 is added to the channel layer 10, which is equivalent to reducing the volume of the channel layer 10 in the device, which can reduce defects in the channel layer 10. Helps to improve device fatigue performance and improve device-to-device variability.
  • the preparation method provided by the embodiment of the present invention avoids the etching of the first dielectric layer 7, the ferroelectric thin film layer 8 and the second dielectric layer 9, which can increase the reliability of the memory.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

本发明公开了一种U形铁电场效应晶体管存储单元串、存储器及制备方法。该存储单元串，包括由两个第一柱状结构通过第二柱状结构连接而成形成的U形体、分离层（6）和间隔设置的多层的栅电极（4）；每层所述栅电极（4），用于包围所述U形体；所述分离层（6），贯穿于所述多层栅电极（4），且位于所述U形体的开口内，用于隔离所述U形体的两个柱状结构，以使所述U形存储单元串中的存储单元的个数为所述U形存储单元串中的栅电极（4）层数的二倍。其中U形的存储单元串相比于现有技术，在设置同样层数的栅电极下，本发明的存储单元的个数更多，存储密度更高。

Description

U形铁电场效应晶体管存储单元串、存储器及制备方法 技术领域
本发明涉及存储器领域，尤其是涉及一种U形铁电场效应晶体管存储单元串、存储器及制备方法。
背景技术
铁电场效应晶体管(FeFET)是以铁电薄膜材料替代场效应晶体管(MOSFET)中的栅介质层，通过改变铁电薄膜材料的极化方向来控制沟道电流的导通和截止，从而实现信息的存储。FeFET存储器具有非易失性、低功耗、读写速度快等优点，且单元结构简单，理论存储密度大。特别地，FeFET可以实现三维集成，被认为是最有潜力的高密度新型存储器之一。
目前，经过研究现有三维FeFET存储器的不足之处是：现有的铁电薄膜层及其器件的均一性和电学性能差，即采用同样方法制备的两个存储器的性能差异性较大；第二，在制备的过程中，铁电薄膜层与沟道层之间的界面缺陷较多，导致器件的疲劳性能较差，器件之间的阈值电压和亚阈值摆幅差异较大，导致存储器的可靠性差；第三，现有的存储器的制备过程中，需要对介质层或铁电薄膜层刻蚀，容易对介质层和铁电薄膜层损伤，造成器件性能受到影响，影响存储器的可靠性。
发明内容
(一)发明目的
本发明的目的是提供一种U形铁电场效应晶体管存储单元串、存储器及制备方法，该存储单元串包括为由两个第一柱状结构通过第二柱状结构连接 而形成的U形体，该U形体是通过沉积方法得到的，能够避免制备过程中对铁电薄膜层进行刻蚀，提高了存储器的可靠性；另外通过设置第一介质层和第二介质层使得铁电薄膜不直接与栅电极层和沟道层接触，避免铁电薄膜中的元素扩散及其与栅电极和沟道层的界面反应，进一步保证了铁电薄膜层和存储单元的质量和性能，减小存储单元之间的差异性，提高存储器的可靠性。
(二)技术方案
为解决上述问题，本发明的第一方面提供一种U形铁电场效应晶体管存储单元串，包括由两个第一柱状结构通过第二柱状结构连接所形成的U形体、分离层和间隔设置的多层的栅电极；每层栅电极，用于包围U形体；分离层，贯穿于多层栅电极，且位于所述U形体的开口内，用于隔离U形体的两个第一柱状结构，以使所述存储单元串中的存储单元的个数为所述存储单元串中的栅电极层数的二倍；所述柱状结构由外层至内层依次设置：第一介质层、铁电薄膜层、第二介质层和沟道层；所述第一介质层和所述第二介质层用于隔离所述铁电薄膜层，以避免所述铁电薄膜层与所述沟道层和所述栅电极直接接触，还使所述第一介质层和第二介质层均作为所述铁电薄膜层生长的种子层或应力调控层，促进所述铁电薄膜层中铁电相的生成，以使所述U形铁电场效应晶体管存储单元串中铁电薄膜层实现存储功能。
进一步的，还包括：填充层，设置在所述沟道层内，用于填满所述柱状结构的中心。
进一步的，所述沟道层的厚度不大于所述沟道层的耗尽层的厚度。
进一步的，相邻的所述栅电极之间设置有隔离层。
进一步的，所述第一介质层为氧化硅(SiO 2)、氮化硅(Si 3N 4)、氮氧化硅(SiON)、氧化铝(Al 2O 3)、氧化铪(HfO 2)、氧化锆(ZrO 2)、氧化钛(TiO 2)、氧化镧(La 2O 3)、氮氧硅铪(HfSiON)、氧化锗(GeO 2)中的一种或多种；所述第二介质层9为氧化硅(SiO 2)、氮化硅(Si 3N 4)、氮氧化硅(SiON)、氧化铝(Al 2O 3)、氧化铪(HfO 2)、氧化锆(ZrO 2)、氧化钛(TiO 2)、氧化镧(La 2O 3)、氮氧硅铪(HfSiON)、氧化锗(GeO 2)等中的一种或多种。
进一步的，所述铁电薄膜层为氧化铪(HfO 2)、掺杂的HfO 2、氧化锆(ZrO 2)或掺杂的ZrO 2中的一种；其中，掺杂的HfO 2中掺杂的元素包括硅(Si)、铝(Al)、锆(Zr)、镧(La)、铈(Ce)、锶(Sr)、镥(Lu)、钆(Gd)、钪(Sc)、钕(Nd)、锗(Ge)、氮(N)等中的一种或多种。
进一步的，所述沟道层为多晶硅(Si)、多晶锗(Ge)、多晶硅锗(SiGe)，或掺杂的多晶硅(Si)、掺杂的多晶锗(Ge)、掺杂的多晶硅锗(SiGe)，掺杂元素为硼(B)、磷(P)和砷(As)中的一种或多种。
根据本发明的第二方面，提供了一种U形铁电场效应晶体管存储器，包括：基底、导电层和多个本发明第一方面提供的所述的U形铁电场效应晶体管存储单元串；所述导电层设置在所述基底表面；所述U形铁电场效应晶体管存储单元串中的所述第二柱状结构嵌设在所述导电层内，所述U形铁电场效应晶体管存储单元串的两个第一柱状结构位于所述导电层外且与所述导电层垂直设置；所述分离层，设置在所述导电层远离所述基底的一面，且位于两个所述第一柱状结构之间，用于隔离两个所述第一柱状结构。
进一步地，多层的所述栅电极设置在所述导电层的表面上，相邻的所述栅电极之间设置有隔离层；多层的所述栅电极中，靠近所述导电层的栅电极与所述导电层之间设置有所述隔离层。
进一步地，所述隔离层为SiO 2或由介电常数比SiO 2的介电常数小的绝缘材料形成；所述栅电极为重掺杂的多晶硅，氮化物金属电极和钨(W)中的任一种。
根据本发明的第三方面，提供了一种电子设备，包括一个或多个第二方面提供的U形铁电场效应晶体管存储器。
根据本发明的第四方面，提供了一种U形铁电场效应晶体管存储器的制备方法，包括：S1：在基底1上形成导电层；S2：在所述导电层中形成至少一个沟槽，并沉积介质以填满所述沟槽；S3：在所述导电层表面依次交叠沉积隔离层和栅电极得到堆叠层，所述栅电极的层数为预设层数；S4：在每个所述沟槽的上方形成两个通孔，所述通孔贯穿所述堆叠层，且直至所述沟槽 的顶部；S5：去除所述沟槽中的填充的介质，以使得所述两个通孔13形成U型通孔；S6：在所述U型通孔的内壁依次沉积第一介质层、铁电薄膜层、第二介质层和沟道层；S7：在所述U型通孔的中部形成分离层，所述分离层至少贯穿所述叠层结构中的栅电极，以形成所述U形铁电场效应晶体管存储器。
进一步地，所述步骤S6之后，在步骤S7之前，还包括：在沟道层的内壁上沉积填充层以充满所述通孔。
进一步地，所述步骤S2包括：采用湿法工艺或者刻蚀工艺在所述导电层中形成沟槽；采用热氧化、化学气相沉积法(CVD)、溅射法(sputtering)、原子层沉积法(ALD)中的任一种或多种方法沉积介质，以填满所述沟槽；所述沉积的所述介质为SiO 2、SiON和Si 3N 4中的一种或多种。
进一步地，所述步骤S7，包括：采用干法或湿法刻蚀工艺对U形通孔的中部刻蚀形成分离孔。
进一步地，在采用干法或湿法刻蚀工艺对U形通孔的中部刻蚀形成分离孔之后，还包括：向所述分离孔内沉积绝缘材料以填充所述分离孔。
(三)有益效果
本发明的上述技术方案具有如下有益的技术效果：
(1)存储单元串通过设置第一介质层和第二介质层使得铁电薄膜不直接与栅电极层和沟道层接触，避免铁电薄膜中的元素扩散及其与栅电极和沟道层的界面反应，进一步保证了铁电薄膜层和存储单元的质量和性能，减小存储单元之间的差异性，提高存储器的可靠性；另外，第一介质层和第二介质层作为铁电薄膜层生长的种子层或应力调控层，从而提升铁电薄膜层的性能，而且还可以有效地降低漏电流，提升FeFET存储器的保持性能。
(2)本发明实施例提供的存储单元串中，在沟道层中增加了填充层，相当于减少了器件中多晶沟道层的体积，这可以减少多晶沟道层中的缺陷，有助于提升器件的疲劳性能和改善器件之间的差异性。
(3)本发明提供的制备方法中采用沉积法形成第一介质层、铁电薄膜层和第二介质层，由于存储单元串为U形，避免了对第一介质层、铁电薄膜层 和第二介质层的刻蚀，可以增加存储器的可靠性。
附图说明
图1是本发明第一实施方式提供的铁电场效应晶体管存储单元的结构示意图。
图2a是本发明第二实施方式提供的U形铁电场效应晶体管存储单元串的结构示意图；
图2b是本发明第二实施方式提供的U形铁电场效应晶体管存储单元串的俯视图；
图3是本发明第三实施方式提供的U形铁电场效应晶体管存储器结构示意图；
图4是本发明第四实施方式提供的U形铁电场效应晶体管存储器的制备方法流程示意图；
图4a是本发明第四实施方式提供的在基底上形成导电层的示意图；
图4b是本发明第四实施方式提供的在导电层上形成沟槽的示意图；
图4c是本发明第四实施方式提供的在导电层上形成堆叠层的示意图；
图4d是本发明第四实施方式提供的在堆叠层上形成通孔的示意图；
图4e是本发明第四实施方式提供的去除沟道12a内的介质的示意图；
图4f是本发明第四实施方式提供的在U形通孔内沉积填充层的示意图；
图4g是本发明第四实施方式提供的形成分离层的示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明了，下面结合具体实施方式并参照附图，对本发明进一步详细说明。应该理解，这些描述只是示例性的，而并非要限制本发明的范围。此外，在以下说明中，省略了对公知结 构和技术的描述，以避免不必要地混淆本发明的概念。
在附图中示出了根据本发明实施例的层结构示意图。这些图并非是按比例绘制的，其中为了清楚的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明的描述中，需要说明的是，术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性。
此外，下面所描述的本发明不同实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。
以下将参照附图更详细地描述本发明。在各个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。
本发明的发明人在研究过程中，发现现有的晶体管在制备过程中栅电极和铁电薄膜层是直接接触的，接触的表面容易生成界面层，且较难控制界面层的质量，从而导致铁电薄膜层及其器件的均一性和电学性能差，即采用同样方法制备的两个存储器的性能差异性较大。
图1是本发明第一实施方式提供的铁电场效应晶体管存储单元的结构示意图。
如图1所示，该存储单元包括：栅电极层4；栅电极层4的厚度方向上嵌设有柱状结构。从柱状结构的外层至靠近轴线的方向上，依次覆盖有第一介质层7、铁电薄膜层8、第二介质层9和沟道层10。
第一介质层7和第二介质层9均为绝缘材质，用于避免所述铁电薄膜层8与所述栅电极层4和沟道层10接触，还使所述第一介质层7和第二介质层 9均作为所述铁电薄膜层8生长的种子层或应力调控层，促进所述铁电薄膜层8中铁电相的生成，以使所述铁电薄膜层8具备优异的铁电性能，保证存储单元的存储功能。
铁电薄膜层8，作为存储介质。
上述存储单元的原理是，通过加在栅电极层4上的电压方向改变铁电薄膜层8的极化方向，从而实现沟道层10的导通和截止来实现存储功能。
可以理解的是，在每一层栅电极及对应的柱状结构对应一个铁电场效应晶体管存储单元。
在一个实施例中，还包括填充层11，设置在所述沟道层10内，用于填满所述柱状结构的中心。
本实施例中，在沟道层中增加了填充层，相当于减少了器件中沟道层的体积，这可以减少沟道层中的缺陷，有助于提升器件的疲劳性能和改善器件之间的差异性。
图2a是本发明第二实施方式提供的U形铁电场效应晶体管存储单元串的结构示意图。该图2a出示的是U形铁电场效应晶体管存储单元串的正视图。图2b是本发明第二实施方式提供的U形铁电场效应晶体管存储单元串的俯视图。
如图2a和2b所示，该U形铁电场效应晶体管存储单元串，包括由两个第一柱状结构的通过第二柱状结构连接而形成的U形体、分离层6和间隔设置的多层的栅电极4。
具体的，该U形体可以是一体成型设置，例如将一个柱状结构的两端朝着柱状结构的一侧弯折而成型。
或者，U形体也可以是两个第一柱状结构(在图2中是竖直设置的两个柱状结构)的端部通过第二柱状结构(图2中为横向设置的柱状结构)连接形成。
再或者，U形体可以是某一第一柱状结构的端部朝与其长度方向垂直的方向延伸形成第二柱状结构，然后第二柱状结构与另一第一柱状结构的端部 连接而成。
可以理解的是，本发明U形体的形成方式有很多，本发明不以此为限。
其中，每层所述栅电极4，用于包围所述U形体。
分离层6，贯穿于所述多层栅电极4，且位于所述U形体的开口内，用于隔离所述U形体的两个第一柱状结构，以使所述存储单元串5中的存储单元的个数为所述存储单元串5中的栅电极4层数的二倍。即，分离层的作用是隔离U形体的两个第一柱状结构，进而使得每个第一柱状结构与多层的栅电极4作为一个柱状的存储单元串，另外由于U形体的两个第一柱状结构连接，这样在分离层的作用下，使得U形体的两个柱状结构串联，使得U形存储单元串5中的存储单元的个数为所述存储单元串5中的栅电极4层数的二倍。
可选的，分离层6为一个孔，例如为梯形孔或方孔，或者分离层6为一层绝缘材质。
可以理解的是，上述柱状结构可以是圆柱形或者方柱形当然也可以是棱柱，本发明不以此为限。
其中，第一所述柱状结构和第二柱状结构均为多层结构，具体的，每个柱状结构由外层至内层依次设置有第一介质层7、铁电薄膜层8、第二介质层9和沟道层10；所述第一介质层7和所述第二介质层9用于隔离所述铁电薄膜层8，以避免所述铁电薄膜层8与所述沟道层10和所述栅电极4直接接触，还使所述第一介质层7和第二介质层9均作为所述铁电薄膜层8生长的种子层或应力调控层，促进所述铁电薄膜层8中铁电相的生成，保证铁电薄膜层8具备优异的铁电性能，以使所述U形存储单元串中铁电薄膜层8实现存储功能。
在一个实施例中，还包括填充层11，设置在所述沟道层10内，用于填满所述柱状结构的中心。
本实施例中，在沟道层10中增加了填充层11，相当于减少了器件中沟道层10的体积，这可以减少沟道层10中的缺陷，有助于提升器件的疲劳性能和改善器件之间的差异性。
需要说明的是，常规的存储单元串为长条状，源极及其选择晶体管设置在存储单元串的上端，漏极及其选择晶体管位于存储单元串的下端。这样会影响后续工艺中的金属布线，造成组装工艺复杂。而本发明提供的U型铁电场效应晶体管存储单元串，使得源极和漏极分别位于U形存储单元串的两个第一柱状结构的顶端，可以获得更为紧凑的布线，实现更高密度集成，使得组装工艺简单易用。
在一个实施例中，沟道层10的厚度不大于所述沟道层10的耗尽层的厚度。
在一个实施例中，相邻的所述栅电极4之间设置有隔离层3。该隔离层3为绝缘材质，用于隔离相邻的栅电极4。
优选的，隔离层3的材质为SiO 2或介电常数比SiO 2的介电常数更小的绝缘材料。
在一个实施例中，第一介质层7为氧化硅(SiO 2)、氮化硅(Si 3N 4)、氮氧化硅(SiON)、氧化铝(Al 2O 3)、氧化铪(HfO 2)、氧化锆(ZrO 2)、氧化钛(TiO 2)、氧化镧(La 2O 3)、氮氧硅铪(HfSiON)、氧化锗(GeO 2)中的一种或多种；所述第二介质层9为氧化硅(SiO 2)、氮化硅(Si 3N 4)、氮氧化硅(SiON)、氧化铝(Al 2O 3)、氧化铪(HfO 2)、氧化锆(ZrO 2)、氧化钛(TiO 2)、氧化镧(La 2O 3)、氮氧硅铪(HfSiON)、氧化锗(GeO 2)等中的一种或多种。
在一个实施例中，铁电薄膜层8为氧化铪(HfO 2)、掺杂的HfO 2、氧化锆(ZrO 2)或掺杂的ZrO 2中的一种；其中，掺杂的HfO 2中掺杂的元素包括硅(Si)、铝(Al)、锆(Zr)、镧(La)、铈(Ce)、锶(Sr)、镥(Lu)、钆(Gd)、钪(Sc)、钕(Nd)、锗(Ge)、氮(N)中的一种或多种。
在一个实施例中，沟道层10为多晶硅(Si)、多晶锗(Ge)、多晶硅锗(SiGe)，或掺杂的多晶硅(Si)、掺杂的多晶锗(Ge)、掺杂的多晶硅锗(SiGe)，掺杂元素为硼(B)、磷(P)和砷(As)中的一种或多种。
图3是本发明第三实施方式提供的U形铁电场效应晶体管存储器结构示意图。
如图3所示，该存储器包括：基底1、导电层2和多个第二实施方式提供的U形铁电场效应晶体管存储单元串5；所述导电层2设置在所述基底1上；所述U形铁电场效应晶体管存储单元串5的第二柱状结构嵌设在所述导电层2内，所述U形铁电场效应晶体管存储单元串5的两个第一柱状结构位于所述导电层2外且与所述导电层2垂直设置；所述分离层6，设置在所述导电层2上，且位于两个所述柱状结构之间，用于隔离两个所述结构。
其中，多层的所述栅电极4设置在所述导电层2的表面上，相邻的所述栅电极4之间设置有隔离层3,所述导电层2与所述栅电极4之间设置有所述隔离层3。
优选的，基底1为半导体衬底，包括但不限于硅(Si)，锗(Ge)，硅锗(SiGe)，砷化镓(GaAs)等。
优选的，所述导电层2，包括但不限于与基底1形成pn结，例如，若基底1为p型半导体，则导电层2为重掺杂的n型半导体。
优选的，所述导电层2还可以为金属电极，且与所述基底1之间通过设置绝缘材料隔离。
优选的，铁电薄膜层8可以为氧化铪(HfO 2)或掺杂的HfO 2，掺杂元素包括硅(Si)、铝(Al)、锆(Zr)、镧(La)、铈(Ce)、锶(Sr)、镥(Lu)、钆(Gd)、钪(Sc)、钕(Nd)、锗(Ge)、氮(N)等中的一种或多种，还可以为氧化锆(ZrO 2)以及掺杂的ZrO 2。
优选的，第一介质层7为氧化硅(SiO 2)、氮化硅(Si 3N 4)、氮氧化硅(SiON)、氧化铝(Al 2O 3)、氧化铪(HfO 2)、氧化锆(ZrO 2)、氧化钛(TiO 2)、氧化镧(La 2O 3)、氮氧硅铪(HfSiON)、氧化锗(GeO 2)中的一种或多种。
优选的，第二介质层9为所述第一介质层为氧化硅(SiO 2)、氮化硅(Si 3N 4)、氮氧化硅(SiON)、氧化铝(Al 2O 3)、氧化铪(HfO 2)、氧化锆(ZrO 2)、氧化钛(TiO 2)、氧化镧(La 2O 3)、氮氧硅铪(HfSiON)、氧化锗(GeO 2)中的一种或多种。
优选的，所述沟道层10为多晶硅(Si)、多晶锗(Ge)、多晶硅锗(SiGe)，或掺杂的多晶硅(Si)、掺杂的多晶锗(Ge)、掺杂的多晶硅锗(SiGe)，掺杂元 素为硼(B)、磷(P)和砷(As)中的一种。
优选的，所述沟道层10的厚度不大于其耗尽层厚度。
优选的，所述填充层11包括但不限于SiO 2、SiON和Si 3N 4。
优选的，所述隔离层3为SiO 2或介电常数比SiO 2更小的绝缘材料。
优选的，所述栅电极4为重掺杂的多晶硅，氮化物金属电极和钨(W)中的任一种。
图4是本发明第四实施方式提供的制备存储器的方法流程示意图。
如图4所示，包括步骤S1-S7。
其中，S1,在基底1上形成导电层2，参见图4a。
在一个实施例中，可以采用离子注入工艺向基底1的表面注入离子，以使导电层2和基底1形成pn结，所注入离子根据基底1确定。
S2,在所述导电层2中形成至少一个沟槽12a，并沉积介质以填满所述沟槽12a，参见图4b。
其中，可以采用湿法或干法刻蚀工艺在导电层中形成沟槽12a，形成沟槽12a的个数根据需求而定。每个沟槽12a的轮廓对应的为U形铁电场效应晶体管存储器的U型铁电场效应晶体管存储单元串的第二柱状结构的轮廓。
其中，沉积的介质为SiO 2、SiON和Si 3N 4中的一种或多种，沉积方法为热氧化、化学气相沉积法(CVD)、溅射法(sputtering)、原子层沉积法(ALD)中的任一种或多种。
S3：在所述导电层2表面依次交叠沉积隔离层3和栅电极4得到堆叠层，所述栅电极4的层数为预设层数。
可选的，在S3中沉积的隔离层3为SiO 2或介电常数比SiO 2更小的绝缘材料，沉积方法为化学气相沉积法(CVD)、溅射法(sputtering)、原子层沉积法(ALD)中的任一种。
可选的，沉积的控制栅电极层4为重掺杂的多晶硅，氮化物金属电极，钨(W)中的任一种，沉积方法为化学气相沉积法(CVD)、溅射法(sputtering)、原子层沉积法(ALD)和金属有机物气相沉积法(MOCVD)中的任一种。
S4：在每个所述沟槽12a的上方形成两个通孔13，所述通孔13贯穿所述堆叠层，且直至所述沟槽12a的顶部。
可选的，采用湿法或干法刻蚀工艺形成通孔13。
S5：去除所述沟槽12a中的填充的介质，以使得所述两个通孔13形成U型通孔。
可选的，去除所述填充介质的方法为湿法刻蚀工艺。
S6：在所述U型通孔的内壁依次沉积第一介质层7、铁电薄膜层8、第二介质层9和沟道层10。
可选的，沉积的铁电薄膜层8可以为氧化铪(HfO 2)或掺杂的HfO 2，掺杂元素包括硅(Si)、铝(Al)、锆(Zr)、镧(La)、铈(Ce)、锶(Sr)、镥(Lu)、钆(Gd)、钪(Sc)、钕(Nd)、锗(Ge)、氮(N)等中的一种或多种，还可以为氧化锆(ZrO 2)以及掺杂的ZrO 2，沉积方法为化学气相沉积法(CVD)或原子层沉积(ALD)。
可选的，沉积的第一介质层7为氧化硅(SiO 2)、氮化硅(Si 3N 4)、氮氧化硅(SiON)、氧化铝(Al 2O 3)、HfO 2、ZrO 2、氧化钛(TiO 2)、氧化镧(La 2O 3)、氮氧硅铪(HfSiON)、氧化锗(GeO 2)等中的一种或多种，沉积方法为化学气相沉积法(CVD)或原子层沉积法(ALD)。
可选的，沉积的第二介质层9为氧化硅(SiO 2)、氮化硅(Si 3N 4)、氮氧化硅(SiON)、氧化铝(Al 2O 3)、氧化铪(HfO 2)、氧化锆(ZrO 2)、氧化钛(TiO 2)、氧化镧(La 2O 3)、氮氧硅铪(HfSiON)、氧化锗(GeO 2)等中的一种或多种，沉积方法为化学气相沉积法(CVD)或原子层沉积法(ALD)。
可选的，沉积的沟道层10为多晶硅(Si)、多晶锗(Ge)、多晶硅锗(SiGe)，或掺杂的多晶硅(Si)、掺杂的多晶锗(Ge)、掺杂的多晶硅锗(SiGe)，掺杂元素为硼(B)、磷(P)和砷(As)中的一种，沉积方法为化学气相沉积法(CVD)或原子层沉积法(ALD)。
可选的，沉积的填充层11包括但不限于SiO 2、SiON和Si 3N 4，沉积方法为化学气相沉积法(CVD)或原子层沉积法(ALD)。
S7：在所述U型通孔的中部形成分离层6，所述分离层6至少贯穿所述叠层结构中的栅电极4，以形成所述U形铁电场效应晶体管存储器。
其中，分离层6例如是孔，或者先形成孔，然后在沉积绝缘材料。
例如采用干法或湿法刻蚀工艺对U形通孔的中部刻蚀，以形成该分离孔，该分离孔即为分离层。
或者，在采用干法或湿法刻蚀工艺对U形通孔的中部刻蚀形成分离孔之后，在沉积绝缘材料以填充分离孔得到分离层。
在一个实施例中，所述步骤S6之后，在步骤S7之前，还包括：
在沟道层10的内壁上沉积填充层11以充满所述通孔13。
其中，沉积的填充层11包括但不限于SiO 2、SiON和Si 3N 4，沉积方法为化学气相沉积法(CVD)或原子层沉积法(ALD)。
本发明的上述技术方案具有如下有益的技术效果：
(1)本发明实施例提供的U型存储单元串，可以获得更为紧凑的布线，实现更高密度集成。
(2)存储单元串通过设置第一介质层7和第二介质层9使得铁电薄膜8不直接与栅电极层4和沟道层10接触，避免铁电薄膜8中的元素扩散及其与栅电极和沟道层的界面反应，进一步保证了铁电薄膜层8和存储单元的质量和性能，减小存储单元之间的差异性，提高存储器的可靠性，另外，第一介质层7和第二介质层9作为铁电薄膜层8生长的种子层或应力调控层，从而提升铁电薄膜层8的性能，而且还可以有效地降低漏电流，提升FeFET存储器的保持性能。
(3)本发明实施例提供的存储单元串中，在沟道层10中增加了填充层11，相当于减少了器件中沟道层10的体积，这可以减少沟道层10中的缺陷，有助于提升器件的疲劳性能和改善器件之间的差异性。
(4)本发明实施例提供的制备方法避免了对第一介质层7、铁电薄膜层8和第二介质层9的刻蚀，可以增加存储器的可靠性。
应当理解的是，本发明的上述具体实施方式仅仅用于示例性说明或解释 本发明的原理，而不构成对本发明的限制。因此，在不偏离本发明的精神和范围的情况下所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。此外，本发明所附权利要求旨在涵盖落入所附权利要求范围和边界、或者这种范围和边界的等同形式内的全部变化和修改例。

Claims (15)

  1. 一种U形铁电场效应晶体管存储单元串，其特征在于，包括由两个第一柱状结构通过第二柱状结构连接而成的U形体、分离层(6)和间隔设置的多层的栅电极(4)；
    每层所述栅电极(4)，用于包围所述U形体的第一柱状结构；
    所述分离层(6)，贯穿于所述多层栅电极(4)，且位于所述U形体的开口内，用于隔离所述U形体的两个所述第一柱状结构，以使所述U形存储单元串中的存储单元的个数为所述U形存储单元串中的栅电极(4)层数的二倍；
    每个柱状结构由外层至内层依次设置有第一介质层(7)、铁电薄膜层(8)、第二介质层(9)和沟道层(10)；
    其中，所述第一介质层(7)和所述第二介质层(9)用于隔离所述铁电薄膜层(8)，以避免所述铁电薄膜层(8)与所述沟道层(10)和所述栅电极(4)直接接触，还使所述第一介质层(9)和第二介质层(11)均作为所述铁电薄膜层(10)生长的种子层或应力调控层，促进所述铁电薄膜层(10)中铁电相的生成，以使所述U形铁电场效应晶体管存储单元串中铁电薄膜层(8)实现存储功能。
  2. 根据权利要求1所述的U形铁电场效应晶体管存储单元串，其特征在于，还包括：
    填充层(11)，设置在所述沟道层(10)内，用于填满所述柱状结构的中心。
  3. 根据权利要求1或2所述的U形铁电场效应晶体管存储单元串，其特征在于，
    所述沟道层(10)的厚度不大于所述沟道层(10)的耗尽层的厚度。
  4. 根据权利要求1或2所述的U形铁电场效应晶体管存储单元串，其特征在于，
    相邻的所述栅电极(4)之间设置有隔离层(3)。
  5. 根据权利要求1或2所述的U形铁电场效应晶体管存储单元串，其特征在于，
    所述第一介质层(7)为氧化硅(SiO 2)、氮化硅(Si 3N 4)、氮氧化硅(SiON)、氧化铝(Al 2O 3)、氧化铪(HfO 2)、氧化锆(ZrO 2)、氧化钛(TiO 2)、氧化镧(La 2O 3)、氮氧硅铪(HfSiON)、氧化锗(GeO 2)中的一种或多种；
    所述第二介质层(9)为氧化硅(SiO 2)、氮化硅(Si 3N 4)、氮氧化硅(SiON)、氧化铝(Al 2O 3)、氧化铪(HfO 2)、氧化锆(ZrO 2)、氧化钛(TiO 2)、氧化镧(La 2O 3)、氮氧硅铪(HfSiON)、氧化锗(GeO 2)等中的一种或多种。
  6. 根据权利要求1或2所述的U形铁电场效应晶体管存储单元串，其特征在于，
    所述铁电薄膜层(8)为氧化铪(HfO 2)、掺杂的HfO 2、氧化锆(ZrO 2)或掺杂的ZrO 2中的一种；其中，掺杂的HfO 2中掺杂的元素包括硅(Si)、铝(Al)、锆(Zr)、镧(La)、铈(Ce)、锶(Sr)、镥(Lu)、钆(Gd)、钪(Sc)、钕(Nd)、锗(Ge)、氮(N)中的一种或多种。
  7. 根据权利要求1或2所述的U形铁电场效应晶体管存储单元串，其特征在于，
    所述沟道层(10)为多晶硅(Si)、多晶锗(Ge)、多晶硅锗(SiGe)，或掺杂的多晶硅(Si)、掺杂的多晶锗(Ge)、掺杂的多晶硅锗(SiGe)，掺杂元素为硼(B)、磷(P)和砷(As)中的一种或多种。
  8. 一种U形铁电场效应晶体管存储器，其特征在于，包括：基底(1)、导电层(2)和多个如权利要求1-7任一项所述的U形铁电场效应晶体管存储单元串(5)；
    所述导电层(2)设置在所述基底(1)表面；
    所述第二柱状结构嵌设在所述导电层(2)内，两个所述第一柱状结构均位于所述导电层(2)外且与所述导电层(2)垂直设置；
    所述分离层(6)，设置在所述导电层(2)远离所述基底(1)的一面， 且位于两个所述第一柱状结构之间，用于隔离两个所述第一柱状结构。
  9. 根据权利要求8所述的U形铁电场效应晶体管存储器，其特征在于，
    多层的所述栅电极(4)设置在所述导电层(2)的表面上，相邻的所述栅电极(4)之间设置有隔离层(3)；
    多层的所述栅电极(4)中，靠近所述导电层(2)的栅电极(4)与所述导电层(2)之间设置有所述隔离层(3)。
  10. 一种电子设备，其特征在于，包括一个或多个如权利要求9所述的U形铁电场效应晶体管存储器。
  11. 一种U形三维铁电场效应晶体管存储器的制备方法，其特征在于，包括：
    S1：在基底(1)上形成导电层(2)；
    S2：在所述导电层(2)中形成至少一个沟槽(12a)，并沉积介质以填满所述沟槽(12a)；
    S3：在所述导电层(2)表面依次交叠沉积隔离层(3)和栅电极(4)得到堆叠层，所述栅电极(4)的层数为预设层数；
    S4：在每个所述沟槽(12a)的上方形成两个通孔(13)，所述通孔(13)贯穿所述堆叠层，且直至所述沟槽(12a)的顶部；
    S5：去除所述沟槽(12a)中的填充的介质，以使得所述两个通孔(13)形成U型通孔；
    S6：在所述U型通孔的内壁依次沉积第一介质层(7)、铁电薄膜层(8)、第二介质层(9)和沟道层(10)；
    S7：在所述U型通孔的中部形成分离层(6)，所述分离层(6)至少贯穿所述叠层结构中的栅电极(4)，以形成所述U形铁电场效应晶体管存储器。
  12. 根据权利要求11所述的方法，其特征在于，所述步骤S6之后，在步骤S7之前，还包括：
    在沟道层(10)的内壁上沉积填充层(11)以充满所述通孔(13)。
  13. 根据权利要求11或12所述的方法，其特征在于，所述步骤S2包括：
    采用湿法工艺或者刻蚀工艺在所述导电层中形成沟槽(12a)；
    采用热氧化、化学气相沉积法(CVD)、溅射法(sputtering)、原子层沉积法(ALD)中的任一种或多种方法沉积介质，以填满所述沟槽(12a)；所述沉积的所述介质为SiO 2、SiON和Si 3N 4中的一种或多种。
  14. 根据权利要求11所述的方法，其特征在于，所述步骤S7，包括：
    采用干法或湿法刻蚀工艺对U形通孔的中部刻蚀形成分离孔。
  15. 根据权利要求14所述的方法，其特征在于，在采用干法或湿法刻蚀工艺对U形通孔的中部刻蚀形成分离孔之后，还包括：
    向所述分离孔内沉积绝缘材料以填充所述分离孔。
PCT/CN2020/119410 2020-06-30 2020-12-01 U形铁电场效应晶体管存储单元串、存储器及制备方法 WO2022000843A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010622379.5 2020-06-30
CN202010622379.5A CN111799262A (zh) 2020-06-30 2020-06-30 U形铁电场效应晶体管存储单元串、存储器及制备方法

Publications (1)

Publication Number Publication Date
WO2022000843A1 true WO2022000843A1 (zh) 2022-01-06

Family

ID=72810044

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/119410 WO2022000843A1 (zh) 2020-06-30 2020-12-01 U形铁电场效应晶体管存储单元串、存储器及制备方法

Country Status (2)

Country Link
CN (1) CN111799262A (zh)
WO (1) WO2022000843A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111799262A (zh) * 2020-06-30 2020-10-20 湘潭大学 U形铁电场效应晶体管存储单元串、存储器及制备方法
CN112687522A (zh) * 2020-12-24 2021-04-20 上海集成电路研发中心有限公司 一种非晶锗硅薄膜结构、集成结构以及制造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102760740A (zh) * 2011-04-29 2012-10-31 海力士半导体有限公司 非易失性存储器件及其制造方法
US20160181259A1 (en) * 2014-12-23 2016-06-23 Imec Vzw Vertical ferroelectric memory device and a method for manufacturing thereof
CN108987400A (zh) * 2017-05-31 2018-12-11 爱思开海力士有限公司 具有铁电层的半导体器件及其制造方法
CN110071116A (zh) * 2019-04-28 2019-07-30 中国科学院微电子研究所 一种三维nand型铁电存储器、制作方法及操作方法
CN111799262A (zh) * 2020-06-30 2020-10-20 湘潭大学 U形铁电场效应晶体管存储单元串、存储器及制备方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102760740A (zh) * 2011-04-29 2012-10-31 海力士半导体有限公司 非易失性存储器件及其制造方法
US20160181259A1 (en) * 2014-12-23 2016-06-23 Imec Vzw Vertical ferroelectric memory device and a method for manufacturing thereof
CN108987400A (zh) * 2017-05-31 2018-12-11 爱思开海力士有限公司 具有铁电层的半导体器件及其制造方法
CN110071116A (zh) * 2019-04-28 2019-07-30 中国科学院微电子研究所 一种三维nand型铁电存储器、制作方法及操作方法
CN111799262A (zh) * 2020-06-30 2020-10-20 湘潭大学 U形铁电场效应晶体管存储单元串、存储器及制备方法

Also Published As

Publication number Publication date
CN111799262A (zh) 2020-10-20

Similar Documents

Publication Publication Date Title
WO2023097743A1 (zh) 半导体存储单元结构、半导体存储器及其制备方法、应用
US8609492B2 (en) Vertical memory cell
KR102377358B1 (ko) 반도체 메모리 소자 및 그 제조 방법
WO2018136734A1 (en) Ferroelectric oxide memory devices
US20170110543A1 (en) Three-dimensional semiconductor devices
CN109148463A (zh) 半导体器件
CN111799263A (zh) 一种三维nand铁电存储器及其制备方法
WO2011095044A1 (zh) 一种动态随机存储器的阵列结构及其制备方法
WO2022000843A1 (zh) U形铁电场效应晶体管存储单元串、存储器及制备方法
CN111627918A (zh) 一种3d nand存储器及其制造方法
WO2022151697A1 (zh) 半导体结构及其制作方法
CN104637945B (zh) 半浮栅存储器及其制造方法和半浮栅存储器阵列
CN108470737A (zh) 三维存储器及其制造方法
CN111799265B (zh) 一种三维nand型铁电场效应晶体管存储器及其制备方法
US20230115307A1 (en) Buried word line structure and method for manufacturing same, and dynamic random access memory
TWI733471B (zh) 三維記憶體元件及其製造方法
WO2023221354A1 (zh) 存储器、动态随机存取存储器和电子设备
CN111799278B (zh) 一种三维铁电存储器及其制备方法
CN111799264B (zh) 一种三维沟槽型铁电存储器及其制备方法
KR20230132109A (ko) 반도체 장치 및 그의 제조방법
KR20220151819A (ko) 반도체 장치 및 그 제조 방법
CN113871395A (zh) 三维铁电场效应晶体管存储单元、存储器及制备方法
WO2023221352A1 (zh) 半导体器件及其制造方法、动态随机存取存储器和电子设备
US9105505B2 (en) Memory cell having a recessed gate and manufacturing method thereof
WO2023134015A1 (zh) 半导体结构及其制备方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20942812

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20942812

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 20942812

Country of ref document: EP

Kind code of ref document: A1