WO2023221469A1 - 半导体器件及其制造方法、电子设备 - Google Patents

半导体器件及其制造方法、电子设备 Download PDF

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Publication number
WO2023221469A1
WO2023221469A1 PCT/CN2022/137718 CN2022137718W WO2023221469A1 WO 2023221469 A1 WO2023221469 A1 WO 2023221469A1 CN 2022137718 W CN2022137718 W CN 2022137718W WO 2023221469 A1 WO2023221469 A1 WO 2023221469A1
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layer
semiconductor
memory cell
bit line
along
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PCT/CN2022/137718
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English (en)
French (fr)
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王祥升
王桂磊
戴瑾
赵超
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北京超弦存储器研究院
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Publication of WO2023221469A1 publication Critical patent/WO2023221469A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to but is not limited to the field of semiconductor devices, and in particular, to a semiconductor device, a manufacturing method thereof, and electronic equipment.
  • DRAM Dynamic Random Access Memory
  • I/O input/output
  • memory cell operations eg, writing or reading
  • Embodiments of the present application provide a semiconductor device, including: a substrate, a peripheral circuit area and a storage area stacked sequentially on one side of the substrate, and the circuits in the peripheral circuit area and the circuits in the storage area are electrically connected. ;
  • the peripheral circuit area includes peripheral circuits;
  • the storage area includes:
  • a plurality of memory cell columns extending along a first direction perpendicular to the substrate, each of the memory cell columns including a plurality of memory cells stacked on one side of the substrate along the first direction, different
  • the memory cell columns are arranged on the substrate along a second direction and a third direction to form an array, the second direction and the third direction intersect and form a plane parallel to the substrate;
  • the memory unit includes a transistor and a capacitor arranged sequentially along the second direction.
  • the transistor includes a semiconductor layer and a gate.
  • the semiconductor layer extends along the second direction into a strip-shaped structure.
  • the strip-shaped structure has side surfaces.
  • the wall and both ends, and the sidewalls in the second direction include a source region, a channel region and a drain region, the source region and the drain region are respectively close to both ends of the semiconductor pillar layer, so
  • the channel region is located between the source region and the drain region, and the gate surrounds the sidewalls of the channel region;
  • the capacitor is disposed on the sidewall of the drain region.
  • the storage area may further include: a plurality of bit lines extending along the first direction and arranged at intervals in the second direction, and two adjacent storage cells along the second direction are distributed in a mirror image, The source regions of the transistors of the two adjacent memory cells are connected to a common bit line.
  • the storage area may further include: a plurality of word lines extending in the third direction and arranged at intervals in the first direction, wherein the storage area is provided with a memory cell column in the third direction.
  • each of the word lines is formed by a gate of a transistor of a memory cell in a memory cell column arranged along the third direction; or, the storage area is provided with multiple memory cell columns in the third direction, each of which The word line is formed by connecting together the gates of the transistors of a plurality of memory cells arranged along the third direction.
  • the capacitor may surround the sidewall of the drain region.
  • the plurality of word lines arranged at intervals along the first direction may have different lengths and form a ladder shape.
  • the material of the word line may include at least one element of indium and tin.
  • the material of the semiconductor layer may be a metal oxide semiconductor material, and the metal in the metal oxide semiconductor material is selected from any of indium zinc, tungsten, tin, titanium, zirconium, hafnium and gallium. one or more.
  • the capacitor may include a first electrode plate, a second electrode plate, a dielectric layer disposed between the first electrode plate and the second electrode plate, and the drain region connected to the first electrode plate.
  • the memory cell column may further include an interlayer isolation layer.
  • the interlayer isolation layer is disposed between the gates of the transistors of two adjacent memory cells in the memory cell column. The gates of the transistors of two adjacent memory cells are isolated.
  • the semiconductor device may further include one or more memory cell isolation pillars extending along the first direction.
  • the memory cell isolation column may be provided every two memory cell columns in the second direction.
  • the semiconductor device may further include an internal support layer, and the internal support layer may be disposed between two adjacent semiconductor layers along the first direction and configured to provide support for the semiconductor layer.
  • the internal support layer may be located on both sides of the bit line, or may be located on both sides of the bit line and the side walls of the memory cell isolation pillar.
  • the peripheral circuit may be a complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) transistor, and the peripheral circuit area may further include a metal contact layer, a metal interconnect layer and an insulating dielectric layer; so The peripheral circuit is provided on one side of the substrate, the metal contact layer is provided on a side of the peripheral circuit away from the substrate, a metal contact post is provided in the metal contact layer, and the metal interconnection layer.
  • the insulating dielectric layer is disposed on the side of the metal contact layer away from the substrate, the metal interconnection layer is provided with metal lines, and the insulating dielectric layer is disposed on the side of the metal interconnection layer away from the substrate;
  • the memory cell column is arranged on a side of the insulating dielectric layer away from the substrate; one end of the metal line is electrically connected to the bit line, word line or capacitor of the storage area, and the other end of the metal line It is electrically connected to the peripheral circuit through the metal contact post.
  • An embodiment of the present application also provides a method for manufacturing a semiconductor device, including:
  • a peripheral circuit is provided on one side of the substrate to form a peripheral circuit area
  • a plurality of composite layers composed of the sacrificial layer and the channel layer are stacked and arranged along the first direction in a staggered order of the sacrificial layer and the channel layer on the side of the peripheral circuit area away from the substrate;
  • the sacrificial layer is removed, and the remaining channel layer forms a plurality of semiconductor layers arranged in arrays along the first direction and the third direction and extending along the second direction.
  • the semiconductor layers extend along the second direction into a strip structure, and the strip structures.
  • the structure has sidewalls and two ends, and the sidewalls in the second direction include source regions and drain regions near the two ends, and a channel region between the source region and the drain region;
  • a gate electrode surrounding the channel region is provided on the sidewall of the channel region of the semiconductor layer to obtain a plurality of transistors formed by the semiconductor layer and the gate electrode; and, semiconductors arranged in a third direction There is one semiconductor layer, and the gate on this semiconductor layer is used as a word line; or, there are multiple semiconductor layers arranged in the third direction, and the gates on the multiple semiconductor layers arranged in the third direction are arranged in the third direction. connected together to form word lines;
  • a capacitor is provided on the sidewall of the drain region of the semiconductor layer
  • the circuits of the storage area and the circuits of the peripheral circuit area are electrically connected.
  • defining memory cell regions in the plurality of composite layers, etching bit line trenches along the first direction, and filling the bit line trenches with isolation material may include:
  • the memory cell isolation trench is filled with memory cell isolation pillars and the bit line trench is filled with isolation material.
  • defining memory cell regions in the plurality of composite layers, etching bit line trenches along the first direction, and filling the bit line trenches with isolation material may also include:
  • the material of the sacrificial layer may be aluminum-doped zinc oxide.
  • a gate dielectric layer and a gate electrode surrounding the channel region are sequentially arranged on the sidewalls of the channel region of the semiconductor layer to obtain a plurality of transistors formed by the semiconductor layer and the gate electrode; and, There is one semiconductor layer arranged in the third direction, and the gate electrode on this semiconductor layer is used as a word line; or, there are multiple semiconductor layers arranged in the third direction, and the gate electrode on the multiple semiconductor layers arranged in the third direction is The gates are connected together in the third direction to form a word line;
  • An interlayer isolation layer is provided between two adjacent semiconductor layers along the first direction, thereby isolating the gate electrodes on the two adjacent semiconductor layers along the first direction.
  • arranging a capacitor on the sidewall of the drain region of the semiconductor layer may include:
  • a first electrode plate, a dielectric layer and a second electrode plate surrounding the side wall of the drain region are sequentially arranged on the side wall of the drain region of the semiconductor layer away from the channel region, so that the first electrode plate, the dielectric layer and the second electrode plate surrounding the drain region are obtained. capacitor on the sidewalls of the drain region.
  • the peripheral circuit is provided on one side of the substrate, and forming the peripheral circuit area may include:
  • a peripheral circuit, a metal contact layer with metal contact posts, a metal interconnection layer with metal lines, and an insulating dielectric layer are sequentially arranged on one side of the substrate, and one end of the metal line is connected to the metal contact post through the metal contact post.
  • the peripheral circuits are electrically connected to obtain the peripheral circuit area.
  • electrically connecting the circuits of the storage area and the circuits of the peripheral circuit area may include:
  • One end of the metal line away from the metal contact post is electrically connected to the bit line, the word line or the capacitor;
  • An embodiment of the present application also provides an electronic device, including the semiconductor device provided in the above embodiment of the present application.
  • the electronic device may include a storage device, a smart phone, a computer, a tablet, an artificial intelligence device, a wearable device, or a mobile power supply.
  • FIG. 1A is a schematic front cross-sectional structural diagram of a semiconductor device according to an exemplary embodiment of the present application
  • FIG. 1B is a schematic top structural view of a transistor of the semiconductor device shown in FIG. 1A;
  • FIG. 2A is a schematic front cross-sectional structural view of a storage area of a semiconductor device according to an exemplary embodiment of the present application
  • FIG. 2B is an enlarged view of the transistor of the semiconductor device shown in FIG. 1A;
  • FIG. 2C is an enlarged view of the capacitor of the semiconductor device shown in FIG. 1A;
  • Figure 3 is a distribution state diagram in the side view direction of a plurality of word lines spaced apart along the first direction of the semiconductor device according to an exemplary embodiment of the present application;
  • FIG. 4A is a schematic front cross-sectional structural view of a storage area of a semiconductor device according to another exemplary embodiment of the present application.
  • Figure 4B is a schematic structural diagram of the storage area of the semiconductor device shown in Figure 4A;
  • 5A is a schematic front cross-sectional structural view of the peripheral circuit area of the semiconductor device according to an exemplary embodiment of the present application.
  • Figure 5B is a schematic top structural view of the peripheral circuit area of the semiconductor device shown in Figure 5A;
  • Figure 6 is a process flow diagram of a manufacturing method of a semiconductor device according to an embodiment of the present application.
  • FIG. 7A is a schematic front cross-sectional structural view of an intermediate product obtained in an intermediate step of the manufacturing method of a semiconductor device according to an exemplary embodiment of the present application;
  • Figure 7B is a schematic top structural view of the intermediate product shown in Figure 7A;
  • FIG. 8A is a schematic front cross-sectional structural view of an intermediate product obtained in an intermediate step of the manufacturing method of a semiconductor device according to an exemplary embodiment of the present application;
  • Figure 8B is a schematic top structural view of the intermediate product shown in Figure 8A;
  • 9A is a schematic front cross-sectional structural view of an intermediate product obtained in an intermediate step of the manufacturing method of a semiconductor device according to an exemplary embodiment of the present application.
  • Figure 9B is a schematic top structural view of the intermediate product shown in Figure 9A;
  • 10A is a schematic front cross-sectional structural view of an intermediate product obtained in an intermediate step of the manufacturing method of a semiconductor device according to an exemplary embodiment of the present application;
  • Figure 10B is a schematic top structural view of the intermediate product shown in Figure 10A;
  • 11A is a schematic front cross-sectional structural view of an intermediate product obtained in an intermediate step of the manufacturing method of a semiconductor device according to an exemplary embodiment of the present application;
  • FIG. 11B is a schematic top structural view of the intermediate product shown in FIG. 11A.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • set and “connection” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • film and “layer” may be interchanged.
  • dielectric layer may sometimes be replaced by “dielectric film”.
  • Embodiments of the present application provide a semiconductor device.
  • the semiconductor device includes: a substrate, a peripheral circuit area and a storage area that are sequentially stacked on one side of the substrate.
  • the circuits in the peripheral circuit area and the storage area The circuit is electrically connected;
  • the peripheral circuit area includes peripheral circuits;
  • the storage area includes:
  • a plurality of memory cell columns extending along a first direction perpendicular to the substrate, each of the memory cell columns including a plurality of memory cells stacked on one side of the substrate along the first direction, different
  • the memory cell columns are arranged on the substrate along a second direction and a third direction to form an array, the second direction and the third direction intersect and form a plane parallel to the substrate;
  • the memory unit includes a transistor and a capacitor arranged sequentially along the second direction.
  • the transistor includes a semiconductor layer and a gate.
  • the semiconductor layer extends along the second direction into a strip-shaped structure.
  • the strip-shaped structure has side surfaces.
  • the wall and both ends, and the sidewalls in the second direction include a source region, a channel region and a drain region, the source region and the drain region are respectively close to both ends of the semiconductor pillar layer, so
  • the channel region is located between the source region and the drain region, and the gate surrounds the sidewalls of the channel region;
  • the capacitor is disposed on the sidewall of the drain region.
  • the semiconductor device may further include: a plurality of bit lines extending along the first direction and spaced apart in the second direction, and two adjacent memory cells along the second direction are distributed in a mirror image. , the source regions of the transistors of the two adjacent memory cells are connected to a common bit line.
  • the semiconductor device may further include: a plurality of word lines extending in the third direction and arranged at intervals in the first direction, wherein the storage area is provided with a memory unit in the third direction. columns, each word line is formed by a gate of a transistor of a memory cell in a memory cell column arranged along the third direction; or, the storage area is provided with multiple memory cell columns in the third direction, each The word line is formed by connecting together the gates of transistors of a plurality of memory cells arranged along the third direction.
  • the capacitor may surround the sidewall of the drain region.
  • the semiconductor device provided by the embodiment of the present application can be applied in the field of DRAM.
  • it can be applied to DRAM with 3D memory cells formed by a superlattice structure.
  • a multi-layer superlattice on a substrate can be used to form multi-layer memory cells.
  • Each layer of memory cells can be array-distributed memory cells.
  • the memory cells at the same position in each layer in the two-dimensional plane form a vertical direction.
  • a column of storage units is referred to as a storage unit column.
  • FIG. 1A is a schematic front cross-sectional structural view of a semiconductor device according to an exemplary embodiment of the present application
  • FIG. 1B is a schematic top structural view of a transistor of the semiconductor device shown in FIG. 1A
  • the semiconductor device may include: a substrate 100 , a peripheral circuit area A and a storage area B.
  • the peripheral circuit area A and the storage area B are sequentially stacked on the substrate 100 On one side, the circuit of the peripheral circuit area A and the circuit of the storage area B are electrically connected.
  • the peripheral circuit area A includes a peripheral circuit 500 disposed on the substrate 100 .
  • Figure 2A is a schematic front cross-sectional structural view of a storage area of a semiconductor device according to an exemplary embodiment of the present application
  • Figure 2B is an enlarged view of a transistor of the semiconductor device shown in Figure 1A
  • Figure 2C is a capacitor of the semiconductor device shown in Figure 1A enlarged image of.
  • the memory area B includes: a plurality of memory cell columns 200 extending along a first direction perpendicular to the substrate 100 , and a plurality of memory cell columns 200 extending along the first direction and arranged at intervals in the second direction.
  • bit line 300 Bit Line, BL
  • word lines 400 Word Line, WL
  • bit line 300 Bit Line, BL
  • word lines 400 Word Line, WL
  • FIG. 1A, Figure 1B or Figure 2A shows a three-layer memory cell formed by a three-layer superlattice. Each layer of memory cell corresponds to There are 4 word lines 400, and there are 12 word lines 400 in total in Figure 1A, Figure 1B or Figure 2A.
  • Each memory cell column 200 includes a plurality of memory cells 1 stacked along a first direction on one side of the substrate 100 .
  • each memory cell column 200 is stacked along a first direction on one side of the substrate 100 .
  • a plurality of memory cells 1 are formed on one side of the substrate 100; different memory cell columns 200 are arranged on the substrate 100 along the second direction and the third direction to form an array, and the second direction and the The third direction is vertical and forms a plane parallel to the substrate.
  • Each of the memory cells 1 includes a transistor 10 and a capacitor 20 arranged sequentially along the second direction.
  • the transistor 10 includes a semiconductor layer 11 and a gate 12 .
  • the semiconductor layer 11 extends in a strip shape along the second direction. structure, the strip-shaped structure has sidewalls and two ends, the cross-section of the strip-shaped structure can be rectangular, circular, elliptical, etc., and the sidewalls in the second direction include the source region 111, the channel region 112 and drain region 113.
  • the source region 111 and the drain region 113 are respectively close to both ends of the semiconductor layer 11.
  • the channel region 112 is located in the source region 111 and the drain region. Between regions 113 , the gate 12 surrounds the sidewalls of the channel region 112 .
  • the capacitor 20 is disposed on the sidewall of the drain region 113.
  • the capacitor 20 surrounds the sidewall of the end of the drain region 113 away from the channel region 112. That is, the capacitor 20 is set on the side walls around the drain region 113 .
  • the capacitor 20 may be disposed on sidewalls on opposite sides of the drain region 113 .
  • the capacitor 20 may include a first electrode plate 21 and a second electrode plate 22.
  • the dielectric layer 23 between the two electrode plates 22, the drain region 113 is connected to the first electrode plate 21;
  • the first electrode plate 21 can be an internal electrode plate, and the second electrode plate can be is the external electrode plate.
  • the second electrode plates 22 of the plurality of capacitors 20 arranged along the third direction may be connected together, but the first electrode plates 21 thereof are separated.
  • Two adjacent memory cells 1 along the second direction are distributed in a mirror image, and the source regions 111 of the transistors 10 of the two adjacent memory cells 1 are connected to a common bit line 300 .
  • Every two adjacent memory units along the second direction are collectively regarded as a repeating unit.
  • each repeating unit contains two structurally mirror-symmetric memory units;
  • two transistors are arranged adjacently, and capacitors located on a semiconductor layer are located at both ends.
  • a bit line 300 distributed along the vertical substrate direction is arranged between the two adjacent transistors.
  • the transistors and capacitors are mirror-symmetrically distributed about the bit line 300 .
  • the storage area B may be provided with one or more memory cell columns 200 in the third direction; when the storage area B is provided with one memory cell column 200 in the third direction, each of the word lines 400 is formed along the third direction.
  • the gate electrodes 12 of the transistors 10 of a memory cell 1 in each layer of a memory cell column 200 arranged in three directions are formed by connecting; or when the peripheral circuit area A is provided with multiple memory cell columns 200 in a third direction, Each word line 400 is formed by connecting together the gate electrodes 12 of the transistors 10 of a plurality of memory cells 1 arranged along the third direction and located in the same layer.
  • the "first direction” is defined as the direction perpendicular to the plane where the substrate is located, that is, the direction in which the height of the semiconductor device is located; the second direction and the third direction are perpendicular and The formed plane is parallel to the main plane of the substrate, the “second direction” may be the direction of the width of the substrate, and the “third direction” may be the direction of the length of the substrate.
  • the “first direction”, “second direction” and “third direction” may be as shown in Figure 1A.
  • the second direction and the third direction may be perpendicular to each other.
  • each memory cell column is formed by a plurality of memory cells stacked on one side of the substrate along the first direction.
  • This application treats one or more memory cells belonging to the same layer as a group. Groups of memory cells are stacked in a direction perpendicular to the substrate, and memory cell groups of different stacks form columns extending along the direction perpendicular to the substrate.
  • the plurality of groups form an array, that is to say, the memory unit groups of each layer form an array, or multiple columns formed by multiple stacked memory unit groups form an array. It can also be expressed as: multiple memory cell columns are arranged along the second direction and the third direction to form an array.
  • the semiconductor device of the embodiment of the present application adopts a lateral transistor semiconductor layer (that is, a transistor semiconductor layer extending along the second direction) and a lateral capacitor (that is, the capacitor is arranged between the transistor semiconductor layers instead of being arranged on the left and right sides of the transistor).
  • a lateral transistor semiconductor layer that is, a transistor semiconductor layer extending along the second direction
  • a lateral capacitor that is, the capacitor is arranged between the transistor semiconductor layers instead of being arranged on the left and right sides of the transistor.
  • the sources of the transistors of multiple memory cells in two adjacent memory cell columns in the second direction can share a bit line, which can also increase the storage density of the semiconductor device.
  • a memory unit column may include 2 to 100 memory units.
  • it may include 2, 3 (as shown in Figure 1A and Figure 2A), 4, 5, 10, 13, 15, 18, 20, 30, 40, 50, 60, 70, 80, 90, 100 storage units.
  • the storage area B may be provided with 2 to 1000 storage unit columns along the second direction, for example, 2, 4 (as shown in Figure 1A and Figure 2A), 6, 8, 10, 12, 14, 16, 18, 20, 30, 40, 50, 60, 70, 80, 90, 100, 200 , 300, 400, 500, 600, 700, 800, 900, 1000 storage unit columns; the storage area B can be provided with 1 to 100 storage unit columns along the third direction, for example , can be set to 1, 2, 3 (as shown in Figure 1B), 4, 5, 12, 14, 16, 18, 20, 30, 40, 50, 60, 70, 80, 90, 100 storage unit columns.
  • the substrate may be a semiconductor substrate, for example, a single crystal silicon substrate, or a semiconductor on insulator (SOI) substrate, for example, silicon on sapphire (Silicon on Sapphire).
  • SOI semiconductor on insulator
  • SOS silicon on sapphire
  • SOG Silicon On Glass
  • silicon epitaxial layer or other semiconductor or optoelectronic material based on the base semiconductor such as silicon-germanium (Si 1-x Ge x , where x may be, for example, a mole fraction between 0.2 and 0.8), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN) or indium phosphide (InP).
  • the substrate may be doped or may be undoped.
  • the plurality of word lines spaced apart along the first direction may have different lengths and form a staircase shape. That is, the plurality of word lines spaced apart along the first direction and located at different layers may form a staircase shape.
  • FIG. 3 is a distribution state diagram in the side view direction of a plurality of word lines arranged at intervals along the first direction of the semiconductor device according to an exemplary embodiment of the present application.
  • the plurality of word lines 400 spaced apart along the first direction have different extending lengths in the third direction, so that the plurality of word lines 400 arranged along the first direction and located at different layers can present a ladder shape.
  • the material of the word line may be a material compatible with the semiconductor layer.
  • the material of the word line may include at least one element of indium and tin.
  • the material of the word line may be indium oxide. Tin (Indium tin oxide, ITO), etc.
  • the material of the bit line may be selected from any one or more of tungsten, Mo, Co and other metal materials with similar properties.
  • the material of the semiconductor layer may be a metal oxide semiconductor material, and the metal in the metal oxide semiconductor material is selected from any of indium zinc, tungsten, tin, titanium, zirconium, hafnium and gallium.
  • the semiconductor layer may be selected from the group consisting of indium gallium zinc oxide (IGZO), zinc stannate (ZTO), and indium zinc oxide (IZO).
  • the height of the semiconductor layer along the first direction can be set according to actual electrical requirements, for example, it can be 10 nm to 50 nm.
  • one transistor 10 can correspond to one capacitor 20 , that is, the memory unit 1 can have a 1T1C structure.
  • two capacitors adjacent along the first direction may share an outer electrode plate.
  • the materials of the first electrode plate and the second electrode plate can be independently selected from titanium nitride (TiN), titanium aluminum (TiAl), tantalum nitride (TaN), etc., which have similar properties. Any one or more types of other metallic materials.
  • the thickness of the first electrode plate may be 5 nm to 15 nm, and the thickness of the second electrode plate may be 5 nm to 15 nm.
  • the material of the dielectric layer may be a high dielectric constant (K) material, for example, it may be selected from hafnium dioxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), and zirconium oxide. Any one or more of (ZrO) and strontium titanate (SrTiO 3 , STO).
  • K dielectric constant
  • the thickness of the dielectric layer may be 5 nm to 15 nm.
  • the memory cell column 200 may further include an interlayer isolation layer 2 , and the interlayer isolation layer 2 is disposed adjacent to the memory cell column 200 . Between the gate electrodes 12 of the transistors 10 of the two memory cells 1, the gate electrodes 12 of the transistors 10 of the two adjacent memory cells 1 are isolated.
  • the material of the interlayer isolation layer may be silicon oxide, for example, SiO 2 .
  • the semiconductor device may further include one or more memory cell isolation pillars 3 extending along the first direction.
  • one memory cell isolation column 3 may be provided every two memory cell columns 200 in the second direction.
  • the material of the memory cell isolation pillar may be silicon oxide, for example, it may be selected from spin-on deposition (SOD) silicon oxide film, high density plasma (HDP) ) silicon oxide film and high aspect ratio process (High Aspect Ratio Process, HARP) silicon oxide film any one or more.
  • SOD spin-on deposition
  • HDP high density plasma
  • HARP High Aspect Ratio Process
  • the transistor may further include a gate dielectric layer (also called a gate insulating layer, not shown in the figure).
  • the gate dielectric layer is disposed between the channel region and the gate. between extremes.
  • the material of the gate dielectric layer may be selected from any one or more of silicon dioxide, HfO 2 , ZrO, and Al 2 O 3 .
  • the thickness of the gate dielectric layer can be set according to actual electrical requirements, for example, it can be 2 nm to 5 nm.
  • the material of the gate may be selected from any one or more of ITO or other low-temperature semiconductor materials.
  • the semiconductor device may further include an internal support layer 4 , the internal support layer 4 being disposed between two adjacent semiconductor layers 11 along the first direction. , configured to provide support for the semiconductor layer 11 .
  • the internal support layer 4 may also be located on both sides of the bit line 300 , or as shown in FIGS. 1A and 2A , it may be located on the bit line 300 on both sides and on the side walls of the storage unit isolation layer 3.
  • internal support layers 4 are provided on both sides of the bit line 300 and the sidewalls of the memory cell isolation layer 3 , stronger support can be provided for the semiconductor layer 11 .
  • the material of the internal support layer may be a thin film material with a supporting function, for example, it may be silicon nitride (SiN).
  • FIG. 4A is a schematic front cross-sectional view of the storage area of the semiconductor device according to another exemplary embodiment of the present application
  • FIG. 4B is a schematic top view of the storage area of the semiconductor device shown in FIG. 4A
  • the empty space between the semiconductor layer, the bit line and the word line may be filled with isolation material 5 .
  • the isolation material may be selected from any one or more of SOD silicon oxide film, HDP silicon oxide film and HARP silicon oxide film.
  • the peripheral circuit may be a CMOS transistor.
  • FIG. 5A is a schematic front cross-sectional structural view of the peripheral circuit area of the semiconductor device according to an exemplary embodiment of the present application
  • FIG. 5B is a schematic top view structural view of the peripheral circuit area of the semiconductor device shown in FIG. 5A .
  • FIG. 1A and FIG. 1A are schematic front cross-sectional structural views of the peripheral circuit area of the semiconductor device according to an exemplary embodiment of the present application
  • FIG. 5B is a schematic top view structural view of the peripheral circuit area of the semiconductor device shown in FIG. 5A .
  • the peripheral circuit area A may include a peripheral circuit 500, a metal contact layer 600, a metal interconnect layer 700 and an insulating dielectric layer 800;
  • the peripheral circuit 500 may is a CMOS transistor;
  • the metal contact layer 600 is provided on a side of the peripheral circuit 500 away from the substrate 100 , and the metal interconnect layer 700 is provided on a side of the metal contact layer 600 away from the substrate 100 side, the insulating dielectric layer 800 is disposed on the side of the metal interconnection layer 700 away from the substrate 100;
  • the metal contact layer 600 may include a metal contact pillar 601 and an insulating dielectric, and the metal interconnection layer 700 It may include a metal line 701 and an insulating medium; one end of the metal line 701 is electrically connected to the bit line 300, the word line 400 of the storage area B or the outer electrode plate of the capacitor 20, and the other end of the metal line 701 passes through
  • the metal contact post 601 is electrically connected to the peripheral circuit 500 .
  • the material of the metal line can be selected from any one or more of copper and aluminum, for example, it can be copper; the material of the metal contact post can be selected from any of tungsten and molybdenum. One or more, for example, may be tungsten.
  • the metal wire when the metal wire needs to be electrically connected to the capacitor, this can be achieved by electrically connecting the metal wire to the second electrode plate of the capacitor, such as an external electrode plate.
  • the CMOS transistor may include a first transistor 501 and a second transistor 502 , and the first transistor 501 and the second transistor 502 are arranged side by side on the substrate 100
  • a P-type well (P well) 503 may be disposed between the first transistor 501 and the substrate 100
  • an N-type well (P well) 503 may be disposed between the second transistor 502 and the substrate 100.
  • Type well (N well) 504; the first transistor 501 includes a first source electrode 5011, a first drain electrode 5012, and a first trench disposed between the first source electrode 5011 and the first drain electrode 5012.
  • the channel 5013, the first gate 5014 provided on one side of the first channel 5013, the materials of the first source 5011 and the first drain 5012 may both be N-type semiconductor materials, and the first
  • the material of the channel 5013 may be a P-type semiconductor material; a first gate dielectric layer (or gate insulating layer, as shown in the figure) may also be provided between the first channel 5013 and the first gate 5014. (not shown);
  • the second transistor 502 includes a second source 5021, a second drain 5022, a second channel 5023 disposed between the second source 5021 and the second drain 5022, The materials of the second gate 5024 on one side of the second channel 5023, the second source 5021 and the second drain 5022 may all be P-type semiconductor materials.
  • the material may be an N-type semiconductor material, and a second gate dielectric layer (or gate insulating layer, not shown in the figure) may be disposed between the second channel 5023 and the second gate 5024 .
  • the semiconductor device may be a dynamic random access memory (DRAM).
  • DRAM dynamic random access memory
  • An embodiment of the present application also provides a method for manufacturing a semiconductor device. As described above, the semiconductor device provided by the embodiment of the present application can be obtained by this manufacturing method.
  • FIG. 6 is a process flow diagram of a manufacturing method of a semiconductor device according to an embodiment of the present application. As shown in Figure 6, the manufacturing method may include:
  • S30 Define memory cell areas in multiple composite layers, etch bit line trenches along the first direction, and fill the bit line trenches with isolation material;
  • S40 Remove the sacrificial layer, and the remaining channel layer forms a plurality of semiconductor layers arranged in arrays along the first direction and the third direction and extending along the second direction, and the semiconductor layers extend along the second direction into a strip structure, said The strip structure has sidewalls and two ends, and the sidewalls in the second direction include source regions and drain regions near both ends, and a channel region located between the source region and the drain region;
  • S50 Arrange a gate surrounding the channel region on the sidewall of the channel region of the semiconductor layer to obtain a plurality of transistors formed by the semiconductor layer and the gate; and arrange them in a third direction.
  • S70 Remove the isolation material in the bit line slot, fill the bit line slot with bit line material to form a bit line extending along the first direction, and connect the bit line and a plurality of bit lines in contact with the bit line
  • the source regions of the semiconductor layers are connected so that the source regions of the plurality of semiconductor layers share a bit line to obtain a storage area;
  • S80 Electrically connect the circuits in the storage area and the circuits in the peripheral circuit area.
  • step S30 may include:
  • S31 Define memory cell areas in multiple composite layers, and etch memory cell isolation trenches and bit line trenches at intervals along the first direction;
  • S32 Perform side etching on the portion corresponding to the bit line trench and the sacrificial layer along the second direction to obtain an internal support trench, and fill the internal support layer with the internal support trench;
  • S33 perform side etching along the second direction on the portion corresponding to the memory cell isolation trench and the sacrificial layer to obtain an internal support trench, and fill the internal support layer with the internal support trench;
  • S34 Fill the memory cell isolation trench with a memory cell isolation layer and fill the bit line trench with isolation material.
  • step S30 may include:
  • S31 Define memory cell areas in multiple composite layers, and etch memory cell isolation trenches and bit line trenches at intervals along the first direction;
  • S32 Perform side etching on the portion corresponding to the bit line trench and the sacrificial layer along the second direction to obtain an internal support trench, and fill the internal support layer with the internal support trench;
  • step S30 may include:
  • S31 Define memory cell areas in multiple composite layers, and etch memory cell isolation trenches and bit line trenches at intervals along the first direction;
  • S32 Perform side etching on the portion corresponding to the bit line trench and the sacrificial layer along the second direction to obtain an internal support trench, and fill the internal support layer with the internal support trench;
  • S33 Perform side etching on the portion corresponding to the memory cell isolation trench and the sacrificial layer along the second direction to obtain an internal support trench, and fill the internal support layer with the internal support trench;
  • S34 Fill the memory cell isolation trench with a memory cell isolation layer and fill the bit line trench with isolation material.
  • step S50 may include:
  • S51 Sequentially arrange a gate dielectric layer and a gate electrode surrounding the channel region on the sidewall of the channel region of the semiconductor layer to obtain a plurality of transistors formed by the semiconductor layer and the gate electrode; And, there is one semiconductor layer arranged in the third direction, and the gate electrode on this semiconductor layer is used as a word line; or, there are multiple semiconductor layers arranged in the third direction, and the multiple semiconductor layers arranged in the third direction are The gates on the layers are connected together in the third direction to form word lines;
  • S52 Set multiple word lines spaced apart along the first direction to different lengths, so that the multiple word lines spaced apart along the first direction present a ladder shape;
  • S53 Set an interlayer isolation layer between two adjacent semiconductor layers along the first direction to isolate the gates on the two adjacent semiconductor layers along the first direction.
  • step S50 may include:
  • S51 Sequentially arrange a gate dielectric layer and a gate electrode surrounding the channel region on the sidewall of the channel region of the semiconductor layer to obtain a plurality of transistors formed by the semiconductor layer and the gate electrode; And, there is one semiconductor layer arranged in the third direction, and the gate electrode on this semiconductor layer is used as a word line; or, there are multiple semiconductor layers arranged in the third direction, and the multiple semiconductor layers arranged in the third direction are The gates on the layers are connected together in the third direction to form word lines;
  • step S50 may include:
  • S51 Sequentially arrange a gate dielectric layer and a gate electrode surrounding the channel region on the sidewall of the channel region of the semiconductor layer to obtain a plurality of transistors formed by the semiconductor layer and the gate electrode; And, there is one semiconductor layer arranged in the third direction, and the gate electrode on this semiconductor layer is used as a word line; or, there are multiple semiconductor layers arranged in the third direction, and the multiple semiconductor layers arranged in the third direction are The gates on the layers are connected together in the third direction to form word lines;
  • S52 Set multiple word lines spaced apart along the first direction to different lengths, so that the multiple word lines spaced apart along the first direction present a ladder shape;
  • step S50 may include:
  • S51 Sequentially arrange a gate dielectric layer and a gate electrode surrounding the channel region on the sidewall of the channel region of the semiconductor layer to obtain a plurality of transistors formed by the semiconductor layer and the gate electrode; And, there is one semiconductor layer arranged in the third direction, and the gate electrode on this semiconductor layer is used as a word line; or, there are multiple semiconductor layers arranged in the third direction, and the multiple semiconductor layers arranged in the third direction are The gates on the layers are connected together in the third direction to form word lines;
  • S53 Set an interlayer isolation layer between two adjacent semiconductor layers along the first direction to isolate the gates on the two adjacent semiconductor layers along the first direction;
  • step S50 may include:
  • S51 Sequentially arrange a gate dielectric layer and a gate electrode surrounding the channel region on the sidewall of the channel region of the semiconductor layer to obtain a plurality of transistors formed by the semiconductor layer and the gate electrode; And, there is one semiconductor layer arranged in the third direction, and the gate electrode on this semiconductor layer is used as a word line; or, there are multiple semiconductor layers arranged in the third direction, and the multiple semiconductor layers arranged in the third direction are The gates on the layers are connected together in the third direction to form word lines;
  • S52 Set multiple word lines spaced apart along the first direction to different lengths, so that the multiple word lines spaced apart along the first direction present a ladder shape;
  • S53 An interlayer isolation layer is provided between two adjacent semiconductor layers along the first direction, thereby isolating the gate electrodes on the two adjacent semiconductor layers along the first direction.
  • step S60 may include: sequentially arranging a first electrode plate surrounding the sidewall of the drain region, a dielectric plate on the sidewall of the end of the drain region of the semiconductor layer away from the channel region. The material layer and the second electrode plate are combined to obtain a capacitor surrounding the sidewalls of the drain region.
  • step S70 may include:
  • S71 Remove the isolation material in the bit line slot, fill the bit line slot with bit line material to form a bit line extending along the first direction, and connect the bit line and multiple bit lines in contact with the bit line.
  • the source regions of the semiconductor layers are connected so that the source regions of the plurality of semiconductor layers share a bit line;
  • S72 Fill the empty space between the semiconductor layer, the bit line and the word line with an isolation material to obtain a storage area.
  • step S10 may include: sequentially arranging peripheral circuits, a metal contact layer with metal contact pillars, a metal interconnection layer with metal lines, and an insulating dielectric layer on one side of the substrate. One end of the metal line is electrically connected to the peripheral circuit through the metal contact post to obtain the peripheral circuit area.
  • step S80 may include: electrically connecting an end of the metal line away from the metal contact post to the bit line; step S30 may also include aligning the bit line slot with the metal line. And penetrate the insulating dielectric layer, and the bit line formed in step S70 passes through the insulating dielectric layer;
  • step S80 may include: electrically connecting an end of the metal line away from the metal contact post to the word line; and step S50 may further include opening a through hole aligned with the metal line in the insulating dielectric layer. and make the gate pass through the through hole in the insulating dielectric layer and align with the metal line;
  • step S80 may include electrically connecting an end of the metal wire away from the metal contact post to the capacitor; step S60 may further include aligning the second electrode plate of the capacitor with the metal wire.
  • step S80 may include: electrically connecting one end of the metal wire away from the metal contact post to the second electrode plate of the capacitor. ;, Step S60 also includes aligning the second electrode plate of the capacitor with the metal line.
  • the metal line may be selectively electrically connected to a bit line, a word line, or a capacitor (eg, a second electrode plate of the capacitor) as needed.
  • FIG. 7A is a schematic front cross-sectional structural view of an intermediate product obtained in an intermediate step of the manufacturing method of a semiconductor device according to an exemplary embodiment of the present application
  • FIG. 7B is a schematic top structural view of the intermediate product shown in FIG. 7A
  • FIG. 8A is an example of the present application.
  • 8B is a schematic top view structural view of the intermediate product shown in FIG. 8A
  • FIG. 9A is a semiconductor device according to an exemplary embodiment of the present application.
  • Figure 9B is a schematic top structural view of the intermediate product shown in Figure 9A
  • Figure 10A is an intermediate step of the manufacturing method of a semiconductor device according to an exemplary embodiment of the present application.
  • FIGS. 7A to 11B A schematic front cross-sectional structural view of the obtained intermediate product;
  • Figure 10B is a schematic top structural view of the intermediate product shown in Figure 10A;
  • Figure 11A is a main view of the intermediate product obtained in the intermediate steps of the manufacturing method of the semiconductor device according to the exemplary embodiment of the present application.
  • Figure 11B is a schematic top structural view of the intermediate product shown in Figure 11A.
  • the manufacturing method of the semiconductor device may include:
  • S31 Define the memory cell area 1' in the multiple composite layers, and etch the memory cell isolation trench 3' and the bit line trench 300' at intervals along the first direction;
  • S32 Perform side etching on the portion corresponding to the bit line trench 300' and the sacrificial layer 900 along the second direction to obtain an internal support trench 4', and fill the internal support layer 4 in the internal support trench 4'. ;
  • S33 Perform side etching on the portion corresponding to the memory cell isolation trench 3' and the sacrificial layer 900 along the second direction to obtain an internal support trench 4', and fill the internal support layer in the internal support trench 4'. 4;
  • S40 Remove the sacrificial layer 900, and the remaining channel layer 11' forms a plurality of semiconductor layers 11 arranged in arrays along the first direction and the third direction and extending along the second direction.
  • the semiconductor layers 11 extend into strips along the second direction.
  • the strip-shaped structure has sidewalls and two ends, and the sidewalls in the second direction include a source region 111 and a drain region 113 near both ends, and located in the source region 111 and the drain region. Channel area 112 between areas 113, to obtain the intermediate product as shown in Figure 9A and Figure 9B;
  • S51 Arrange a gate dielectric layer (not shown in the figure) and a gate electrode 12 surrounding the channel region 112 in sequence on the sidewalls of the channel region 112 of the semiconductor layer 11 to obtain a plurality of semiconductor layers. 11 and the transistor 10 formed by the gate electrode 12; and, if there is one semiconductor layer 11 arranged in the third direction, use the gate electrode 12 on this semiconductor layer 11 as the word line 400; or, if there is one semiconductor layer 11 arranged in the third direction, There are multiple semiconductor layers 11 arranged, and the gate electrodes 12 on the multiple semiconductor layers 11 arranged in the third direction are connected together in the third direction to form a word line 400;
  • S52 Set the plurality of word lines 400 spaced apart along the first direction to different lengths, so that the plurality of word lines 400 spaced apart along the first direction present a ladder shape;
  • S71 Remove the isolation material in the bit line trench 300', fill the bit line trench 300' with bit line material to form a bit line 300 extending along the first direction, and connect the bit line 300 and the bit line 300 with the bit line material.
  • the source regions 111 of the plurality of semiconductor layers 11 in contact with the line 300 are connected, so that the source regions 111 of the plurality of semiconductor layers 11 share the one bit line 300, as shown in FIGS. 1A to 2A storage area;
  • S80 Electrically connect the circuit in the storage area and the circuit in the peripheral circuit area to obtain the semiconductor device as shown in Figure 1A and Figure 1B.
  • the peripheral circuit in step S10, can be formed through a traditional CMOS process, and then a metal contact layer, a metal interconnection layer and an insulating dielectric layer are formed on the peripheral circuit.
  • the metal contact layer may be formed of a metal contact post and an insulating medium. A whole layer of insulating dielectric may be provided first, and then through holes are opened in the insulating medium and filled with metal to form the metal contact post.
  • the metal interconnection layer may be formed of a metal line and an insulating medium. A whole layer of insulating medium may be provided first, and then through holes are opened in the insulating medium and filled with metal to form the metal line.
  • the insulating dielectric layer can be formed using an atomic layer deposition (ALD) process.
  • ALD atomic layer deposition
  • step S20 may include using an ALD process to set the sacrificial layer and the channel layer.
  • the material of the sacrificial layer may be selected from any one or more of other conductive materials with similar properties such as aluminum-doped zinc oxide (AZO).
  • the thickness of the sacrificial layer may be 30 nm to 50 nm, for example, it may be 30 nm, 35 nm, 40 nm, 45 nm, or 50 nm.
  • the same layer of patterned photo mask can be used to perform patterning and etching through light exposure to form trenches arranged along the third direction and extending along the second direction to combine multiple sacrifices.
  • the layer/channel layer forms isolation in the third direction to obtain the memory cell area.
  • step S32 or S33 the side of the bit line trench or the memory cell isolation trench corresponding to the sacrificial layer may be etched by wet etching.
  • the internal support layer can be filled in the internal support layer groove through the ALD process.
  • SiN can be filled in the internal support layer groove through the ALD process to form an internal support. layer.
  • the memory cell isolation pillars can be filled in the memory cell isolation trenches and the bit line trenches can be filled with isolation materials through SOD, HDP or HARP processes.
  • SOD, HDP or HARP processes can be used.
  • the HARP process forms a silicon oxide film in the memory cell isolation trench and the bit line trench.
  • the sacrificial layer in step S40, can be etched away while retaining the channel layer by selecting an ultra-high sacrificial layer/channel layer etching ratio.
  • the etching method can be dry etching. etching or wet etching.
  • a staircase word line (staircase WL) can be obtained by trim etch.
  • the interlayer isolation layer in step S53, can be set through ALD or chemical vapor deposition (Chemical Vapor Deposition, CVD) process.
  • ALD Physical Vapor Deposition
  • CVD chemical Vapor Deposition
  • SiO 2 can be filled through ALD or CVD process to form the interlayer isolation layer.
  • the isolation material in step S72, can be filled in the blank space through SOD, HDP or HARP process.
  • an SOD silicon oxide film and an HDP silicon oxide film can be formed in the blank space through SOD, HDP or HARP process. and any one or more of HARP silicon oxide films.
  • An embodiment of the present application also provides an electronic device, including the semiconductor device provided in the above embodiment of the present application.
  • the electronic device may include a storage device, a smart phone, a computer, a tablet, an artificial intelligence device, a wearable device, or a mobile power supply.

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Abstract

一种半导体器件及其制造方法电子设备，半导体器件包括衬底（100）、依次层叠设置在衬底（100）一侧的外围电路区（A）和存储区（B），外围电路区（A）的电路和存储区（B）的电路电连接；外围电路区（A）包括外围电路（500），存储区（B）包括：沿垂直于衬底（100）的第一方向延伸的多个存储单元列（200），每个存储单元列（200）均包括沿第一方向堆叠设置的多个存储单元（1），不同的存储单元列（200）在衬底（100）上沿第二方向和第三方向排列形成阵列，第二方向和第三方向交叉并且构成的平面与衬底（100）平行；存储单元包（1）括晶体管（10）和电容器（20），晶体管（10）包括沿第二方向延伸为条状结构的半导体层（11）和栅极（12），半导体层（11）的侧壁依次包括源极区（111）、沟道区（112）和漏极区（113），栅极（12）环绕在沟道区（112）的侧壁；电容器（20）设置在漏极区（113）的侧壁上。

Description

半导体器件及其制造方法、电子设备
本申请要求于2022年05月17日提交中国专利局、申请号为202210540732.4、发明名称为“一种半导体器件结构及其制造方法、DRAM和电子设备”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本申请涉及但不限于半导体器件领域，尤指一种半导体器件及其制造方法、电子设备。
背景技术
动态随机存取存储器(Dynamic Random Access Memory,DRAM)是一种常见的系统内存，它将数据存储在具有电容器和阵列晶体管的存储单元中。电容器可以被设置到充电状态或放电状态，采取这两种状态来表示“0”和“1”。DRAM还包括外围晶体管，以形成外围电路。外围电路和阵列晶体管操纵数据输入/输出(I/O)以及存储单元操作(例如，写或读)。
随着DRAM技术朝向更高密度和高容量发展，现在世界前三大DRAM公司正在进入1a技术节点，其栅极长度已经到达15nm(和逻辑的7nm接近)，较难再进一步微缩。而且电容器的数量提高、尺寸下降，导致电容器的制造需要更长的工艺时间以及更复杂的工艺流程。
发明概述
以下是对本文详细描述的主题的概述。本概述并非是为了限制本申请的保护范围。
本申请实施例提供了一种半导体器件，包括：衬底、依次层叠设置在所述衬底一侧的外围电路区和存储区，所述外围电路区的电路和所述存储区的电路电连接；所述外围电路区包括外围电路；所述存储区包括：
沿垂直于所述衬底的第一方向延伸的多个存储单元列，每个所述存储单元列均包括沿第一方向堆叠设置在所述衬底一侧的多个存储单元，不同的所述存储单元列在所述衬底上沿第二方向和第三方向排列形成阵列，所述第二方向和所述第三方向交叉并且构成的平面与所述衬底平行；
所述存储单元包括沿着所述第二方向依次设置的晶体管和电容器，所述晶体管包括半导体层和栅极，所述半导体层沿第二方向延伸为条状结构，所述条状结构具有侧壁和两端，并且在第二方向上的侧壁包括源极区、沟道区和漏极区，所述源极区和所述漏极区分别靠近所述半导体柱层的两端，所述沟道区位于所述源极区和所述漏极区之间，所述栅极环绕在所述沟道区的侧壁；
所述电容器设置在所述漏极区的侧壁上。
在本申请实施例中，所述存储区还可以包括：多条沿第一方向延伸且在第二方向上间隔排列的位线，沿第二方向上相邻的两个存储单元呈镜像分布，所述相邻的两个存储单元的晶体管的源极区与一条共用的位线连接。
在本申请实施例中，所述存储区还可以包括：多条沿第三方向延伸且在第一方向上间隔排列的字线，其中，所述存储区在第三方向上设置有一个存储单元列，每条所述字线由沿第三方向排列的一个存储单元列的一个存储单元的晶体管的栅极形成；或者，所述存储区在第三方向上设置有多个存储单元列，每条所述字线由沿第三方向排列的多个存储单元的晶体管的栅极连接在一起形成。
在本申请实施例中，所述电容器可以环绕在所述漏极区的侧壁上。
在本申请实施例中，沿第一方向间隔排列的多条字线的长度可以不同，形成阶梯状。
在本申请实施例中，所述字线的材料可以包含铟和锡中至少一种元素。
在本申请实施例中，所述半导体层的材料可以为金属氧化物半导体材料，所述金属氧化物半导体材料中的金属选自铟锌、钨、锡、钛、锆、铪和镓中的任意一种或多种。
在本申请实施例中，所述电容器可以包括第一电极板、第二电极板、设 置在所述第一电极板和所述第二电极板之间的介电质层，所述漏极区与所述第一电极板相连接。
在本申请实施例中，所述存储单元列还可以包括层间隔离层，所述层间隔离层设置在所述存储单元列中相邻的两个存储单元的晶体管的栅极之间，将相邻的两个存储单元的晶体管的栅极隔离开。
在本申请实施例中，所述半导体器件还可以包括一个或多个沿第一方向延伸的存储单元隔离柱。在第二方向上每间隔两个存储单元列可以设置有一个所述存储单元隔离柱。
在本申请实施例中，所述半导体器件还可以包括内部支撑层，所述内部支撑层可以设置在沿第一方向相邻的两个半导体层之间，配置为对所述半导体层提供支撑。
在本申请实施例中，所述内部支撑层可以位于所述位线两侧，或者可以位于所述位线两侧和所述存储单元隔离柱的侧壁上。
在本申请实施例中，所述外围电路可以为互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)晶体管，所述外围电路区还可以包括金属接触层、金属互连层和绝缘介质层；所述外围电路设置在所述衬底一侧，所述金属接触层设置在所述外围电路远离所述衬底的一侧，所述金属接触层中设置有金属接触柱，所述金属互连层设置在所述金属接触层远离所述衬底的一侧，所述金属互连层中设置有金属线，所述绝缘介质层设置在所述金属互连层远离所述衬底的一侧；所述存储单元列设置在所述绝缘介质层远离所述衬底的一侧；所述金属线的一端与所述存储区的位线、字线或电容器电连接，所述金属线的另一端通过所述金属接触柱与所述外围电路电连接。
本申请实施例还提供了一种半导体器件的制造方法，包括：
在衬底一侧设置外围电路，形成外围电路区；
在所述外围电路区远离所述衬底的一侧按照牺牲层和沟道层交错的顺序沿第一方向堆叠设置多个由所述牺牲层和所述沟道层组成的复合层；
在多个所述复合层中定义出存储单元区，并沿第一方向刻蚀出位线槽， 以及在所述位线槽中填充隔离材料；
去除牺牲层，剩余的沟道层形成多条沿第一方向和第三方向阵列排列并且沿第二方向延伸的半导体层，所述半导体层沿第二方向延伸为条状结构，所述条状结构具有侧壁和两端，并且在第二方向上的侧壁包括靠近两端的源极区和漏极区、位于所述源极区和所述漏极区之间的沟道区；
在所述半导体层的沟道区的侧壁上设置环绕所述沟道区的栅极，得到多个由所述半导体层和所述栅极形成的晶体管；以及，在第三方向上排列的半导体层有一条，将这一条半导体层上的栅极作为字线；或者，在第三方向上排列的半导体层有多条，将在第三方向上排列的多条半导体层上的栅极在第三方向上连接在一起形成字线；
在所述半导体层的漏极区的侧壁上设置电容器；
去除所述位线槽中的隔离材料，在所述位线槽中填充位线材料，形成沿第一方向延伸的位线，将所述位线和与该位线相接触的多条半导体层的所述源极区连接，使得所述多条半导体层的所述源极区共用一条位线，得到存储区；
将所述存储区的电路和所述外围电路区的电路电连接。
在本申请实施例中，所述在多个所述复合层中定义出存储单元区，并沿第一方向刻蚀出位线槽，以及在所述位线槽中填充隔离材料可以包括：
在多个所述复合层中定义出存储单元区，并沿第一方向间隔刻蚀出存储单元隔离槽和位线槽；
沿第二方向对所述位线槽与所述牺牲层对应的部分进行侧边刻蚀，得到内部支撑槽，在所述内部支撑槽中填充内部支撑层；
在所述存储单元隔离槽中填充存储单元隔离柱和在所述位线槽中填充隔离材料。
在本申请实施例中，所述在多个所述复合层中定义出存储单元区，并沿第一方向刻蚀出位线槽，以及在所述位线槽中填充隔离材料还可以包括：
沿第二方向对所述存储单元隔离槽与所述牺牲层对应的部分进行侧边刻蚀，得到内部支撑槽，在所述内部支撑槽中填充内部支撑层。
在本申请实施例中，所述牺牲层的材料可以为掺铝氧化锌。
在本申请实施例中，所述在所述半导体层的沟道区的侧壁上设置环绕所述沟道区的栅极，得到多个由所述半导体层和所述栅极形成的晶体管；以及，在第三方向上排列的半导体层有一条，使这一条半导体层上的栅极作为字线；或者，在第三方向上排列的半导体层有多条，使在第三方向上排列的多条半导体层上的栅极在第三方向上连接在一起形成字线可以包括：
在所述半导体层的沟道区的侧壁上依次设置环绕所述沟道区的栅极介电层和栅极，得到多个由所述半导体层和所述栅极形成的晶体管；以及，在第三方向上排列的半导体层有一条，将这一条半导体层上的栅极作为字线；或者，在第三方向上排列的半导体层有多条，将在第三方向上排列的多条半导体层上的栅极在第三方向上连接在一起形成字线；
将沿第一方向间隔排列的多条字线设置为不同的长度，使得沿第一方向间隔排列的多条字线呈现出阶梯状；
在沿第一方向上相邻的两个半导体层之间设置层间隔离层，从而将沿第一方向上相邻的两条半导体层上的栅极隔离开。
在本申请实施例中，所述在所述半导体层的漏极区的侧壁上设置电容器可以包括：
在所述半导体层的漏极区远离所述沟道区一端的侧壁上依次设置环绕所述漏极区侧壁的第一电极板、介电质层和第二电极板，得到环绕所述漏极区侧壁的电容器。
在本申请实施例中，所述在衬底一侧设置外围电路，形成外围电路区可以包括：
在所述衬底一侧依次设置外围电路、带有金属接触柱的金属接触层、带有金属线的金属互连层和绝缘介质层，将所述金属线的一端通过所述金属接触柱与所述外围电路电连接，得到所述外围电路区。
在本申请实施例中，所述将所述存储区的电路和所述外围电路区的电路电连接可以包括：
将所述金属线远离所述金属接触柱的一端与所述位线、所述字线或所述 电容器电连接；
本申请实施例还提供一种电子设备，包括如上本申请实施例提供的所述半导体器件。
在本申请实施例中，所述电子设备可以包括存储装置、智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源。
本申请的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得更加清楚，或者通过实施本申请而了解。本申请的其他优点可通过在说明书以及附图中所描述的方案来实现和获得。
附图概述
附图用来提供对本申请技术方案的理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1A为本申请示例性实施例的半导体器件的主视剖面结构示意图；
图1B为图1A所示的半导体器件的晶体管的俯视结构示意图；
图2A为本申请示例性实施例的半导体器件的存储区的主视剖面结构示意图；
图2B为图1A所示的半导体器件的晶体管的放大图；
图2C为图1A所示的半导体器件的电容器的放大图；
图3为本申请示例性实施例的半导体器件的沿第一方向间隔排列的多条字线在侧视方向上的分布状态图；
图4A为本申请另一示例性实施例的半导体器件的存储区的主视剖面结构示意图；
图4B为图4A所示的半导体器件的存储区俯视结构示意图；
图5A为本申请示例性实施例的半导体器件的外围电路区的主视剖面结构示意图；
图5B为图5A所示的半导体器件的外围电路区的俯视结构示意图；
图6为本申请实施例的半导体器件的制造方法的工艺流程图；
图7A为本申请示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的主视剖面结构示意图；
图7B为图7A所示的中间品的俯视结构示意图；
图8A为本申请示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的主视剖面结构示意图；
图8B为图8A所示的中间品的俯视结构示意图；
图9A为本申请示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的主视剖面结构示意图；
图9B为图9A所示的中间品的俯视结构示意图；
图10A为本申请示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的主视剖面结构示意图；
图10B为图10A所示的中间品的俯视结构示意图；
图11A为本申请示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的主视剖面结构示意图；
图11B为图11A所示的中间品的俯视结构示意图。
附图中的标记符号的含义为：
A-外围电路区；B-存储区；100-衬底；200-存储单元列；300-位线；300’-位线槽；400-字线；500-外围电路；501-第一晶体管；5011-第一源极；5012-第一漏极；5013-第一沟道；5014-第一栅极；502-第二晶体管；5021-第二源极；5022-第二漏极；5023-第二沟道；5024-第二栅极；503-P型阱；504-N型阱；600-金属接触层；601-金属接触柱；700-金属互连层；701-金属线；800-绝缘介质层；900-牺牲层；1-存储单元；1’-存储单元区；10-晶体管；11-半导体层；11’-沟道层；111-源极区；112-沟道区；113-漏极区；12-栅极；20-电容器；21-第一电极板；22-第二电极板；23-介电质层；2-层间隔离层；3-存储单元隔离柱；3’-存储单元隔离槽；4-内部支撑层；4’-内部支撑槽；5-隔离材料。
详述
为使本申请的目的、技术方案和优点更加清楚明白，下文中将结合附图对本申请的实施例进行详细说明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
本文中的实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是实现方式和内容可以在不脱离本申请的宗旨及其范围的条件下被变换为各种各样的形式。因此，本申请不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
本申请中的附图比例可以作为实际工艺中的参考，但不限于此。例如：各个膜层的宽长比、各个膜层的厚度和间距，可以根据实际需要进行调整。本申请中所描述的附图仅是示意图，本申请的一个方式不局限于附图所示的形状或数值等。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“垂直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“设置”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
在本申请的描述中，“第一”、“第二”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“介电质层”换成为“介电质膜”。
本申请实施例提供了一种半导体器件，所述半导体器件包括：衬底、依次层叠设置在所述衬底一侧的外围电路区和存储区，所述外围电路区的电路和所述存储区的电路电连接；所述外围电路区包括外围电路；所述存储区包括：
沿垂直于所述衬底的第一方向延伸的多个存储单元列，每个所述存储单元列均包括沿第一方向堆叠设置在所述衬底一侧的多个存储单元，不同的所述存储单元列在所述衬底上沿第二方向和第三方向排列形成阵列，所述第二方向和所述第三方向交叉并且构成的平面与所述衬底平行；
所述存储单元包括沿着所述第二方向依次设置的晶体管和电容器，所述晶体管包括半导体层和栅极，所述半导体层沿第二方向延伸为条状结构，所述条状结构具有侧壁和两端，并且在第二方向上的侧壁包括源极区、沟道区和漏极区，所述源极区和所述漏极区分别靠近所述半导体柱层的两端，所述沟道区位于所述源极区和所述漏极区之间，所述栅极环绕在所述沟道区的侧壁；
所述电容器设置在所述漏极区的侧壁上。
在本申请实施例中，所述的半导体器件还可以包括：多条沿第一方向延伸且在第二方向上间隔排列的位线，沿第二方向上相邻的两个存储单元呈镜像分布，所述相邻的两个存储单元的晶体管的源极区与一条共用的位线连接。
在本申请实施例中，所述的半导体器件还可以包括：多条沿第三方向延伸且在第一方向上间隔排列的字线，其中，所述存储区在第三方向上设置有一个存储单元列，每条所述字线由沿第三方向排列的一个存储单元列的一个存储单元的晶体管的栅极形成；或者，所述存储区在第三方向上设置有多个存储单元列，每条所述字线由沿第三方向排列的多个存储单元的晶体管的栅极连接在一起形成。
在本申请实施例中，所述电容器可以环绕在所述漏极区的侧壁上。
本申请实施例提供的半导体器件可以应用于DRAM领域，例如，可以应 用于通过超晶格结构形成的具有3D存储单元的DRAM。
例如，衬底上的多层超晶格可以用于形成多层存储单元，每层存储单元可以是阵列分布的存储单元，各层中在二维平面中相同位置的存储单元构成一个垂直方向的一列存储单元，简称存储单元列。
图1A为本申请示例性实施例的半导体器件的主视剖面结构示意图；图1B为图1A所示的半导体器件的晶体管的俯视结构示意图。如图1A和图1B所示，所述半导体器件可以包括：衬底100、外围电路区A和存储区B，所述外围电路区A和所述存储区B依次层叠设置在所述衬底100一侧，所述外围电路区A的电路和所述存储区B的电路并且电连接。
如图1A所示，所述外围电路区A包括设置在所述衬底100上的外围电路500。
图2A为本申请示例性实施例的半导体器件的存储区的主视剖面结构示意图；图2B为图1A所示的半导体器件的晶体管的放大图；图2C为图1A所示的半导体器件的电容器的放大图。如图1A和图2A所示，所述存储区B包括：沿垂直于衬底100的第一方向延伸的多个存储单元列200、多条沿第一方向延伸且在第二方向上间隔排列的位线300(Bit Line,BL)和多条沿第三方向延伸且在第一方向上间隔排列的字线400(Word Line,WL)；在图1A或图2A中，两个存储单元列200共用一条位线300，图1A、图1B或图2A中共有6条位线300；图1A、图1B或图2A为三层超晶格形成的三层存储单元，每层存储单元对应有4条字线400，图1A、图1B或图2A中共有12条字线400。
每个所述存储单元列200均包括沿第一方向堆叠设置在所述衬底100一侧的多个存储单元1，例如，每个所述存储单元列200均由沿第一方向堆叠设置在所述衬底100一侧的多个存储单元1形成；不同的所述存储单元列200在所述衬底100上沿第二方向和第三方向排列形成阵列，所述第二方向和所述第三方向垂直并且构成的平面与所述衬底平行。
每个所述存储单元1包括沿着所述第二方向依次设置的晶体管10和电容器20，所述晶体管10包括半导体层11和栅极12，所述半导体层11沿第二方向延伸为条状结构，所述条状结构具有侧壁和两端，所述条状结构的横截 面可以为矩形、圆形、椭圆形等，并且在第二方向上的侧壁包括源极区111、沟道区112和漏极区113，所述源极区111和所述漏极区113分别靠近所述半导体层11的两端，所述沟道区112位于所述源极区111和所述漏极区113之间，所述栅极12环绕在所述沟道区112的侧壁。
所述电容器20设置在所述漏极区113的侧壁上，例如，可以如图1A所示，所述电容器20环绕在所述漏极区113远离所述沟道区112一端的侧壁，即所述电容器20套设在所述漏极区113四周的侧壁上。在其他实施例中，所述电容器20可以设置在所述漏极区113的相对两侧的侧壁上。
在本申请实施例中，如图1A、图2A和图2C所示，所述电容器20可以包括第一电极板21、第二电极板22、设置在所述第一电极板21和所述第二电极板22之间的介电质层23，所述漏极区113与所述第一电极板21相连接；所述第一电极板21可以为内电极板，所述第二电极板可以为为外电极板。沿第三方向排列的多个电容器20的第二电极板22可以连接在一起，但其第一电极板21是分开的。
沿第二方向上相邻的两个存储单元1呈镜像分布，所述相邻的两个存储单元1的晶体管10的源极区111与一条共用的位线300连接。沿第二方向上每相邻两个存储单元整体作为一个重复单元，第二方向上有2n个存储单元时，有n个重复单元，每个重复单元包含两个结构上镜像对称的存储单元；一个重复单元中，两个晶体管相邻设置，位于一个半导体层上的电容器位于两端，两个相邻设置的晶体管之间设置有沿垂直衬底方向分布的位线300，两个存储单元中的晶体管和电容器关于所述位线300镜像对称分布。
所述存储区B在第三方向上可以设置有一个或多个存储单元列200；当所述存储区B在第三方向上设置有一个存储单元列200时，每条所述字线400由沿第三方向排列的一个存储单元列200的各个层的一个存储单元1的晶体管10的栅极12连接形成；或者，当所述外围电路区A在第三方向上设置有多个存储单元列200时，每条所述字线400由沿第三方向排列的多个存储单元1的位于同一层的晶体管10的栅极12连接在一起形成。
在本申请的描述中，“第一方向”定义为与所述衬底所在的平面垂直的方向，即所述半导体器件的高度所在的方向；所述第二方向和所述第三方向 垂直且构成的平面与所述衬底的主平面平行，“第二方向”可以为所述衬底的宽度所在的方向；“第三方向”可以为所述衬底的长度所在的方向。“第一方向”、“第二方向”和“第三方向”可以如图1A所示。示例性地，所述第二方向与所述第三方向可以相互垂直。
在本申请的描述中，每个存储单元列均由沿第一方向堆叠设置在衬底一侧的多个存储单元形成，本申请将属于同一层的一个或多个存储单元作为一个组，该组存储单元在垂直衬底的方向叠层设置，不同叠层的存储单元组构成沿着垂直衬底方向延伸的列。
所述的多个组构成一个阵列，也就是说每个层的存储单元组构成一个阵列，或多个叠层的存储单元组形成的多列构成一个阵列。还可以表述为：多个存储单元列沿第二方向和第三方向排列形成阵列。
本申请实施例的半导体器件，通过采用横向晶体管半导体层(即沿第二方向延伸的晶体管半导体层)和横向电容器(即将电容器设置在晶体管半导体层之间，而不是设置在晶体管左右两侧)，使得晶体管和电容器可以形成立体堆叠结构，并且由晶体管和电容器形成的存储单元可以堆叠在一起，增加了半导体器件的存储密度；而且，采用CuA(CMOS under Array)结构将外围电路设置在存储单元列下方，也可以减小半导体器件的尺寸，从而增加半导体器件的存储密度，从而减少单位Gb的制作成本，为DRAM微缩瓶颈下，提供了一种新的技术研发方向。
另外，本申请实施例的半导体器件在第二方向上相邻的两个存储单元列的多个存储单元的晶体管的源极可以共用一条位线，也可以增加半导体器件的存储密度。
在本申请实施例中，一个存储单元列可以包括2个至100个存储单元，例如，可以包括2个、3个(如图1A和图2A所示)、4个、5个、10个、13个、15个、18个、20个、30个、40个、50个、60个、70个、80个、90个、100个存储单元。
在本申请实施例中，所述存储区B沿第二方向上可以设置有2个至1000个存储单元列，例如，可以设置有2个、4个(如图1A和图2A所示)、6个、8个、10个、12个、14个、16个、18个、20个、30个、40个、50个、 60个、70个、80个、90个、100个、200个、300个、400个、500个、600个、700个、800个、900个、1000个存储单元列；所述存储区B沿第三方向上可以设置有1个至100个存储单元列，例如，可以设置有1个、2个、3个(如图1B所示)、4个、5个、12个、14个、16个、18个、20个、30个、40个、50个、60个、70个、80个、90个、100个存储单元列。
在本申请实施例中，所述衬底可以为半导体衬底，例如，可以为单晶硅衬底，还可以为绝缘体上半导体(Semiconductor on Insulator,SOI)衬底，例如，蓝宝石上硅(Silicon On Sapphire,SOS)衬底、玻璃上硅(Silicon On Glass,SOG)衬底，基底半导体基础上的硅的外延层或其它半导体或光电材料，例如硅-锗(Si 1-xGe x，其中x可以是例如0.2与0.8之间的摩尔分数)、锗(Ge)、砷化镓(GaAs)、氮化镓(GaN)或磷化铟(InP)。所述衬底可经掺杂或可未经掺杂。
在本申请实施例中，沿第一方向间隔排列的多条字线的长度可以不同，形成阶梯状，即沿第一方向间隔排列的位于不同层的多条字线形成阶梯状。
图3为本申请示例性实施例的半导体器件的沿第一方向间隔排列的多条字线在侧视方向上的分布状态图。如图3所示，沿第一方向间隔排列的多条字线400在第三方向上的延伸长度不同，使得沿第一方向排列的位于不同层的多条字线400可以呈现出阶梯状。
在本申请实施例中，所述字线的材料可以为与所述半导体层兼容的材料，例如，所述字线的材料可以包含铟和锡中至少一种元素，还例如，可以为氧化铟锡(Indium tin oxide,ITO)等。
在本申请实施例中，所述位线的材料可以选自钨、Mo、Co等具有相似性质的其他金属材料中的任意一种或多种。
在本申请实施例中，所述半导体层的材料可以为金属氧化物半导体材料，所述金属氧化物半导体材料中的金属选自铟锌、钨、锡、钛、锆、铪和镓中的任意一种或多种，又例如，所述半导体层的材料可以选自铟镓锌氧化物(Indium Gallium Zinc Oxide,IGZO)、锡酸锌(ZTO)、铟锌氧化物(Indium Zinc Oxide,IZO)、锌氧化物(ZnO x)、铟钨氧化物(InWO)、铟锌锡氧化物(Indium Zinc Tin Oxide,IZTO)、铟氧化物(InO x，例如，In 2O 3)、锡氧 化物(SnO x，例如，SnO 2)、钛氧化物(TiO x)、锌氮氧化物(Zn xO yN z)、镁锌氧化物(Mg xZn yO z)、锆铟锌氧化物(Zr xIn yZn zO a)、铪铟锌氧化物(Hf xIn yZn zO a)、铝锡铟锌氧化物(Al xSn yIn zZn aO d)、硅铟锌氧化物(Si xIn yZn zO a)、铝锌锡氧化物(Al xZn ySn zO a)、镓锌锡氧化物(Ga xZn ySn zO a)、锆锌锡氧化物(Zr xZn ySn zO a)和铟镓硅氧化物(InGaSiO x)中的任意一种或多种。
在本申请实施例中，所述半导体层沿第一方向上的高度可以根据实际的电性需求来设置，例如，可以为10nm至50nm。
在本申请实施例中，如图1A和图2A所示，一个晶体管10可以对应一个电容器20，即所述存储单元1可以为1T1C结构。
在本申请实施例中，沿第一方向相邻的两个电容器可以共用一个外电极板。
在本申请实施例中，所述第一电极板和所述第二电极板的材料可以各自独立地选自氮化钛(TiN)、钛铝(TiAl)、氮化钽(TaN)等具有相似性质的其他金属材料的任意一种或多种。所述第一电极板的厚度可以为5nm至15nm，所述第二电极板的厚度可以为5nm至15nm。
在本申请实施例中，所述介电质层的材料可以为高介电常数(K)材料，例如，可以选自二氧化铪(HfO 2)、氧化铝(Al 2O 3)、氧化锆(ZrO)和钛酸锶(SrTiO 3,STO)中的任意一种或多种。所述介电质层的厚度可以为5nm至15nm。
在本申请实施例中，如图1A和图2A所示，所述存储单元列200还可以包括层间隔离层2，所述层间隔离层2设置在所述存储单元列200中相邻的两个存储单元1的晶体管10的栅极12之间，将相邻的两个存储单元1的晶体管10的栅极12隔离开。
在本申请实施例中，所述层间隔离层的材料可以为氧化硅，例如，可以为SiO 2。
在本申请实施例中，如图1A和图2A所示，所述半导体器件还可以包括一个或多个沿第一方向延伸的存储单元隔离柱3。例如，在第二方向上每间 隔两个存储单元列200可以设置有一个所述存储单元隔离柱3。
在本申请实施例中，所述存储单元隔离柱的材料可以为氧化硅，例如，可以选自旋转涂敷(Spin-On Deposition,SOD)氧化硅薄膜、高密度等离子体(High Density Plasma,HDP)氧化硅薄膜和高深宽比工艺(High Aspect Ratio Process，HARP)氧化硅薄膜中的任意一种或多种。
在本申请实施例中，所述晶体管还可以包括栅极介电层(又叫栅极绝缘层，图中未示)，所述栅极介电层设置在所述沟道区与所述栅极之间。
在本申请实施例中，所述栅极介电层的材料可以选自二氧化硅、HfO 2、ZrO和Al 2O 3中的任意一种或多种。
在本申请实施例中，所述栅极介电层的厚度可以根据实际的电性需求来设置，例如，可以为2nm至5nm。
在本申请实施例中，所述栅极的材料可以选自ITO或其他低温半导体材料中的任意一种或多种。
在本申请实施例中，如图1A和图2A所示，所述半导体器件还可以包括内部支撑层4，所述内部支撑层4设置在沿第一方向相邻的两个半导体层11之间，配置为对所述半导体层11提供支撑。
在本申请实施例中，如图1A和图2A所示，所述内部支撑层4还可以位于所述位线300两侧，或者如图1A和图2A所示，可以位于所述位线300两侧和所述存储单元隔离层3的侧壁上。当所述位线300两侧和所述存储单元隔离层3的侧壁上均设置有内部支撑层4时可以对所述半导体层11提供更牢固的支撑。
在本申请实施例中，所述内部支撑层的材料可以为具有支撑作用的薄膜材料，例如，可以为氮化硅(SiN)。
图4A为本申请另一示例性实施例的半导体器件的存储区的主视剖面示意图；图4B为图4A所示的半导体器件的存储区的俯视示意图。如图4A和图4B所示，在本申请示例性实施例中，所述半导体层、所述位线和所述字线之间的空白空间中可以填充有隔离材料5。
在本申请实施例中，所述隔离材料可以选自SOD氧化硅薄膜、HDP氧 化硅薄膜和HARP氧化硅薄膜中的任意一种或多种。
在本申请实施例中，所述外围电路可以为CMOS晶体管。
图5A为本申请示例性实施例的半导体器件的外围电路区的主视剖面结构示意图；图5B为图5A所示的半导体器件的外围电路区的俯视结构示意图。在本申请实施例中，如图1A和图5A所示，所述外围电路区A可以包括外围电路500、金属接触层600、金属互连层700和绝缘介质层800；所述外围电路500可以为CMOS晶体管；所述金属接触层600设置在所述外围电路500远离所述衬底100的一侧，所述金属互连层700设置在所述金属接触层600远离所述衬底100的一侧，所述绝缘介质层800设置在所述金属互连层700远离所述衬底100的一侧；所述金属接触层600可以包括金属接触柱601和绝缘介质，所述金属互连层700可以包括金属线701和绝缘介质；所述金属线701的一端与所述存储区B的位线300、字线400或电容器20的外电极板电连接，所述金属线701的另一端通过所述金属接触柱601与所述外围电路500电连接。
在本申请实施例中，所述金属线的材料可以选自铜和铝中的任意一种或多种，例如，可以为铜；所述金属接触柱的材料可以选自钨和钼中的任意一种或多种，例如，可以为钨。
在本申请实施例中，当需要所述金属线与所述电容器电连接时，可以通过将所述金属线与所述电容器的第二电极板，例如外电极板电连接来实现。
在本申请实施例中，如图5A所示，所述CMOS晶体管可以包括第一晶体管501和第二晶体管502，所述第一晶体管501和所述第二晶体管502并排设置在所述衬底100一侧，并且所述第一晶体管501与所述衬底100之间还可以设置有P型阱(P well)503，所述第二晶体管502与所述衬底100之间还可以设置有N型阱(N well)504；所述第一晶体管501包括第一源极5011、第一漏极5012、设置在所述第一源极5011和所述第一漏极5012之间的第一沟道5013、设置在所述第一沟道5013一侧的第一栅极5014，所述第一源极5011和所述第一漏极5012的材料可以均为N型半导体材料，所述第一沟道5013的材料可以为P型半导体材料；所述第一沟道5013与所述第一栅极5014之间还可以设置有第一栅极介电层(或叫栅极绝缘层，图中未示)； 所述第二晶体管502包括第二源极5021、第二漏极5022、设置在所述第二源极5021和所述第二漏极5022之间的第二沟道5023、设置在所述第二沟道5023一侧的第二栅极5024，所述第二源极5021和所述第二漏极5022的材料可以均为P型半导体材料，所述第二沟道5023的材料可以为N型半导体材料，所述第二沟道5023与所述第二栅极5024之间还可以设置有第二栅极介电层(或叫栅极绝缘层，图中未示)。
在本申请实施例中，所述半导体器件可以为动态随机存取存储器(DRAM)。
本申请实施例还提供一种半导体器件的制造方法。如上所述本申请实施例提供的半导体器件可以通过该制造方法得到。
图6为本申请实施例的半导体器件的制造方法的工艺流程图。如图6所示，所述制造方法可以包括：
S10：在衬底一侧设置外围电路，形成外围电路区；
S20在所述外围电路区远离所述衬底的一侧按照牺牲层和沟道层交错的顺序沿第一方向堆叠设置多个由所述牺牲层和所述沟道层组成的复合层；
S30：在多个所述复合层中定义出存储单元区，并沿第一方向刻蚀出位线槽，以及在所述位线槽中填充隔离材料；
S40：去除牺牲层，剩余的沟道层形成多条沿第一方向和第三方向阵列排列并且沿第二方向延伸的半导体层，所述半导体层沿第二方向延伸为条状结构，所述条状结构具有侧壁和两端，并且在第二方向上的侧壁包括靠近两端的源极区和漏极区、位于所述源极区和所述漏极区之间的沟道区；
S50：在所述半导体层的沟道区的侧壁上设置环绕所述沟道区的栅极，得到多个由所述半导体层和所述栅极形成的晶体管；以及，在第三方向上排列的半导体层有一条，将这一条半导体层上的栅极作为字线；或者，在第三方向上排列的半导体层有多条，将在第三方向上排列的多条半导体层上的栅极在第三方向上连接在一起形成字线；
S60：在所述半导体层的漏极区的侧壁上设置电容器；
S70：去除所述位线槽中的隔离材料，在所述位线槽中填充位线材料， 形成沿第一方向延伸的位线，将所述位线和与该位线相接触的多条半导体层的所述源极区连接，使得所述多条半导体层的所述源极区共用一条位线，得到存储区；
S80：将所述存储区的电路和所述外围电路区的电路电连接。
在本申请实施例中，步骤S30可以包括：
S31：在多个所述复合层中定义出存储单元区，并沿第一方向间隔刻蚀出存储单元隔离槽和位线槽；
S32：沿第二方向对所述位线槽与所述牺牲层对应的部分进行侧边刻蚀，得到内部支撑槽，在所述内部支撑槽中填充内部支撑层；
任选地，S33：沿第二方向对所述存储单元隔离槽与所述牺牲层对应的部分进行侧边刻蚀，得到内部支撑槽，在所述内部支撑槽中填充内部支撑层；
S34：在所述存储单元隔离槽中填充存储单元隔离层和在所述位线槽中填充隔离材料。
例如，在本申请示例性实施例中，i)步骤S30可以包括：
S31：在多个所述复合层中定义出存储单元区，并沿第一方向间隔刻蚀出存储单元隔离槽和位线槽；
S32：沿第二方向对所述位线槽与所述牺牲层对应的部分进行侧边刻蚀，得到内部支撑槽，在所述内部支撑槽中填充内部支撑层；
S34：在所述存储单元隔离槽中填充存储单元隔离层和在所述位线槽中填充隔离材料；
或者，ii)步骤S30可以包括：
S31：在多个所述复合层中定义出存储单元区，并沿第一方向间隔刻蚀出存储单元隔离槽和位线槽；
S32：沿第二方向对所述位线槽与所述牺牲层对应的部分进行侧边刻蚀，得到内部支撑槽，在所述内部支撑槽中填充内部支撑层；
S33：沿第二方向对所述存储单元隔离槽与所述牺牲层对应的部分进行侧边刻蚀，得到内部支撑槽，在所述内部支撑槽中填充内部支撑层；
S34：在所述存储单元隔离槽中填充存储单元隔离层和在所述位线槽中填充隔离材料。
在本申请实施例中，步骤S50可以包括：
S51：在所述半导体层的沟道区的侧壁上依次设置环绕所述沟道区的栅极介电层和栅极，得到多个由所述半导体层和所述栅极形成的晶体管；以及，在第三方向上排列的半导体层有一条，将这一条半导体层上的栅极作为字线；或者，在第三方向上排列的半导体层有多条，将在第三方向上排列的多条半导体层上的栅极在第三方向上连接在一起形成字线；
任选地，S52：将沿第一方向间隔排列的多条字线设置为不同的长度，使得沿第一方向间隔排列的多条字线呈现出阶梯状；
任选地，S53：在沿第一方向上相邻的两个半导体层之间设置层间隔离层，从而将沿第一方向上相邻的两条半导体层上的栅极隔离开。
例如，在本申请示例性实施例中，i)步骤S50可以包括：
S51：在所述半导体层的沟道区的侧壁上依次设置环绕所述沟道区的栅极介电层和栅极，得到多个由所述半导体层和所述栅极形成的晶体管；以及，在第三方向上排列的半导体层有一条，将这一条半导体层上的栅极作为字线；或者，在第三方向上排列的半导体层有多条，将在第三方向上排列的多条半导体层上的栅极在第三方向上连接在一起形成字线；
或者，ii)步骤S50可以包括：
S51：在所述半导体层的沟道区的侧壁上依次设置环绕所述沟道区的栅极介电层和栅极，得到多个由所述半导体层和所述栅极形成的晶体管；以及，在第三方向上排列的半导体层有一条，将这一条半导体层上的栅极作为字线；或者，在第三方向上排列的半导体层有多条，将在第三方向上排列的多条半导体层上的栅极在第三方向上连接在一起形成字线；
S52：将沿第一方向间隔排列的多条字线设置为不同的长度，使得沿第一方向间隔排列的多条字线呈现出阶梯状；
或者，iii)步骤S50可以包括：
S51：在所述半导体层的沟道区的侧壁上依次设置环绕所述沟道区的栅 极介电层和栅极，得到多个由所述半导体层和所述栅极形成的晶体管；以及，在第三方向上排列的半导体层有一条，将这一条半导体层上的栅极作为字线；或者，在第三方向上排列的半导体层有多条，将在第三方向上排列的多条半导体层上的栅极在第三方向上连接在一起形成字线；
S53：在沿第一方向上相邻的两个半导体层之间设置层间隔离层，从而将沿第一方向上相邻的两条半导体层上的栅极隔离开；
或者，iiii)步骤S50可以包括：
S51：在所述半导体层的沟道区的侧壁上依次设置环绕所述沟道区的栅极介电层和栅极，得到多个由所述半导体层和所述栅极形成的晶体管；以及，在第三方向上排列的半导体层有一条，将这一条半导体层上的栅极作为字线；或者，在第三方向上排列的半导体层有多条，将在第三方向上排列的多条半导体层上的栅极在第三方向上连接在一起形成字线；
S52：将沿第一方向间隔排列的多条字线设置为不同的长度，使得沿第一方向间隔排列的多条字线呈现出阶梯状；
S53：在沿第一方向上相邻的两个半导体层之间设置层间隔离层，从而将沿第一方向上相邻的两条半导体层上的栅极隔离开。
在本申请实施例中，步骤S60可以包括：在所述半导体层的漏极区远离所述沟道区一端的侧壁上依次设置环绕所述漏极区侧壁的第一电极板、介电质层和第二电极板，得到环绕所述漏极区侧壁的电容器。
在本申请实施例中，步骤S70可以包括：
S71：去除所述位线槽中的隔离材料，在所述位线槽中填充位线材料，形成沿第一方向延伸的位线，将所述位线和与该位线相接触的多条半导体层的所述源极区连接，使得所述多条半导体层的所述源极区共用一条位线；
S72：在所述半导体层、所述位线和所述字线之间的空白空间中填充隔离材料，得到存储区。
在本申请实施例中，步骤S10可以包括：在所述衬底一侧依次设置外围电路、带有金属接触柱的金属接触层、带有金属线的金属互连层和绝缘介质层，将所述金属线的一端通过所述金属接触柱与所述外围电路电连接，得到 所述外围电路区。
在本申请实施例中，步骤S80可以包括：将所述金属线远离所述金属接触柱的一端与所述位线电连接；，步骤S30还包括使所述位线槽与所述金属线对齐并贯穿所述绝缘介质层，步骤S70中形成的位线穿过所述绝缘介质层；
或者，步骤S80可以包括：将所述金属线远离所述金属接触柱的一端与所述字线电连接；，步骤S50还包括在所述绝缘介质层中开设与所述金属线对齐的通孔，并使所述栅极穿过所述绝缘介质层中的通孔与所述金属线对齐；
或者，步骤S80可以包括：将所述金属线远离所述金属接触柱的一端与所述电容器电连接；步骤S60还包括使所述电容器的第二电极板与所述金属线对齐。
在本申请实施例中，当需要所述金属线与所述电容器电连接时，步骤S80可以包括：将所述金属线远离所述金属接触柱的一端与所述电容器的第二电极板电连接；，步骤S60还包括使所述电容器的第二电极板与所述金属线对齐。
可以根据需要选择将金属线与位线、字线或电容器(例如，所述电容器的第二电极板)电连接。
图7A为本申请示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的主视剖面结构示意图；图7B为图7A所示的中间品的俯视结构示意图；图8A为本申请示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的主视剖面结构示意图；图8B为图8A所示的中间品的俯视结构示意图；图9A为本申请示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的主视剖面结构示意图；图9B为图9A所示的中间品的俯视结构示意图；图10A为本申请示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的主视剖面结构示意图；图10B为图10A所示的中间品的俯视结构示意图；图11A为本申请示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的主视剖面结构示意图；图11B为图11A所示的中间品的俯视结构示意图。如图7A至图11B所示，在示例性实施例中，所述半导体器件的制造方法可以包括：
S10：在衬底100一侧依次设置外围电路500、带有金属接触柱601的金 属接触层600、带有金属线701的金属互连层700和绝缘介质层800，将所述金属线701的一端通过所述金属接触柱601与所述外围电路500电连接，得到如图5A和图5B所示的外围电路区；
S20：在所述绝缘介质层800远离所述衬底100的一侧按照牺牲层900和沟道层11’交错的顺序沿第一方向堆叠设置多个由牺牲层900和沟道层11’组成的复合层，得到如图7A和图7B所示的中间品；
S31：在所述多个复合层中定义出存储单元区1’，并沿第一方向间隔刻蚀出存储单元隔离槽3’和位线槽300’；
S32：沿第二方向对所述位线槽300’与所述牺牲层900对应的部分进行侧边刻蚀，得到内部支撑槽4’，在所述内部支撑槽4’中填充内部支撑层4；
S33：沿第二方向对所述存储单元隔离槽3’与所述牺牲层900对应的部分进行侧边刻蚀，得到内部支撑槽4’，在所述内部支撑槽4’中填充内部支撑层4；
S34：在所述存储单元隔离槽3’中填充存储单元隔离柱3和在所述位线槽300’中填充隔离材料5，得到如图8A和图8B所示的中间品；
S40：去除牺牲层900，剩余的沟道层11’形成多条沿第一方向和第三方向阵列排列并且沿第二方向延伸的半导体层11，所述半导体层11沿第二方向延伸为条状结构，所述条状结构具有侧壁和两端，并且在第二方向上的侧壁包括靠近两端的源极区111和漏极区113、位于所述源极区111和所述漏极区113之间的沟道区112，得到如图9A和图9B所示的中间品；
S51：在所述半导体层11的沟道区112侧壁上依次设置环绕所述沟道区112的栅极介电层(图中未示)和栅极12，得到多个由所述半导体层11和所述栅极12形成的晶体管10；以及，若在第三方向上排列的半导体层11有一条，将这一条半导体层11上的栅极12作为字线400；或者，若在第三方向上排列的半导体层11有多条，将在第三方向上排列的多条半导体层11上的栅极12在第三方向上连接在一起形成字线400；
S52：将沿第一方向间隔排列的多条字线400设置为不同的长度，使得沿第一方向间隔排列的多条字线400呈现出阶梯状；
S53：在沿第一方向上相邻的两个半导体层11之间设置层间隔离层2，从而将沿第一方向上相邻的两条半导体层11上的栅极12隔离开，得到如图10A和图10B所示的中间品；
S60：在所述半导体层11的漏极区113远离所述沟道区112一端的侧壁上依次设置环绕所述漏极区113侧壁的第一电极板21、介电质层23和第二电极板22，得到环绕所述漏极区113侧壁的电容器20，得到如图11A和图11B所示的中间品；
S71：去除所述位线槽300’中的隔离材料，在所述位线槽300’中填充位线材料，形成沿第一方向延伸的位线300，将所述位线300和与该位线300相接触的多条半导体层11的所述源极区111连接，使得所述多条半导体层11的所述源极区111共用该一条位线300，得到如图1A至图2A所示的存储区；
S72：在所述半导体层11、所述位线和所述字线之间的空白空间中填充隔离材料，得到如图4A和图4B所示的存储区；
S80：将所述存储区的电路和所述外围电路区的电路电连接，得到如图1A和图1B所示的半导体器件。
在本申请实施例中，步骤S10中可以通过传统的CMOS工艺形成所述外围电路，然后在所述外围电路上制作金属接触层、金属互连层和绝缘介质层。所述金属接触层可以由金属接触柱和绝缘介质形成，可以先设置整层的绝缘介质，然后在绝缘介质中开设通孔并填充金属形成所述金属接触柱。所述金属互连层可以由金属线和绝缘介质形成，可以先设置整层的绝缘介质，然后在绝缘介质中开设通孔并填充金属形成所述金属线。所述绝缘介质层可以采用原子层沉积(Atomic layer deposition,ALD)工艺形成。
在本申请实施例中，步骤S20可以包括采用ALD工艺设置牺牲层和沟道层。
在本申请实施例中，所述牺牲层的材料可以选自掺铝氧化锌(Aluminum-doped Zinc Oxide,AZO)等具有相似性质的其他导电材料中的任意一种或多种。所述牺牲层的厚度可以为30nm至50nm，例如，可以为30nm、35nm、40nm、45nm、50nm。
在本申请实施例中，步骤S31中可以利用同一层图案光罩(Photo mask)通过光照曝光进行图案化刻蚀，形成沿第三方向排列并沿第二方向延伸的沟槽从而将多个牺牲层/沟道层在第三方向上形成隔离，得到存储单元区。
在本申请实施例中，步骤S32或S33中，可以通过湿法刻蚀对所述位线槽或所述存储单元隔离槽的与所述牺牲层对应的部分进行侧边刻蚀。
在本申请实施例中，步骤S32或S33中，可以通过ALD工艺在所述内部支撑层槽中填充内部支撑层，例如，可以通过ALD工艺在所述内部支撑层槽中填充SiN，形成内部支撑层。
在本申请实施例中，步骤S34中可以通过SOD、HDP或HARP工艺在所述存储单元隔离槽中填充存储单元隔离柱和在所述位线槽中填充隔离材料，例如，可以通过SOD、HDP或HARP工艺在所述存储单元隔离槽和所述位线槽中形成氧化硅薄膜。
在本申请实施例中，步骤S40中可以通过刻蚀法、选择超高牺牲层/沟道层刻蚀比将牺牲层刻蚀掉而保留沟道层，所述刻蚀法可以为干法刻蚀或湿法刻蚀。
在本申请实施例中，步骤S52中可以通过修整刻蚀(trim etch)得到阶梯状字线(staircase WL)。
在本申请实施例中，步骤S53中可以通过ALD或化学气相沉积(Chemical Vapor Deposition,CVD)工艺设置层间隔离层，例如，可以通过ALD或CVD工艺填充SiO 2，形成层间隔离层。
在本申请实施例中，步骤S72中可以通过SOD、HDP或HARP工艺在空白空间中填充隔离材料，例如，可以通过SOD、HDP或HARP工艺在空白空间中形成SOD氧化硅薄膜、HDP氧化硅薄膜和HARP氧化硅薄膜中的任意一种或多种。
本申请实施例还提供一种电子设备，包括如上本申请实施例提供的所述半导体器件。
在本申请实施例中，所述电子设备可以包括存储装置、智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源。
虽然本申请所揭露的实施方式如上，但所述的内容仅为便于理解本申请而采用的实施方式，并非用以限定本申请。任何本申请所属领域内的技术人员，在不脱离本申请所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本申请的保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (23)

  1. 一种半导体器件，包括：衬底、依次层叠设置在所述衬底一侧的外围电路区和存储区，所述外围电路区的电路和所述存储区的电路电连接；所述外围电路区包括外围电路；所述存储区包括：
    沿垂直于所述衬底的第一方向延伸的多个存储单元列，每个所述存储单元列均包括沿第一方向堆叠设置在所述衬底一侧的多个存储单元，不同的所述存储单元列在所述衬底上沿第二方向和第三方向排列形成阵列，所述第二方向和所述第三方向交叉并且构成的平面与所述衬底平行；
    所述存储单元包括沿着所述第二方向依次设置的晶体管和电容器，所述晶体管包括半导体层和栅极，所述半导体层沿第二方向延伸为条状结构，所述条状结构具有侧壁和两端，并且在第二方向上的侧壁包括源极区、沟道区和漏极区，所述源极区和所述漏极区分别靠近所述半导体柱层的两端，所述沟道区位于所述源极区和所述漏极区之间，所述栅极环绕在所述沟道区的侧壁；
    所述电容器设置在所述漏极区的侧壁上。
  2. 根据权利要求1所述的半导体器件，其中，所述存储区还包括：多条沿第一方向延伸且在第二方向上间隔排列的位线，沿第二方向上相邻的两个存储单元呈镜像分布，所述相邻的两个存储单元的晶体管的源极区与一条共用的位线连接。
  3. 根据权利要求1或2所述的半导体器件，其中，所述存储区还包括：多条沿第三方向延伸且在第一方向上间隔排列的字线，其中，所述存储区在第三方向上设置有一个存储单元列，每条所述字线由沿第三方向排列的一个存储单元列的一个存储单元的晶体管的栅极形成；或者，所述存储区在第三方向上设置有多个存储单元列，每条所述字线由沿第三方向排列的多个存储单元的晶体管的栅极连接在一起形成。
  4. 根据权利要求3所述的半导体器件，其中，所述电容器环绕在所述漏极区的侧壁上。
  5. 根据权利要求3或4所述的半导体器件，其中，沿第一方向间隔排列 的多条字线的长度不同，形成阶梯状。
  6. 根据权利要求3至5中任一项所述的半导体器件，其中，所述字线的材料包含铟和锡中至少一种元素。
  7. 根据权利要求1至4中任一项所述的半导体器件，其中，所述半导体层的材料为金属氧化物半导体材料，所述金属氧化物半导体材料中的金属选自铟锌、钨、锡、钛、锆、铪和镓中的任意一种或多种。
  8. 根据权利要求1至4中任一项所述的半导体器件，其中，所述电容器包括第一电极板、第二电极板、设置在所述第一电极板和所述第二电极板之间的介电质层，所述漏极区与所述第一电极板相连接。
  9. 根据权利要求1至8中任一项所述的半导体器件，其中，所述存储单元列还包括层间隔离层，所述层间隔离层设置在所述存储单元列中相邻的两个存储单元的晶体管的栅极之间，将相邻的两个存储单元的晶体管的栅极隔离开。
  10. 根据权利要求9所述的半导体器件，还包括一个或多个沿第一方向延伸的存储单元隔离柱，在第二方向上每间隔两个存储单元列设置有一个所述存储单元隔离柱。
  11. 根据权利要求2至8中任一项所述的半导体器件，还包括内部支撑层，所述内部支撑层设置在沿第一方向相邻的两个半导体层之间，配置为对所述半导体层提供支撑。
  12. 根据权利要求11所述的半导体器件，其中，所述内部支撑层位于所述位线两侧，或者位于所述位线两侧和所述存储单元隔离柱的侧壁上。
  13. 根据权利要求1至12中任一项所述的半导体器件，其中，所述外围电路为CMOS晶体管，所述外围电路区还包括金属接触层、金属互连层和绝缘介质层；所述外围电路设置在所述衬底一侧，所述金属接触层设置在所述外围电路远离所述衬底的一侧，所述金属接触层中设置有金属接触柱，所述金属互连层设置在所述金属接触层远离所述衬底的一侧，所述金属互连层中设置有金属线，所述绝缘介质层设置在所述金属互连层远离所述衬底的一侧；所述存储单元列设置在所述绝缘介质层远离所述衬底的一侧；所述金属线的 一端与所述存储区的位线、字线或电容器电连接，所述金属线的另一端通过所述金属接触柱与所述外围电路电连接。
  14. 一种半导体器件的制造方法，包括：
    在衬底一侧设置外围电路，形成外围电路区；
    在所述外围电路区远离所述衬底的一侧按照牺牲层和沟道层交错的顺序沿第一方向堆叠设置多个由所述牺牲层和所述沟道层组成的复合层；
    在多个所述复合层中定义出存储单元区，并沿第一方向刻蚀出位线槽，以及在所述位线槽中填充隔离材料；
    去除牺牲层，剩余的沟道层形成多条沿第一方向和第三方向阵列排列并且沿第二方向延伸的半导体层，所述半导体层沿第二方向延伸为条状结构，所述条状结构具有侧壁和两端，并且在第二方向上的侧壁包括靠近两端的源极区和漏极区、位于所述源极区和所述漏极区之间的沟道区；
    在所述半导体层的沟道区的侧壁上设置环绕所述沟道区的栅极，得到多个由所述半导体层和所述栅极形成的晶体管；以及，在第三方向上排列的半导体层有一条，将这一条半导体层上的栅极作为字线；或者，在第三方向上排列的半导体层有多条，将在第三方向上排列的多条半导体层上的栅极在第三方向上连接在一起形成字线；
    在所述半导体层的漏极区的侧壁上设置电容器；
    去除所述位线槽中的隔离材料，在所述位线槽中填充位线材料，形成沿第一方向延伸的位线，将所述位线和与该位线相接触的多条半导体层的所述源极区连接，使得所述多条半导体层的所述源极区共用一条位线，得到存储区；
    将所述存储区的电路和所述外围电路区的电路电连接。
  15. 根据权利要求14所述的制造方法，其中，所述在多个所述复合层中定义出存储单元区，并沿第一方向刻蚀出位线槽，以及在所述位线槽中填充隔离材料，包括：
    在多个所述复合层中定义出存储单元区，并沿第一方向间隔刻蚀出存储单元隔离槽和位线槽；
    沿第二方向对所述位线槽与所述牺牲层对应的部分进行侧边刻蚀，得到内部支撑槽，在所述内部支撑槽中填充内部支撑层；
    在所述存储单元隔离槽中填充存储单元隔离柱和在所述位线槽中填充隔离材料。
  16. 根据权利要求15所述的制造方法，其中，所述在多个所述复合层中定义出存储单元区，并沿第一方向刻蚀出位线槽，以及在所述位线槽中填充隔离材料还包括：
    沿第二方向对所述存储单元隔离槽与所述牺牲层对应的部分进行侧边刻蚀，得到内部支撑槽，在所述内部支撑槽中填充内部支撑层。
  17. 根据权利要求15或16所述的制造方法，其中，所述牺牲层的材料为掺铝氧化锌。
  18. 根据权利要求15所述的制造方法，其中，所述在所述半导体层的沟道区的侧壁上设置环绕所述沟道区的栅极，得到多个由所述半导体层和所述栅极形成的晶体管；以及，在第三方向上排列的半导体层有一条，使这一条半导体层上的栅极作为字线；或者，在第三方向上排列的半导体层有多条，使在第三方向上排列的多条半导体层上的栅极在第三方向上连接在一起形成字线，包括：
    在所述半导体层的沟道区的侧壁上依次设置环绕所述沟道区的栅极介电层和栅极，得到多个由所述半导体层和所述栅极形成的晶体管；以及，在第三方向上排列的半导体层有一条，将这一条半导体层上的栅极作为字线；或者，在第三方向上排列的半导体层有多条，将在第三方向上排列的多条半导体层上的栅极在第三方向上连接在一起形成字线；
    将沿第一方向间隔排列的多条字线设置为不同的长度，使得沿第一方向间隔排列的多条字线呈现出阶梯状；
    在沿第一方向上相邻的两个半导体层之间设置层间隔离层，从而将沿第一方向上相邻的两条半导体层上的栅极隔离开。
  19. 根据权利要求14至18中任一项所述的制造方法，其中，所述在所述半导体层的漏极区的侧壁上设置电容器包括：
    在所述半导体层的漏极区远离所述沟道区一端的侧壁上依次设置环绕所述漏极区侧壁的第一电极板、介电质层和第二电极板，得到环绕所述漏极区侧壁的电容器。
  20. 根据权利要求14至19中任一项所述的制造方法，其中，所述在衬底一侧设置外围电路，形成外围电路区包括：
    在所述衬底一侧依次设置外围电路、带有金属接触柱的金属接触层、带有金属线的金属互连层和绝缘介质层，将所述金属线的一端通过所述金属接触柱与所述外围电路电连接，得到所述外围电路区。
  21. 根据权利要求20所述的制造方法，其中，所述将所述存储区的电路和所述外围电路区的电路电连接包括：
    将所述金属线远离所述金属接触柱的一端与所述位线、所述字线或所述电容器电连接。
  22. 一种电子设备，包括根据权利要求1至13中任一项所述的半导体器件。
  23. 根据权利要求22所述的电子设备，包括存储装置、智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源。
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