WO2024093178A1 - 一种存储器、电子设备 - Google Patents

一种存储器、电子设备 Download PDF

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Publication number
WO2024093178A1
WO2024093178A1 PCT/CN2023/092974 CN2023092974W WO2024093178A1 WO 2024093178 A1 WO2024093178 A1 WO 2024093178A1 CN 2023092974 W CN2023092974 W CN 2023092974W WO 2024093178 A1 WO2024093178 A1 WO 2024093178A1
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Prior art keywords
transistor
channel
gate
conductive layer
substrate
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PCT/CN2023/092974
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English (en)
French (fr)
Inventor
毛淑娟
王桂磊
赵超
戴瑾
项金娟
王祥升
桂文华
于伟
Original Assignee
北京超弦存储器研究院
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Publication of WO2024093178A1 publication Critical patent/WO2024093178A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/10—DRAM devices comprising bipolar components

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of semiconductor technology, and in particular to a memory and an electronic device.
  • DRAM Dynamic Random Access Memory
  • an embodiment of the present disclosure provides a memory comprising at least one memory cell, wherein the memory cell comprises a substrate and a first transistor and a second transistor stacked in sequence in a direction perpendicular to the substrate, wherein the first transistor serves as a read transistor, and the second transistor serves as a write transistor, wherein the first transistor comprises a first channel which is a silicon semiconductor, and the second transistor comprises a second channel which is an oxide semiconductor.
  • the first transistor includes: a first gate, a first channel, a first conductive layer, and a second conductive layer.
  • the first gate is located on the substrate and is in a columnar shape; the first channel is located outside the first gate and is insulated from the first gate; the first conductive layer is located on a side of the first channel close to the substrate, the first conductive layer is connected to the first channel, and the first conductive layer overlaps the first channel in an orthographic projection portion of the substrate; the second conductive layer is located on a side of the first channel away from the substrate and is connected to the first channel.
  • the second transistor includes: a second gate, a second channel, and a third conductive layer.
  • the second gate is located on a side of the first gate away from the substrate, and the second gate is in a columnar shape; the second channel is located outside the second gate and is insulated from the second gate; the third conductive layer is located outside the second channel, and the third conductive layer is connected to the second channel.
  • the second channel is connected to the first gate.
  • the memory further includes a first word line and a first bit line, the first word line is connected to the first conductive layer, and the first bit line is connected to the second conductive layer.
  • the memory further includes a second word line and a second bit line, the second word line is connected to the second gate, and the second bit line is connected to the third conductive layer.
  • the first transistor further includes a first gate insulating layer between the first gate and the first channel.
  • the second transistor further includes a second gate insulating layer between the second gate and the second channel.
  • both the first transistor and the second transistor are vertical transistors.
  • an orthographic projection of the first transistor and the second transistor on the substrate has an overlapping region.
  • the first channel of the first transistor is a full-surround channel
  • the second channel of the second transistor is a full-surround channel
  • an embodiment of the present disclosure further provides an electronic device, comprising the aforementioned memory.
  • FIG1 is an equivalent circuit diagram of a memory device according to an embodiment of the present application.
  • FIG2 is a cross-sectional view 1 of the memory device according to an embodiment of the present application.
  • FIG3 is a second cross-sectional view of the memory device according to an embodiment of the present application.
  • FIG. 4a is a schematic diagram of a memory device after forming a first conductive layer, a first semiconductor layer, and a second conductive layer in a manufacturing process of the memory device according to an embodiment of the present application;
  • FIG4 b is a schematic diagram of a memory after a first slot is formed during the preparation process of the memory according to an embodiment of the present application;
  • FIG4c is a schematic diagram of a memory device after forming a first gate in the manufacturing process of the memory device according to the embodiment of the present application;
  • FIG4d is a schematic diagram of a memory device after forming a third conductive layer in the manufacturing process of the memory device according to the embodiment of the present application;
  • FIG. 4 e is a schematic diagram of a memory after forming a second gate in the memory manufacturing process according to an embodiment of the present application.
  • ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (also referred to as a drain electrode terminal, a drain region, or a drain) and a source electrode (also referred to as a source electrode terminal, a source region, or a source), and current can flow through the drain electrode, the channel region, and the source electrode.
  • the channel region refers to a region through which current mainly flows.
  • the first conductive layer mentioned below can be a drain electrode
  • the second conductive layer can be a source electrode
  • the first conductive layer can be a source electrode
  • the second conductive layer can be a drain electrode.
  • which of the first conductive layer and the second conductive layer is the source electrode and which is the drain electrode is related to the direction of current flow.
  • current flows from the source electrode to the drain electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in this specification, the "source electrode” and the “drain electrode” can be interchanged.
  • electrical connection includes the situation where the components are connected together through an element having some electrical function, such as a physical connection relationship or a signal connection relationship.
  • element having some electrical function There is no particular limitation on the “element having some electrical function” as long as it can transmit electrical signals between the connected components.
  • Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.
  • parallel means the state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore also includes the state where the angle is greater than -5° and less than 5°.
  • perpendicular means the state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore also includes the state where the angle is greater than 85° and less than 95°.
  • film and “layer” may be interchanged.
  • conductive layer may be replaced by “conductive film”.
  • insulating film may be replaced by “insulating layer”.
  • multiple transistors of a dynamic random access memory are connected on the same plane using planar channels.
  • a 2T0C or 2T1C DRAM structure generally uses two planar channel transistors connected on the same plane, without overlap in the direction perpendicular to the substrate, occupying a large area, which is not conducive to improving the integration density.
  • the planar channels are the channels of planar transistors, relative to vertical transistors.
  • the arrangement between the storage cells in the storage array is an array distribution, with multiple rows and columns, and the storage cells are located at the intersection of the rows and columns, and the storage density needs to be improved.
  • Dynamic random access memory (DRAM) and enhanced or embedded dynamic random access memory (eDRAM) can be used for high-density or high-bandwidth storage devices.
  • a storage device (such as DRAM or eDRAM) can include multiple memory cells, and the memory cells can include transistors that can control access to the memory cells.
  • the present application provides a memory including at least one memory cell, wherein the memory cell includes a substrate and a first transistor and a second transistor sequentially stacked in a direction perpendicular to the substrate, wherein the first transistor is used as The first transistor is a read transistor, the second transistor is a write transistor, the first transistor includes a first channel, the first channel is a silicon semiconductor, and the second transistor includes a second channel, the second channel is an oxide semiconductor.
  • FIG. 1 is an equivalent circuit diagram of a memory device according to an embodiment of the present application. Take the memory cell of the memory device according to an embodiment of the present application as 2T0C as an example.
  • the memory cell of the memory device according to an embodiment of the present application includes a first transistor and a second transistor sequentially stacked on a substrate, the first transistor can be used as a read transistor (referred to as a read transistor), the second transistor can be used as a write transistor (referred to as a write transistor), the first channel in the first transistor is a silicon semiconductor, and the second channel in the second transistor is an oxide semiconductor. The first gate in the first transistor is connected to the second channel in the second transistor.
  • the memory of the embodiment of the present application changes the charge in the gate electrode of the read transistor by writing a transistor, thereby affecting the resistance state between the source and drain of the read transistor, thereby achieving the distinction between "0" and "1".
  • the principle of the memory of this example is as follows.
  • a positive voltage greater than the threshold voltage Vth
  • a positive voltage is applied to the write word line (WWL) of the write transistor to turn on the write transistor
  • a positive voltage is applied to the write bit line (WBL) of the write transistor to inject charge into the first gate of the read transistor.
  • the voltages of the write word line (WWL) and the write bit line (WBL) of the write transistor are removed to save the "1" state;
  • a positive voltage greater than the threshold voltage Vth
  • a negative voltage is applied to the write bit line (WBL) of the write transistor to extract charge from the first gate of the read transistor.
  • the voltages of the write word line (WWL) and the write bit line (WBL) of the write transistor are removed to save the "0" state;
  • a read voltage is applied to the read bit line (RBL) of the read transistor. Since there is no charge in the first gate of the read transistor, the read transistor is in a higher resistance state and obtains a smaller current, which is then amplified and identified by the peripheral circuit to complete the process of reading "0".
  • FIG2 is a cross-sectional view 1 of the memory of the embodiment of the present application.
  • the memory of the embodiment of the present application includes at least one memory cell, the memory cell includes a substrate 100 and a first transistor and a second transistor sequentially stacked in a direction (direction Z) perpendicular to the substrate 100, the first transistor being located on a side of the second transistor close to the substrate 100.
  • the first transistor is used as a read transistor, and the second transistor is used as a write transistor.
  • the first transistor includes a first channel 11, which is a silicon semiconductor, and the second transistor includes a second channel 21, which is an oxide semiconductor.
  • the oxide semiconductor may be indium gallium zinc oxide (IGZO), indium aluminum zinc oxide (IAZO), indium oxide, zinc oxide, or the like.
  • IGZO indium gallium zinc oxide
  • IAZO indium aluminum zinc oxide
  • IAZO indium oxide
  • zinc oxide or the like.
  • the first channel is a silicon semiconductor, so that the first transistor has a strong driving capability
  • the second channel is an oxide semiconductor, so that the second transistor has a low leakage current, thereby greatly improving the data retention time and read speed of the storage unit.
  • the first transistor and the second transistor are both vertical transistors.
  • the first transistor and the second transistor are vertical channel all around (VCAA) transistors.
  • the first transistor and the second transistor are both vertical transistors, which reduces the area of the memory unit and improves the storage density, so that the area size of the memory can be reduced to 4F2, where F is the critical size of the node.
  • the first transistor and the second transistor are projected on the substrate 100.
  • Overlapping region For example, an orthographic projection of the first channel 11 of the first transistor on the substrate 100 and an orthographic projection of the second channel 21 of the second transistor on the substrate may partially overlap.
  • the memory of the embodiment of the present application can reduce the area of the storage unit and achieve a density of 4F2/N by arranging the first transistor and the second transistor to have an overlapping area in the orthographic projection on the substrate 100, where N is the number of stacked arrays.
  • the first transistor may include a first gate 12 , a first channel 11 , a first conductive layer 13 , and a second conductive layer 14 .
  • the first gate 12 is located on the substrate 100 , extends in a direction perpendicular to the substrate 300 (direction Z), is columnar, and has a T-shaped vertical cross section.
  • the first gate 12 may be made of at least one of polysilicon, metal, metal nitride and oxide.
  • the material of the first gate 12 may be titanium nitride, metal tungsten or indium tin oxide.
  • the first channel 11 is located outside the first gate 12 and is insulated from the first gate 12.
  • the first gate 12 may include a sidewall, and the first channel 11 may be located outside the sidewall of the first gate 12 and be insulated from the sidewall of the first gate 12.
  • the first channel 11 is a full-surrounding channel, and the first channel 11 surrounds the first gate 12 .
  • the first channel 11 is a fully surrounding channel, thereby enhancing the gate control of the first transistor and increasing the area of the channel region.
  • the first conductive layer 13 is disposed on the substrate 100 and is located on the side of the first channel 11 and the first gate 12 close to the substrate 100.
  • the orthographic projections of the first channel 11 and the first gate 12 on the substrate 100 are both located in the orthographic projection of the first conductive layer 13 on the substrate 100.
  • the first conductive layer 13 is insulated from the first gate 12, and the first conductive layer 13 is connected to the first channel 11.
  • the first conductive layer 13 may be made of a semiconductor material, for example, the first conductive layer 13 may be made of n++-Si.
  • the orthographic projections of the first conductive layer 13 and the first channel 11 on the substrate 100 may partially overlap. There is a non-overlapping region between the orthographic projections of the first conductive layer 13 and the first channel 11 on the substrate 100, and the non-overlapping region is a peripheral region of the first conductive layer 13, which is used to connect to the first word line.
  • the second conductive layer 14 is located outside the first gate 12, and the second conductive layer 14 can be arranged around the first gate 12.
  • the second conductive layer 14 is located on the side of the first channel 11 away from the substrate 100, and the second conductive layer 14 is connected to the surface of the first channel 11.
  • the second conductive layer 14 contacts the surface of the first channel 11 away from the substrate 100, and the orthographic projection of the second conductive layer 14 on the substrate 100 overlaps with the orthographic projection of the first channel 11 on the substrate 100.
  • the orthographic projection of the second conductive layer 14 on the substrate 100 is located in the orthographic projection of the first conductive layer 13 on the substrate 100.
  • the second conductive layer 14 can be made of semiconductor material, for example, the second conductive layer 14 can be made of n++-Si.
  • the first transistor further includes a first gate insulating layer 15, which is located between the first gate 12 and the first channel 11 to insulate the first gate 12 from the first channel 11.
  • the first gate insulating layer 15 may be made of a material with a wide bandgap and a high dielectric constant, such as silicon dioxide or hafnium dioxide.
  • the first gate insulating layer 15 may be made of a single-layer dielectric material, such as an oxide or a nitride; or, the first gate insulating layer 15 may be made of a multi-layer dielectric material, such as a combination of an oxide and a nitride.
  • the second transistor includes a second gate 22 , a second channel 21 , and a third conductive layer 23 .
  • the second gate 22 is located on a side of the first gate 12 away from the substrate 100 .
  • the second gate 22 extends along a direction perpendicular to the substrate 300 (direction Z), and the second gate 22 is columnar, and a vertical cross section of the second gate 22 may be T-shaped.
  • the orthographic projections of the second gate 22 and the first gate 12 on the substrate 100 overlap.
  • the orthographic projection of the second gate 22 on the substrate 100 is located in the orthographic projection of the first gate 12 on the substrate 100 .
  • the second gate 22 may be made of at least one of polysilicon, metal, metal nitride and oxide.
  • the second gate 22 may be made of titanium nitride, metal tungsten or indium tin oxide.
  • the second channel 21 is located outside the second gate 22 and is insulated from the second gate 22.
  • the second gate 22 may include a sidewall and a bottom wall, and the second channel 21 may be located outside the sidewall and the bottom wall of the second gate 22 and be insulated from the sidewall and the bottom wall of the second gate 22.
  • the second channel 21 is a full-surrounding channel, and the second channel 21 surrounds the second gate 22 .
  • the second channel 21 is a fully surrounding channel, which enhances the gate control of the second transistor and increases the area of the channel region.
  • the third conductive layer 23 is located outside the second channel 21, and the third conductive layer 23 can be arranged around the second channel 21.
  • the third conductive layer 23 is connected to the second channel 21.
  • the orthographic projection of the third conductive layer 23 on the substrate 100 is located in the orthographic projection of the first conductive layer 13 on the substrate 100.
  • the third conductive layer 23 can be made of a metal material or indium tin oxide, for example, the third conductive layer 23 can be made of titanium or aluminum.
  • the bottom of the second channel 21 is connected to the top of the first gate 12 , so that the first transistor is electrically connected to the second transistor.
  • the second transistor further includes a second gate insulating layer 24, which is located between the second gate 22 and the second channel 21 to insulate the second gate 22 from the second channel 21.
  • the second gate insulating layer 24 may be made of a material with a wide bandgap and a high dielectric constant, such as silicon dioxide or hafnium dioxide.
  • the second gate insulating layer 24 may be made of a single-layer dielectric material, such as an oxide or a nitride; or, the second gate insulating layer 24 may be made of a multi-layer dielectric material, such as a combination of an oxide and a nitride.
  • the memory of the embodiment of the present application may further include: a first insulating layer 31, a second insulating layer 32, and a third insulating layer 33.
  • the first insulating layer 31 is disposed on the substrate 100, covering the sidewalls of the first channel 11, the first conductive layer 13, and the second conductive layer 14.
  • the second insulating layer 32 is disposed on the first insulating layer 31, covering the first gate 12 and a portion of the sidewalls of the second channel 21, and the third conductive layer 23 is disposed on the second insulating layer 32.
  • the third insulating layer 33 is disposed on the second insulating layer 32, covering the third conductive layer 23 and a portion of the sidewalls of the second channel 21.
  • the first insulating layer 31, the second insulating layer 32, and the third insulating layer 33 may all be made of silicon dioxide.
  • FIG3 is a second cross-sectional view of the memory of the embodiment of the present application.
  • the memory of the embodiment of the present application may further include: a first word line 41, a first bit line 42, a second word line and a second bit line 43, wherein the first word line 41, the first bit line 42, the second word line and the second bit line 43 are all located on the third insulating layer 33, the first word line 41 is connected to the peripheral area of the first conductive layer 13 through a first via hole, the first bit line 42 is connected to the peripheral area of the second conductive layer 14 through a second via hole, the second word line is connected to the second gate 22, and the second bit line 43 is connected to the peripheral area of the third conductive layer 23 through a third via hole.
  • the first word line 41 may be a read word line
  • the first bit line 42 may be a read bit line
  • the second word line may be a write word line
  • the second bit line 43 may be a write bit line.
  • the preparation process of the memory is exemplarily described below with reference to FIGS. 4 a to 4 e .
  • the “patterning process” mentioned in the embodiments of the present disclosure includes, for metal materials, inorganic materials or transparent conductive materials, coating of photoresist, mask exposure, development, etching, stripping of photoresist and the like, and for organic materials, coating of organic Materials, mask exposure and development and other processing.
  • Deposition can be any one or more of sputtering, evaporation, chemical vapor deposition
  • coating can be any one or more of spraying, spin coating and inkjet printing
  • etching can be any one or more of dry etching and wet etching, and the present disclosure does not limit it.
  • Thin film refers to a layer of thin film made of a certain material on a substrate by deposition, coating or other processes.
  • the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • the preparation process of the memory may include:
  • the substrate may be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components, such as silicon on insulator (SOI), bulk silicon, silicon carbide, germanium, silicon germanium, gallium arsenide or germanium on insulator, etc., and the corresponding top semiconductor material is silicon, germanium, silicon germanium or gallium arsenide, etc.
  • the semiconductor layer on the substrate may be doped according to the device type to form a P-well (for nMOSFET) or an n-well (for pMOSFET).
  • a first conductive layer, a first semiconductor layer, and a second conductive layer are formed.
  • forming a first conductive layer, a first semiconductor layer, and a second conductive layer includes: depositing a first conductive material layer, a first semiconductor material layer, and a second conductive material layer in sequence on the above-mentioned substrate 100, and patterning the first conductive material layer, the first semiconductor material layer, and the second conductive material layer through a patterning process, so that the first conductive material layer forms a first conductive layer 13 arranged on the substrate 100, the first semiconductor material layer forms a first semiconductor layer 51 arranged on the first conductive layer 13, and the second conductive material layer forms a second conductive layer 14 arranged on the first semiconductor layer 51, as shown in Figure 4a.
  • forming the first groove body includes: depositing a first insulating film on the substrate on which the aforementioned pattern is formed, and patterning the first insulating film through a patterning process so that the first insulating film forms a first insulating layer 31; then, forming a first groove body 61 in the first insulating layer 31 through an etching process, and the first groove body 61 sequentially passes through the first insulating layer 31, the second conductive layer 14, and the first channel 11 to the surface of the first conductive layer 13 away from the substrate 100, exposing a portion of the surface of the first conductive layer 13, so that the first semiconductor layer forms a first channel 11, as shown in Figure 4b.
  • forming the first gate includes: on the substrate forming the aforementioned pattern, sequentially depositing a second insulating film and a first gate material layer in the first groove body, patterning the second insulating film and the first gate material layer through a patterning process, so that the second insulating film forms a first gate insulating layer 15 covering the inner wall of the first groove body, and the first gate material layer forms a first gate 12 at least partially located in the first groove body, and the first gate 12 is insulated from the first channel 11 by the first gate insulating layer 15, as shown in Figure 4c.
  • the first channel 11 may be a silicon semiconductor.
  • the first gate 12, the first channel 11, the first conductive layer 13 and the second conductive layer 14 constitute a first transistor.
  • the first transistor may be used as a read transistor.
  • forming the third conductive layer includes: depositing a third insulating film and a third conductive material layer in sequence on the substrate on which the aforementioned pattern is formed, patterning the third insulating film and the third conductive material layer through a patterning process, so that the third insulating film forms a second insulating layer 32 covering the first insulating layer 31 and the first gate 12, and the third conductive material layer forms a third conductive layer 23 arranged on the second insulating layer 32, as shown in Figure 4d.
  • forming the second groove body includes: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, and patterning the fourth insulating film through a patterning process so that the fourth insulating film forms a third insulating layer 33 covering the third conductive layer 23; then, forming a second groove body 62 in the third insulating layer 33 through an etching process, and the second groove body 62 sequentially passes through the third insulating layer 33, the third conductive layer 23, and the second insulating layer 32 to the surface of the first gate 12 away from the substrate 100, exposing a portion of the surface of the first gate 12, as shown in Figure 4e.
  • forming the second gate includes: on the substrate forming the aforementioned pattern, sequentially depositing a second semiconductor material layer, a fifth insulating film, and a second gate material layer in the second groove body, patterning the second semiconductor material layer, the fifth insulating film, and the second gate material layer through a patterning process, so that the second semiconductor material layer forms a second channel 21 covering the inner wall of the second groove body, the fifth insulating film forms a second gate insulating layer 24 covering the second channel 21, and the second gate material layer forms a second gate 22 located in the second groove body, and the second gate 22 is insulated from the second channel 21 by the second gate insulating layer 24, as shown in Figure 2.
  • the second channel 21 may be an oxide semiconductor.
  • the second gate 22, the second channel 21 and the third conductive layer 23 constitute a second transistor.
  • the second transistor may be used as a write transistor.
  • the method for preparing the memory of the embodiment of the present application makes the first channel a silicon semiconductor so that the first transistor has a strong driving capability, and makes the second channel an oxide semiconductor so that the second transistor has a low leakage current, thereby greatly improving the data retention time and read speed of the storage unit.
  • the preparation process of the memory of the exemplary embodiment of the present disclosure has good process compatibility, simple process realization, easy implementation, high production efficiency, low production cost and high yield rate.
  • the structure of the memory of the exemplary embodiment of the present disclosure and its preparation process are only an exemplary description.
  • the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs.
  • after preparing the second gate it can also include: forming a first word line, a first bit line, a second word line and a second bit line, wherein the first bit line, the second word line and the second bit line can all be located on the third insulating layer, and the first word line can be connected to the peripheral area of the first conductive layer through the first via hole, for example, the third insulating layer, the second insulating layer and the first insulating layer in the first via hole can be removed to expose the partial surface of the peripheral area of the first conductive layer; the first bit line can be connected to the peripheral area of the second conductive layer through the second via hole, for example, the third insulating layer, the second insulating layer and the first insulating layer in the second via hole can be removed to expose the partial surface of
  • the embodiment of the present application further provides an electronic device, comprising any of the above-mentioned memories.
  • the embodiment of the present application does not impose any special limitation on the form of the above-mentioned electronic device.

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Abstract

一种存储器，涉及半导体技术领域，该存储器包括至少一个存储单元，所述存储单元包括衬底以及在垂直所述衬底的方向上依次层叠设置的第一晶体管和第二晶体管，所述第一晶体管作为读取晶体管，所述第二晶体管作为写入晶体管，所述第一晶体管包括第一沟道，所述第一沟道为硅半导体，所述第二晶体管包括第二沟道，所述第二沟道为氧化物半导体。

Description

一种存储器、电子设备
本申请要求于2022年11月1日提交中国专利局、申请号为202211358555.4、发明名称为“一种存储器、电子设备”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开实施例涉及但不限于半导体技术领域，尤其涉及一种存储器、电子设备。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是一种半导体存储器，和静态存储器相比，DRAM存储器具有结构较为简单、制造成本较低、容量密度较高的优点，随着技术的发展，DRAM存储器的应用日益广泛。
存储器具有较高的集成度是重要的发展方向，以满足消费者对优良的性能以及低廉的价格的需求。对于存储器，由于它们的集成度会是决定产品价格的重要因素，因此会特别期望提高集成度。对于二维或平面存储器，由于它们的集成度主要由存储器占据的面积决定，因此集成度受精细图案形成技术的水平的影响很大。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开实施例提供了一种存储器，包括至少一个存储单元，所述存储单元包括衬底以及在垂直所述衬底的方向上依次层叠设置的第一晶体管和第二晶体管，所述第一晶体管作为读取晶体管，所述第二晶体管作为写入晶体管，所述第一晶体管包括第一沟道，所述第一沟道为硅半导体，所述第二晶体管包括第二沟道，所述第二沟道为氧化物半导体。
在示例性实施例中，所述第一晶体管包括：第一栅极、第一沟道、第一导电层和第二导电层。第一栅极位于所述衬底上，所述第一栅极呈柱状；第一沟道位于所述第一栅极的外侧，与所述第一栅极绝缘；第一导电层位于所述第一沟道靠近所述衬底一侧，所述第一导电层与所述第一沟道连接，所述第一导电层与所述第一沟道在所述衬底的正投影部分交叠；第二导电层位于所述第一沟道远离所述衬底一侧，且与所述第一沟道连接。
在示例性实施例中，所述第二晶体管包括：第二栅极、第二沟道和第三导电层。第二栅极位于所述第一栅极远离所述衬底一侧，所述第二栅极呈柱状；第二沟道位于所述第二栅极的外侧，与所述第二栅极绝缘；第三导电层位于所述第二沟道的外侧，所述第三导电层与所述第二沟道连接。
在示例性实施例中，所述第二沟道与所述第一栅极连接。
在示例性实施例中，存储器还包括第一字线和第一位线，所述第一字线与所述第一导电层连接，所述第一位线与所述第二导电层连接。
在示例性实施例中，存储器还包括第二字线和第二位线，所述第二字线与所述第二栅极连接，所述第二位线与所述第三导电层连接。
在示例性实施例中，所述第一晶体管还包括第一栅极绝缘层，所述第一栅极绝缘层位于所述第一栅极与所述第一沟道之间。
在示例性实施例中，所述第二晶体管还包括第二栅极绝缘层，所述第二栅极绝缘层位于所述第二栅极与所述第二沟道之间。
在示例性实施例中，所述第一晶体管和所述第二晶体管均为垂直晶体管。
在示例性实施例中，所述第一晶体管与所述第二晶体管在所述衬底的正投影存在交叠区域。
在示例性实施例中，所述第一晶体管的第一沟道为全环绕型沟道，所述第二晶体管的第二沟道为全环绕型沟道。
第二方面，本公开实施例还提供了一种电子设备，包括前述的存储器。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本申请技术方案的理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1为本申请实施例存储器的等效电路图；
图2为本申请实施例存储器的剖视图一；
图3为本申请实施例存储器的剖视图二；
图4a为本申请实施例存储器制备过程中形成第一导电层、第一半导体层和第二导电层后的示意图；
图4b为本申请实施例存储器制备过程中形成第一槽体后的示意图；
图4c为本申请实施例存储器制备过程中形成第一栅极后的示意图；
图4d为本申请实施例存储器制备过程中形成第三导电层后的示意图；
图4e为本申请实施例存储器制备过程中形成第二栅极后的示意图。
详述
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为多种形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水 平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(也称为漏电极端子、漏区域或漏极)与源电极(也称为源电极端子、源区域或源极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，下面提及的第一导电层可以为漏电极、第二导电层可以为源电极，或者第一导电层可以为源电极、第二导电层可以为漏电极。实际应用中，第一导电层和第二导电层哪一个为源电极，哪一个为漏电极与电流的流向有关，一般的，电流从源极流向漏极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况，比如实物连接关系，或信号连接关系。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有一种或多种功能的元件等。
在本说明书中，下述的平行或垂直是在误差范围内的大约平行和大约垂直。“平行”是指两个直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两个直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
相关技术中，动态随机存储器(DRAM)的多个晶体管采用平面排布的沟道在同一平面上连接，例如，2T0C或2T1C的DRAM结构一般采用2个平面沟道的晶体管在同一平面上连接，在垂直衬底的方向上无交叠，占用面积较大，不利于提高集成密度。所述平面排布的沟道为平面晶体管的沟道，相对于垂直晶体管而言。另外，存储阵列中存储单元之间的排布是呈现阵列分布，多行多列，且存储单元位于行列交叉的交叉点上，存储密度还有待提升。
动态随机存取存储器(DRAM)和增强式或嵌入式动态随机存取存储器(eDRAM)可以用于高密度或高带宽存储装置。存储装置(例如DRAM或eDRAM)可以包括多个存储单元，存储单元可以包括晶体管，晶体管可以控制对存储单元的存取。
本申请实施例提供了一种存储器，包括至少一个存储单元，所述存储单元包括衬底以及在垂直所述衬底的方向上依次层叠设置的第一晶体管和第二晶体管，所述第一晶体管作 为读取晶体管，所述第二晶体管作为写入晶体管，所述第一晶体管包括第一沟道，所述第一沟道为硅半导体，所述第二晶体管包括第二沟道，所述第二沟道为氧化物半导体。
图1为本申请实施例存储器的等效电路图。以本申请实施例存储器的存储单元为2T0C为例。在示例性实施例中，如图1所示，本申请实施例存储器的存储单元包括依次层叠设置在衬底上的第一晶体管和第二晶体管，第一晶体管可以作为读取晶体管(简称为读取管)，第二晶体管可以作为写入晶体管(简称为写入管)，第一晶体管中的第一沟道为硅半导体，第二晶体管中的第二沟道为氧化物半导体。第一晶体管中的第一栅极与第二晶体管中的第二沟道连接。
本申请实施例的存储器通过写入晶体管改变读取晶体管的栅电极中的电荷，进而影响读取晶体管源漏之间的阻态，从而实现“0”和“1”的区分，本示例的存储器的原理如下。
写“1”过程，在写入晶体管的写入字线(WWL)施加正电压(大于阈值电压Vth)使得写入晶体管开启，在写入晶体管的写入位线(WBL)施加正电压向读取晶体管的第一栅极注入电荷。电荷注入后，撤去写入晶体管的写入字线(WWL)和写入位线(WBL)的电压，保存“1”状态；
读“1”过程，在读取晶体管的读取位线(RBL)施加读取电压，由于读取晶体管的第一栅极中存有一定电荷，读取晶体管处于较低阻态，获得较大的电流，再由外围电路放大识别后完成读取“1”过程；
写“0”过程，在写入晶体管的写入字线(WWL)施加正电压(大于阈值电压Vth)使得写入晶体管开启，在写入晶体管的写入位线(WBL)施加负电压向读取晶体管的第一栅极抽取电荷。电荷抽取后，撤去写入晶体管的写入字线(WWL)和写入位线(WBL)的电压，保存“0”状态；
读“0”过程，在读取晶体管的读取位线(RBL)施加读取电压，由于读取晶体管的第一栅极中没有电荷，读取晶体管处于较高阻态，获得较小的电流，再由外围电路放大识别后完成读取“0”过程。
图2本申请实施例存储器的剖视图一。在示例性实施例中，如图2所示，本申请实施例存储器包括至少一个存储单元，存储单元包括衬底100以及在垂直衬底100的方向(方向Z)上依次层叠设置的第一晶体管和第二晶体管，第一晶体管位于第二晶体管靠近衬底100一侧。第一晶体管作为读取晶体管，第二晶体管作为写入晶体管，第一晶体管包括第一沟道11，第一沟道11为硅半导体，第二晶体管包括第二沟道21，第二沟道21为氧化物半导体。
在示例性实施例中，氧化物半导体可以为铟镓锌氧化物(IGZO)、铟铝锌氧化物(IAZO)、氧化铟、氧化锌等材质。
本申请实施例存储器通过第一沟道为硅半导体，使第一晶体管具有强驱动能力，以及通过第二沟道为氧化物半导体，使第二晶体管具有低漏电电流，从而大幅提高存储单元的数据保持时间和读出速度。
在示例性实施例中，如图2所示，第一晶体管和第二晶体管均为垂直晶体管，示例性的，第一晶体管和第二晶体管分别为垂直全环绕型沟道(VCAA，Vertical Channel All Around)晶体管。
本申请实施例存储器通过第一晶体管与第二晶体管均为垂直晶体管，降低存储单元的面积，提高存储密度，使存储器的面积大小可被减小到4F2，其中F是节点的临界尺寸。
在示例性实施例中，如图2所示，第一晶体管和第二晶体管在衬底100的正投影存在 交叠区域。例如，第一晶体管的第一沟道11在衬底100的正投影与第二晶体管的第二沟道21在衬底的正投影可以部分交叠。
本申请实施例存储器通过设置第一晶体管和第二晶体管在衬底100的正投影存在交叠区域，可以降低存储单元的面积，实现4F2/N的密度，其中N是堆叠式阵列的数量。
在示例性实施例中，如图2所示，第一晶体管可以包括第一栅极12、第一沟道11、第一导电层13以及第二导电层14。
在示例性实施例中，如图2所示，第一栅极12位于衬底100上，第一栅极12沿着垂直于衬底300方向(方向Z)延伸，第一栅极12呈柱状，第一栅极12的竖截面可以为T形。
在示例性实施例中，第一栅极12可以采用多晶硅、金属、金属氮化物和氧化物中的至少一种。示例的，第一栅极12材料可以采用氮化钛、金属钨或氧化铟锡。
在示例性实施例中，如图2所示，第一沟道11位于第一栅极12的外侧，与第一栅极12绝缘。示例的，第一栅极12可以包括侧壁，第一沟道11可以位于第一栅极12侧壁的外侧，并与第一栅极12的侧壁绝缘。
在示例性实施例中，如图2所示，第一沟道11为全环绕型沟道，第一沟道11环绕第一栅极12的四周。
本申请实施例存储器通过第一沟道11为全环绕型沟道，增强第一晶体管的栅控，增加沟道区的面积。
在示例性实施例中，如图2所示，第一导电层13设置在衬底100上，并位于第一沟道11和第一栅极12靠近衬底100一侧。第一沟道11和第一栅极12在衬底100的正投影均位于第一导电层13在衬底100的正投影中。第一导电层13与第一栅极12绝缘，第一导电层13与第一沟道11连接。其中，第一导电层13可以采用半导体材料，例如，第一导电层13可以采用n++-Si。
在示例性实施例中，如图2所示，第一导电层13与第一沟道11在衬底100的正投影可以部分交叠。第一导电层13与第一沟道11在衬底100的正投影存在不交叠区域，该不交叠区域为第一导电层13的外围区域，用于与第一字线连接。
在示例性实施例中，如图2所示，第二导电层14位于第一栅极12的外侧，第二导电层14可以环绕第一栅极12的四周设置。第二导电层14位于第一沟道11远离衬底100一侧，且第二导电层14与第一沟道11的表面连接。示例的，第二导电层14与第一沟道11远离衬底100一侧的表面接触，且第二导电层14在衬底100的正投影与第一沟道11在衬底100的正投影交叠。第二导电层14在衬底100的正投影位于第一导电层13在衬底100的正投影中。其中，第二导电层14可以采用半导体材料，例如，第二导电层14可以采用n++-Si。
在示例性实施例中，如图2所示，第一晶体管还包括第一栅极绝缘层15，第一栅极绝缘层15位于第一栅极12与第一沟道11之间，将第一栅极12与第一沟道11绝缘。其中，第一栅极绝缘层15可以选择宽带隙和高介电常数的材料，例如二氧化硅或二氧化铪。第一栅极绝缘层15可以采用单层介质材料，例如，氧化物或氮化物；或者，第一栅极绝缘层15可以采用多层介质材料，例如，氧化物和氮化物的组合。
在示例性实施例中，如图2所示，第二晶体管包括第二栅极22、第二沟道21以及第三导电层23。
在示例性实施例中，如图2所示，第二栅极22位于第一栅极12远离衬底100一侧， 第二栅极22沿着垂直于衬底300方向(方向Z)延伸，第二栅极22呈柱状，第二栅极22的竖截面可以为T形。
在示例性实施例中，如图2所示，第二栅极22与第一栅极12在衬底100的正投影存在交叠，示例的，第二栅极22在衬底100的正投影位于第一栅极12在衬底100的正投影中。
在示例性实施例中，第二栅极22可以采用多晶硅、金属、金属氮化物和氧化物中的至少一种。示例的，第二栅极22材料可以采用氮化钛、金属钨或氧化铟锡。
在示例性实施例中，如图2所示，第二沟道21位于第二栅极22的外侧，与第二栅极22绝缘。示例的，第二栅极22可以包括侧壁和底壁，第二沟道21可以位于第二栅极22的侧壁和底壁的外侧，并与第二栅极22的侧壁和底壁绝缘。
在示例性实施例中，如图2所示，第二沟道21为全环绕型沟道，第二沟道21环绕第二栅极22的四周。
本申请实施例存储器通过第二沟道21为全环绕型沟道，增强第二晶体管栅控，增加沟道区的面积。
在示例性实施例中，如图2所示，第三导电层23位于第二沟道21的外侧，第三导电层23可以环绕第二沟道21的四周设置。第三导电层23与第二沟道21连接。第三导电层23在衬底100的正投影位于第一导电层13在衬底100的正投影中。其中，第三导电层23可以采用金属材料或氧化铟锡，例如，第三导电层23可以采用钛或铝。
在示例性实施例中，如图2所示，第二沟道21的底部与第一栅极12的顶部连接，使第一晶体管与第二晶体管实现电连接。
在示例性实施例中，如图2所示，第二晶体管还包括第二栅极绝缘层24，第二栅极绝缘层24位于第二栅极22与第二沟道21之间，将第二栅极22与第二沟道21绝缘。其中，第二栅极绝缘层24可以选择宽带隙和高介电常数的材料，例如二氧化硅或二氧化铪。第二栅极绝缘层24可以采用单层介质材料，例如，氧化物或氮化物；或者，第二栅极绝缘层24可以采用多层介质材料，例如，氧化物和氮化物的组合。
在示例性实施例中，如图2所示，本申请实施例的存储器还可以包括：第一绝缘层31、第二绝缘层32和第三绝缘层33。第一绝缘层31设置在衬底100上，覆盖第一沟道11的侧壁、第一导电层13以及第二导电层14。第二绝缘层32设置在第一绝缘层31上，覆盖第一栅极12和第二沟道21的部分侧壁，第三导电层23设置在第二绝缘层32上。第三绝缘层33设置在第二绝缘层32上，覆盖第三导电层23以及第二沟道21的部分侧壁。其中，第一绝缘层31、第二绝缘层32和第三绝缘层33均可以采用二氧化硅。
图3本申请实施例存储器的剖视图二。在示例性实施例中，如图3所示，本申请实施例存储器还可以包括：第一字线41、第一位线42、第二字线和第二位线43，第一字线41、第一位线42、第二字线和第二位线43均位于第三绝缘层33上，第一字线41通过第一过孔与第一导电层13的外围区域连接，第一位线42通过第二过孔与第二导电层14的外围区域连接，第二字线与第二栅极22连接，第二位线43通过第三过孔与第三导电层23的外围区域连接。例如，第一字线41可以为读取字线，第一位线42可以为读取位线，第二字线可以为写入字线，第二位线43可以为写入位线。
下面参照图4a至图4e对存储器的制备过程进行示例性说明。
本公开实施例所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机 材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在衬底基板上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。
在示例性实施方式中，存储器的制备过程可以包括：
(1)提供衬底。
在示例性实施例中，衬底可以是本领域技术人员熟知的任何用以承载半导体集成电路组成元件的底材，例如绝缘体上硅(silicon on insulator，SOI)、体硅(bulk silicon)、碳化硅、锗、锗硅、砷化镓或者绝缘体上锗等，相应的顶层半导体材料为硅、锗、锗硅或砷化镓等。而且，该衬底上的半导体层可以根据器件类型确定掺杂类型，以形成P阱(用于nMOSFET)或者n阱(用于pMOSFET)。
(2)形成第一导电层、第一半导体层和第二导电层。
在示例性实施例中，形成第一导电层、第一半导体层和第二导电层包括：在上述衬底100上，依次沉积第一导电材料层、第一半导体材料层和第二导电材料层，通过图案化工艺对第一导电材料层、第一半导体材料层和第二导电材料层进行图案化，使第一导电材料层形成设置在衬底100上的第一导电层13，使第一半导体材料层形成设置在第一导电层13上的第一半导体层51，使第二导电材料层形成设置在第一半导体层51上的第二导电层14，如图4a所示。
(3)形成第一槽体。
在示例性实施例中，形成第一槽体包括：在形成前述图案的衬底上，沉积第一绝缘薄膜，通过图案化工艺对第一绝缘薄膜进行图案化，使第一绝缘薄膜形成第一绝缘层31；然后，通过刻蚀工艺，在第一绝缘层31中形成第一槽体61，第一槽体61依次穿过第一绝缘层31、第二导电层14、第一沟道11，至第一导电层13远离衬底100一侧的表面，将第一导电层13的部分表面暴露，使第一半导体层形成第一沟道11，如图4b所示。
(4)形成第一栅极。
在示例性实施例中，形成第一栅极包括：在形成前述图案的衬底上，在第一槽体中依次沉积第二绝缘薄膜和第一栅极材料层，通过图案化工艺对第二绝缘薄膜和第一栅极材料层进行图案化，使第二绝缘薄膜形成覆盖第一槽体内壁的第一栅极绝缘层15，使第一栅极材料层形成至少部分位于第一槽体中的第一栅极12，第一栅极12通过第一栅极绝缘层15与第一沟道11绝缘，如图4c所示。
其中，第一沟道11可以为硅半导体。第一栅极12、第一沟道11、第一导电层13以及第二导电层14构成第一晶体管。第一晶体管可以作为读取晶体管。
(5)形成第三导电层。
在示例性实施例中，形成第三导电层包括：在形成前述图案的衬底上，依次沉积第三绝缘薄膜和第三导电材料层，通过图案化工艺对第三绝缘薄膜和第三导电材料层进行图案化，使第三绝缘薄膜形成覆盖第一绝缘层31和第一栅极12的第二绝缘层32，使第三导电材料层形成设置在第二绝缘层32上的第三导电层23，如图4d所示。
(6)形成第二槽体。
在示例性实施例中，形成第二槽体包括：在形成前述图案的衬底上，沉积第四绝缘薄膜，通过图案化工艺对第四绝缘薄膜进行图案化，使第四绝缘薄膜形成覆盖第三导电层23的第三绝缘层33；然后，通过刻蚀工艺，在第三绝缘层33中形成第二槽体62，第二槽体62依次穿过第三绝缘层33、第三导电层23、第二绝缘层32，至第一栅极12远离衬底100一侧的表面，将第一栅极12的部分表面暴露，如图4e所示。
(7)形成第二栅极。
在示例性实施例中，形成第二栅极包括：在形成前述图案的衬底上，在第二槽体中依次沉积第二半导体材料层、第五绝缘薄膜和第二栅极材料层，通过图案化工艺对第二半导体材料层、第五绝缘薄膜和第二栅极材料层进行图案化，使第二半导体材料层形成覆盖第二槽体内壁的第二沟道21，使第五绝缘薄膜形成覆盖第二沟道21的第二栅极绝缘层24，使第二栅极材料层形成位于第二槽体中的第二栅极22，第二栅极22通过第二栅极绝缘层24与第二沟道21绝缘，如图2所示。
其中，第二沟道21可以为氧化物半导体。第二栅极22、第二沟道21和第三导电层23构成第二晶体管。第二晶体管可以作为写入晶体管。
本申请实施例存储器的制备方法通过第一沟道为硅半导体，使第一晶体管具有强驱动能力，以及通过第二沟道为氧化物半导体，使第二晶体管具有低漏电电流，从而大幅提高存储单元的数据保持时间和读出速度。
本公开示例性实施例存储器的制备过程具有良好的工艺兼容性，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本公开示例性实施例存储器的结构及其制备过程仅仅是一种示例性说明。在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少图案化工艺。在另一些示例中，在制备第二栅极之后，还可以包括：形成第一字线、第一位线、第二字线和第二位线，其中，第一位线、第二字线和第二位线可以均位于第三绝缘层上，第一字线可以通过第一过孔与第一导电层的外围区域连接，例如，第一过孔内的第三绝缘层、第二绝缘层和第一绝缘层可以被去掉以暴露出第一导电层的外围区域的部分表面；第一位线可以通过第二过孔与第二导电层的外围区域连接，例如，第二过孔内的第三绝缘层、第二绝缘层和第一绝缘层可以被去掉以暴露出第二导电层的部分表面；第二字线可以与第二栅极直接连接，第二位线可以通过第三过孔与第三导电层的外围区域连接，第三过孔内的第三绝缘层可以被去掉，以暴露出第三导电层的部分表面。
本申请实施例还提供了一种电子设备，包括前面任一所述的存储器。本申请实施例对上述电子设备的形式不做特殊限制。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (12)

  1. 一种存储器，包括至少一个存储单元，所述存储单元包括衬底以及在垂直所述衬底的方向上依次层叠设置的第一晶体管和第二晶体管，所述第一晶体管作为读取晶体管，所述第二晶体管作为写入晶体管，所述第一晶体管包括第一沟道，所述第一沟道为硅半导体，所述第二晶体管包括第二沟道，所述第二沟道为氧化物半导体。
  2. 根据权利要求1所述的存储器，其中，所述第一晶体管包括：
    第一栅极，位于所述衬底上，所述第一栅极呈柱状；
    第一沟道，位于所述第一栅极的外侧，与所述第一栅极绝缘；
    第一导电层，位于所述第一沟道靠近所述衬底一侧，所述第一导电层与所述第一沟道连接，所述第一导电层与所述第一沟道在所述衬底的正投影部分交叠；
    第二导电层，位于所述第一沟道远离所述衬底一侧，且与所述第一沟道连接。
  3. 根据权利要求2所述的存储器，其中，所述第二晶体管包括：
    第二栅极，位于所述第一栅极远离所述衬底一侧，所述第二栅极呈柱状；
    第二沟道，位于所述第二栅极的外侧，与所述第二栅极绝缘；
    第三导电层，位于所述第二沟道的外侧，所述第三导电层与所述第二沟道连接。
  4. 根据权利要求3所述的存储器，其中，所述第二沟道与所述第一栅极连接。
  5. 根据权利要求2所述的存储器，还包括：第一字线和第一位线，所述第一字线与所述第一导电层连接，所述第一位线与所述第二导电层连接。
  6. 根据权利要求3所述的存储器，还包括：第二字线和第二位线，所述第二字线与所述第二栅极连接，所述第二位线与所述第三导电层连接。
  7. 根据权利要求2所述的存储器，其中，所述第一晶体管还包括第一栅极绝缘层，所述第一栅极绝缘层位于所述第一栅极与所述第一沟道之间。
  8. 根据权利要求3所述的存储器，其中，所述第二晶体管还包括第二栅极绝缘层，所述第二栅极绝缘层位于所述第二栅极与所述第二沟道之间。
  9. 根据权利要求1至8任一所述的存储器，其中，所述第一晶体管和所述第二晶体管均为垂直晶体管。
  10. 根据权利要求9所述的存储器，其中，所述第一晶体管与所述第二晶体管在所述衬底的正投影存在交叠区域。
  11. 根据权利要求1至8任一所述的存储器，其中，所述第一晶体管的第一沟道为全环绕型沟道，所述第二晶体管的第二沟道为全环绕型沟道。
  12. 一种电子设备，包括权利要求1至11任一所述的存储器。
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