WO2021128447A1 - 一种存储器件、存储器及其制作方法、电子设备和芯片 - Google Patents

一种存储器件、存储器及其制作方法、电子设备和芯片 Download PDF

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Publication number
WO2021128447A1
WO2021128447A1 PCT/CN2020/070193 CN2020070193W WO2021128447A1 WO 2021128447 A1 WO2021128447 A1 WO 2021128447A1 CN 2020070193 W CN2020070193 W CN 2020070193W WO 2021128447 A1 WO2021128447 A1 WO 2021128447A1
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Prior art keywords
substrate
transistor
memory
negative capacitance
capacitor
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PCT/CN2020/070193
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English (en)
French (fr)
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殷华湘
张青竹
张兆浩
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中国科学院微电子研究所
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Publication of WO2021128447A1 publication Critical patent/WO2021128447A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/056—Making the transistor the transistor being a FinFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/36—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being a FinFET

Definitions

  • This application relates to the field of memory technology, in particular to a storage device, a memory and a manufacturing method thereof, electronic equipment, and a chip.
  • DRAM Dynamic Random Access Memory
  • storage devices are the core of DRAM and are used to store data.
  • DRAM storage devices include transistors and capacitors.
  • the transistor is used to control the data reading and programming of the storage device, and the capacitor is used to store the data.
  • DRAM also periodically refreshes the storage device to improve the storage capacity of the storage device.
  • periodically refreshing the storage device cannot fundamentally improve the storage capacity of the DRAM.
  • the purpose of this application is to provide a storage device, a memory and a manufacturing method thereof, an electronic device and a chip, so as to prolong the data storage time of the storage device, thereby improving the storage capacity of the storage device.
  • the storage device includes:
  • the gate structure contained in the negative capacitance transistor is a ferroelectric gate stack structure.
  • the gate structure contained in the negative capacitance transistor includes a gate conductive layer and at least one dielectric layer stacked together, and the at least one dielectric layer is located between the substrate and the gate. Between the conductive layers, at least one of the at least one dielectric layer is a ferroelectric dielectric layer.
  • the negative capacitance transistor is a fin transistor or a buried channel transistor.
  • a negative capacitance transistor and a capacitor electrically connected to the negative capacitance transistor are formed on the substrate.
  • the negative capacitance transistor has an ultra-steep sub-threshold swing, a smaller threshold voltage, a faster switching rate, and a smaller leakage current, so that the negative capacitance transistor has a very high gate control capability. It can be seen that when the storage device provided by the present application contains a negative capacitance transistor, the storage device has a smaller leakage current. When the storage device has a small leakage current, the data storage time of the storage device is inversely proportional to the leakage current of the storage device.
  • the storage device when the negative capacitance transistor is in the off state, the storage device has a relatively long data storage time. Not only the storage performance of the storage device is improved, but also the refresh frequency of the storage device can be reduced to a certain extent to achieve the purpose of reducing power consumption.
  • the application also provides a memory.
  • the memory includes at least one storage device described in the above technical solution and a peripheral circuit; the peripheral circuit is electrically connected to at least one negative capacitance transistor included in the storage device.
  • the storage device further includes an isolation structure, a passivation layer, and A pressure point structure for electrical circuit connection, the isolation structure and the peripheral circuit are both formed on the substrate; the negative capacitance transistors included in the plurality of storage devices are electrically isolated from each other by the isolation structure; the passivation The layer covers the surface of the isolation structure, the plurality of negative capacitance transistors, the plurality of capacitors and the peripheral circuit away from the substrate; the pressure point structure is formed on the surface of the passivation layer away from the substrate.
  • the present application also provides a method for manufacturing a memory, which is characterized in that it includes:
  • the at least one capacitor and the peripheral circuit are electrically connected together.
  • the gate structure contained in the negative capacitance transistor is a ferroelectric gate stack structure.
  • the gate structure contained in the negative capacitance transistor includes a gate conductive layer and at least one dielectric layer stacked together, and the at least one dielectric layer is located between the substrate and the gate. Between the conductive layers, at least one of the at least one dielectric layer is a ferroelectric dielectric layer.
  • the negative capacitance transistor is a fin transistor or a buried channel transistor.
  • the manufacturing method of the memory further includes:
  • the manufacturing method of the memory further includes:
  • a pressure point structure electrically connected with the peripheral circuit is formed on the surface of the passivation layer away from the substrate.
  • the application also provides an electronic device.
  • the electronic device includes the memory described in the above technical solution.
  • the electronic device further includes a processor; the processor is electrically connected to the memory.
  • the beneficial effects of the electronic device provided in the present application are the same as the beneficial effects of the memory described in the above technical solutions, and will not be repeated here.
  • the application also provides a chip.
  • the chip includes the memory described in the above technical solution.
  • the chip further includes a processor electrically connected to the memory.
  • Figure 1 is a schematic diagram of the structure of an electronic device in the prior art
  • Figure 2 is a structural block diagram of an electronic device in the prior art
  • FIG. 3 is a schematic diagram of the structure of a storage array in the prior art
  • FIG. 4 is a schematic diagram of a circuit structure of a memory device in the prior art
  • FIG. 5 is a schematic diagram of a circuit structure of a storage device provided by an embodiment of the application.
  • FIG. 6 is a schematic diagram of a three-dimensional structure of a storage device provided by an embodiment of the application.
  • FIG. 7 is a first cross-sectional view of the memory device along the extension direction of the fin structure according to an embodiment of the application.
  • FIG. 8 is a first cross-sectional view of the memory device along the extending direction of the gate structure according to an embodiment of the application;
  • FIG. 9 is a second cross-sectional view of the memory device along the extension direction of the fin structure according to an embodiment of the application.
  • FIG. 10 is a second cross-sectional view of the memory device along the extending direction of the gate structure according to an embodiment of the application;
  • FIG. 11 is a schematic structural diagram of a memory provided by an embodiment of the application.
  • FIG. 12 is a main flow chart of a method for manufacturing a memory provided by an embodiment of the application.
  • FIG. 13 is a specific flowchart of a method for manufacturing a memory provided by an embodiment of the application.
  • FIG. 14 is a schematic structural diagram of an electronic device provided by an embodiment of the application.
  • FIG. 15 is a schematic diagram of a chip structure provided by an embodiment of the application.
  • connection should be understood in a broad sense.
  • “connected” can be a fixed connection, a detachable connection, or a whole; it can be a direct connection, or It can be indirectly connected through an intermediary.
  • Fig. 1 shows a schematic diagram of the structure of an electronic device in the prior art.
  • the electronic device can be a computer, a mobile phone, a base station, a server, etc., but is not limited to this.
  • the electronic device includes a processor 110 and a dynamic random access memory 120 (Dynamic Random Access Memory, abbreviated as DRAM).
  • the processor 110 is electrically connected to the DRAM.
  • the processor 110 can store data in the DRAM or read data stored in the DRAM.
  • the processor 110 may be one processor, or may be a collective term for multiple processing elements.
  • the processor 110 may be a central processing unit (Central Processing Unit, CPU for short), or a specific integrated circuit (Application Specific Integrated Circuit, ASIC for short), or may be configured to implement one or more of the embodiments of the present application.
  • An integrated circuit for example, one or more microprocessors (digital signal processor, DSP for short), or one or more Field Programmable Gate Array (Field Programmable Gate Array, FPGA for short).
  • Fig. 2 shows a structural block diagram of an electronic device in the prior art.
  • the dynamic random access memory 120 includes a memory array 121, a peripheral circuit 122, and interconnection lines (not shown in FIG. 2).
  • the storage array 121 includes storage devices 1210 arranged in an array.
  • the peripheral circuit 122 includes a logic circuit 1221, an input/output circuit 1222, an address decoder 1223, a power supply circuit (not shown in FIG. 2), and the like.
  • FIG. 2 is only an example showing some circuits included in the peripheral circuit and the main connection relationship between each circuit, and does not illustrate the connection relationship between the logic circuit 1221 and each circuit.
  • the logic circuit 1221 and the address decoder 1223 between the logic circuit 1221 and the power supply circuit, between the logic circuit 1221 and the input/output circuit 1222, between the memory array 121 and the address decoder 1223, between the memory array
  • Between 121 and the power supply circuit, between the storage array 121 and the input-output circuit 1222, and between the address decoder 1223 and the input-output circuit 1222 are interconnected by interconnecting lines.
  • the above-mentioned input and output circuit 1222 includes a sense amplifier, a data register, an address register, and the like.
  • the above-mentioned electronic device further includes a system bus IOB0 and an address bus IOB1, a data bus IOB2, and a read-write control bus IOB3 respectively coupled to the system bus IOB0.
  • the processor 110 and the address register are electrically connected through the address bus IOB1
  • the processor 110 and the input/output circuit 1222 are electrically connected through the data bus IOB2
  • the processor 110 and the logic circuit 1221 are electrically connected through the read-write control bus IOB3.
  • the processor 110 sends a data address and an access instruction to the storage array 121, and the address register in the input/output circuit 1222 can find the target address according to the data address, and send it to the address decoder 1223.
  • the address decoder 1223 parses out the required target address according to the target address, and the address decoder 1223 selects the storage device 1210 matching the target address from the storage array 121 according to the required target address under the control of the logic circuit 1221.
  • the access command is a read command
  • the storage device 1210 outputs data through the data register included in the input/output circuit 1222. The output data is transmitted to the processor through the data bus.
  • the processor 110 sends the data to the data register included in the input/output circuit 1222 through the data bus, and under the control of the logic circuit 1221, the data register included in the input/output circuit 1222 sends the data into The storage device 1210 is selected to use the storage device 1210 to store data.
  • FIG. 3 shows a schematic structural diagram of a storage array in the technology.
  • the storage array 121 includes matrixed storage devices 1210.
  • the matrixed storage device 1210 includes 5 rows of storage devices 1210 and 6 columns of storage devices 1210.
  • the above-mentioned interconnection line contains 5 word lines WL and 6 bit lines BL.
  • the aforementioned address decoder 12231223 includes a row decoder 1223R and a column decoder 1223C.
  • the row decoder 1223R is connected to the 5 row memory devices 1210 in a one-to-one correspondence through 5 word lines WL, and is used to provide row strobe signals to the corresponding memory device 1210 to control the corresponding column of the memory device 1210 to turn on.
  • the column decoder 1223C passes The 6 bit lines BL are connected to the 6 columns of memory devices 1210 in a one-to-one correspondence, and are used to control the corresponding memory devices 1210 to provide row strobe signals to control the memory devices 1210 of the corresponding column to output or store data.
  • FIG. 4 shows a schematic diagram of the structure of a memory device in the prior art.
  • each memory device 1210 includes a substrate (not shown in FIG. 4) and a transistor M1 and a capacitor C1 formed on the substrate.
  • the gate of the transistor M1 is connected to the word line WL
  • the first electrode of the transistor M1 is electrically connected to the bit line BL
  • the second electrode of the transistor M1 is electrically connected to the capacitor C1.
  • the type of transistor can be selected according to actual needs, such as common NMOS or PMOS.
  • the transistor M1 is used to control data reading and programming of the storage device 1210, and the capacitor C1 is used to store data. Since the capacitor C1 is prone to leakage, resulting in the loss of the data signal stored in the capacitor C1, therefore, in the memory array 121 shown in FIG. 3, the power supply circuit (not shown in FIG. 3) also passes through 6 power supply lines (not shown in FIG. 3) It is electrically connected to the capacitor C1, so that under the control of the logic circuit 1221, the power circuit periodically charges the memory cells contained in the 6 columns of memory devices 1210 through the 6 power lines in a one-to-one correspondence, so as to ensure the data signal stored in the capacitor C1 It is not lost, and the storage performance of the storage device 1210 is improved. However, the storage device 1210 still has electric leakage, so that the periodic refreshing of the storage device 1210 cannot fundamentally improve the storage capacity of the DRAM.
  • FIG. 5 shows a schematic structural diagram of a storage device provided by an embodiment of the present application. As shown in FIG. 5, the memory device 200 is applied to DRAM. Moreover, when the storage device 200 is applied to a DRAM, the interconnection of the storage device 200 and the DRAM peripheral circuits can be referred to the foregoing, and will not be described in detail below.
  • the above-mentioned storage device 200 includes a substrate 210, a negative capacitance transistor M2 formed on the substrate 210, and a capacitor C2 electrically connected to the negative capacitance transistor M2.
  • the substrate 210 here may be a semiconductor substrate, and its material may be a semiconductor material such as silicon and germanium.
  • the negative capacitance transistor M2 has an ultra-steep subthreshold swing, a smaller threshold voltage, a faster switching rate, and a smaller leakage current
  • the negative capacitance transistor M2 has a very high gate control capability, so When the negative capacitance transistor M2 is in the off state, the leakage current of the negative capacitance transistor M2 is relatively small, so that the leakage current of the storage device 200 is relatively reduced.
  • the storage device 200 has a small leakage current, due to the data of the storage device 200 The storage time is inversely proportional to the leakage current of the storage device 200.
  • the storage device 200 when the negative capacitance transistor M2 is in the off state, the storage device 200 has a longer data storage time, which not only improves the storage performance of the storage device 200, but also The refresh frequency of the storage device 200 is reduced to a certain extent to achieve the purpose of reducing power consumption.
  • the above-mentioned negative capacitance transistor M2 includes a gate structure G and two electrode structures of a conventional transistor. As shown in FIG. 7 and FIG. 9, one of the two electrode structures is a source structure S, and the other electrode structure is a drain structure D and so on.
  • the type of the negative capacitance transistor M2 it can be a PMOS negative capacitance transistor or an MMOS negative capacitance transistor, which is not limited here.
  • the negative capacitance transistor M2 when the negative capacitance transistor M2 is a PMOS negative capacitance transistor, the gate structure G and the source structure S are electrically connected to the input and output circuit, and the drain structure D is electrically connected to the input and output circuit.
  • the capacitor C2 is electrically connected.
  • the negative capacitance transistor M2 is an NMOS negative capacitance transistor, both the gate structure G and the drain structure D are electrically connected to the input and output circuit, and the source structure S is electrically connected to the capacitor C2.
  • the above-mentioned gate structure G is a ferroelectric gate stack structure.
  • This ferroelectric gate stack structure can improve the gate control capability of the negative capacitance transistor M2 and reduce the power consumption of the negative capacitance transistor M2.
  • the above-mentioned gate structure G or ferroelectric gate stack structure includes a gate conductive layer GE and at least one dielectric layer GI stacked together.
  • the at least one dielectric layer GI is located between the gate conductive layer GE and the substrate 210.
  • At least one of the at least one dielectric layer GI is a ferroelectric dielectric layer.
  • the second dielectric layer GI2 is a ferroelectric dielectric layer.
  • the second dielectric layer GI2 is located between the gate conductive layer GE and the first dielectric layer GI1.
  • the first dielectric layer GI1, the second dielectric layer GI2, and the gate conductive layer GE are sequentially stacked along a direction away from the substrate 210.
  • the third dielectric layer GI3 is a ferroelectric dielectric layer.
  • the second dielectric layer GI2 is located between the first dielectric layer GI1 and the third dielectric layer GI3.
  • the first dielectric layer GI1, the second dielectric layer GI2, the third dielectric layer GI3, and the gate conductive layer GE are sequentially stacked along a direction away from the substrate 210.
  • the gate conductive layer GE may be a metal gate or a polysilicon gate, and of course, it may also be a gate made of conductive materials such as indium tin oxide.
  • the above-mentioned ferroelectric dielectric layer may be a dielectric layer prepared by oxides of one or two of semiconductors and rare earths.
  • ferroelectric HMOx can be used to represent the material contained in the ferroelectric dielectric layer.
  • M can be semiconductor or rare earth. It should be understood that the semiconductor here may be one or two of silicon and zirconium, but is not limited thereto.
  • the rare earth may be one or two of lanthanum and yttrium, but is not limited thereto.
  • the ferroelectric dielectric layer is an oxide containing zirconium. This oxide can contain not only zirconium, but also other semiconductors, rare earths and the like.
  • the above-mentioned first dielectric layer GI1 may be a common insulating layer 220, which may be a dielectric layer formed of organic insulating materials and inorganic oxides.
  • the first dielectric layer GI1 may be a dielectric layer made of photoresist or the like.
  • the first dielectric layer GI1 may be a dielectric layer made of materials such as silicon oxide and aluminum oxide.
  • the above-mentioned negative capacitance transistor M2 is a fin transistor.
  • the fin transistor is a fin field-effect transistor (Fin Field-Effect Transistor, abbreviated as FinFET). It is a new complementary metal oxide semiconductor transistor.
  • FinFET can improve circuit control, reduce leakage current, and shorten the gate length of the transistor, thereby further improving the storage performance of the storage device 200.
  • the above-mentioned negative capacitance transistor M2 is a buried trench transistor.
  • the negative capacitance transistor M2 can also reduce the thickness of the memory device 200 while ensuring a higher gate control capability, so that the memory is developed towards lightness, thinness and miniaturization.
  • the negative capacitance transistor M2 is a fin transistor
  • the fin transistor may be a buried channel transistor.
  • the above fin transistors can be silicon-on-insulator (SOI) fin transistors or bulk silicon fin transistors.
  • SOI silicon-on-insulator
  • bulk silicon fin transistors As for the types of capacitors, you can choose Stacked Capacitor (SC) or Trench Capacitor (TC).
  • the memory device provided by the embodiment of the application is composed of bulk silicon fin transistors and stacked capacitors.
  • a bulk silicon fin transistor mainly includes a substrate 210 (such as a silicon substrate) having a fin structure FIN, an insulating layer 220, a gate structure G, a source structure S, a drain structure D, and so on.
  • the stacked capacitor includes an upper electrode PC, a lower electrode SN, and a capacitive dielectric layer CI provided between the upper electrode PC and the lower electrode SN.
  • the fin structure FIN and the substrate 210 are an integral structure.
  • the insulating layer 220 is formed on the area of the substrate 210 that is not covered by the fin structure FIN.
  • the insulating layer 220 may be formed on the substrate 210 in an area not covered by the fin structure FIN by using a shallow trench isolation technology.
  • the cross-sectional shape of the fin structure FIN can be rectangular, trapezoidal or heterogeneous, and is not limited here.
  • the above-mentioned fin structure FIN passes through the gate structure G.
  • various process methods can be used to fabricate the gate structure G in the region where the fin structure FIN is used to form the conductive channel.
  • There are various process methods for fabricating the gate structure For example: atomic layer deposition (ALD), chemical vapor deposition (chemical vapor deposition, CVD), physical vapor deposition (PVD), evaporation and reflow processes.
  • the source structure S and the drain structure D described above are formed on the fin structure FIN.
  • ion implantation can be used to form the source structure S and the drain structure D on the surface of the fin structure FIN away from the substrate 210.
  • the gate structure G is located between the source structure S and the drain structure D.
  • two inner walls SW can be arranged in the gap, so that the gate structure G passes through one of the inner walls SW and the drain.
  • the pole structure D and the fin structure FIN are electrically isolated, and are electrically isolated from the source structure S and the fin structure FIN by another inner wall SW. It should be understood that the bottoms of the two inner walls SW should be in contact with the substrate 210 (that is, the bottoms of the two inner walls should be flush with the roots of the fin structure FIN) to ensure the effectiveness of electrical isolation.
  • the above-mentioned bulk silicon fin transistor further includes conductive contact layers formed on the surface of the source structure S away from the substrate 210 and the drain structure D away from the surface of the substrate 210.
  • the conductive contact layer contains a material with high conductivity and relatively low resistance. Since the conductivity of the conductive contact layer is relatively high, the loss of electrical signals can be reduced. Therefore, when accessing data, it can be ensured that the accuracy of the data stored in the capacitor or the data taken out from the capacitor is relatively high.
  • a combination of a physical sputtering process and an annealing process may be used to form a conductive contact layer on the surface of the source structure S away from the substrate 210 and the drain structure D away from the substrate 210.
  • a physical sputtering process is used to sputter titanium on the surface of the source structure S away from the substrate 210 and the drain structure D away from the surface of the substrate 210, and then an annealing process is used for the titanium metal Annealing makes the titanium metal film silicidated to form TiSi 2 .
  • both the surface of the source structure S away from the substrate 210 and the surface of the drain structure D away from the substrate 210 form a conductive contact layer made of TiSi 2.
  • the source structure S away from the surface of the substrate 210 forms a capacitor conductive contact layer SNY, and the drain structure D away from the surface of the substrate 210 forms a bit line conductive contact layer BLY.
  • the bulk silicon fin transistor After the bulk silicon fin transistor is fabricated, it is necessary to deposit an interlayer dielectric layer ILC on the surface of the bulk silicon fin transistor as a planarization layer, and use the interlayer dielectric layer ILC to open bit line contact holes The BLC and the capacitor contact hole SNC, so that the bit line BL formed on the surface of the interlayer dielectric layer ILC away from the substrate 210 and the bottom electrode PC of the stacked capacitor can be electrically connected to the bulk silicon fin transistor.
  • the word line signal is transmitted through the word line WL arranged in the same layer.
  • the bit line BL may contact the bit line conductive contact layer BLY through the bit line contact hole BLC.
  • the bit line contact hole BLC provides an electrical connection channel for the bit line conductive contact layer BLY and the bit line BL.
  • the lower electrode SN of the stacked capacitor can be electrically connected to the capacitor conductive contact layer SNY through the capacitor contact hole SNC, and the upper electrode PC of the stacked capacitor is connected to the power supply line VDD.
  • the capacitor contact hole SNC provides an electrical connection channel for the capacitor conductive contact layer SNY and the capacitor contact hole SNC, and the power line VDD is formed on the surface of the upper electrode PC of the stacked capacitor to provide a power signal to the upper electrode PC.
  • FIG. 11 shows a schematic structural diagram of a memory provided in an embodiment of the present application.
  • the memory 300 includes at least one storage device and peripheral circuits.
  • the storage device may be the storage device 210 shown in FIGS. 5 to 10.
  • the peripheral circuit may be the peripheral circuit 122 shown in FIG. 2.
  • the peripheral circuit 122 shown in FIG. 2 is electrically connected to at least one negative capacitance transistor C2 and a capacitor C2 included in the storage device 210 shown in FIG. 5.
  • the memory 300 shown in FIG. 11 includes a plurality of storage devices 200 shown in FIG. 5.
  • a plurality of memory devices 200 share the substrate 11 shown in FIG. 11.
  • Peripheral circuits, storage devices, and capacitors may constitute the intermediate layer 320 shown in FIG. 11.
  • the memory 300 shown in FIG. 11 includes a plurality of storage devices 200 shown in FIG. 5, as shown in FIG. 11, the memory 300 includes a substrate 310, In addition to the intermediate layer 320, it also includes an isolation structure (not shown in FIG. 11), a passivation layer 330, and a pressure point structure 340. Both the peripheral circuit 122 and the isolation structure shown in FIG. 2 are formed on the substrate 210.
  • the passivation layer 330 covers the surface of the intermediate layer 320 away from the substrate 310.
  • the pressure point structure 340 is formed on the surface of the passivation layer 330 away from the substrate 210. At this time, the pressure point structure is electrically connected to the peripheral circuit.
  • the negative capacitance transistors M2 included in the plurality of memory devices 200 shown in FIG. 5 are electrically isolated from each other by the isolation structure.
  • the pressure point structure 340 can receive a signal input from an external device through a pin, or output data output from a memory through a pin.
  • an embodiment of the present application also provides a method for manufacturing a memory.
  • the manufacturing method of the memory includes:
  • Step S101 Provide a substrate.
  • the substrate is generally a semiconductor substrate such as silicon and germanium.
  • Step S102 forming at least one negative capacitance transistor on the surface of the substrate.
  • the negative capacitance transistor is the negative capacitance transistor M2 shown in FIG. 5.
  • the type of the negative capacitance transistor it can be a PMOS negative capacitance transistor or an MMOS negative capacitance transistor, which is not limited here. It should be understood that whether the substrate is a P-type substrate or an N-type substrate should be determined according to the type of the negative capacitance transistor.
  • the negative capacitance transistor is a PMOS negative capacitance transistor, the substrate is an N-type substrate.
  • the negative capacitance transistor is an NMOS negative capacitance transistor, the substrate is a P-type substrate.
  • Step S103 forming a peripheral circuit above the substrate.
  • the specific circuit composition of the peripheral circuit can be referred to the related description in FIG. 2, which will not be described in detail here.
  • the peripheral circuit includes a plurality of logic transistors.
  • forming a peripheral circuit on the surface of the substrate includes:
  • the gate structure of a plurality of logic transistors is formed above the substrate; the source structure and the drain structure of a plurality of logic transistors are formed above the substrate. It should be understood that, here is only a simple description of forming a peripheral circuit above the substrate, and each logic transistor also includes other layers such as an insulating layer.
  • Step S104 At least one negative capacitance transistor is electrically connected to the peripheral circuit.
  • the electrical connection here can be interconnected through interconnection lines. This step is also called Zhongdao Interconnection. It should be understood that the interconnection of the negative capacitance transistor and the peripheral circuit can be referred to the foregoing, and will not be described in detail here.
  • Step S105 forming at least one capacitor above the substrate, and at least one negative capacitor transistor and the at least one capacitor are electrically connected to form at least one storage device.
  • the capacitor can be the capacitor C2 shown in FIG. 5.
  • the electrical connection here can be interconnected through interconnection lines.
  • the interconnection method is one-to-one correspondence interconnection, that is, a capacitor is interconnected with a negative capacitance transistor. It should be understood that the specific forming position of the capacitor should be determined here according to the different types of capacitors. For example: when the capacitor is a stacked capacitor, the capacitor should be located above the negative capacitance transistor.
  • Step S106 electrically connect at least one capacitor and the peripheral circuit together.
  • the electrical connection here can be interconnected through interconnection lines, of course, other ways of interconnection can also be selected, which is not limited in detail.
  • the manufacturing method of the memory provided in the embodiment of the present application has the same beneficial effects as the storage device provided in the foregoing embodiment, and will not be repeated here.
  • the manufacturing method of the above-mentioned memory further includes an assembly process and a packaging process.
  • the manufacturing method of the above-mentioned memory further includes an assembly process and a packaging process.
  • the above-mentioned negative capacitance transistor includes a gate structure, a source structure, a drain structure, and the like of a conventional transistor.
  • the gate structure included in the above-mentioned negative capacitance transistor may refer to the foregoing description of the gate structure of the negative capacitance transistor M2.
  • the gate structure of the negative capacitance transistor M2 is a ferroelectric gate stack structure.
  • the gate structure or the ferroelectric gate stack structure should include a gate conductive layer and at least one dielectric layer stacked together.
  • the at least one dielectric layer is located between the substrate and the gate conductive layer.
  • At least one of the at least one dielectric layer is a ferroelectric dielectric layer.
  • the above-mentioned negative capacitance transistor may be a fin transistor or a buried channel transistor.
  • forming at least one negative capacitance transistor on the surface of the substrate includes: forming a plurality of negative capacitance transistors on the surface of the substrate.
  • the manufacturing method of the above-mentioned memory further includes:
  • the isolation structure is formed on the surface of the substrate, so that a plurality of negative capacitance transistors are electrically isolated from each other through the isolation structure.
  • the isolation structure may be a junction isolation structure, a dielectric isolation structure, a local oxidation isolation structure, a trench isolation structure, etc., but it is not limited to the list, and will not be listed here.
  • the manufacturing method of the above-mentioned memory further includes:
  • a passivation layer 330 is formed on the surface of the isolation structure, multiple negative capacitance transistors, multiple electrical and peripheral circuits away from the substrate; a pressure point structure 340 is formed on the surface of the passivation layer 330 away from the substrate 310 that is electrically connected to the peripheral circuit, Refer to Figure 11 for the specific structure.
  • the manufacturing method of the memory provided by the embodiment of the present application will be described below with reference to FIG. 13. It should be understood that the storage devices included in the memory shown in FIG. 13 are the storage devices shown in FIGS. 6 to 11 as examples.
  • Step S201 Provide a substrate 210.
  • Step S202 forming a fin structure FIN on the surface of the substrate 210.
  • the number of fin structures FIN is not limited here, and can be determined according to the actual process.
  • Step S203 using a shallow trench trench isolation method to form an insulating layer 220 in a region of the substrate 210 where the fin structure FIN is not formed.
  • Step S204 forming a plurality of gate structures G of bulk silicon fin transistors in the fin structure FIN.
  • Step S205 forming the source structure S and the drain structure D of a plurality of bulk silicon fin transistors in the fin structure FIN to obtain a plurality of bulk silicon fin transistors. It should be understood that the structure of each bulk silicon fin transistor can be referred to the foregoing, and will not be repeated here.
  • Step S206 forming an isolation structure on the surface of the substrate 210, so that a plurality of bulk silicon fin transistors are electrically isolated from each other through the isolation structure.
  • Step S207 forming the gate structure, the source structure and the drain structure of the peripheral circuit on the surface of the insulating layer 220 away from the substrate 210. At this time, the transistors included in the peripheral circuit and the already fabricated bulk silicon fin transistor share the insulating layer 220, which can effectively simplify the memory fabrication process.
  • Step S208 interconnect multiple bulk silicon fin transistors with peripheral circuits.
  • Step S209 forming an interlayer dielectric layer ILD on the surface of the plurality of bulk silicon fin transistors and the surface of the peripheral circuit.
  • Step S210 forming a plurality of stacked capacitors and a bit line BL on the surface of the interlayer dielectric layer ILD facing away from the substrate 210, and the plurality of stacked capacitors are electrically connected to the plurality of bulk silicon fin transistors in a one-to-one correspondence.
  • each stacked capacitor passes through the capacitor contact hole SNC opened by the interlayer dielectric layer ILC and the source structure S of the corresponding bulk silicon fin transistor. Electric connection.
  • the bit line BL it is electrically connected to the drain structure D of the bulk silicon fin transistor through the bit line contact hole BLC opened in the interlayer dielectric layer ILC.
  • Step 211 interconnect multiple stacked capacitors with peripheral circuits. That is, when the peripheral circuit includes a power supply circuit, the upper electrode PC included in each stacked capacitor is interconnected with the power supply circuit included in the peripheral circuit through the power supply line VDD. It should be understood that when the step 210 is completed, the fabricated structure is essentially the intermediate layer 320 without the passivation layer 330 and the pressure point structure 340 in FIG. 11.
  • Step S212 forming the passivation layer 330 shown in FIG. 11 on the surface of the isolation structure, multiple bulk silicon fin transistors, multiple stacked capacitors, and peripheral circuits away from the substrate 210.
  • Step S213 forming the pressure point structure 340 shown in FIG. 11 that is electrically connected to the peripheral circuit on the surface of the passivation layer away from the substrate 210.
  • an embodiment of the present application also provides a chip.
  • the chip includes the memory described in the above embodiment.
  • the beneficial effects of the chip provided by the embodiments of the present application are the same as the beneficial effects of the memory device 200 shown in FIGS. 5 to 10, and will not be repeated here.
  • FIG. 14 shows a schematic structural diagram of an electronic device provided in an embodiment of the present application.
  • the electronic device 400 includes a memory 410.
  • the memory 410 is the memory 300 shown in FIG. 11.
  • the above-mentioned electronic device 400 further includes a processor 420 that communicates with the memory 410.
  • the memory 410 and the processor 420 included in the above electronic device 400 may be integrated with devices such as a communication interface and packaged into a chip to form a chip applied to an electronic device.
  • FIG. 15 shows a schematic structural diagram of a chip provided by an embodiment of the present application.
  • the chip 500 may be a chip applied to the electronic device 400 shown in FIG. 14.
  • the chip 500 includes a processor 510, a memory 520, and a communication interface 530.
  • the processor 510, the communication interface 530, and the memory 520 are coupled together through a bus system 540.
  • the memory 520 is the memory 300 described in FIG. 11.
  • the above-mentioned memory 520 is used to store computer programs, instructions, and data.
  • the aforementioned processor 510 may be a single-core processor or a dual-core processor, and is configured to run a computer program or instruction, and execute the method or step represented by the computer program or instruction.
  • the above-mentioned communication interface 530 uses any device such as a transceiver to communicate with other devices or communication networks.
  • the above-mentioned bus system 540 has a path for transferring information between the above-mentioned components.
  • the bus system 540 may also include a power bus, an address bus, a read-write control bus, and a data bus.
  • various buses are marked as bus systems in FIG. 15.

Abstract

一种存储器件、存储器及其制作方法、电子设备和芯片，涉及存储器技术领域，以延长存储器件数据保存时长，从而提高存储器件的存储能力。所述存储器件（200）包括衬底（210）以及形成在衬底（210）上的负电容晶体管（M2）以及与负电容晶体管（M2）电连接的电容（C2）。所述存储器包括上述存储器件（200），所述存储器件用于电子设备中。

Description

一种存储器件、存储器及其制作方法、电子设备和芯片
本申请要求于2019年12月27日提交中国国家知识产权局、申请号为201911382949.1、发明名称为“一种存储器件、存储器及其制作方法、电子设备和芯片”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及存储器技术领域,尤其涉及一种存储器件、存储器及其制作方法、电子设备和芯片。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，缩写为DRAM)，是一种最为常见的系统内存。它主要包括存储器件和外围电路，存储器件是DRAM的核心，用以存储数据。
对于DRAM来说，存储器件包括晶体管和电容。晶体管用以控制存储器件的数据读取和编程，电容用以存储数据。同时，DRAM还周期性刷新存储器件，以提高存储器件的存储能力。但是，周期性刷新存储器件无法从根本上提高DRAM的存储能力。
发明内容
本申请的目的在于提供一种存储器件、存储器及其制作方法、电子设备和芯片，以延长存储器件数据保存时长，从而提高存储器件的存储能力。
为了实现上述目的，本申请提供一种存储器件。该存储器件包括：
衬底；
形成在所述衬底上的负电容晶体管以及与所述负电容晶体管电连接的电容，所述负电容晶体管用于控制所述存储器件的漏电程度。
可选的，所述负电容晶体管含有的栅极结构为铁电栅极堆叠结构。
可选的，所述负电容晶体管含有的栅极结构包括栅极导电层以及层叠设在一起的至少一层介电层，所述至少一层介电层位于所述衬底与所述栅极导电层之间，所述至少一层介电层中至少一层介电层为铁电介电层。
可选的，所述负电容晶体管为鳍式晶体管或埋沟式晶体管。
与现有技术相比，本申请提供的存储器件中，在衬底上形成有负电容 晶体管以及与所述负电容晶体管电连接的电容。而负电容晶体管具有超陡亚阈摆幅、更小的阈值电压、更快的开关速率以及更小漏电流，使得负电容晶体管具有极高的栅控能力。由此可见，本申请提供的存储器件含有负电容晶体管时，存储器件具有较小的漏电流。当存储器件具有较小的漏电流时，由于存储器件的数据保存时长与存储器件的漏电流呈反比，因此，当负电容晶体管处于关断状态时，存储器件具有比较久的数据保存时长，这不仅提高了存储器件的存储性能，而且还可以在一定程度上降低存储器件的刷新频率，达到降低功耗的目的。
本申请还提供一种存储器。该存储器包括至少一个上述技术方案所述存储器件和外围电路；所述外围电路与至少一个所述存储器件所包括的负电容晶体管电连接。
可选的，所述存储器件为多个，多个所述存储器件包括的负电容晶体管和电容形成在同一所述衬底上；所述存储器还包括隔离结构、钝化层以及与所述外围电路电连接的压点结构，所述隔离结构和所述外围电路均形成在所述衬底上；多个所述存储器件包括的负电容晶体管通过所述隔离结构相互电学隔离；所述钝化层覆盖在所述隔离结构、多个所述负电容晶体管、多个所述电容和所述外围电路背离衬底的表面；所述压点结构形成在所述钝化层背离衬底的表面。
与现有技术相比，本申请提供的存储器的有益效果与上述技术方案所述存储器件的有益效果相同，在此不做赘述。
本申请还提供一种存储器的制作方法，其特征在于，包括：
提供一衬底；
在所述衬底的表面形成至少一个负电容晶体管；在所述衬底的上方形成外围电路；将所述至少一个负电容晶体管与所述外围电路电连接在一起；
在所述衬底的表面形成至少一个电容；所述至少一个电容与所述至少一个负电容晶体管电连接为至少一个存储器件；
将所述至少一个电容与所述外围电路电连接在一起。
可选的，所述负电容晶体管含有的栅极结构为铁电栅极堆叠结构。
可选的，所述负电容晶体管含有的栅极结构包括栅极导电层以及层叠设在一起的至少一层介电层，所述至少一层介电层位于所述衬底与所述栅极导电层之间，所述至少一层介电层中至少一层为铁电介电层。
可选的，所述负电容晶体管为鳍式晶体管或埋沟式晶体管。
可选的，所述至少一个电容和所述至少一个负电容晶体管为多个；所述在所述衬底的表面形成至少一个负电容晶体管后，所述在所述衬底的表面形成外围电路前，所述存储器的制作方法还包括：
在所述衬底的表面形成隔离结构，使得多个所述负电容晶体管通过所述隔离结构相互电学隔离；
所述将所述至少一个电容与所述外围电路电连接在一起后，所述存储器的制作方法还包括：
在所述隔离结构、多个所述负电容晶体管、多个所述电容和所述外围电路背离衬底的表面形成钝化层；
在所述钝化层背离衬底的表面形成与所述外围电路电连接的压点结构。
与现有技术相比，本申请实施例提供的存储器的制作方法的有益效果与上述技术方案所述存储器件的有益效果相同，在此不做赘述。
本申请还提供一种电子设备。该电子设备包括上述技术方案所述存储器。
可选的，所述电子设备还包括处理器；所述处理器与所述存储器电连接。
与现有技术相比，本申请提供的电子设备的有益效果与上述技术方案所述存储器的有益效果相同，在此不做赘述。
本申请还提供一种芯片。该芯片包括上述技术方案所述存储器。
可选的，所述芯片还包括与所述存储器电连接的处理器。
与现有技术相比，本申请提供的芯片的有益效果与上述技术方案所述存储器件的有益效果相同，在此不做赘述。
附图说明
此处所说明的附图用来提供对本申请的进一步理解，构成本申请的一部分，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在附图中：
图1为现有技术中电子设备的结构示意图；
图2为现有技术中电子设备的结构框图；
图3为现有技术中存储阵列的结构示意图；
图4为现有技术中存储器件的电路结构示意图；
图5为本申请实施例提供的存储器件的电路结构示意图；
图6为本申请实施例提供的存储器件的立体结构示意图；
图7为本申请实施例提供的存储器件沿鳍状结构延伸方向的剖视图一；
图8为本申请实施例提供的存储器件沿栅极结构延伸方向的剖视图一；
图9为本申请实施例提供的存储器件沿鳍状结构延伸方向的剖视图二；
图10为本申请实施例提供的存储器件沿栅极结构延伸方向的剖视图二；
图11为本申请实施例提供的存储器的结构示意图；
图12为本申请实施例提供的存储器的制作方法的主体流程图；
图13为本申请实施例提供的存储器的制作方法的具体流程图；
图14为本申请实施例提供的电子设备的结构示意图；
图15为本申请实施例提供的芯片结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
在附图中示出本申请实施例的各种示意图，这些图并非按比例绘制。其中，为了清楚明白的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能呢由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
以下，术语“第一”、“第二”等仅用于描述目的，而不能理解为指示或暗示相对重要性或隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
此外，本申请中，“上”、“下”等方位术语是相对于附图中的部件示意置放的方位来定义，应当能理解到，这些方向性术语是相对概念，它们用于相对的描述和澄清，其可以根据附图中部件所放置的方位变化而相应地发生变化。
在本申请中，除非另有明确的规定和限定，术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以是通过中间媒介间接相连。
图1示出了现有技术中电子设备的结构示意图。该电子设备可以计算机、手机、基站、服务器等，但不仅限于此。该电子设备包括处理器110和动态随机存取存储器120(Dynamic Random Access Memory，缩写为DRAM)。处理器110与DRAM电连接。处理器110可以向DRAM中存储数据或读取DRAM所存储的数据。
其中，如图1所示，处理器110可以是一个处理器，也可以是多个处理元件的统称。例如，该处理器110可以是中央处理器(Central Processing Unit，简称CPU)，也可以是特定集成电路(Application Specific Integrated Circuit，简称ASIC)，或者是被配置成实施本申请实施例的一个或多个集成电路，例如：一个或多个微处理器(digitalsignal processor，简称DSP)，或，一个或者多个现场可编程门阵列(Field ProgrammableGate Array，简称FPGA)。
图2示出了现有技术中电子设备的结构框图。如图2所示，动态随机存取存储器120包括存储阵列121、外围电路122和互联线路(图2未示出)。存储阵列121包括阵列化排布的存储器件1210。外围电路122包括逻辑电路1221、输入输出电路1222、地址译码器1223和电源电路(图2未示出)等。
图2仅是示例的示出外围电路所包括的一些电路和各个电路之间的主要连接关系，并未示例出逻辑电路1221与各个电路之间的连接关系。但应当理解，逻辑电路1221与地址译码器1223之间、逻辑电路1221与电源电路之间、逻辑电路1221与输入输出电路1222之间、存储阵列121与地址译码器1223之间、存储阵列121与电源电路之间、存储阵列121与输入输出电路1222之间、地址译码器1223与输入输出电路1222之间均通过互联线路互联在一起。
如图2所示，上述输入输出电路1222包括感知放大器、数据寄存器、 地址寄存器等。为了支持处理器存取DRAM所存储的数据，上述电子设备还包括系统总线IOB0以及分别与系统总线IOB0耦接的地址总线IOB1、数据总线IOB2和读写控制总线IOB3。处理器110与地址寄存器通过地址总线IOB1电连接，处理器110与输入输出电路1222通过数据总线IOB2电连接，处理器110与逻辑电路1221通过读写控制总线IOB3电连接。
如图2所示，处理器110向存储阵列121发送数据地址和存取指令，输入输出电路1222中的地址寄存器可以根据数据地址查找目标地址，并发送至地址译码器1223。地址译码器1223根据目标地址解析出所需的目标地址，地址译码器1223在逻辑电路1221的控制下根据所需的目标地址从存储阵列121选中与目标地址匹配的存储器件1210。当存取指令为读取指令时，存储器件1210通过输入输出电路1222所包括的数据寄存器输出数据。所输出的数据通过数据总线传输至处理器。当存取指令为写入指令时，处理器110通过数据总线将数据送入输入输出电路1222所包括的数据寄存器，在逻辑电路1221的控制下输入输出电路1222所包括的数据寄存器将数据送入选中的存储器件1210，以利用存储器件1210保存数据。
示例性的，图3示例出现有技术中存储阵列的结构示意图。如图3所示，该存储阵列121包括矩阵化的存储器件1210。该矩阵化的存储器件1210包括5行存储器件1210和6列存储器件1210。相应的，上述互联线路含有5个字线WL和6个位线BL。上述地址译码器12231223包括行译码器1223R和列译码器1223C。行译码器1223R通过5条字线WL与5行存储器件1210一一对应连接，用以向对应存储器件1210提供行选通信号控制对应列的存储器件1210打开，上述列译码器1223C通过6条位线BL与6列存储器件1210一一对应连接，用以控制对应存储器件1210提供行选通信号控制对应列的存储器件1210输出或存入数据。
图4示出了现有技术中存储器件的结构示意图。如图4所示，对于DRAM来说，每个存储器件1210包括衬底(图4未示出)以及形成在衬底上的晶体管M1和电容C1。晶体管M1的栅极与字线WL连接，晶体管M1的第一电极与位线BL电连接，晶体管M1的第二电极与电容C1电连接。晶体管的类型可以根据实际需要选择，如常见的NMOS或PMOS均可以。至于晶体管M1的第一电极和第二电极是源极还是漏极，则可以根据常规技术决定。晶体管M1用以控制存储器件1210的数据读取和编程，电容C1用以存储数据。由于电容C1容易漏电，导致电容C1所存储的数 据信号丢失，因此，图3所示的存储阵列121中，电源电路(图3未示出)还通过6条电源线(图3未示出)与电容C1电连接，以在逻辑电路1221的控制下，电源电路周期性通过6条电源线一一对应的向6列存储器件1210所含有的存储单元充电，从而保证电容C1所存储的数据信号不被丢失，提高存储器件1210的存储性能。但是，存储器件1210仍然存在漏电，使得周期性刷新存储器件1210无法从根本上提高DRAM的存储能力。
针对上述问题，发明人对图4所示的存储器件1210进行分析发现：由于存储器件1210的数据保存时长与存储器件1210的漏电流的增大而减小。而存储器件1210的漏电流不仅来自电容C1，而且来自晶体管M1等。基于此，图5示出了本申请实施例提供的存储器件的结构示意图。如图5所示，该存储器件200应用于DRAM。并且，当存储器件200应用于DRAM时，存储器件200与DRAM的外围电路互联方式可以参考前文，下文不在详细描述。
如图5～图10所示，上述存储器件200包括衬底210以及形成在衬底210上的负电容晶体管M2以及与负电容晶体管M2电连接的电容C2。应理解，此处衬底210可以为半导体衬底，其材料可以为硅、锗等半导体材料。
如图5所示，由于负电容晶体管M2具有超陡亚阈摆幅、更小的阈值电压、更快的开关速率以及更小漏电流，使得负电容晶体管M2具有极高的栅控能力，因此，当负电容晶体管M2在关断状态时，负电容晶体管M2的漏电流比较小，使得存储器件200的漏电流相对降低，当存储器件200具有较小的漏电流时，由于存储器件200的数据保存时长与存储器件200的漏电流呈反比，因此，当负电容晶体管M2处于关断状态时，存储器件200具有比较久的数据保存时长，这不仅提高了存储器件200的存储性能，而且还可以在一定程度上降低存储器件200的刷新频率，达到降低功耗的目的。
作为一种可能的实现方式，如图6所示，上述负电容晶体管M2包括常规晶体管所具有的栅极结构G和两个电极结构。如图7和图9所示，这两个电极结构中一个电极结构为源极结构S，另一个电极结构为漏极结构D等。至于负电容晶体管M2的类型，可以为PMOS负电容晶体管或MMOS负电容晶体管，此处不做限定。
示例性的，如图7和图9所示，当上述负电容晶体管M2为PMOS负 电容晶体管时，则上述栅极结构G和源极结构S均与输入输出电路电连接，漏极结构D与电容C2电连接。当上述负电容晶体管M2为NMOS负电容晶体管时，则上述栅极结构G和漏极结构D均与输入输出电路电连接，源极结构S与电容C2电连接。
在一种可选方式，如图5和图6所示，上述栅极结构G为铁电栅极堆叠结构。这种铁电栅极堆叠结构可以提高负电容晶体管M2的栅控能力，并降低负电容晶体管M2的功耗。
在一种可选方式，如图7～图10所示，上述栅极结构G或者说铁电栅极堆叠结构包括栅极导电层GE以及层叠设在一起的至少一层介电层GI。该至少一层介电层GI位于栅极导电层GE与衬底210之间。至少一层介电层GI中至少一层为铁电介电层。此时，这种栅极结构G可以提高负电容晶体管M2的栅控能力，并降低负电容晶体管M2的功耗。
在第一种示例中，如图7和图8所示，当至少一层介电层GI包括：层叠在一起的第一介电层GI1和第二介电层GI2。第二介电层GI2为铁电介电层。第二介电层GI2位于栅极导电层GE和第一介电层GI1之间。并且，第一介电层GI1、第二介电层GI2和栅极导电层GE沿着背离衬底210的方向依次层叠。
在第二种示例中，如图9和图10所示，当至少一层介电层GI包括：依次层叠在一起的第一介电层GI1、第二介电层GI2以及与栅极导电层GE相邻的第三介电层GI3。第三介电层GI3为铁电介电层。第二介电层GI2位于第一介电层GI1和第三介电层GI3之间。并且，第一介电层GI1、第二介电层GI2、第三介电层GI3和栅极导电层GE沿着远离衬底210的方向依次层叠。
需要说明的是，如图6～图8所示，上述栅极导电层GE可以为金属栅极或多晶硅栅极，当然也可以是氧化铟锡等导电材料所制作的栅极。
上述铁电介电层可以为半导体、稀土中的一种或两种的氧化物所制备的介电层，一般可以用铁电HMOx表示铁电介电层所含有的材料。M可以为半导体或者稀土。应理解，此处半导体可以为硅、锆中的一种或两种，但不限于此。稀土可以为镧、钇中的一种或两种，但不限于此。例如，该铁电介电层为含有锆的氧化物。这种氧化物不仅可以含有锆，而且还可以含有其他半导体、稀土等。
如图7和图8所示，上述第一介电层GI1可以为普通的绝缘层220， 其可以是采用有机绝缘材料、无机氧化物所形成的介电层。例如：第一介电层GI1可以为光刻胶等制作的介电层。又例如：第一介电层GI1可以为氧化硅、氧化铝等材料制作的介电层。
作为一种可能的实现方式，如图5所示，上述负电容晶体管M2为鳍式晶体管。例如：鳍式晶体管为鳍式场效应晶体管(Fin Field-Effect Transistor，缩写为FinFET)。它是一种新的互补式金氧半导体晶体管。FinFET可以改善电路控制并减少漏电流，缩短晶体管的闸长，从而进一步提高存储器件200的存储性能。
作为一种可能的实现方式，如图5所示，上述负电容晶体管M2为埋沟式晶体管。此时，负电容晶体管M2还可以在保证较高的栅控能力的同时，降低存储器件200的厚度，使得存储器向轻薄化和小型化发展。例如：当负电容晶体管M2为鳍式晶体管时，鳍式晶体管可以为埋沟式晶体管。
对于鳍式晶体管来说，如图6～图10所示，上述鳍式晶体管可以为绝缘衬底上硅(silicon-on-insulator，缩写为SOI)鳍式晶体管，也可以为体硅鳍式晶体管。至于电容的种类，则可以选择堆叠式电容器(Stacked Capacitor，缩写为SC)或沟渠式电容器(Trench Capacitor，缩写为TC)。
下面结合图7～图10描述本申请实施例提供的存储器件。应理解，以下描述仅用于解释，不作为限定。
本申请实施例提供的存储器件由体硅鳍式晶体管和堆叠式电容器构成。具体来说，体硅鳍式晶体管主要包括具有鳍状结构FIN的衬底210(如硅衬底)、绝缘层220、栅极结构G、源极结构S和漏极结构D等。堆叠式电容器包括上电极PC、下电极SN以及设在上电极PC和下电极SN之间的电容介电层CI。
在实际结构中，鳍状结构FIN与衬底210为一体式结构。绝缘层220形成在衬底210上没有被鳍状结构FIN覆盖的区域。并且，绝缘层220可以采用浅槽隔离技术形成在衬底210上没有被鳍状结构FIN覆盖的区域。鳍状结构FIN的横截面形状可以为矩形、梯形或异性等形状，此处不做限定。
从结构上来说，上述鳍状结构FIN穿过栅极结构G。在工艺上来说，可以采用各种工艺方法在鳍状结构FIN用以形成导电沟道的区域制作栅极结构G。制作栅极结构的工艺方法多种多样。例如：原子层沉积(atomic layer deposition，缩写为ALD)、化学气相沉积(chemical vapor deposition，缩 写为CVD)、物理气相沉积(Physical Vapor Deposition，缩写为PVD)、蒸发和回流工艺等。
上述源极结构S和漏极结构D形成在鳍状结构FIN上。例如：可以采用离子注入的方式在鳍状结构FIN背离衬底210的表面形成源极结构S和漏极结构D。而且，栅极结构G位于源极结构S和漏极结构D之间。并且，为了保证栅极结构G与源极结构S、漏极结构D和鳍状结构FIN电学隔离，可以在空隙内设置两个内侧墙SW，使得栅极结构G通过其中一个内侧墙SW与漏极结构D和鳍状结构FIN电学隔离，通过另一个内侧墙SW与源极结构S和鳍状结构FIN电学隔离。应理解，两个内侧墙SW的底部应当与衬底210(即两个内侧墙的底部应当与鳍状结构FIN的根部平齐)接触，以保证电学隔离的有效性。
为了减少不必要的电学损耗，上述体硅鳍式晶体管还包括形成在源极结构S背离衬底210表面和漏极结构D背离衬底210表面的导电接触层。该导电接触层含有导电性高、电阻比较低的材料。由于该导电接触层的导电性比较高，可以减少电信号的损耗，因此，当存取数据时，可以保证存入电容的数据或从电容取出的数据准确性比较高。
示例性的，可以采用物理溅射工艺和退火工艺结合的方式在源极结构S背离衬底210表面和漏极结构D背离衬底210表面形成导电接触层。例如：当衬底210为硅衬底时，采用物理溅射工艺在源极结构S背离衬底210表面和漏极结构D背离衬底210表面溅射钛金属，然后采用退火工艺对钛金属进行退火，使得钛金属膜硅化，形成TiSi 2。此时，源极结构S背离衬底210表面和漏极结构D背离衬底210表面均形成材质为TiSi 2的导电接触层。
当上述体硅鳍式晶体管为N型体硅鳍式晶体管时，上述源极结构S背离衬底210表面形成电容器导电接触层SNY，上述漏极结构D背离衬底210表面形成位线导电接触层BLY。
在实际应用中，在完成体硅鳍式晶体管的制作后，需要在体硅鳍式晶体管表面沉积层间介电层ILC作为平坦化层，并采用在层间介电层ILC开设位线接触孔BLC和电容器接触孔SNC，以使得形成在层间介电层ILC远离衬底210的表面形成位线BL和堆叠式电容所具有的下电极PC可以与体硅鳍式晶体管电连接。至于栅极结构，则通过同层设置的字线WL传输字线信号。
当体硅鳍式晶体管为NMOS体硅鳍式晶体管时，位线BL可以通过位线接触孔BLC与位线导电接触层BLY接触。此时，位线接触孔BLC为位线导电接触层BLY与位线BL提供电连接通道。堆叠式电容器所具有的下电极SN可以通过电容器接触孔SNC与电容器导电接触层SNY电连接，堆叠式电容器所具有的上电极PC与电源线VDD连接。此时，电容器接触孔SNC为电容器导电接触层SNY和电容器接触孔SNC提供电连接通道，电源线VDD形成在堆叠式电容器所具有的上电极PC的表面，以向上电极PC提供电源信号。
图11示出了本申请实施例还提供一种存储器的结构示意图。如图10所示，该存储器300包括至少一个存储器件和外围电路。该存储器件可以为图5～图10所示的存储器件210。外围电路可以为图2所示的外围电路122。具体来说，图2所示的外围电路122与至少一个图5所示的存储器件210所包括的负电容晶体管C2和电容C2电连接。
与现有技术相比，本申请实施例提供的存储器的有益效果与本申请实施例描述的存储器件的有益效果相同，在此不做赘述。
应理解，当图11所示的存储器300包括多个图5所示的存储器件200。多个存储器件200共用图11所示的衬底11。外围电路、存储器件和电容可以构成图11所示的中间层320。
作为一种可能的实现方式，当图11所示的存储器300包括多个图5所示的存储器件200时，如图11所示，该存储器300除了包括多个存储器件共用的衬底310、中间层320外，还包括隔离结构(图11未示出)、钝化层330以及与压点结构340。图2所示的外围电路122和隔离结构均形成在衬底210上。钝化层330覆盖在中间层320背离衬底310的表面。压点结构340形成在钝化层330背离衬底210的表面。此时，该压点结构与外围电路电连接。并且，多个图5所示的存储器件200包括的负电容晶体管M2通过隔离结构相互电学隔离。压点结构340可以通过引脚接收外部设备所输入的信号，或者通过引脚输出存储器所输出的数据。
如图5所示，本申请实施例还提供一种存储器的制作方法。该存储器的制作方法包括：
步骤S101：提供一衬底。该衬底一般为硅、锗等半导体衬底。
步骤S102：在衬底的表面形成至少一个负电容晶体管。该负电容晶体管为图5所示的负电容晶体管M2。至于负电容晶体管的类型，可以为 PMOS负电容晶体管或MMOS负电容晶体管，此处不做限定。应理解，衬底为P型衬底还是N型衬底，应当根据负电容晶体管的类型决定。当负电容晶体管为PMOS负电容晶体管，则衬底为N型衬底。当负电容晶体管为NMOS负电容晶体管，则衬底为P型衬底。
步骤S103：在衬底的上方形成外围电路。外围电路的具体电路构成可以参考图2相关描述，此处不做详述。但从外围电路包括的各个电路含有的器件类型来说，外围电路包括多个逻辑晶体管。此时，在衬底的表面形成外围电路包括：
在衬底的上方形成多个逻辑晶体管的栅极结构；在衬底的上方形成多个逻辑晶体管的源极结构和漏极结构。应理解，此处只是简单描述了在衬底的上方形成外围电路，每个逻辑晶体管还包括绝缘层等其他膜层。
步骤S104：将至少一个负电容晶体管与外围电路电连接在一起。此处的电连接可以是通过互联线路进行互联。该步骤也称中道互联。应理解，负电容晶体管与外围电路的互联方式可以参考前文，此处不做详述。
步骤S105：在衬底的上方形成至少一个电容，至少一个负电容晶体管与至少一个电容电连接为至少一个存储器件。电容可以为图5所示的电容C2。此处的电连接可以是通过互联线路进行互联。互联方式是一一对应互联，即一个电容与一个负电容晶体管互联。应理解，此处应当根据电容类型的不同决定电容的具体形成位置。例如：当电容为堆叠式电容时，电容应当位于负电容晶体管的上方。
步骤S106：将至少一个电容与外围电路电连接在一起。此处的电连接可以是通过互联线路进行互联，当然也可以选择其他方式互联，不做详细限定。
与现有技术相比，本申请实施例提供的存储器的制作方法与上述实施例提供的存储器件的有益效果相同，此处不做赘述。
需要说明的是，为了保证上述存储器芯片化，在步骤S107后，上述存储器的制作方法还包括装配工艺和封装工艺，具体可以参考现有技术，此处不做限定。
作为一种可能的实现方式，上述负电容晶体管包括常规晶体管所具有的栅极结构、源极结构和漏极结构等。
示例性的，如图5～图10所示，上述负电容晶体管所包括的栅极结构可以参考前文有关负电容晶体管M2的栅极结构描述。但无论如何，负电 容晶体管M2的栅极结构均为铁电栅极堆叠结构。
并且，栅极结构或者说铁电栅极堆叠结构均应包括栅极导电层和层叠设在一起的至少一层介电层。该至少一个介电层位于衬底与栅极导电层之间。至少一层介电层中至少一层为铁电介电层。
作为一种可能的实现方式，上述负电容晶体管可以为鳍式晶体管或埋沟式晶体管。
作为一种可能的实现方式，上述至少一个电容和至少一个负电容晶体管为多个。此时，在衬底的表面形成至少一个负电容晶体管包括：在衬底的表面形成多个负电容晶体管。
示例性的，在衬底的表面形成至少一个负电容晶体管后，在衬底的上方形成外围电路前，上述存储器的制作方法还包括：
在衬底的表面形成隔离结构，使得多个负电容晶体管通过隔离结构相互电学隔离。隔离结构可以为结隔离结构、介质隔离结构、局部氧化隔离结构、沟道隔离结构等，但不仅限于所列，在此不做一一列举。
将至少一个电容与外围电路电连接在一起后，上述存储器的制作方法还包括：
在隔离结构、多个负电容晶体管、多个电和外围电路背离衬底的表面形成钝化层330；在钝化层330背离衬底310的表面形成与外围电路电连接的压点结构340，具体结构参考图11。
为了清楚的描述本申请实施例提供的存储器的制作方法，下面结合图12详细描述。应理解，下文仅是简单的介绍本申请实施例存储器的制作方法的主要步骤，具体细节步骤不做描述。
下面结合图13描述本申请实施例提供的存储器的制作方法。应理解，图13所示的存储器含有的存储器件以图6～图11所示的存储器件为例。
步骤S201：提供一衬底210。
步骤S202：在衬底210的表面形成鳍状结构FIN。此处鳍状结构FIN的数量不做限定，可以根据实际工艺决定。
步骤S203：采用浅槽沟道隔离方法在衬底210没有形成鳍状结构FIN的区域形成绝缘层220。
步骤S204：在鳍状结构FIN形成多个体硅鳍式晶体管的栅极结构G。
步骤S205：在鳍状结构FIN形成多个体硅鳍式晶体管的源极结构S和漏极结构D，获得多个体硅鳍式晶体管。应理解，每个体硅鳍式晶体管的 结构可参考前文，此处不做赘述。
步骤S206：在衬底210的表面形成隔离结构，使得多个体硅鳍式晶体管通过隔离结构相互电学隔离。
步骤S207：在绝缘层220背离衬底210的表面形成外围电路的栅极结构、源极结构和漏极结构。此时，外围电路所包括的晶体管与已经制作的体硅鳍式晶体管共用绝缘层220，可以有效简化存储器制作流程。
步骤S208：将多个体硅鳍式晶体管与外围电路进行互联。
步骤S209：在多个体硅鳍式晶体管的表面和外围电路的表面形成层间介电层ILD。
步骤S210：在层间介电层ILD背离衬底210的表面形成多个堆叠式电容器和位线BL，多个堆叠式电容器与多个体硅鳍式晶体管一一对应电连接。例如：当体硅鳍式晶体管为N型体硅鳍式晶体管时，每个堆叠式电容器通过层间介电层ILC所开设的电容器接触孔SNC与对应的体硅鳍式晶体管的源极结构S电连接。至于位线BL，则通过层间介电层ILC所开设的位线接触孔BLC与体硅鳍式晶体管的漏极结构D电连接。
步骤211：将多个堆叠式电容器与外围电路互联在一起。即外围电路包括电源电路的情况下，每个堆叠式电容器所包括的上电极PC通过电源线VDD与外围电路所含有的电源电路互联。应理解，当步骤210完后成，所制作的结构实质为图11中没有钝化层330和压点结构340的中间层320。
步骤S212：在隔离结构、多个体硅鳍式晶体管、多个堆叠式电容器和外围电路背离衬底210的表面形成图11所示的钝化层330。
步骤S213：在钝化层背离衬底210的表面形成图11所示的与外围电路电连接的压点结构340。
当上述存储器经过装配和封装后，上述存储器以芯片的形式存在。基于此，本申请实施例还提供一种芯片。该芯片包括上述实施例描述的存储器。与现有技术相比，本申请实施例提供的芯片的有益效果与图5～图10所示的存储器件200的有益效果相同，在此不做赘述。
图14示出了本申请实施例还提供一种电子设备的结构示意图。如图14所示，该电子设备400包括存储器410。存储器410为图11所示的存储器300。
与现有技术相比，本申请实施例提供的电子设备的有益效果与图5～图10所示的存储器件的有益效果相同，在此不做赘述。
作为一种可能的实现方式，如图14所示，上述电子设备400还包括与存储器410通信的处理器420。
在一些情况下，如图14所示，上述电子设备400所包括的存储器410和处理器420可以与通信接口等装置集成在一起，并封装成芯片，构成应用于电子设备的芯片。
图15示出了本申请实施例提供的一种芯片的结构示意图。如图15所示，该芯片500可以为应用于图14所示的电子设备400的芯片。如图15所示，该芯片500包括处理器510、存储器520和通信接口530。处理器510、通信接口530以及存储器520通过总线系统540耦合在一起。存储器520为图11所描述的存储器300。
如图15所示，上述存储器520用于存储计算机程序或指令、数据。上述处理器510可以为单核处理器或双核处理器，用于运行计算机程序或指令，执行计算机程序或指令所表示的方法或步骤。
如图15所示，上述通信接口530使用任何收发器一类的装置，用于与其他设备或通信网络通信。
如图15所示，上述总线系统540具有一通路，在上述组件之间传送信息。该总线系统540包括数据总线之外，还可以包括电源总线、地址总线、读写控制总线和数据总线等。但是为了清楚说明起见，在图15中将各种总线都标为总线系统。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于设备实施例而言，由于其基本相似于方法实施例，所以描述得比较简单，相关之处参见方法实施例的部分说明即可。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种存储器件，包括：
    衬底；
    形成在所述衬底上的负电容晶体管以及与所述负电容晶体管电连接的电容，所述负电容晶体管用于控制所述存储器件的漏电程度。
  2. 根据权利要求1所述的存储器件，其中，所述负电容晶体管含有的栅极结构为铁电栅极堆叠结构。
  3. 根据权利要求1所述的存储器件，其中，所述负电容晶体管含有的栅极结构包括栅极导电层以及层叠设在一起的至少一层介电层，所述至少一层介电层位于所述衬底与所述栅极导电层之间，所述至少一层介电层中至少一层为铁电介电层。
  4. 根据权利要求1～3任一项所述的存储器件，其中，所述负电容晶体管为鳍式晶体管或埋沟式晶体管。
  5. 一种存储器，其特征在于，包括外围电路和至少一个权利要求1～4任一项所述存储器件；所述外围电路与至少一个所述存储器件所包括的负电容晶体管和电容电连接。
  6. 根据权利要求5所述的存储器，其中，所述存储器件为多个，多个所述存储器件包括的负电容晶体管和电容形成在同一所述衬底上；所述存储器还包括隔离结构、钝化层以及与所述外围电路电连接的压点结构，所述隔离结构和所述外围电路均形成在所述衬底上；多个所述存储器件包括的负电容晶体管通过所述隔离结构相互电学隔离；所述钝化层覆盖在所述隔离结构、多个所述负电容晶体管、多个所述电容和所述外围电路背离衬底的表面；所述压点结构形成在所述钝化层背离衬底的表面。
  7. 一种存储器的制作方法，其中，包括：
    提供一衬底；
    在所述衬底的表面形成至少一个负电容晶体管；在所述衬底的上方形成外围电路；将所述至少一个负电容晶体管与所述外围电路电连接在一起；
    在所述衬底的上方形成至少一个电容，所述至少一个电容与所述至少一个负电容晶体管电连接为至少一个存储器件；
    将所述至少一个电容与所述外围电路电连接在一起。
  8. 根据权利要求7所述的存储器的制作方法，其中，所述负电容晶体管含有的栅极结构为铁电栅极堆叠结构。
  9. 根据权利要求7所述的存储器的制作方法，其中，所述负电容晶体管含有的栅极结构包括栅极导电层以及层叠设在一起的至少一层介电层，所述至少一层介电层位于所述衬底与所述栅极导电层之间，所述至少一层介电层中至少一层为铁电介电层。
  10. 根据权利要求7～9任一项所述的存储器的制作方法，其中，所述负电容晶体管为鳍式晶体管或埋沟式晶体管。
  11. 根据权利要求7～9任一项所述的存储器的制作方法，其中，所述至少一个电容和所述至少一个负电容晶体管为多个；所述在所述衬底的表面形成至少一个负电容晶体管后，所述在所述衬底的上方形成外围电路前，所述存储器的制作方法还包括：
    在所述衬底的表面形成隔离结构，使得多个所述负电容晶体管通过所 述隔离结构相互电学隔离；
    所述将所述至少一个电容与所述外围电路电连接在一起后，所述存储器的制作方法还包括：
    在所述隔离结构、多个所述负电容晶体管、多个所述电容和所述外围电路背离衬底的表面形成钝化层；
    在所述钝化层背离衬底的表面形成与所述外围电路电连接的压点结构。
  12. 一种电子设备，包括权利要求5或6所述存储器。
  13. 根据权利要求12所述的电子设备，其中，所述电子设备还包括处理器；所述处理器与所述存储器电连接。
  14. 一种芯片，其中，包括权利要求5或6所述存储器。
  15. 根据权利要求14所述的芯片，其中，所述芯片还包括与所述存储器电连接的处理器。
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