WO2023272536A1 - 铁电存储器及其形成方法、电子设备 - Google Patents

铁电存储器及其形成方法、电子设备 Download PDF

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Publication number
WO2023272536A1
WO2023272536A1 PCT/CN2021/103315 CN2021103315W WO2023272536A1 WO 2023272536 A1 WO2023272536 A1 WO 2023272536A1 CN 2021103315 W CN2021103315 W CN 2021103315W WO 2023272536 A1 WO2023272536 A1 WO 2023272536A1
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pole
ferroelectric
layer
semiconductor layer
memory
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PCT/CN2021/103315
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English (en)
French (fr)
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景蔚亮
黄凯亮
冯君校
王正波
吴颖
许俊豪
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华为技术有限公司
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Priority to PCT/CN2021/103315 priority Critical patent/WO2023272536A1/zh
Priority to CN202180095760.3A priority patent/CN117063625A/zh
Publication of WO2023272536A1 publication Critical patent/WO2023272536A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes

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  • the present application relates to the technical field of semiconductors, and in particular to a ferroelectric memory, its forming method, and electronic equipment containing the ferroelectric memory.
  • ferroelectric memory As a new type of memory, ferroelectric memory is more and more widely used due to its advantages of non-volatility, high speed and low power consumption compared with traditional dynamic random access memory (DRAM).
  • DRAM dynamic random access memory
  • existing ferroelectric memories include ferroelectric field effect transistor (ferroelectric filed-effect-transistor, FeFET) memories.
  • Fig. 1a, Fig. 1b and Fig. 1c show the process structure diagrams of memory cells in FeFET memories with three different structures.
  • the source 02 and the drain 03 of the memory cell are formed by doping the substrate 01, and a channel layer 04 is formed between the source 02 and the drain 03 of the substrate 01, and the channel layer 04 is formed in the channel A stacked insulating layer 05 and a gate 07 are formed above the track layer 04 , and a ferroelectric layer 06 for storing data information is formed between the insulating layer 05 and the gate 07 .
  • the gate 07 can be made of a metal material, so such a structure can be called a metal-ferroelectric-insulator-semiconductor (MFIS) memory cell structure.
  • MFIS metal-ferroelectric-insulator-semiconductor
  • the difference between the memory cell shown in FIG. 1b and the memory cell shown in FIG. 1a is that, on the basis of the structure in FIG. It is called a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) memory cell structure.
  • MFMIS metal-ferroelectric-metal-insulator-semiconductor
  • Figure 1c is a process structure diagram of another memory cell, in which the channel layer 04 has a columnar structure, the ferroelectric layer 06 surrounds the periphery of the channel layer 04, and an insulating layer 05 is used to connect the channel layer 04 and the ferroelectric layer 06, and the gate 07, source 02 and drain 03 are all around the periphery of the ferroelectric layer 06.
  • the channel layer 04 in this structure is a vertical channel perpendicular to the substrate, more memory cells can be integrated on the unit area of the substrate compared with the structure of the horizontal channel.
  • the channel layer 04 , the ferroelectric layer 06 and the insulating layer 05 are all columnar structures, and the radial size (as shown in the D direction of FIG. 1c) is relatively large, and there is also a large bottleneck in its reduction capability, so that the improvement of storage density is also limited.
  • the present application provides a ferroelectric memory and its forming method, and electronic equipment including the ferroelectric memory.
  • the main purpose is to provide a ferroelectric memory that can increase storage density and storage capacity.
  • the present application provides a ferroelectric memory, which includes: a substrate and a plurality of memory cells formed on the substrate, each memory cell includes a ferroelectric field effect transistor; wherein the ferroelectric field effect transistor Including a gate, a semiconductor layer (also referred to as a channel layer), a first pole and a second pole, and a ferroelectric layer; the first pole and the second pole are arranged along a first direction perpendicular to the substrate, The gate is located between the first pole and the second pole, and one of the opposite sides of the gate along the second direction has a semiconductor layer, that is to say, the semiconductor layer is not arranged around the periphery of the gate, or It is said that the gate will not be arranged around the periphery of the semiconductor layer, the semiconductor layer is electrically connected to the first pole and the second pole respectively, and the gate and the semiconductor layer are separated by a ferroelectric layer, wherein the second direction is defined as direction parallel to the substrate.
  • the ferroelectric field effect transistor Including a gate,
  • the ferroelectric field effect transistor formed in this way is a kind of channel with vertical
  • the channel transistor structure that is, the vertical planar channel structure transistor, can reduce the projected area of the memory on the substrate compared with the horizontal channel transistor, so as to increase the storage density and increase the storage capacity of the electric memory.
  • the ferroelectric field effect transistor in the ferroelectric field effect transistor, a semiconductor layer is provided on one of the opposite sides of the gate along the second direction, instead of surrounding the semiconductor along the periphery of the gate, further, it can By reducing the size of the entire ferroelectric field effect transistor in the second direction, the storage unit can be further miniaturized. Based on these characteristics, the ferroelectric field effect transistor can reach an occupied area of about 4F 2 , which is even larger than the existing 6F 2 The occupied area is smaller, and the storage unit has been effectively shrunk, so that more storage units can be integrated on the unit area of the substrate to increase the storage capacity.
  • the semiconductor layer is a vertical structure extending along the first direction, and one end of the opposite ends of the semiconductor layer along the first direction is in contact with the first pole, and the other end is in contact with the second pole. pole contact.
  • the semiconductor layer By arranging the semiconductor layer along a vertical structure and making ohmic contact with the first pole and the second pole, the semiconductor layer forms a vertical channel structure perpendicular to the substrate, thereby further enabling the memory cell to obtain miniature.
  • the semiconductor layer is a vertical structure extending along the first direction, the surface opposite to the second pole in the first pole is the first wall surface, and the surface opposite to the first pole in the second pole
  • the opposite surface of the semiconductor layer is the second wall surface; one of the opposite ends of the semiconductor layer along the first direction is in contact with the first wall surface, and the other end is in contact with the second wall surface.
  • the vertical semiconductor layer is arranged in the region between the first pole and the second pole.
  • the semiconductor layer is a vertical structure extending along the first direction, the surface opposite to the second pole in the first pole is the first wall surface, and the surface opposite to the first wall surface in the first pole is Adjacent to the first side; in the second pole, the opposite surface to the first pole is the second wall, and in the second pole, the second wall is adjacent to the second side, and the first side and the second side are at the same side; one end of the opposite ends of the semiconductor layer along the first direction is in contact with the first side face, and the other end is in contact with the second side face.
  • the semiconductor layer stands upright on one side of the first pole and the second pole.
  • the semiconductor layer includes a first portion and a second portion both extending along the second direction, and a third portion extending along the first direction and connected to the first portion and the second portion;
  • the surface opposite to the second pole in one pole is the first wall surface, and the surface opposite to the first pole in the second pole is the second wall surface; the first part is arranged on the first wall surface, and the second part is arranged on the second wall surface superior.
  • the contact area between the semiconductor layer and the first pole and the second pole can be increased to reduce the contact area between the first pole and the semiconductor layer and between the second pole and the semiconductor layer. resistance, increase the current flow rate, and ultimately increase the reading and writing speed of the memory unit; from the perspective of the process of forming the memory unit, it can simplify the manufacturing process and reduce the difficulty of the process.
  • the first part, the second part and the third part are connected to form an integrated structure.
  • the semiconductor layer includes a first portion extending along the second direction, and a third portion extending along the first direction and connected to the first portion; is the first wall surface, and the surface opposite to the first pole in the second pole is the second wall surface; the memory also includes a connection electrode, and the connection electrode is arranged on the second wall surface; the third part is in contact with the first wall surface, and the first part is in contact with the first wall surface. Connect the electrode contacts.
  • both the semiconductor layer and the ferroelectric layer are designed to be close to the L-shaped structure.
  • the etching process steps in the preparation process can be reduced, and the production efficiency can be improved.
  • Reducing the number of times of etching will reduce the risk of greater contamination of the ferroelectric layer due to etching, and further improve the storage performance of the ferroelectric layer.
  • the surface opposite to the second pole in the first pole is the first wall surface, and the surface opposite to the first pole in the second pole is the second wall surface; the gate is located at the first In the area between the wall and the second wall.
  • Disposing the gate in the region between the first pole and the second pole can further reduce the projected area of the memory cell on the substrate, so as to further increase the integration density.
  • the surface opposite to the second pole in the first pole is the first wall, and the side adjacent to the first wall in the first pole is the first side;
  • the opposite surface of one pole is the second wall, and the second side is adjacent to the second wall in the second pole, and the first side and the second side are on the same side;
  • the gate is located on one side of the first side and the second side side.
  • the ferroelectric field effect transistor is manufactured by a back-end process.
  • the control circuit is made by the front-end process.
  • the control circuit may include one or more circuits of a decoder, a driver, a timing controller, a buffer, or an input/output driver, and may also include other functional circuits.
  • the memory cell can be stacked along the direction perpendicular to the substrate using a three-dimensional integration method to achieve high-density integration of the memory.
  • the multiple storage units include a first storage unit and a second storage unit that are arranged in a direction parallel to the substrate and adjacent to each other; the semiconductor layer in the first storage unit and the second storage unit The semiconductor layers in the two storage units are arranged oppositely.
  • the ferroelectric memory further includes: a bit line, a source line, and a word line; wherein, the gate is electrically connected to the word line, the first pole is electrically connected to the source line, and the second pole is electrically connected to the bit line electrical connection.
  • the bit line, the source line and the word line can be produced by a back-end process, or can be produced by a front-end process, or partly can be produced by a front-end process and partly can be produced by a back-end process.
  • both the source line and the bit line extend along a second direction parallel to the substrate;
  • the word lines extend along a third direction parallel to the substrate, and the second direction is perpendicular to the third direction ;
  • the first poles of the plurality of memory cells arranged along the second direction are electrically connected to the same source line;
  • the second poles of the plurality of memory cells arranged along the second direction are electrically connected to the same bit line;
  • the gates of the plurality of memory cells arranged in the third direction are electrically connected to the same word line.
  • the plurality of first electrodes along the second direction share the same source line
  • the plurality of second electrodes along the second direction share the same bit line
  • the plurality of gate electrodes along the third direction share the same word line
  • the source line extending along the second direction in the first layer memory array is close to the bit line extending along the second direction in the second layer memory array; wherein, the source line extending along the second direction in the first layer memory array
  • the source line and the bit line in the second layer memory array are signal lines independent of each other.
  • an insulating layer may be formed between the source lines of the memory array at the first level and the bit lines of the memory array at the second level, so that the bit lines and the source lines are signal lines independent of each other.
  • a plurality of storage units form a first layer storage array and a second layer storage array arranged along the first direction; the source lines extending along the second direction in the first layer storage array are close to The source lines extending along the second direction in the second storage array; wherein, the source lines in the first storage array and the source lines in the second storage array share the same signal line.
  • the height of each storage array can be reduced to achieve higher Integration density.
  • the word line in the writing phase, is used to receive the word line control signal, the source line and the bit line are used to receive the same control signal, and the word line control signal and the control signal on the source line
  • the voltage difference polarizes the ferroelectric layer. For example, when the word line control signal is greater than zero and greater than the operating voltage, the ferroelectric film layer is positively polarized, and when the word line control signal is less than zero and its absolute value is greater than the operating voltage, the ferroelectric film layer is negatively polarized.
  • the word line is used to receive the ground
  • the source line is used to receive the source line control signal
  • the source line is used to receive the bit line control signal, the source line control signal and the bit line control signal
  • the ferroelectric field effect transistor turns on. For example, when the ferroelectric field effect transistor is on, read "1".
  • the word line is used to receive the ground
  • the source line is used to receive the source line control signal
  • the source line is used to receive the bit line control signal, the source line control signal and the bit line control signal
  • the ferroelectric field effect transistor turns off. For example, when the FFET is off, read "0".
  • the ferroelectric memory further includes a controller, and the controller is configured to: output a word line control signal to control the voltage on the word line; output a source line control signal to control the voltage on the source line; and output bit line control signal to control the voltage on the bit line.
  • the present application further provides an electronic device, including a processor and the ferroelectric memory in any implementation manner of the first aspect above, and the processor is electrically connected to the ferroelectric memory.
  • the electronic device provided by the embodiment of the present application includes the ferroelectric memory of the embodiment of the first aspect, so the electronic device provided by the embodiment of the present application and the ferroelectric memory of the above technical solution can solve the same technical problem and achieve the same expected effect.
  • the processor and the ferroelectric memory are integrated in the same chip.
  • the memory thus formed may be referred to as an embedded memory structure.
  • the present application also provides a method for forming a ferroelectric memory, the forming method comprising: forming a first pole and a second pole along a first direction perpendicular to the substrate, and forming a semiconductor layer, a gate and a A ferroelectric layer, and a semiconductor layer is formed on one of the opposite sides of the gate along the second direction, the semiconductor layer is electrically connected to the first pole and the second pole respectively, and the ferroelectric layer is formed between the gate and the semiconductor layer , to form a ferroelectric field effect transistor.
  • the semiconductor layer is a vertical channel perpendicular to the substrate, so, The projected area of the storage unit on the substrate is small, and high-density integration of the storage unit can be realized.
  • the size of the entire transistor in the second direction can be reduced, and the memory cell can be further miniaturized. Based on these features, The storage density and storage capacity of the memory will be significantly improved, thereby increasing the read and write speed of the memory.
  • the forming method before forming the storage unit, further includes: forming a control circuit on the substrate; and forming an interconnection line electrically connecting the control circuit and the storage unit on the control circuit.
  • the memory cells in the memory are manufactured through a back-end process, and the memory cells can be stacked along a direction perpendicular to the substrate by using a three-dimensional integration method to achieve high-density integration of the memory.
  • the ferroelectric field effect transistor when forming the ferroelectric field effect transistor, it includes: sequentially stacking the first conductive layer, the sacrificial layer and the second conductive layer along the first direction; , and the first groove of the first conductive layer; along the second direction parallel to the substrate, sequentially form a ferroelectric layer and a gate on the side wall surface of the first groove; remove the sacrificial layer in contact with the ferroelectric layer , to form a cavity, the first pole and the second pole are formed on both sides of the cavity; a semiconductor layer is formed on at least the wall surface of the cavity close to the ferroelectric layer, so as to make a ferroelectric field effect transistor.
  • the ferroelectric field effect transistor when forming the ferroelectric field effect transistor, it includes: sequentially stacking the first conductive layer, the sacrificial layer and the second conductive layer along the first direction; , and the first groove of the first conductive layer; along a second direction parallel to the substrate, forming a semiconductor layer on the sidewall surface of the first groove; removing the sacrificial layer in contact with the semiconductor layer to form a cavity, A first pole and a second pole are formed on both sides of the concave cavity; a gate and a ferroelectric layer for isolating the gate and the semiconductor layer are formed in the cavity to make a ferroelectric field effect transistor.
  • the ferroelectric field effect transistor when forming the ferroelectric field effect transistor, it includes: sequentially stacking the first conductive layer, the sacrificial layer and the second conductive layer along the first direction; , and the first groove of the first conductive layer; the sacrificial layer is removed to form a cavity, and the first pole and the second pole are formed on both sides of the cavity; a semiconductor layer, a gate and an isolation cavity are formed in the cavity Gate and ferroelectric layers of semiconductor layers to make ferroelectric field effect transistors.
  • the ferroelectric field effect transistor when forming the ferroelectric field effect transistor, it includes: sequentially stacking the first conductive layer, the sacrificial layer and the second conductive layer along the first direction; A groove; a ferroelectric layer and a semiconductor layer are sequentially formed on the side of the first groove, so that the second conductive layer forms a gate, and the first conductive layer forms a first pole; a second pole is formed on the semiconductor layer to make ferroelectric field effect transistor.
  • Fig. 1 a is a process structure diagram of a FeFET memory storage unit in the prior art
  • Figure 1b is a process structure diagram of a FeFET memory storage unit in the prior art
  • FIG. 1c is a process structure diagram of a FeFET memory storage unit in the prior art
  • FIG. 2 is a circuit diagram of an electronic device provided in an embodiment of the present application.
  • FIG. 3 is a circuit diagram of a ferroelectric memory provided by an embodiment of the present application.
  • FIG. 4 is a circuit diagram of a storage array of a ferroelectric memory provided by an embodiment of the present application.
  • Fig. 5a is a process structure diagram of a memory cell of a ferroelectric memory provided by an embodiment of the present application.
  • Fig. 5b is the A-A sectional view of Fig. 5a;
  • FIG. 6 is a schematic top view of a storage array of a ferroelectric memory provided by an embodiment of the present application.
  • Fig. 7a is a process structure diagram of a memory cell of a ferroelectric memory provided by an embodiment of the present application.
  • Fig. 7b is the B-B sectional view of Fig. 7a;
  • FIG. 8a is a process structure diagram of a memory cell of a ferroelectric memory provided by an embodiment of the present application.
  • Figure 8b is a C-C sectional view of Figure 8a;
  • Fig. 9a is a process structure diagram of a memory cell of a ferroelectric memory provided by an embodiment of the present application.
  • Figure 9b is a D-D sectional view of Figure 9a;
  • Fig. 10a is a process structure diagram of a memory cell of a ferroelectric memory provided by an embodiment of the present application.
  • Fig. 10b is the E-E sectional view of Fig. 10a;
  • Fig. 11a is a process structure diagram of a memory cell of a ferroelectric memory provided by an embodiment of the present application.
  • Fig. 11b is the F-F sectional view of Fig. 11a;
  • FIG. 12 is a three-dimensional process structure diagram of a one-layer storage array of a ferroelectric memory provided by an embodiment of the present application.
  • Fig. 13 is the M1 direction view of Fig. 12;
  • FIG. 14 is a three-dimensional process structure diagram of a multilayer storage array of a ferroelectric memory provided by an embodiment of the present application.
  • Fig. 15 is the M2 direction view of Fig. 14;
  • FIG. 16 is a three-dimensional process structure diagram of a multilayer storage array of a ferroelectric memory provided by an embodiment of the present application.
  • Fig. 17 is the M3 direction view of Fig. 16;
  • FIG. 18 is a process schematic diagram of a memory chip provided by an embodiment of the present application.
  • FIG. 19 is a circuit diagram of a storage array of a ferroelectric memory provided by an embodiment of the present application.
  • 20a to 20j are process structure diagrams after each step of forming a memory cell provided by the embodiment of the present application.
  • Fig. 21a to Fig. 21j are process structure diagrams after each step of forming a memory cell provided by the embodiment of the present application;
  • Fig. 22a to Fig. 22j are process structure diagrams after each step of forming a memory cell provided by the embodiment of the present application;
  • 23a to 23i are process structure diagrams after each step of forming a memory cell provided by the embodiment of the present application.
  • 24a to 24g are process structure diagrams after each step of forming a memory cell provided by the embodiment of the present application.
  • Ferroelectric memory stores data based on the ferroelectric effect of ferroelectric materials. Due to its ultra-high storage density, low power consumption and high speed, ferroelectric memory is expected to become the main competitor to replace DRAM.
  • a memory cell in a ferroelectric memory contains a ferroelectric capacitor comprising a ferroelectric layer made of a ferroelectric material. Due to the nonlinear characteristics of ferroelectric materials, the dielectric constant of ferroelectric materials can not only be adjusted, but also the difference before and after the polarization state of the ferroelectric layer is very large, which makes ferroelectric capacitors smaller in size compared with other capacitors, For example, it is much smaller than the capacitor used to store charge in DRAM.
  • the ferroelectric layer can be formed using common ferroelectric materials, such as ZrO 2 , HfO 2 and the like.
  • common ferroelectric materials such as ZrO 2 , HfO 2 and the like.
  • the central atoms follow the electric field and stay in a low-energy state.
  • the central atoms move in the crystal along the direction of the electric field and stop. in another low energy state.
  • a large number of central atoms move and couple in the crystal unit cell to form ferroelectric domains, and the ferroelectric domains form polarized charges under the action of an electric field.
  • the polarization charge formed by the ferroelectric domain reversal under the electric field is higher, and the polarization charge formed by the ferroelectric domain without reversal under the electric field is lower.
  • the binary stable state of this ferroelectric material makes ferroelectricity can be used as memory.
  • FIG. 2 is a circuit diagram in an electronic device 200 provided by the embodiment of the present application.
  • the electronic device 200 can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (personal computer, PC), server , workstations, etc.
  • the electronic device 200 includes a bus 205, and a system on chip (system on chip, SOC) 210 and a read-only memory (read-only memory, ROM) 220 connected to the bus 205.
  • SOC system on chip
  • ROM read-only memory
  • the SOC 210 can be used to process data, such as processing application data, processing image data, and caching temporary data.
  • ROM 220 can be used to save non-volatile data, such as audio files, video files, etc.
  • ROM220 can be PROM (programmable read-only memory, programmable read-only memory), EPROM (erasable programmable read-only memory, erasable programmable read-only memory), flash memory (flash memory) and so on.
  • the electronic device 200 may further include a communication chip 230 and a power management chip 240 .
  • the communication chip 230 can be used to process the protocol stack, or to amplify and filter the analog radio frequency signal, or to realize the above functions at the same time.
  • the power management chip 240 can be used to supply power to other chips.
  • the SOC 210 may include an application processor (application processor, AP) 211 for processing application programs, an image processing unit (graphics processing unit, GPU) 212 for processing image data, and a cache data random access memory (random access memory, RAM) 213.
  • application processor application processor, AP
  • image processing unit graphics processing unit, GPU
  • cache data random access memory random access memory
  • the above-mentioned AP211, GPU212 and RAM213 may be integrated into one die, or respectively integrated into multiple dies, and packaged in a package structure, such as a 2.5D (dimension) package, or 3D (dimension) packaging, or other advanced packaging technologies.
  • the above-mentioned AP211 and GPU212 are integrated in one die, RAM213 is integrated in another die, and these two dies are packaged in a package structure, so as to obtain a faster data transmission rate between dies and higher data transfer bandwidth.
  • FIG. 3 is a circuit diagram of a ferroelectric memory 300 in an electronic device provided by an embodiment of the present application.
  • the ferroelectric memory 300 may be a RAM 213 as shown in FIG. 2 , which belongs to FeRAM.
  • the ferroelectric memory 300 may also be a RAM disposed outside the SOC 210 .
  • the present application does not limit the location of the ferroelectric memory 300 in the electronic device and the location relationship with the SOC 210 .
  • the ferroelectric memory 300 includes a memory array 310 , a decoder 320 , a driver 330 , a timing controller 340 , a buffer 350 and an input/output driver 360 .
  • the storage array 310 includes a plurality of storage units 400 arranged in an array, wherein each storage unit 400 can be used to store 1-bit or multi-bit data.
  • the memory array 310 also includes signal lines such as word lines (word line, WL), bit lines (bit line, BL), and source lines (source line, SL). Each memory cell 400 is electrically connected to the corresponding word line WL, bit line BL and source line SL.
  • One or more of the above-mentioned word line WL, bit line BL or source line SL is used to select the memory cell 400 to be read and written in the memory array by receiving the control level output by the control circuit, so as to change the iron level in the memory cell 400.
  • the polarization direction of the capacitor is used to realize the read and write operations of data.
  • the word line WL, the bit line BL and the source line SL are collectively referred to as signal lines.
  • the decoder 320 is used to decode the received address to determine the memory unit 400 to be accessed.
  • the driver 330 is used to control the level of the signal line according to the decoding result generated by the decoder 320 , so as to realize the access to the specified storage unit 400 .
  • the buffer 350 is used for caching the read data, for example, first-in-first-out (FIFO) may be used for caching.
  • the timing controller 330 is used for controlling the timing of the register 350 and controlling the driver 330 to drive the signal lines in the memory array 310 .
  • the input/output driver 360 is used to drive transmission signals, such as driving received data signals and driving data signals to be sent, so that the data signals can be transmitted over long distances.
  • the memory array 310 , decoder 320 , driver 330 , timing controller 340 , buffer 350 and input/output driver 360 may be integrated into one chip, or may be integrated into multiple chips respectively.
  • Fig. 4 has provided the partial circuit diagram of the memory array 310 in a kind of ferroelectric memory, and this memory array 310 has provided 4 memory cells 400 exemplary, each memory cell all comprises ferroelectric field-effect transistor (ferroelectric filed-effect -transistor, FeFET), wherein the gate (gate) of the ferroelectric field effect transistor is electrically connected to the word line (word line, WL), and the first pole of the ferroelectric field effect transistor is electrically connected to the source line (source line, SL), The second electrode of the ferroelectric field effect transistor is electrically connected to a bit line (bit line, BL).
  • ferroelectric field-effect transistor ferroelectric filed-effect -transistor, FeFET
  • the gate (gate) of the ferroelectric field effect transistor is electrically connected to the word line (word line, WL)
  • the first pole of the ferroelectric field effect transistor is electrically connected to the source line (source line, SL)
  • the second electrode of the ferroelectric field effect transistor is electrically connected
  • one of the drain or the source of the ferroelectric field effect transistor is called the first pole, and the corresponding other pole is called the second pole.
  • the drain and source can be determined according to the flow direction of the current. For example, in Figure 4, when the current flows from left to right, the left end is the drain, and the right end is the source. Conversely, when the current flows from right to left, the right end is the drain, and the left end is the source.
  • the ferroelectric field effect transistor includes a ferroelectric layer for storing data information, and the existence of the self-polarization field of the ferroelectric layer makes the threshold voltage of the ferroelectric field effect transistor shift, positive The upward and negative polarization fields shift the threshold voltage in different directions, and the gap between the two forms the storage window of the ferroelectric field effect transistor.
  • the gate of the ferroelectric transistor that is, the word line in Figure 4
  • the two states can be separated by applying a voltage between the source and the drain and reading the current, so as to realize the storage function.
  • the number of transistors per unit area on the chip of electronic equipment continues to increase, so that the performance of electronic equipment is continuously optimized.
  • the amount of data that the processor can calculate per unit time continues to increase, for example, the amount of data calculated by GPU212 in the above-mentioned figure 2 is rapidly increasing; on the other hand, the storage density of the memory is also increasing, so as to meet the information The demand for data processing in the era.
  • the degree of performance improvement between the processor and the memory due to say, the storage density of the memory is low, and the reading and writing speed cannot keep up with the computing speed of the processor, which restricts the rapid improvement of the performance of electronic equipment.
  • the embodiment of the present application provides a ferroelectric memory, which has higher storage density, higher storage capacity, and faster read and write speeds, thereby reducing the gap with processor performance improvement.
  • Fig. 5a shows a memory cell 400 in a ferroelectric memory and a three-dimensional process structure diagram of the substrate 100
  • Fig. 5b is a sectional view along line A-A of Fig. 5a.
  • the memory cell 400 includes a ferroelectric field effect transistor, and it can also be said that a ferroelectric field effect transistor is just a memory cell 400, then, 400 shown in Fig. 5a and Fig. 5b is also a ferroelectric field effect transistor
  • the ferroelectric field effect transistor includes a first pole 51 and a second pole 52, a semiconductor layer 53 and a gate 55, and the semiconductor layer 53 may also be called a channel layer.
  • the ferroelectric field effect transistor here is a transistor device with three terminals, then, the ferroelectric field effect transistor can be selected from NMOS (N-channel metal oxide semiconductor, N-channel metal oxide semiconductor) tube, or can Select PMOS (P-channel metal oxide semiconductor, P-channel metal oxide semiconductor) tube.
  • NMOS N-channel metal oxide semiconductor, N-channel metal oxide semiconductor
  • PMOS P-channel metal oxide semiconductor, P-channel metal oxide semiconductor
  • the first pole 51 and the second pole 52 are arranged along the first direction Z direction perpendicular to the substrate 100, the gate 55 is located between the first pole 51 and the second pole 52, and The gate 55 is insulated from the first pole 51 , and the gate 55 is insulated from the second pole 52 .
  • one of the opposite sides of the grid 55 provided in the present application along a direction parallel to the substrate 100 (such as the Y direction in FIG. 5a and FIG. 5b) has a semiconductor layer 53, and the semiconductor layer 53 are electrically connected to the first pole 51 and the second pole 52, respectively.
  • the opposite sides of the gate 55 along the Y direction parallel to the substrate 100 has a semiconductor layer 53" can be understood in this way.
  • the opposite sides of the gate 55 along the Y direction The side surfaces are respectively the P1 side and the P2 side, and the semiconductor layer 53 is located on the side of the P2 side, or the semiconductor layer 53 is located on the side of the P1 side, that is, one side of the P1 side and the P2 side of the gate 55 is provided with a semiconductor layer.
  • layer 53 the other side is not provided with the semiconductor layer 53 , or in other words, the semiconductor layer 53 is not provided around the periphery of the gate 55 .
  • Designing the positional relationship between the gate 55 and the semiconductor layer 53 in the process structure can reduce the size of the ferroelectric field effect transistor in the Y direction, and then the size of the ferroelectric field effect transistor can be miniaturized to realize the memory cell.
  • High-density integration increases the storage capacity.
  • it can also increase the reading and writing speed of the memory and reduce the degree of mismatch with the development of the processor.
  • higher performance can be achieved. Data transfer bandwidth.
  • the semiconductor layer 53 between the first pole 51 and the second pole 52 is a vertical channel arranged vertically to the substrate 100, compared with a horizontal channel transistor structure, can reduce the projected area on the substrate 100, realize the miniaturization of the storage unit 400, so as to increase the storage density of the memory, increase the storage capacity, and increase the reading and writing speed.
  • the semiconductor layer 53 between the first pole 51 and the second pole 52 is a vertical channel arranged vertically to the substrate 100, compared with a horizontal channel transistor structure, can reduce the projected area on the substrate 100, realize the miniaturization of the storage unit 400, so as to increase the storage density of the memory, increase the storage capacity, and increase the reading and writing speed.
  • the ferroelectric field effect transistor with this structure may be referred to as a vertical oxide semiconductor ferroelectric field effect transistor (vertical oxide semiconductor FeFET, VOS-FeFET).
  • first pole 51 and the second pole 52 are both a film structure, for example, can be produced by deposition or sputtering process, rather than doping in the substrate 100.
  • the memory unit 400 may implement three-dimensional (3D) stacking on the substrate 100 to achieve high-density integration.
  • the memory cell 400 also includes a ferroelectric layer 54 for storing charges, and the gate 55 and the semiconductor layer 53 are separated by the ferroelectric layer 54, that is, the ferroelectric layer 54 is separated by the ferroelectric layer 54. It is provided between the gate electrode 55 and the semiconductor layer 53 .
  • the materials of the above-mentioned first pole 51 and the second pole 52 are conductive materials, such as metal materials.
  • the materials of the first pole 51 and the second pole 52 can be TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In- One or more of conductive materials such as Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver).
  • the material of the above-mentioned gate 55 is a conductive material, such as a metal material.
  • it can be TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide),
  • conductive materials such as Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver).
  • the material of the above-mentioned semiconductor layer 53 can be Si (silicon), poly-Si (p-Si, polycrystalline silicon), amorphous-Si (a-Si, amorphous silicon), In-Ga-Zn-O (IGZO, indium gallium Zinc oxide) multi-component compound, ZnO (zinc oxide), ITO (indium tin oxide), TiO 2 (titanium dioxide), MoS 2 (molybdenum disulfide), WS 2 (tungsten disulfide) and other semiconductor materials or one or more kind.
  • the above-mentioned materials for insulating the gate 55 and the first pole 51, and the insulating layer between the gate 55 and the second pole 52 can be SiO 2 (silicon dioxide), Al 2 O 3 (aluminum oxide), HfO 2
  • insulating materials such as (hafnium dioxide), ZrO 2 (zirconia), TiO 2 (titanium dioxide), Y 2 O 3 (yttrium trioxide), and Si 3 N 4 (silicon nitride).
  • the material of the above-mentioned ferroelectric layer 54 can be ZrO 2 , HfO 2 , Al-doped HfO 2 , Si-doped HfO 2 , Zr-doped HfO 2 , La-doped HfO 2 , Y-doped HfO 2 and other ferroelectric materials or One or more of the materials based on the material to be doped with other elements.
  • the semiconductor layer 53 is a vertical structure extending along the Z direction perpendicular to the substrate, and the first pole 51 has a first wall M1 opposite to the second pole 52, and the second pole 52 has a wall M1 opposite to the first pole 52.
  • the second wall M2 opposite to the pole 51 one end of the opposite ends of the semiconductor layer 53 along the Z direction is in contact with the first wall M1 for coupling and electrical connection, and the other end of the semiconductor layer 53 is connected to the opposite ends of the Z direction.
  • the second wall surface M2 contacts to couple the electrical connection.
  • ferroelectric layer 54 is also a vertical structure, and the ferroelectric layer 54 and the semiconductor layer 53 are arranged side by side along the Y direction parallel to the substrate 100 .
  • the gate electrode 55 is located in a region between the first wall surface M1 of the first pole 51 and the second wall surface M2 of the second pole 52 .
  • the second pole 52, the first insulating layer, the gate 55 and the second insulating layer can be sequentially stacked along the Z direction shown in FIG.
  • the groove of the second pole 52, and the ferroelectric layer 54 and the semiconductor layer 53 are stacked successively on the side of the groove; finally the first pole 51 is formed on the second insulating layer, where the first insulating layer is used as the insulating gate 52 and the second insulating layer.
  • the insulating structure of the pole 52, here the second insulating layer serves as the insulating structure of the insulating gate 52 and the first pole 51.
  • the semiconductor layer 53 is a vertical channel perpendicular to the substrate 100, and has only one layer of structure along the Y direction.
  • the storage unit 400 is scaled in the Y direction to increase the storage density.
  • Figure 7a and Figure 7b show another process structure diagram of a memory cell 400
  • Figure 7b is a B-B sectional view of Figure 7a, shown in conjunction with Figure 7a and Figure 7b, and the above memory cell 400 shown in Figure 5a and Figure 5b
  • the semiconductor layer 53 is also a vertical structure extending along the Z direction perpendicular to the substrate.
  • the setting position of the semiconductor layer 53 in this embodiment is the same as that in the above-mentioned 5a and FIG. 5b
  • the placement position of the semiconductor layer 53 is different.
  • the first pole 51 has a first wall surface M1 opposite to the second pole 52
  • the second pole 52 has a second wall surface M2 opposite to the first pole 51.
  • the first pole 51 has a first side C1 adjacent to the first wall M1
  • the second pole 52 has a second side C2 adjacent to the second wall M2
  • the first side C1 and the second side C2 are located on the same side
  • the semiconductor layer 53 is located on one side of the first side C1 and the second side C2, and one end of the opposite ends of the semiconductor layer 53 along the Z direction is in contact with the first side C1 for coupling electrical connection, and the opposite ends of the semiconductor layer 53 along the Z direction The other end of the two ends is in contact with the second side C2 to couple the electrical connection.
  • the end of the semiconductor layer 53 in contact with the first pole 51 is flush with the end face of the first pole 51 away from the second pole 52, and the end of the semiconductor layer 53 is flush with the second pole 52.
  • the end in contact with 52 is flush with the end face of second pole 52 facing away from first pole 51 .
  • the gate 55 is located in the region between the first wall M1 and the second wall M2, in this case, the projected area of the memory cell 400 on the substrate can be further reduced, so that the Storage unit size shrinks.
  • the ferroelectric layer 54 includes a first portion 541 and a second portion 542 extending along the Y direction parallel to the substrate, and a third portion 543 connecting the first portion 541 and the second portion 542,
  • the first portion 541 is formed on the first wall M1
  • the second portion 542 is formed on the second wall M2, so that the ferroelectric layer 54 encloses a cavity structure with an opening, and the gate 55 is disposed in the cavity.
  • the first part 541 serves as an insulating structure for insulating the gate 55 and the first pole 51
  • the second part 542 serves as an insulating structure for insulating the gate 55 and the second pole 52 .
  • the second pole 52, the sacrificial layer (which is defined as a sacrificial layer structure) and the first pole 51 can be sequentially stacked first; groove, and form a semiconductor layer 53 on the sides of the groove near the first pole 51, the sacrificial layer and the second pole 52; then remove the sacrificial layer to form a cavity between the first pole 51 and the second pole 52; A ferroelectric layer 54 and a gate 55 are formed in the cavity to produce a memory cell as shown in FIG. 7b.
  • the preparation process is simple and easy to implement.
  • the semiconductor layer 53 of each memory cell 400 only includes a channel structure extending along the Z direction, so as to reduce the size of the multiple memory cells along the Y direction parallel to the substrate, so that on a unit surface of the substrate form more memory cells.
  • Figure 8a and Figure 8b show another process structure diagram of a memory cell 400
  • Figure 8b is a C-C cross-sectional view of Figure 8a, shown in conjunction with Figure 8a and Figure 8b
  • the semiconductor layer 53 is also a vertical structure extending along the Z direction perpendicular to the substrate
  • the ferroelectric layer 54 also includes a first part 541 extending along the Y direction parallel to the substrate And the second part 542, and the third part 543 connecting the first part 541 and the second part 542, the first part 541 is formed on the first wall surface M1, and the second part 542 is formed on the second wall surface M2, so that the ferroelectric layer
  • the siege 54 has an open cavity structure, and the grid 55 is located in the cavity.
  • the difference from the memory cell 400 shown in the above-mentioned FIG. 7a and FIG. 7b is that the setting position of the semiconductor layer 53 in this embodiment is different from the setting position of the semiconductor layer 53 in the above-mentioned 7a and FIG. 7b.
  • one of the opposite ends of the semiconductor layer 53 along the Z direction is in contact with the first wall surface M1 of the first pole 51 to be electrically coupled, and the other end of the semiconductor layer 53 is connected to the second end of the opposite ends of the Z direction.
  • the second wall surface M2 of the pole 52 is in contact to couple the electrical connection.
  • the gate 55, the semiconductor layer 53 and the ferroelectric layer 54 are all located in the region between the first pole 51 and the second pole 52, in this case, it will further make The size of the memory cell 400 in the Y direction can be shrunk.
  • the ferroelectric layer 54 since the ferroelectric layer 54 includes a first part 541, a second part 542, and a third part 543, the ferroelectric layer 54 has a larger area, which can improve the performance of the ferroelectric layer 54. The read and write efficiency of the memory.
  • the first part 541, the second part 542, and the third part 543 may be integrally formed structures, that is, In the realized process steps, the first part 541 , the second part 542 and the third part 543 are formed at one time through one process.
  • Figure 9a and Figure 9b show another process structure diagram of a memory cell 400
  • Figure 9b is a D-D cross-sectional view of Figure 9a, shown in conjunction with Figure 9a and Figure 9b
  • the above memory cell 400 shown in Figure 8a and Figure 8b The same thing is that in this embodiment, the ferroelectric layer 54 also includes a first portion 541 and a second portion 542 extending along the Y direction parallel to the substrate, and a third portion 543 connecting the first portion 541 and the second portion 542, so that Enclosing the ferroelectric layer 54 with an open cavity structure, the gate 55 is located in the cavity, the difference is that the semiconductor layer 53 includes a first portion 531 and a second portion that both extend along the Y direction parallel to the substrate 100 532 , and includes a third portion 533 extending along the Z direction perpendicular to the substrate 100 , and the third portion 533 is connected to the first portion 531 and the second portion 532 .
  • the semiconductor layer 53 in this embodiment forms a cavity structure with an opening
  • the first part 531 is disposed on the first wall M1
  • the second part 532 is disposed on the second wall M1
  • the ferroelectric layer 54 and the gate 55 is located in the concave cavity surrounded by the semiconductor layer 53 .
  • both the first wall M1 of the first pole 51 and the second wall M2 of the second pole 52 have a semiconductor layer.
  • the ohmic contact area between the semiconductor layer and the first pole 51 can be increased, and the ohmic contact area between the semiconductor layer and the second pole 52 can be increased, thereby reducing the contact area between the semiconductor layer and the first pole 51. resistance, and reduce the resistance between the semiconductor layer and the second electrode 52, so as to increase the current flow rate, and finally increase the reading and writing speed of the memory cell.
  • PVD photosensitive polymer
  • CVD chemical vapor deposition
  • the memory cell 400 Based on the above description of the structure of the memory cell 400, along the Y direction parallel to the substrate 100, there is only one layer of semiconductor layer structure. Compared with the existing two-layer semiconductor layer structure, the memory cell can be miniaturized and improved. The storage density of the entire memory.
  • Figures 10a and 10b show a process structure diagram of another memory cell 400
  • Figure 10b is an E-E cross-sectional view of Figure 10a, shown in conjunction with Figures 10a and 10b, and the memory cell 400 shown in Figures 9a and 9b above
  • the semiconductor layer 53 in this embodiment also includes a first portion 531 and a second portion 532 extending along the Y direction parallel to the substrate 100, and a third portion extending along the Z direction perpendicular to the substrate 100. part 533, and the third part 533 is connected with the first part 531 and the second part 532.
  • the semiconductor layer 53 in this embodiment forms a cavity structure with an opening
  • the first portion 531 is disposed on the first wall M1
  • the second portion 532 is disposed on the second wall M1 .
  • the difference from the memory cell shown in FIG. 9a and FIG. 9b is that the location of the gate 55 is different.
  • the gate 55 is located on the side of the first side C1 and the second side C2.
  • the gate 55 is isolated from the first electrode 51 , the second electrode 52 and the semiconductor layer 53 by the ferroelectric layer 54 .
  • the end of the gate 55 close to the first pole 51 is flush with the end face of the first pole 51 away from the second pole 52, and the gate 55 close to the second pole 52
  • the end of the second pole 52 is flush with the end face of the second pole 52 facing away from the first pole 51 .
  • Such a structure can also be defined such that the gate 55 is located between the first pole 51 and the second pole 52 .
  • Both the first wall surface M1 of the first pole 51 and the second wall surface M2 of the second pole 52 have a semiconductor layer.
  • the ohmic contact area between the semiconductor layer and the first pole 51 can be increased, and the ohmic contact area between the semiconductor layer and the second pole 52 can be increased, thereby reducing the contact area between the semiconductor layer and the first pole 51. resistance, and reduce the resistance between the semiconductor layer and the second electrode 52, so as to increase the current flow rate and increase the reading and writing speed of the memory cell.
  • the first part 531 , the second part 532 and the third part 533 enclose a cavity with an opening, and another insulating layer 56 is filled in the cavity.
  • the second pole, the sacrificial layer and the first pole can be sequentially stacked along the Z direction shown in FIG. Pole groove, and stack the ferroelectric layer 54 and gate 55 sequentially on the side of the groove; then remove the sacrificial layer to form a cavity between the first pole 51 and the second pole 52, and fill the cavity with a semiconductor layer 33 , and then fill the remaining space of the cavity with an insulating material to form an insulating layer 56 .
  • Fig. 11a and Fig. 11b have provided another kind of memory cell 400 process structural diagram
  • Fig. 11b is the F-F sectional view of Fig. 11a, in conjunction with Fig. 11a and Fig.
  • a first part 531 extending in the Y direction parallel to the bottom 100, and a third part 533 extending in a Z direction perpendicular to the substrate 100, and the third part 533 is connected to the first part 531, wherein one end of the third part 533 is connected to
  • the first wall M1 of the first pole 51 is in contact with, and the second pole 52 is further provided with a connection electrode 59 , and the first portion 531 is in contact coupling and electrically connected with the connection electrode 59 .
  • the semiconductor layer 53 in this embodiment has a nearly L-shaped structure
  • the ferroelectric layer 54 also has a nearly L-shaped structure.
  • the material of the connecting electrode 59 here may be the same as that of the second pole 52 or different.
  • the memory cell can be implemented Microscaling improves the storage density of the entire memory.
  • the semiconductor layer 53 of the storage unit provided in this application can be made of an oxide semiconductor material, from a process point of view, the uniformity of the oxide semiconductor material of the semiconductor layer 53 is easy to control, and from a performance point of view, the semiconductor layer 53 The oxide semiconductor material of layer 53 has higher mobility, so that the memory unit has the characteristics of high band gap, high hole mobility, low refresh frequency, and better storage performance.
  • the channel in the memory cell is a ferroelectric field effect transistor with a vertical channel, it is within the scope of protection of this application, and the rest of the structures will not be explained here. .
  • the gate 53 is electrically connected to the word line WL
  • the first pole 51 is electrically connected to the source line SL
  • the second pole is electrically connected to the bit line BL.
  • a layer of memory array 310 will be formed.
  • the first poles 51 of the plurality of memory cells arranged along the second direction Y share a source line SL extending along the second direction Y
  • the first poles 51 of the plurality of memory cells arranged along the second direction Y The second pole 52 shares a bit line BL extending along the second direction Y
  • the gates 55 of a plurality of memory cells arranged along the third direction X share a word line extending along the third direction X.
  • WL, and a plurality of word lines WL are arranged in parallel along the second direction Y.
  • FIG. 13 which is a view of the M1 direction of the structure shown in FIG. 12 , among the multiple storage units arranged along the second direction Y, two adjacent storage units
  • the semiconductor layer 53 is arranged oppositely.
  • the storage unit 401, the storage unit 402, the storage unit 403 and the storage unit 404 arranged in sequence along the second direction Y are shown, wherein the semiconductor of the storage unit 401 Layer 53 is arranged opposite to the semiconductor layer 53 of the storage unit 402, the gate 55 of the storage unit 402 is arranged opposite to the gate 55 of the storage unit 403, and then the semiconductor layer 53 of the storage unit 403 is arranged opposite to the semiconductor layer 53 of the storage unit 404 .
  • the multi-layer memory array can be stacked sequentially along the first direction Z direction perpendicular to the substrate 100 to form a three-dimensional memory Structures, for example, Fig. 14 and Fig. 16 show three-dimensional stacked memory arrays with two different structures.
  • FIG. 14 illustrates a three-dimensional process structure diagram of a memory 300, which includes a first-layer memory array 3101 arranged along a first direction Z direction perpendicular to the substrate, a second-layer memory array 3102 and a third-layer memory array. storage array 3103.
  • the source line SL of the first storage array 3101 is close to the bit line BL of the second storage array 3102
  • the source line SL of the second storage array 3102 is close to the bit line BL of the third storage array 3103
  • the first The source line SL of the layer memory array 3101 and the bit line BL of the second layer memory array 3102 are signal lines independent of each other
  • the source line SL of the second layer memory array 3102 and the bit line BL of the third layer memory array 3103 are Signal lines independent of each other. That is to say, the source lines and bit lines in every two adjacent layers of memory arrays are independent of each other.
  • the source line SL of the first layer memory array 3101 may be close to the source line SL of the second layer memory array 3102, and the bit line BL of the second layer memory array 3102 may be close to the second layer.
  • the bit line BL of the three-layer memory array 3103, the source line SL of the first-layer memory array 3101, and the source line SL of the second-layer memory array 3102 are signal lines independent of each other, and the bit line BL of the second-layer memory array 3102,
  • the bit line BL and the bit line BL of the memory array 3102 of the third layer are signal lines independent of each other.
  • FIG. 16 illustrates another three-dimensional process structure diagram of a memory 300. Similar to the above-mentioned FIG. 14 and FIG. 15, the memory 300 in FIG. A first-tier storage array 3101 , a second-tier storage array 3102 and a third-tier storage array 3103 . Wherein, the source line SL of the first storage array 3101 is close to the source line SL of the second storage array 3102, the bit line BL of the second storage array 3102 is close to the bit line BL of the third storage array 3103, and the above-mentioned FIG. 14 The difference from FIG.
  • the source line SL of the first layer memory array 3101 and the source line SL of the second layer memory array 3102 share the same signal line
  • the bit line BL of the second layer memory array 3102 and the third layer The bit lines BL of the layer memory array 3103 also share the same signal line.
  • the multi-layer memory array adopts the layout method shown in Figure 16, since the signal lines close to each other are shared between two adjacent layers of memory arrays, in this case, as shown in Figure 17, more layers of memory can be integrated in the first direction Z direction array to further increase the density of the storage array and form a high-density storage array structure.
  • the ferroelectric memory provided in this application can be fabricated by back end of line (BEOL), and FIG. 18 shows a schematic diagram of the BEOL of the back end process.
  • the control circuit is fabricated on the substrate through a front end of line (FEOL) process.
  • the control circuit may include one or more circuits of decoder 320 , driver 330 , timing controller 340 , buffer 350 or input/output driver 360 as shown in FIG. 3 , and may also include other functional circuits.
  • the control circuit can control the signal lines (word line WL, source line SL, bit line BL) in the embodiment of the present application.
  • interconnect lines and storage arrays are manufactured through the back-end process BEOL.
  • the memory array includes a plurality of corresponding ferroelectric field effect transistors and signal lines (word lines WL, source lines SL, and bit lines BL) in a plurality of memory cells, as described above.
  • the above-mentioned interconnection lines include not only the interconnection lines connecting the devices in the control circuit, but also other parts of the above-mentioned signal lines. Fabricating the ferroelectric field effect transistors in the memory array through the back-end process can make the circuit density per unit area higher, thereby improving the performance per unit area.
  • the voltage value list shown in Table 1 is when the memory cell 401 in the memory array 310 in FIG. Voltage values on each signal line corresponding to the storage unit 404 .
  • V is the first working voltage
  • V1 is the second working voltage
  • V2 is the third working voltage
  • V3 is the fourth working voltage.
  • the present application does not limit the specific values of the first working voltage V, the second working voltage V1, the third working voltage V2, and the fourth working voltage V3.
  • the word line electrically connected to the memory cell 401 is called the selected word line WL
  • the bit line is called the selected bit line BL
  • the source line is called the selected bit line BL.
  • the source line SL, the word lines that are electrically connected to the remaining unselected memory cells 402, 403, and 404 are called unselected word lines Unsel WL, and the bit lines are called unselected bit lines Unsel BL. It is called the unselected source line Unsel SL.
  • the writing operation to the memory cell 401 actually changes the polarization state of the ferroelectric film layer in the memory cell 401 .
  • the polarization state of the ferroelectric film layer changes; when the absolute value of the voltage difference across the ferroelectric film layer is less than or equal to the ferroelectric film layer
  • the coercive electric field of the electric film layer is applied, the polarization state of the ferroelectric film layer does not change.
  • the strength of the coercive electric field can be measured according to the material of the ferroelectric film layer, and then an operating voltage V0 can be set.
  • the polarization state of the ferroelectric film layer changes; when the absolute value of the voltage difference across the ferroelectric film layer is less than or equal to V0, the polarization state of the ferroelectric film layer The state does not change.
  • Table 1 For example, when the absolute value of the voltage difference across the ferroelectric film layer is greater than V/3, the polarization state of the ferroelectric film layer changes, and when the voltage difference across the ferroelectric film layer When the absolute value is less than or equal to V/3, the polarization state of the ferroelectric film layer does not change.
  • the selected word line WL receives the first operating voltage V
  • the selected bit line BL is grounded
  • the selected source line SL is grounded
  • the unselected bit line Unsel BL and the unselected source line Unsel SL electrically connected to the memory cell 402 both receive 2V/3, and the ferroelectric layer of the memory cell 402
  • the unselected word line Unsel WL receives V/3
  • the unselected bit line Unsel BL and unselected source line Unsel SL both receive 2V/3
  • the voltage difference across the ferroelectric layer of the memory cell 402 is V/3
  • the change of the state means that the operation of writing "1" to the storage unit 403 will not be performed.
  • the unselected bit line Unsel BL and the unselected source line Unsel SL electrically connected to the memory cell 402 all receive V/3, then the ferroelectric layer at both ends of the memory cell 402
  • 404 performs a write "0" operation.
  • the unselected word line Unsel WL receives 2V/3
  • the unselected bit line Unsel BL and the unselected source line Unsel SL both receive V/3
  • the selected word line WL receives V3 (for example, V3 is 0, or V3 is a voltage between two threshold voltages), and the selected bit line BL receives V2 (because the NPOS tube is selected, V2 is greater than 0), select the source line SL to ground.
  • V3 for example, V3 is 0, or V3 is a voltage between two threshold voltages
  • V2 because the NPOS tube is selected, V2 is greater than 0
  • the ferroelectric film layer of the memory cell 401 is in a positively polarized state, that is, the data stored in the memory cell 401 is "1"
  • the ferroelectric field effect transistor of the memory cell 401 is in a conduction state, and is detected by detecting the current of the selected bit line BL. Read the "1" state of a memory cell.
  • ferroelectric film layer of the memory cell 401 is in a negatively polarized state, that is, the data stored in the memory cell 401 is "0"
  • the ferroelectric field effect transistor of the memory cell 401 is in an off state, and is detected by detecting the current of the selected bit line BL. Read the "0" state of a memory cell.
  • the unselected bit line Unsel BL and the unselected source line Unsel SL electrically connected to the memory cell 402 are both grounded, and thus the memory cell 402 will not be read.
  • the unselected word line Unsel WL receives V1, so that the ferroelectric field effect transistor of the memory cell 403 is in an off state, and the ferroelectric field of the memory cell 404 The effect transistor is also in the off state, and the memory unit 403 and the memory unit 404 will not be read.
  • a control circuit is first formed on the substrate; then interconnection lines are formed on the control circuit; memory cells, and electrically connect the control circuit to a plurality of memory cells through interconnection lines, so that the read and write of the memory cells can be controlled by the control circuit.
  • the first pole and the second pole are formed along the first direction perpendicular to the substrate, and the semiconductor layer, the gate and the ferroelectric layer are formed, and the opposite sides of the gate along the second direction
  • One side has a semiconductor layer, the semiconductor layer is electrically connected to the first pole and the second pole respectively, and the ferroelectric layer is formed between the gate and the semiconductor layer to form a ferroelectric field effect transistor of the memory unit.
  • the present application provides specific preparation methods for preparing various memory cell structures, which will be explained in detail below.
  • 20a to 20j show cross-sectional views of the process structure after each step in the process of manufacturing a memory cell involved in the present application.
  • the first electrode 51 , the insulating layer 561 , the gate 55 and the insulating layer 562 are sequentially stacked along the first direction Z perpendicular to the substrate.
  • the materials of the first electrode 51 , the insulating layer 561 , the gate 55 and the insulating layer 562 have been described above, and will not be described here again.
  • first grooves 101 As shown in FIG. 20 b , along the second direction Y parallel to the substrate, a plurality of first grooves 101 arranged at intervals are opened, and the first grooves 101 penetrate the insulating layer 562 , the gate 55 and the insulating layer 561 . That is to say, the first groove 101 cannot penetrate through the first electrode 51 because the first electrode 51 here can be used as a bit line BL or a source line SL of the memory array.
  • an insulating material is filled in the first groove 101 to form an insulating layer 563 .
  • a deposition process such as physical vapor deposition (PVD), chemical vapor deposition (CVD) or electrochemical deposition (ECD) can be selected.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • ECD electrochemical deposition
  • a second groove 102 is opened, and the second groove 102 is opened between adjacent insulating layers 563 , and the second groove 102 penetrates the insulating layer 562 , the gate 55 and the insulating layer 561 .
  • a ferroelectric layer 54 is formed in the second groove 102 .
  • the ferroelectric layer 54 can be formed by deposition, sputtering and other processes. For example, when the deposition method is used, the ferroelectric layer 54 will be formed on the bottom and side surfaces of the second groove 102 and the upper surface of the insulating layer 562 .
  • the bottom surface of the second groove 102 and the upper surface of the insulating layer 562 need to be removed, such as dry etching, to remove the bottom surface of the second groove 102 and the ferroelectric layer on the upper surface of the insulating layer 562. layer 54 to obtain the structure shown in Figure 20f.
  • a semiconductor layer 53 is formed.
  • the remaining space in the second groove 102 is filled with an insulating material to form an insulating layer 564 .
  • the second pole 52 is formed on the insulating layer 562 .
  • the second pole 52 here forms the source line SL or the bit line BL of the memory array.
  • a plurality of memory cells arranged along the Y direction can be manufactured, and the first poles 51 of these memory cells are connected to form one of the bit line BL or the source line SL, and Yes, the second poles 52 of these memory cells are connected to form either the bit line BL or the source line SL.
  • 21a to 21j show cross-sectional views of the process structure after each step in the process of manufacturing another memory cell involved in the present application.
  • the first electrode 51 , the insulating layer 561 , the gate 55 and the insulating layer 562 are sequentially stacked along the first direction Z direction perpendicular to the substrate.
  • a plurality of first grooves 101 arranged at intervals are opened, and the first grooves 101 penetrate the insulating layer 562 , the gate 55 and the insulating layer 561 .
  • an insulating material is filled in the first groove 101 to form an insulating layer 563 .
  • a second groove 102 is opened, and the second groove 102 is opened between adjacent insulating layers 563 , and the second groove 102 penetrates the insulating layer 562 , the gate 55 and the insulating layer 561 .
  • the ferroelectric layer 54 , the semiconductor layer 55 and the insulating layer 564 are sequentially formed in the second groove 102 .
  • the insulating layer 564, the semiconductor layer 55 and the ferroelectric layer 53 on the bottom surface of the second groove 102, and the insulating layer 564, the semiconductor layer 55 and the ferroelectric layer 53 on the upper surface of the insulating layer 562 are removed, so that a pattern will be formed.
  • 21f shows a structure in which the ferroelectric layer 53 , the semiconductor layer 55 , and the insulating layer 564 are sequentially formed only on the side wall surface of the second groove 102 .
  • the connecting electrodes 59 are formed to form the connecting electrodes 59 on the bottom surface of the second groove 102 , on the insulating layer 564 , and on the upper surface of the insulating layer 562 .
  • the semiconductor layer 53 can be electrically connected to the first electrode 51 through the connection electrode 59 .
  • an insulating material is filled in the remaining space in the second groove 102 to form an insulating layer 564 .
  • the second pole 52 is formed on the insulating layer 562 .
  • a plurality of memory cells arranged along the Y direction can also be produced, the first pole 51 is electrically connected to the second pole 52 through the semiconductor layer 53 and the connecting electrode 59, and the first poles of these memory cells 51 to form one of the bit line BL or the source line SL, and the second electrodes 52 of these memory cells are connected to form the other of the bit line BL or the source line SL.
  • Figures 22a to 22j show cross-sectional views of the process structure after each step in the process of manufacturing another memory cell involved in the present application.
  • the conductive layer 581 , the first pole 51 , the sacrificial layer 57 and the second pole 52 are sequentially stacked along the first direction Z direction perpendicular to the substrate.
  • first grooves 101 As shown in Figure 22b, along the second direction Y direction parallel to the substrate, a plurality of first grooves 101 arranged at intervals are opened, and the first grooves 101 penetrate the second pole 52, the sacrificial layer 57 and the first pole 51, that is, That is to say, the first groove 101 cannot penetrate through the conductive layer 581, because the conductive layer 581 finally serves as the source line SL or the bit line BL of the memory array.
  • an insulating material is filled in the first groove 101 to form an insulating layer 562, and a second groove 102 is opened, and the second groove 102 is located between two adjacent insulating layers 562, and the second groove 102 penetrates through the second pole 52 , the sacrificial layer 57 and the first pole 51 .
  • the sacrificial layer 57 in contact with the insulating layer 562 is removed to form a plurality of cavities 103 as shown in FIG. 22d.
  • a semiconductor layer, a ferroelectric layer and a gate can be formed in the cavity 103 .
  • the sacrificial layer 57 can be removed by selecting an etching process.
  • an etching process For example, when the material of the sacrificial layer 57 is silicon oxide, hydrofluoric acid etching medium can be used for etching.
  • a semiconductor layer 53 is formed on the wall surface of the cavity 8 .
  • the semiconductor layer 53 is not only formed on the wall surface of the concave cavity 103, but also on the side surfaces of the second pole 52 and the first pole 51 away from the insulating layer 562. A semiconductor layer 53 is also formed.
  • a ferroelectric layer 54 is formed again, and the ferroelectric layer 54 is formed on the semiconductor layer 53 .
  • the semiconductor layer 53 and the ferroelectric layer 54 are formed, there is still a space in the concave cavity 103, and the space is for accommodating the gate.
  • a gate 55 is formed in the remaining space of the cavity 103 .
  • a third groove 103 is opened so that the adjacent memory cells along the Y direction The gates 55 of the two memory cells are disconnected.
  • an insulating layer 563 is formed in the third groove 103 to insulate gates 55 of two adjacent memory cells along the Y direction.
  • a conductive layer 582 is formed on the upper surface of the second electrode 52 , and the conductive layer 582 is used as a source line SL or a bit line BL of the memory array.
  • the semiconductor layer 53 is formed with a cavity, and the ferroelectric layer 54 and the gate 55 are located in the cavity. Also, by forming the source line SL (or bit line BL) on the side close to the first pole 51, a plurality of memory cells share one source line SL, and by forming the bit line SL on the side close to the second pole 51 Line BL (or source line SL), so that multiple memory cells share one bit line BL.
  • the source line SL or bit line BL
  • Figures 23a to 23j show cross-sectional views of the process structure after each step in the process of manufacturing another memory cell involved in the present application.
  • the conductive layer 581 , the first pole 51 , the sacrificial layer 57 and the second pole 52 are sequentially stacked along the first direction Z direction perpendicular to the substrate.
  • first grooves 101 As shown in FIG. 23 b , along the second direction Y parallel to the substrate, a plurality of first grooves 101 arranged at intervals are opened, and the first grooves 101 penetrate the second pole 52 , the sacrificial layer 57 and the first pole 51 . That is, the first groove 101 cannot penetrate through the conductive layer 581, because the conductive layer 581 finally serves as the source line SL or the bit line BL of the memory array.
  • the semiconductor layer 53 is formed on the side wall surface of the first groove 101, and the insulating layer 562 is formed in the remaining space of the first groove 101, and the second groove 102 is opened again, and the second groove 102 is located in the adjacent Between the two insulating layers 562 , and the second groove 102 penetrates through the second pole 52 , the sacrificial layer 57 and the first pole 51 .
  • the sacrificial layer 57 in contact with the semiconductor layer 53 is removed to form a plurality of cavities 103 as shown in FIG. 23d. In this way, a ferroelectric layer and a gate can be formed in the cavity 103 .
  • a ferroelectric layer 54 is formed on the wall surface of the concave cavity 8 .
  • the ferroelectric layer 54 is not only formed on the wall surface of the concave cavity 103, but also on the walls of the second pole 52 and the first pole 51 away from the insulating layer 562.
  • a ferroelectric layer 54 is also formed on the sides of the .
  • the gate 55 is formed in the remaining space of the cavity 103 .
  • an insulating layer 563 is formed in the third groove 103 to insulate the gates 55 of two adjacent memory cells along the Y direction.
  • a conductive layer 582 is formed on the upper surface of the second electrode 52 , and the conductive layer 582 serves as a source line SL or a bit line BL of the memory array.
  • 24a to 24g show cross-sectional views of the process structure after each step in the process of manufacturing a memory cell involved in the present application.
  • the second pole 52, the sacrificial layer 57 and the first pole 51 are sequentially stacked along the first direction Z direction perpendicular to the substrate.
  • first grooves 101 As shown in FIG. 24 b , along the second direction Y parallel to the substrate, a plurality of first grooves 101 arranged at intervals are opened, and the first grooves 101 penetrate the first pole 51 , the sacrificial layer 57 and the second pole 52 .
  • a ferroelectric layer 54 and a gate 55 are sequentially formed on the side of the first groove 101 , and an insulating material is filled in the remaining space of the first groove 101 to form an insulating layer 581 .
  • an insulating material is filled in the remaining space of the first groove 101 to form an insulating layer 581 .
  • the second groove 102 is set in the adjacent structure with the ferroelectric layer 54 and the gate 55, and the second groove 102 penetrates the first pole 51, the sacrificial layer 57 and the second pole 52 .
  • the sacrificial layer 57 is removed to form a cavity 103 with an opening between the first pole 51 and the second pole 52 .
  • the surface of the first pole 51 facing the second pole 52 is the first wall surface, and the surface of the second pole 52 facing the first pole 51 is the second wall surface.
  • the semiconductor layer 53 is formed in the cavity 103 .
  • the semiconductor layer 53 is formed on the first wall of the first pole 51 , the second wall of the second pole 52 , and the side of the ferroelectric layer 54 away from the gate 55 .
  • it can be formed by deposition and other processes. For example, when the deposition method is used, as shown in FIG. 24e, the semiconductor layer 53 will be formed on the side of the first pole 51 and the side of the second pole 52 respectively.
  • the semiconductor layer 53 on the side surfaces of the first pole 51 and the second pole 52 needs to be removed, for example, dry etching, to obtain the structure shown in FIG. 24f .
  • insulating material is filled in the remaining space of the concave cavity and between the divided first pole 51 and the divided second pole 52 to form an insulating layer 582 .
  • the metal layer is formed on the side, and when the first groove 101 and the second groove 102 are opened, these grooves cannot penetrate through the metal layer.
  • the metal layer can be used as an electrical connection for multiple devices arranged along the Y direction.
  • the bit line BL of the second pole 52 of the memory cell is not limited to the bit lines BL.
  • a semiconductor layer is provided on one of the two opposite sides of the gate along the second direction, instead of surrounding the semiconductor along the periphery of the gate, so that More storage units are fabricated on the substrate to increase the storage capacity of the memory and the read/write speed of the memory.

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Abstract

本申请实施例提供一种铁电存储器及其形成方法、包含有该铁电存储器的电子设备。主要用于提升铁电存储器的存储密度。该铁电存储器包括：衬底和形成在衬底上的多个存储单元，每个存储单元包括铁电场效应晶体管；其中，铁电场效应晶体管包括栅极、半导体层、第一极和第二极，以及铁电层；第一极和第二极沿与衬底相垂直的第一方向排布，特别的是，栅极的沿与衬底平行的第二方向的相对两侧中的其中一侧具有半导体层，也就是说，半导体层不会沿着栅极的外围环绕设置，栅极和半导体层之间被铁电层隔离开。这样的话，通过仅在栅极的其中一侧设置半导体层，可以减少每个存储单元在衬底上所占据的面积，进而提升存储密度。

Description

铁电存储器及其形成方法、电子设备 技术领域
本申请涉及半导体技术领域，尤其涉及一种铁电存储器及其形成方法、包含有该铁电存储器的电子设备。
背景技术
铁电存储器作为一种新型存储器，较传统的动态随机存取存储器(dynamic random access memory，DRAM)，因同时具有非易失性、高速率，低功耗等优势，越来越广泛的被利用。现有的铁电存储器包括铁电场效应晶体管(ferroelectric filed-effect-transistor，FeFET)存储器。
图1a、图1b和图1c示出了三种不同结构的FeFET存储器中存储单元的工艺结构图。
如图1a，该存储单元的源极02和漏极03均通过在衬底01中掺杂形成，并在衬底01的位于源极02和漏极03之间形成沟道层04，在沟道层04上方形成有相堆叠的绝缘层05和栅极07，用于存储数据信息的铁电层06形成在绝缘层05和栅极07之间。在可实现的方式中，栅极07可以采用金属材料制得，从而，这样的结构可以被称为金属-铁电-绝缘层-半导体(metal-ferroelectric-insulator-semiconductor，MFIS)存储单元结构。
图1b所示存储单元和图1a所示存储单元的区别在于，在图1a结构的基础上还包括浮栅08，浮栅08位于绝缘层05和铁电层06之间，这样的结构可以被称为金属-铁电-金属-绝缘层-半导体(metal-ferroelectric-metal-insulator-semiconductor，MFMIS)存储单元结构。
由图1a和图1b可以看出，由于晶体管的源极02和漏极03均需要在衬底01中掺杂得到，进而该存储单元只能采用前道工艺(front end of line，FEOL)制作，这样的话，无法实现这些存储单元的三维堆叠，该存储器的存储密度就会受到限制，以使存储器的读写速度跟不上处理器的运算速度，最终导致计算机，手机等电子产品性能的提升受限。
图1c是另一种存储单元的工艺结构图，其中，沟道层04呈柱状结构，铁电层06环绕在沟道层04的外围，并采用绝缘层05将沟道层04和铁电层06隔离开，还有，栅极07、源极02和漏极03均环绕在铁电层06的外围。尽管该结构中的沟道层04为与衬底相垂直的垂直沟道，相比水平沟道的结构，可以在衬底的单位面积上集成更多的存储单元，但是，由于沟道层04、铁电层06和绝缘层05均为柱形结构，径向尺寸(如图1c的D方向尺寸)较大，其缩减能力也存在较大瓶颈，以使存储密度的提升也受到限制。
发明内容
本申请提供一种铁电存储器及其形成方法、包含有该铁电存储器的电子设备，主要目的提供一种可提升存储密度，提高存储容量的铁电存储器。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，本申请提供了一种铁电存储器，该铁电存储器包括：衬底和形成在衬底上的多个存储单元，每个存储单元包括铁电场效应晶体管；其中，铁电场效应晶体管包括栅极、半导体层(也可以被称为沟道层)、第一极和第二极，以及铁电层；第一极和第二极沿与衬底相垂直的第一方向排布，栅极位于第一极和第二极之间，栅极的沿第二方向相对两侧中的其中一侧具有半导体层，也就是说，半导体层不会沿着栅极的外围环绕设置，或者说栅极不会沿着半导体层的外围环绕设置，半导体层分别与第一极和第二极电连接，栅极和半导体层之间被铁电层隔离开，其中，第二方向被定义为与衬底相平行的方向。
本申请给出的铁电存储器中，由于存储单元中铁电场效应晶体管的第一极和第二极沿与衬底相垂直的方向排布，这样形成的铁电场效应晶体管是一种沟道为垂直沟道的晶体管结构，也就是垂直平面沟道结构晶体管，相比水平沟道的晶体管，可以减小该存储器在衬底上的投影面积，以提升存储密度，提高该电存储器的存储容量。
除此之外，特别的是，在该铁电场效应晶体管中，栅极的沿第二方向相对两侧中的其中一侧设置半导体层，而不是将半导体沿栅极的外围环绕，进而，可以减小整个铁电场效应晶体管在第二方向上的尺寸，存储单元又可以进一步得到微缩，基于这些特征，铁电场效应晶体管可以达到4F 2左右的占用面积，相比现有的6F 2甚至更大的占用面积，存储单元得到了有效的微缩，从而在衬底的单位面积上可以集成更多的存储单元，提升存储容量。
在第一方面可能的实现方式中，半导体层为沿第一方向延伸的竖直状结构，且半导体层的沿第一方向的相对两端中的一端与第一极接触，另一端与第二极接触。
通过将半导体层设置成沿竖直状结构，并使得与第一极和第二极欧姆接触，以使该半导体层形成与衬底垂直的垂直沟道结构，从而会进一步的使得该存储单元得到微缩。
在第一方面可能的实现方式中，半导体层为沿第一方向延伸的竖直状结构，在第一极中与第二极相对的面为第一壁面，在第二极中与第一极的相对的面为第二壁面；半导体层的沿第一方向的相对两端中的一端与第一壁面接触，另一端与第二壁面接触。
也就是说，竖直状的半导体层设置在第一极和第二极之间的区域内。
在第一方面可能的实现方式中，半导体层为沿第一方向延伸的竖直状结构，在第一极中与第二极相对的面为第一壁面，在第一极中与第一壁面毗邻的为第一侧面；在第二极中与第一极的相对的面为第二壁面，在第二极中与第二壁面毗邻的为第二侧面，第一侧面和第二侧面处于同一侧；半导体层的沿第一方向的相对两端中的一端与第一侧面接触，另一端与第二侧面接触。
可以这样讲，半导体层直立于第一极和第二极的一侧。
在第一方面可能的实现方式中，半导体层包括均沿第二方向延伸的第一部分和第二部分，以及沿第一方向延伸的且与第一部分和第二部分连接的第三部分；在第一极中与第二极相对的面为第一壁面，在第二极中与第一极的相对的面为第二壁面；第一部分设置在第一壁面上，第二部分设置在第二壁面上。
这样的话，从形成的该存储单元的性能角度讲，可以增加半导体层与第一极和第二极的接触面积，以降低第一极和半导体层之间，第二极和半导体层之间的电阻，提 高电流流速，最终提高该存储单元的读写速度；从形成该存储单元的工艺角度讲，可以简化制造工艺流程，降低工艺难度。
在第一方面可能的实现方式中，第一部分、第二部分和第三部分连接呈一体成型结构。
在第一方面可能的实现方式中，半导体层包括沿第二方向延伸的第一部分，和沿第一方向延伸且与第一部分连接的第三部分；在第一极中与第二极相对的面为第一壁面，在第二极中与第一极的相对的面为第二壁面；存储器还包括连接电极，连接电极设置在第二壁面上；第三部分与第一壁面接触，第一部分与连接电极接触。
也就是说，半导体层和铁电层均设计为接近L型的结构，从形成该存储单元的工艺角度讲，可以减少制备过程中刻蚀工艺步骤，进而可以提升制备效率，重要的是，因为减少刻蚀次数，会降低因为刻蚀造成铁电层具有较大污染的风险，进而，可以提升该铁电层的存储性能。
在第一方面可能的实现方式中，在第一极中与第二极相对的面为第一壁面，在第二极中与第一极的相对的面为第二壁面；栅极位于第一壁面和第二壁面之间的区域内。
将栅极设置在第一极和第二极之间的区域内，可以进一步减少该存储单元在衬底上的投影面积，以进一步提升集成密度。
在第一方面可能的实现方式中，在第一极中与第二极相对的面为第一壁面，在第一极中与第一壁面毗邻的为第一侧面；在第二极中与第一极的相对的面为第二壁面，在第二极中与第二壁面毗邻的为第二侧面，第一侧面和第二侧面处于同一侧；栅极位于第一侧面和第二侧面的一侧。
在第一方面可能的实现方式中，铁电场效应晶体管采用后道工艺制作。
当铁电场效应晶体管采用后道工艺制作时，控制电路通过前道工艺制作。该控制电路可以包括译码器、驱动器、时序控制器、缓冲器或输入输出驱动中的一个或多个电路，还可以包括其他功能电路。这样一来，通过将存储单元的铁电场效应晶体管通过后道工艺制作，该存储单元就可以采用三维集成法沿着与衬底相垂直的方向堆叠，实现该存储器的高密度集成。
在第一方面可能的实现方式中，多个存储单元包括沿与衬底相平行方向排布，且相邻的第一存储单元和第二存储单元；第一存储单元中的半导体层，与第二存储单元中的半导体层相对布设。
在第一方面可能的实现方式中，铁电存储器还包括：位线、源线和字线；其中，栅极与字线电连接，第一极与源线电连接，第二极与位线电连接。
也就是说，通过给字线、位线和源线施加电压，以控制铁电层两端的电压差，实现读写操作。
该位线、源线和字线可以通过后道工艺制作，或者，可以通过前道工艺制作，或者，部分通过前道工艺制作，部分通过后道工艺制作。
在第一方面可能的实现方式中，源线和位线均沿与衬底相平行的第二方向延伸；字线沿与衬底相平行的第三方向延伸，第二方向与第三方向垂直；沿第二方向排布的多个存储单元中的第一极与同一条源线电连接；沿第二方向排布的多个存储单元中的第二极与同一条位线电连接；沿第三方向排布的多个存储单元中的栅极与同一条字线 电连接。
通过使沿第二方向的多个第一极共用同一条源线，沿第二方向的多个第二极共用同一条位线，以及沿第三方向的多个栅极共用同一条字线，在进行读写时，可以多条位线、多条源线，以及多条字线施加电压，以选择要读写的存储单元。
在第一方面可能的实现方式中，第一层存储阵列中沿第二方向延伸的源线，靠近第二层存储阵列中沿第二方向延伸的位线；其中，第一层存储阵列中的源线，与第二层存储阵列中的位线为彼此独立的信号线。
在可实现的结构中，可以在第一层存储阵列的源线和第二层存储阵列的位线之间形成绝缘层，以使位线和源线为彼此独立的信号线。
在第一方面可能的实现方式中，多个存储单元形成沿第一方向排布的第一层存储阵列和第二层存储阵列；第一层存储阵列中沿第二方向延伸的源线，靠近第二层存储阵列中沿第二方向延伸的源线；其中，第一层存储阵列中的源线，与第二层存储阵列中的源线共用同一条信号线。
由于第一层存储阵列中的源线，与第二层存储阵列中的源线共用同一条信号线，这样的话，可以减小每一层存储阵列的高度，实现在第一方向上更高的集成密度。
在第一方面可能的实现方式中，在写入阶段，字线用于接收字线控制信号，源线和位线用于接收相同的控制信号，字线控制信号和源线上的控制信号的电压差使得铁电膜层极化。比如，字线控制信号大于零且大于操作电压时，铁电膜层发生正极化，字线控制信号小于零且绝对值大于操作电压时，铁电膜层发生负极化。
在第一方面可能的实现方式中，在读取阶段，字线用于接收接地，源线用于接收源线控制信号，位于用于接收位线控制信号，源线控制信号和位线控制信号具有正电压差，铁电场效应晶体管导通。比如，当铁电场效应晶体管导通，读取“1”。
在第一方面可能的实现方式中，在读取阶段，字线用于接收接地，源线用于接收源线控制信号，位于用于接收位线控制信号，源线控制信号和位线控制信号具有负电压差，铁电场效应晶体管断开。比如，当铁电场效应晶体管断开，读取“0”。
在第一方面可能的实现方式中，铁电存储器还包括控制器，控制器用于：输出字线控制信号以控制字线上的电压；输出源线控制信号以控制源线上的电压；以及输出位线控制信号以控制位线上的电压。
第二方面，本申请还提供了一种电子设备，包括处理器和上述第一方面任一实现方式中的铁电存储器，处理器与铁电存储器电连接。
本申请实施例提供的电子设备包括第一方面实施例的铁电存储器，因此本申请实施例提供的电子设备与上述技术方案的铁电存储器能够解决相同的技术问题，并达到相同的预期效果。
在第二方面可能的实现方式中，处理器和铁电存储器被集成在同一芯片中。
这样形成的存储器可以被称为嵌入式存储结构。
第三方面，本申请还提供了一种铁电存储器的形成方法，该形成方法包括：沿与衬底相垂直的第一方向形成第一极和第二极，以及形成半导体层、栅极和铁电层，且 栅极的沿第二方向相对两侧中的其中一侧形成半导体层，半导体层分别与第一极和第二极电连接，铁电层形成在栅极和半导体层之间，以形成铁电场效应晶体管。
这样的话，通过该方法制得的存储单元中，由于第一极和第二极沿与衬底相垂直的方向布设，进而，半导体层是一种与衬底相垂直的垂直沟道，所以，该存储单元在衬底上的投影面积较小，可以实现存储单元的高密度集成。
还有，由于栅极的沿第二方向相对两侧中的其中一侧具有半导体层，进而，可以减小整个晶体管在第二方向上的尺寸，存储单元又可以进一步得到微缩，基于这些特征，会明显的提升该存储器的存储密度，提高存储容量，从而提升该存储器的读写速度。
在第三方面可能的实现方式中，在形成存储单元之前，形成方法还包括：在衬底上形成控制电路；在控制电路上形成电连接控制电路和存储单元的互连线。
也就是说，该存储器中的存储单元是通过后道工艺制作，该存储单元就可以采用三维集成法沿着与衬底相垂直的方向堆叠，实现该存储器的高密度集成。
在第三方面可能的实现方式中，在形成所述铁电场效应晶体管时，包括：沿第一方向依次堆叠第一导电层、牺牲层和第二导电层；开设贯通第二导电层和牺牲层，以及所述第一导电层的第一槽；沿与衬底相平行的第二方向，在第一槽的侧壁面依次形成铁电层和栅极；去除与铁电层相接触的牺牲层，以形成凹腔，凹腔的两侧形成第一极和第二极；在凹腔的至少靠近铁电层的壁面上形成半导体层，以制得铁电场效应晶体管。
在第三方面可能的实现方式中，在形成所述铁电场效应晶体管时，包括：沿第一方向依次堆叠第一导电层、牺牲层和第二导电层；开设贯通第二导电层和牺牲层，以及所述第一导电层的第一槽；沿与衬底相平行的第二方向，在第一槽的侧壁面形成半导体层；去除与半导体层相接触的牺牲层，以形成凹腔，凹腔的两侧形成第一极和第二极；在凹腔内形成栅极和用于隔离栅极和半导体层的铁电层，以制得铁电场效应晶体管。
在第三方面可能的实现方式中，在形成所述铁电场效应晶体管时，包括：沿第一方向依次堆叠第一导电层、牺牲层和第二导电层；开设贯通第二导电层和牺牲层，以及所述第一导电层的第一槽；去除牺牲层，以形成凹腔，凹腔的两侧形成第一极和第二极；在凹腔内形成半导体层、栅极和用于隔离栅极和半导体层的铁电层，以制得铁电场效应晶体管。
在第三方面可能的实现方式中，在形成所述铁电场效应晶体管时，包括：沿第一方向依次堆叠第一导电层、牺牲层和第二导电层；开设贯通至第一导电层的第一槽；在第一槽的侧面依次形成铁电层和半导体层，以使所述第二导电层形成栅极，第一导电层形成第一极；在半导体层上形成第二极，以制得铁电场效应晶体管。
附图说明
图1a为现有技术中一种FeFET存储器存储单元的工艺结构图；
图1b为现有技术中一种FeFET存储器存储单元的工艺结构图；
图1c为现有技术中一种FeFET存储器存储单元的工艺结构图；
图2为本申请实施例提供的一种电子设备中的电路图；
图3为本申请实施例提供的一种铁电存储器的电路图；
图4为本申请实施例提供的一种铁电存储器的存储阵列的电路图；
图5a为本申请实施例提供的一种铁电存储器的存储单元的工艺结构图；
图5b为图5a的A-A剖面图；
图6为本申请实施例提供的一种铁电存储器的存储阵列的简单俯视示意图；
图7a为本申请实施例提供的一种铁电存储器的存储单元的工艺结构图；
图7b为图7a的B-B剖面图；
图8a为本申请实施例提供的一种铁电存储器的存储单元的工艺结构图；
图8b为图8a的C-C剖面图；
图9a为本申请实施例提供的一种铁电存储器的存储单元的工艺结构图；
图9b为图9a的D-D剖面图；
图10a为本申请实施例提供的一种铁电存储器的存储单元的工艺结构图；
图10b为图10a的E-E剖面图；
图11a为本申请实施例提供的一种铁电存储器的存储单元的工艺结构图；
图11b为图11a的F-F剖面图；
图12为本申请实施例提供的一种铁电存储器的一层存储阵列的三维工艺结构图；
图13为图12的M1向视图；
图14为本申请实施例提供的一种铁电存储器的多层存储阵列的三维工艺结构图；
图15为图14的M2向视图；
图16为本申请实施例提供的一种铁电存储器的多层存储阵列的三维工艺结构图；
图17为图16的M3向视图；
图18为本申请实施例提供的一种存储器芯片的工艺原理图；
图19为本申请实施例提供的一种铁电存储器的存储阵列的电路图；
图20a至图20j为本申请实施例提供的形成一种存储单元各步骤完成后的工艺结构图；
图21a至图21j为本申请实施例提供的形成一种存储单元各步骤完成后的工艺结构图；
图22a至图22j为本申请实施例提供的形成一种存储单元各步骤完成后的工艺结构图；
图23a至图23i为本申请实施例提供的形成一种存储单元各步骤完成后的工艺结构图；
图24a至图24g为本申请实施例提供的形成一种存储单元各步骤完成后的工艺结构图。
附图标记：
01、100-衬底；02-源极；03-漏极；04-沟道层；05-绝缘层；06-铁电层；07-栅极；08-浮栅；
51-第一极；52-第二极；53-半导体层；531-第一部分；532-第二部分；533-第三部分；54-铁电层；541-第一部分；542-第二部分；543-第三部分；55-栅极；561、562、563、564-绝缘层；57-牺牲层、581、582-导电层；59-连接电极；3101-第一层存储阵 列；3102-第二层存储阵列；3103-第三层存储阵列；400、401、402、403、404-存储单元；101-第一槽；102-第二槽；103-凹腔；104-第三槽。
具体实施方式
铁电存储器是基于铁电材料的铁电效应来存储数据。铁电存储器因其超高的存储密度、低功耗和高速度等优势，有望成为替代DRAM的主要竞争者。铁电存储器中的存储单元包含铁电电容，铁电电容包括由铁电材料制得的铁电层。由于铁电材料的非线性特性，铁电材料的介电常数不仅可以调节，而且在铁电层极化状态翻转前后的差值非常大，这使得铁电电容与其他电容相比体积较小，比如，比DRAM中的用于存储电荷的电容体积小很多。
在铁电存储器中，铁电层可以采用常见的铁电材料形成，比如，ZrO 2，HfO 2等。当一个电场被施加到铁电层时，中心原子顺着电场停在低能量状态，反之，当电场反转被施加到该铁电层时，中心原子顺着电场的方向在晶体里移动并停在另一低能量状态。大量中心原子在晶体单胞中移动耦合形成铁电畴(ferroelectric domains)，铁电畴在电场作用下形成极化电荷。铁电畴在电场下反转所形成的极化电荷较高，铁电畴在电场下无反转所形成的极化电荷较低，这种铁电材料的二元稳定状态使得铁电可以作为存储器。
本申请实施例提供一种包含铁电存储器的电子设备。图2为本申请实施例提供的一种电子设备200中的电路图，该电子设备200可以是终端设备，例如手机，平板电脑，智能手环，也可以是个人电脑(personal computer，PC)、服务器、工作站等。电子设备200包括总线205，以及与总线205连接的片上系统(system on chip，SOC)210和只读存储器(read-only memory，ROM)220。SOC210可以用于处理数据，例如处理应用程序的数据，处理图像数据，以及缓存临时数据。ROM220可以用于保存非易失性数据，例如音频文件、视频文件等。ROM220可以为PROM(programmable read-only memory，可编程序只读存储器)，EPROM(erasable programmable read-only memory，可擦除可编程只读存储器)，闪存(flash memory)等。
此外，电子设备200还可以包括通信芯片230和电源管理芯片240。通信芯片230可以用于协议栈的处理，或对模拟射频信号进行放大、滤波等处理，或同时实现上述功能。电源管理芯片240可以用于对其他芯片进行供电。
在一种实施方式中，SOC210可以包括用于处理应用程序的应用处理器(application processor，AP)211，用于处理图像数据的图像处理单元(graphics processing unit，GPU)212，以及用于缓存数据的随机存取存储器(random access memory，RAM)213。
上述AP211、GPU212和RAM213可以被集成于一个裸片(die)中，或者分别集成于多个裸片(die)中，并被封装在一个封装结构中，例如采用2.5D(dimension)封装，或者3D(dimension)封装，或其他的先进封装技术。在一种实施方式中，上述AP211和GPU212被集成于一个die中，RAM213被集成于另一个die中，这两个die被封装在一个封装结构中，以此获得更快的die间数据传输速率和更高的数据传输带宽。
图3为本申请实施例提供的电子设备中的一种铁电存储器300的电路图。该铁电存储器300可以是如图2所示的RAM213，属于FeRAM。在一种实施方式中，铁电存储器300也可以是设置于SOC210外部的RAM。本申请不对铁电存储器300在电子设备中的位置以及与SOC210的位置关系进行限定。
继续如图3，铁电存储器300包括存储阵列310、译码器320、驱动器330、时序控制器340、缓存器350和输入输出驱动360。存储阵列310包括多个呈阵列排列的存储单元400，其中每个存储单元400可以用于存储1bit或者多bit的数据。存储阵列310还包括字线(word line，WL)、位线(bit line，BL)、源线(source line，SL)等信号线。每一个存储单元400都与对应的字线WL、位线BL和源线SL电连接。上述字线WL、位线BL或源线SL中的一个或多个用于通过接收控制电路输出的控制电平，选择存储阵列中待读写的存储单元400，以改变存储单元400中的铁电电容的极化方向，从而实现数据的读写操作。为了方便，本申请实施例将上述字线WL、位线BL和源线SL统称为信号线。
在图3所示铁电存储器300结构中，译码器320用于根据接收到的地址进行译码，以确定需要访问的存储单元400。驱动器330用于根据译码器320产生的译码结果来控制信号线的电平，从而实现对指定存储单元400的访问。缓存器350用于将读取的数据进行缓存，例如可以采用先入先出(first-in first-out，FIFO)来进行缓存。时序控制器330用于控制缓存器350的时序，以及控制驱动器330驱动存储阵列310中的信号线。输入输出驱动360用于驱动传输信号，例如驱动接收的数据信号和驱动需要发送的数据信号，使得数据信号可以被远距离传输。
上述存储阵列310、译码器320、驱动器330、时序控制器340、缓存器350和输入输出驱动360可以集成于一个芯片中，或者，也可以分别集成于多个芯片中。
图4给出了一种铁电存储器中的存储阵列310的部分电路图，该存储阵列310示例性的给出了4个存储单元400，每个存储单元均包括铁电场效应晶体管(ferroelectric filed-effect-transistor，FeFET)，其中，铁电场效应晶体管的栅极(gate)与字线(word line，WL)电连接，铁电场效应晶体管的第一极与源线(source line，SL)电连接，铁电场效应晶体管的第二极与位线(bit line，BL)电连接。
在本申请中，铁电场效应晶体管的漏极(drain)或源极(source)中的一极称为第一极，相应的另一极称为第二极。漏极和源极可以根据电流的流向而确定，比如，在图4中，电流从左至右时，则左端为漏极，右端为源极，相反的，当电流从右向左时，右端为漏极，左端为源极。
图4所示的每一个存储单元400中，铁电场效应晶体管包括用于存储数据信息的铁电层，铁电层的自身极化场的存在使得铁电场效应晶体管的阈值电压发生偏移，正向和负向极化场使得阈值电压往不同方向偏移，两者之间的差距形成铁电场效应晶体管的存储窗口。当铁电晶体管的栅极即图4中的字线施加介于两个阈值电压之间的电平，铁电场效应晶体管的源漏极之间存在高阻和低阻状态中的某一种状态,可以通过在源漏间施加电压，读取电流来分别这两种状态，从而实现存储的功能。
随着电子设备中集成电路技术的不断演进，电子设备的芯片上单位面积的晶体管 数量不断增加，从而让电子设备的性能得到不断的优化。一方面，处理器在单位时间能够运算的数据量不断提高，比如，在上述图2中的GPU212的运算的数据量在快速的提升；另一方面，存储器的存储密度也不断增长，从而满足信息时代下对于数据处理的需求。然而，由于处理器中的逻辑单元和存储器存储单元结构上和工艺上的不同，导致处理器和存储器二者的性能提高的程度出现差距。也就是说，存储器的存储密度较低、读写速度跟不上处理器的运算速度，制约着电子设备性能的快速提升。
本申请实施例给出了一种铁电存储器，该铁电存储器具有较大的存储密度，较高的存储容量，以及读写速度也较快，从而，可以缩小与处理器性能提升的差距。
图5a给出了一种铁电存储器中一个存储单元400，以及衬底100的三维工艺结构图，图5b是图5a的A-A剖面图。
结合图5a和图5b，存储单元400包括铁电场效应晶体管，也可以这样讲，一个铁电场效应晶体管就为一个存储单元400，那么，图5a和图5b示出的400也是一个铁电场效应晶体管的工艺结构图，该铁电场效应晶体管包括第一极51和第二极52，以及半导体层53和栅极55，该半导体层53也可以被称为沟道层。
可以这样理解，这里的铁电场效应晶体管是一种具有三端子的晶体管器件，那么，该铁电场效应晶体管可以选择NMOS(N-channel metal oxide semiconductor，N沟道金属氧化物半导体)管，或者可以选择PMOS(P-channel metal oxide semiconductor，P沟道金属氧化物半导体)管。
继续结合图5a和图5b，第一极51和第二极52沿与衬底100相垂直的第一方向Z方向排布，栅极55位于第一极51和第二极52之间，并且栅极55与第一极51之间绝缘，栅极55与第二极52之间绝缘。
特别的是，本申请给出的栅极55的沿与衬底100相平行方向(如图5a和图5b的Y方向)的相对两侧中的其中一侧具有半导体层53，并且，半导体层53分别与第一极51和第二极52电连接。
可以这样理解“栅极55的沿与衬底100相平行的Y方向的相对两侧中的其中一侧具有半导体层53”该特征，如图5b所示，栅极55沿Y方向的相对两侧面分别为P1侧面和P2侧面，半导体层53位于P2侧面一侧，或者是，半导体层53位于P1侧面一侧，也就是说，栅极55的P1侧面和P2侧面中的一侧面设置有半导体层53，另一侧面没有设置半导体层53，或者说，半导体层53没有沿栅极55的外围环绕设置。
这样设计栅极55与半导体层53在工艺结构上的位置关系，可以减少该铁电场效应晶体管在Y方向上的尺寸，进而，可以使得该铁电场效应晶体管的尺寸得以微缩，实现该存储单元的高密度集成，提升存储容量，相对应的，也可以提升该存储器的读写速度，降低与处理器发展不匹配的程度，当存储密度增大，存储容量提升的情况下，可以实现更高的数据传输带宽。
基于图5a和图5b对该存储单元400的描述，位于第一极51和第二极52之间的半导体层53是与衬底100相垂直布设的垂直沟道，相比水平沟道的晶体管结构，可以减小在衬底100上的投影面积，实现该存储单元400的微缩，以提升存储器的存储密度，提高存储容量，提升读写速度。比如，如图6所示，该铁电存储器中一个存储单元400在X方向和Y方向上分别仅具有1F的活动区域和1F的场区域，最终一个存储 单元400占据2FX2F＝4F 2个区域，随着半导体器件的不断微缩，相比其他的平行沟道的晶体管结构，本申请给出的具有垂直沟道的铁电场效应晶体管可以明显的提升存储密度。该结构的铁电场效应晶体管可以被称为具有垂直结构的氧化物半导体铁电场效应晶体管(vertical oxide semiconductor FeFET，VOS-FeFET)。
另外，这里的第一极51和第二极52均是一种膜层结构，比如，可以通过沉积、溅射工艺制得，而不是在衬底100中掺杂制得，这样一来，该存储单元400可以实现在衬底100上的三维(3D)堆叠，以实现高密度集成。
还有，再结合图5a和图5b，该存储单元400还包括用于存储电荷的铁电层54，栅极55和半导体层53之间被铁电层54隔离开，即铁电层54被设置在栅极55和半导体层53之间。
上述的第一极51和第二极52的材料均为导电材料，例如金属材料。在可选择的实施方式中，第一极51和第二极52的材料可以为TiN(氮化钛)、Ti(钛)、Au(金)、W(钨)、Mo(钼)、In-Ti-O(ITO，氧化铟锡)、Al(铝)、Cu(铜)、Ru(钌)、Ag(银)等导电材料中的一种或多种。
上述的栅极55的材料为导电材料，例如金属材料。在可选择的实施方式中，可以为TiN(氮化钛)、Ti(钛)、Au(金)、W(钨)、Mo(钼)、In-Ti-O(ITO，氧化铟锡)、Al(铝)、Cu(铜)、Ru(钌)、Ag(银)等导电材料中的一种或多种。
上述的半导体层53的材料可以为Si(硅)、poly-Si(p-Si，多晶硅)、amorphous-Si(a-Si，非晶硅)、In-Ga-Zn-O(IGZO，铟镓锌氧化物)多元化合物、ZnO(氧化锌)、ITO(氧化铟锡)、TiO 2(二氧化钛)、MoS 2(二硫化钼)、WS 2(二硫化钨)等半导体材料中的一种或多种。
上述的用于绝缘栅极55和第一极51，以及栅极55和第二极52之间的绝缘层的材料可以SiO 2(二氧化硅)、Al 2O 3(氧化铝)、HfO 2(二氧化铪)、ZrO 2(氧化锆)、TiO 2(二氧化钛)、Y 2O 3(三氧化二钇)和Si 3N 4(氮化硅)等绝缘材料中的一种或多种。
上述的铁电层54的材料可以为ZrO 2，HfO 2，Al掺杂HfO 2，Si掺杂HfO 2，Zr参杂HfO 2，La掺杂HfO 2，Y掺杂HfO 2等铁电材料或者基于该材料的进行其他元素掺杂的材料中的一种或者多种。
本申请给出的半导体层53和铁电层54具有多种可实现的结构。下面结合附图分别进行解释。
结合图5b，半导体层53为沿与衬底垂直的Z方向延伸的竖直状结构，并且，第一极51具有与第二极52相对的第一壁面M1，第二极52具有与第一极51相对的第二壁面M2，半导体层53的沿Z方向的相对两端中的一端与第一壁面M1接触以耦合电连接，半导体层53的沿Z方向的相对两端中的另一端与第二壁面M2接触以耦合电连接。
还有，铁电层54也为竖直状结构，并且铁电层54与半导体层53沿与衬底100相平行的Y方向并列排布。
另外，栅极55位于第一极51的第一壁面M1和第二极52的第二壁面M2之间的 区域内。
在可实现的工艺中，可以沿图5b所示的Z方向依次堆叠第二极52、第一绝缘层、栅极55和第二绝缘层，然后在堆叠的这些结构中沿Z方向开设贯通至第二极52的槽，并在槽的侧面依次堆叠铁电层54和半导体层53；最后在第二绝缘层上形成第一极51，这里的第一绝缘层作为绝缘栅极52和第二极52的绝缘结构，这里的第二绝缘层作为绝缘栅极52和第一极51的绝缘结构。
基于上述对该存储单元工艺流程，以及存储单元结构的描述，可以看出，半导体层53为与衬底100相垂直的垂直沟道，且沿Y方向仅具有一层结构，这样的话，可以实现该存储单元400在Y方向的微缩，以提升存储密度。
图7a和图7b给出了另一种存储单元400的工艺结构图，图7b是图7a的B-B剖面图，结合图7a和图7b所示，和上述图5a和图5b所示存储单元400相同之处在于，半导体层53也为沿与衬底垂直的Z方向延伸的竖直状结构，不同之处在于，本实施例中的半导体层53的设置位置和上述的5a和图5b中的半导体层53的设置位置不一样，在图7b中，第一极51具有与第二极52相对的第一壁面M1，第二极52具有与第一极51相对的第二壁面M2，另外，第一极51具有与第一壁面M1相毗邻的第一侧面C1，第二极52具有与第二壁面M2相毗邻的第二侧面C2，并且第一侧面C1和第二侧面C2位于同一侧，半导体层53位于第一侧面C1和第二侧面C2一侧，半导体层53的沿Z方向的相对两端中的一端与第一侧面C1接触以耦合电连接，半导体层53的沿Z方向的相对两端中的另一端与第二侧面C2接触以耦合电连接。
在实际可实现的工艺中，半导体层53的与第一极51接触的端部与第一极51的背离第二极52的端面是齐平的，还有，半导体层53的与第二极52接触的端部与第二极52的背离第一极51的端面是齐平的。
继续结合图7b所示，由于栅极55位于第一壁面M1和第二壁面M2之间的区域内，这样的话，可以进一步减小该存储单元400在衬底上的投影面积，以进一步使该存储单元尺寸微缩。
在本实施例中，结合图7b，铁电层54包括沿与衬底平行的Y方向延伸的第一部分541和第二部分542，以及连接第一部分541和第二部分542的第三部分543，第一部分541形成在第一壁面M1上，第二部分542形成在第二壁面M2上，以使铁电层54围城具有开口的凹腔结构，栅极55设置在该凹腔内。
如此一来，第一部分541作为用于绝缘栅极55和第一极51的绝缘结构，第二部分542作为用于绝缘栅极55和第二极52的绝缘结构。
在可实现的工艺中，可以先依次堆叠第二极52、牺牲层(因为最终需要去除，从而被定义为牺牲层结构)和第一极51；然后在堆叠的三层结构内开设贯通他们的槽，并在槽的靠近第一极51、牺牲层和第二极52的侧面形成半导体层53；再去除牺牲层，以在第一极51和第二极52之间形成凹腔；再在凹腔内形成铁电层54和栅极55，以制得图7b所示的存储单元。从形成图7a和图7b所示结构的工艺角度讲，制备工艺简单，易于实现。特别的是，每一个存储单元400的半导体层53仅包括沿Z方向延伸的沟道结构，以减小多个存储单元沿与衬底平行的Y方向的尺寸，从而使得在衬底的单 位面上形成更多的存储单元。
图8a和图8b给出了另一种存储单元400的工艺结构图，图8b是图8a的C-C剖面图，结合图8a和图8b所示，和上述图7a和图7b所示存储单元400相同之处在于，半导体层53也为沿与衬底垂直的Z方向延伸的竖直状结构，相同之处还包括：铁电层54也包括沿与衬底平行的Y方向延伸的第一部分541和第二部分542，以及连接第一部分541和第二部分542的第三部分543，第一部分541形成在第一壁面M1上，第二部分542形成在第二壁面M2上，以使铁电层54围城具有开口的凹腔结构，栅极55位于该凹腔内。和上述图7a和图7b所示存储单元400不同之处在于，本实施例中的半导体层53的设置位置和上述的7a和图7b中的半导体层53的设置位置不一样，在该实施例中，半导体层53的沿Z方向的相对两端中的一端与第一极51的第一壁面M1接触以耦合电连接，半导体层53的沿Z方向的相对两端中的另一端与第二极52的第二壁面M2接触以耦合电连接。
基于对图8a和图8b所示存储单元的描述，由于栅极55、半导体层53和铁电层54均位于第一极51和第二极52之间的区域内，这样的话，会进一步使得该存储单元400在Y方向上的尺寸得以微缩，另外，由于铁电层54包括第一部分541和第二部分542，以及第三部分543，从而使得铁电层54具有较大的面积，可以提升该存储器的读写效率。
在上述的包括第一部分541和第二部分542，以及第三部分543的铁电层54结构中，该第一部分541和第二部分542，以及第三部分543可以是一体成型结构，即在可实现的工艺步骤中，通过一次工艺一次性形成第一部分541、第二部分542和第三部分543。
图9a和图9b给出了另一种存储单元400的工艺结构图，图9b是图9a的D-D剖面图，结合图9a和图9b所示，和上述图8a和图8b所示存储单元400相同之处在于，该实施例中铁电层54也包括沿与衬底平行的Y方向延伸的第一部分541和第二部分542，以及连接第一部分541和第二部分542的第三部分543，以使铁电层54围城具有开口的凹腔结构，栅极55位于该凹腔内，不同之处在于，半导体层53包括均沿与衬底100平行的Y方向延伸的第一部分531和第二部分532，以及包括沿与衬底100垂直的Z方向延伸的第三部分533，且第三部分533与第一部分531和第二部分532相连接。也就是说，该实施例中的半导体层53形成具有开口的凹腔结构，第一部分531设置在第一壁面M1上，第二部分532设置在第二壁面M1上，铁电层54和栅极55位于半导体层53围城的凹腔内。
从形成这种结构的晶体管的性能上讲，由于第一极51的第一壁面M1和第二极52的第二壁面M2均具有半导体层。这样的话，就可以增加半导体层与第一极51之间的欧姆接触面积，以及增加半导体层与第二极52之间的欧姆接触面积，进而，会减小半导体层与第一极51之间的电阻，以及减小半导体层与第二极52之间的电阻，从而提高电流流速，最终提高该存储单元的读写速度。
从形成这种结构的晶体管的工艺角度讲，在形成该晶体管时，如图9b所示，在第 一极51和第二极52之间的区域内，采用物理气相沉积法(physical vapor deposition，
PVD)，或者化学气相沉积法(chemical vapor deposition，CVD)在第一壁面M1和第二壁面M2，以及第一壁面M1和第二壁面M2之间形成半导体层结构，不需要去除第一壁面M1和第二壁面M2上的半导体层，这样的话，就可以简化制造工艺流程，降低工艺难度。
基于上述对该存储单元400结构的描述，沿与衬底100相平行的Y方向，仅具有一层半导体层结构，相比现有的两层半导体层结构，可以实现该存储单元的微缩，提升整个存储器的存储密度。
图10a和图10b给出了另一种存储单元400的工艺结构图，图10b是图10a的E-E剖面图，结合图10a和图10b所示，和上述图9a和图9b所示存储单元400相同之处在于，该实施例中的半导体层53也包括均沿与衬底100平行的Y方向延伸的第一部分531和第二部分532，以及沿与衬底100垂直的Z方向延伸的第三部分533，且第三部分533与第一部分531和第二部分532相连接。也就是说，该实施例中的半导体层53形成具有开口的凹腔结构，第一部分531设置在第一壁面M1上，第二部分532设置在第二壁面M1上。和上述图9a和图9b所示存储单元不同之处在于，栅极55的设置位置不同，在该实施例中，如图10b，栅极55位于第一侧面C1和第二侧面C2一侧，且栅极55与第一极51、第二极52和半导体层53之间均被铁电层54隔离开。
在实际可实现的工艺中，栅极55的靠近第一极51的端部与第一极51的背离第二极52的端面是齐平的，还有，栅极55的靠近第二极52的端部与第二极52的背离第一极51的端面是齐平的。这样的结构也可以被定为栅极55处于第一极51和第二极52之间。
由于第一极51的第一壁面M1和第二极52的第二壁面M2均具有半导体层。这样的话，就可以增加半导体层与第一极51之间的欧姆接触面积，以及增加半导体层与第二极52之间的欧姆接触面积，进而，会减小半导体层与第一极51之间的电阻，以及减小半导体层与第二极52之间的电阻，以提高电流流速，提高该存储单元的读写速度。
另外，如图10b，第一部分531、第二部分532和第三部分533围城具有开口的凹腔，在凹腔内填充有另一绝缘层56。
在可实现的工艺中，可以沿图10b所示的Z方向依次堆叠第二极、牺牲层和第一极，然后在堆叠的这些结构中沿Z方向开设贯通第二极、牺牲层和第一极的槽，并在槽的侧面依次堆叠铁电层54和栅极55；再去除牺牲层，以在第一极51和第二极52之间形成凹腔，并在凹腔内填充半导体层33，再在凹腔的剩余空间内填充绝缘材料，形成绝缘层56。
图11a和图11b给出了另一种存储单元400的工艺结构图，图11b是图11a的F-F剖面图，结合图11a和图11b所示，该实施例中的半导体层53包括沿与衬底100平行的Y方向延伸的第一部分531，以及沿与衬底100垂直的Z方向延伸的第三部分533，且第三部分533与第一部分531相连接，其中，第三部分533的一端与第一极51的第 一壁面M1接触，第二极52上还设置有连接电极59，第一部分531与连接电极59接触耦合电连接。也就是说，该实施例中的半导体层53为接近L型的结构，铁电层54也为接近L型的结构。
这里的连接电极59的材料可以与第二极52的材料相同，或者不同。
当制备图11a和图11b所示结构的存储单元时，可以避免因为较多次数的刻蚀工艺对铁电层54造成损坏，影响该存储单元的读写性能的现象，下面会对制备该结构的存储单元的工艺步骤进行详细解释。
基于上述对各种不同结构的存储单元400的描述，沿与衬底100相平行的Y方向，仅具有一层半导体层结构，相比现有的两层半导体层结构，可以实现该存储单元的微缩，提升整个存储器的存储密度。
除此之外，由于本申请给出的存储单元的半导体层53可以采用氧化物半导体材料制得，从工艺角度讲，半导体层53的氧化物半导体材料均匀性易于控制，从性能角度讲，半导体层53的氧化物半导体材料具有较高的迁移率，以使该存储单元具有高禁带宽度，高地空穴迁移率、刷新频率低，存储性能更优等特点。
除上述给出的几种不同结构的存储单元之外，只要存储单元中的沟道为垂直沟道的铁电场效应晶体管均在本申请保护的范围之内，在此不在对其余的结构进行解释。
在上述的不同结构的存储单元400中，栅极53与字线WL电连接，第一极51与源线SL电连接，第二极与位线BL电连接。
当多个如上述所示的存储单元400沿与衬底100相平行的第二方向Y方向和第三方向X方向呈阵列排布时，如图12所示，会形成一层存储阵列310。这样一来，沿第二方向Y方向排布的多个存储单元的第一极51共用一条沿第二方向Y方向延伸的源线SL，沿第二方向Y方向排布的多个存储单元的第二极52共用一条沿第二方向Y方向延伸的位线BL，还有，沿第三方向X方向排布的多个存储单元的栅极55共用一条沿第三方向X方向延伸的字线WL，并且，多条字线WL沿第二方向Y方向平行排布。
在一些可选择的实施方式中，如图13所示，图13是图12所示结构的M1向视图，沿第二方向Y方向排布的多个存储单元中，相邻两个存储单元中的半导体层53相对布设，比如，在图13中，示出了沿第二方向Y方向依次排布的存储单元401、存储单元402、存储单元403和存储单元404，其中，存储单元401的半导体层53与存储单元402的半导体层53相对布设，存储单元402的栅极55与存储单元403的栅极55相对布设，进而，存储单元403的半导体层53与存储单元404的半导体层53相对布设。
在图12和图13所示存储阵列的基础上，还包括更多的存储单元400时，就可以沿与衬底100相垂直的第一方向Z方向依次堆叠多层存储阵列，以形成三维存储器结构，比如，图14和图16给出了两种不同结构的三维堆叠存储阵列。
图14示例了一种存储器300的三维工艺结构图，该存储器300包含了沿与衬底垂直的第一方向Z方向排布的第一层存储阵列3101，第二层存储阵列3102和第三层存储阵列3103。其中，第一层存储阵列3101的源线SL靠近第二层存储阵列3102的位 线BL，第二层存储阵列3102的源线SL靠近第三层存储阵列3103的位线BL，并且，第一层存储阵列3101的源线SL，和第二层存储阵列3102的位线BL为彼此独立的信号线，第二层存储阵列3102的源线SL，和第三层存储阵列3103的位线BL为彼此独立的信号线。也就是说，每相邻两层存储阵列中的源线和位线是彼此独立的。
在另外可选择的的实施例方式，如图15，可以是第一层存储阵列3101的源线SL靠近第二层存储阵列3102的源线SL，第二层存储阵列3102的位线BL靠近第三层存储阵列3103的位线BL，第一层存储阵列3101的源线SL，和第二层存储阵列3102的源线SL为彼此独立的信号线，第二层存储阵列3102的位线BL，和第三层存储阵列3102的位线BL为彼此独立的信号线。
图16示例了另一种存储器300的三维工艺结构图，和上述图14和图15相同的是，图16的存储器300也示出了沿与衬底垂直的第一方向Z方向排布的第一层存储阵列3101，第二层存储阵列3102和第三层存储阵列3103。其中，第一层存储阵列3101的源线SL靠近第二层存储阵列3102的源线SL，第二层存储阵列3102的位线BL靠近第三层存储阵列3103的位线BL，和上述图14和图15不相同的是，第一层存储阵列3101的源线SL，和第二层存储阵列3102的源线SL共用同一条信号线，第二层存储阵列3102的位线BL，和第三层存储阵列3103的位线BL也共用同一条信号线。
当多层存储阵列采用图16所示的布设方式时，由于相邻两层的存储阵列彼此靠近的信号线共用，这样的话，如图17，可以在第一方向Z方向上集成更多层存储阵列，以进一步提升存储阵列密度，形成高密度存储阵列结构。
本申请给出的铁电存储器可以采用通过后道工艺(back end of line，BEOL)制作，图18示出了后道工艺BEOL原理图。在图18中，控制电路通过前道工艺(front end of line，FEOL)制作在衬底上。该控制电路可以包括如图3所示的译码器320、驱动器330、时序控制器340、缓冲器350或输入输出驱动360中的一个或多个电路，还可以包括其他功能电路。该控制电路可以控制本申请实施例中的信号线(字线WL、源线SL、位线BL)。在完成前道工艺FEOL后，互连线和存储阵列均通过后道工艺BEOL制作。这里的存储阵列，如前所述，包括多个存储单元中的相对应的多个铁电场效应晶体管和信号线(字线WL、源线SL、位线BL)的部分。上述互连线既包括连接控制电路中的器件的互连线，也包括上述信号线的其他部分。将存储阵列中的铁电场效应晶体管通过后道工艺制作，可以使得单位面积内的电路密度更大，从而提升单位面积的性能。
下面针对上述所示存储单元的读写操作过程分别进行详细介绍，并以铁电场效应晶体管为NMOS管为例来解释。
表1所示的电压值列表，是对图19中存储阵列310中的存储单元401进行读和写操作时，与存储单元401对应的各个信号线上，以及其余的存储单元402、存储单元403和存储单元404对应的各个信号线上的电压值。其中V为第一工作电压，V1为第二工作电压，V2为第三工作电压，V3为第四工作电压。本申请不对第一工作电压V和第二工作电压V1以及第三工作电压V2，第四工作电压V3的具体数值做限定。
操作 WL Unsel WL BL Unsel BL SL Unsel SL
写1 V V/3 0 2V/3 0 2V/3
写0 0 2V/3 V V/3 V V/3
读0/1 0 V1 V2 0 0 0
表1
结合图19，由于需要对选中的存储单元401进行读写操作，因此，将与存储单元401电连接的字线称为选中字线WL，位线称为选中位线BL，源线称为选中源线SL，其余的没有被选中的存储单元402、存储单元403、存储单元404相对应电连接的字线称为未选中字线Unsel WL，位线称为未选中位线Unsel BL，源线称为未选中源线Unsel SL。
对存储单元401进行写操作，实际上是改变存储单元401中铁电膜层的极化状态。当铁电膜层两端的电压差的绝对值大于铁电膜层的矫顽电场时，铁电膜层的极化状态发生改变；当铁电膜层两端的电压差的绝对值小于或等于铁电膜层的矫顽电场时，铁电膜层的极化状态不发生改变。可以根据铁电膜层的材料测得该矫顽电场的强度，然后设置一个操作电压V0。当铁电膜层两端的电压差绝对值大于V0时，铁电膜层的极化状态发生改变；当铁电膜层两端的电压差绝对值小于或等于V0时，铁电膜层的极化状态不发生改变。在表一所示的电压数值中，示例的，当铁电膜层两端的电压差绝对值大于V/3时，铁电膜层的极化状态发生改变，当铁电膜层两端的电压差绝对值小于或等于V/3时，铁电膜层的极化状态不发生改变。
如表1所示，当对存储单元401进行写“1”操作时，选中字线WL接收第一工作电压V，选中位线BL接地，选中源线SL接地，则存储单元401的铁电层两端的电压差为V，且V大于操作电压V0＝V/3，因此存储单元401中的铁电膜层的极化状态变为正极化，从而实现对存储单元401的写“1”操作。
此外，由于不用对存储单元402进行写“1”操作，因此与存储单元402电连接的未选中位线Unsel BL和未选中源线Unsel SL均接收2V/3，则存储单元402的铁电层两端的电压差为V/3，且V/3小于或者等于操作电压V0＝V/3，因此不会导致存储单元402中的铁电膜层发生极化状态的改变，进而不会对存储单元402进行写“1”操作。
由于也不需要对存储单元403和存储单元404进行写“1”操作，那么，未选中字线Unsel WL接收V/3，未选中位线Unsel BL和未选中源线Unsel SL均接收2V/3，则，存储单元402的铁电层两端的电压差为V/3，且V/3小于或者等于操作电压V0＝V/3，因此不会导致存储单元403中的铁电膜层发生极化状态的改变，也就不会对存储单元403进行写“1”操作，还有，存储单元404的铁电层两端的电压差为-V/3，即电压差绝对值小于或者等于操作电压V0＝V/3，因此不会导致存储单元404中的铁电膜层发生极化状态的改变，进而不会对存储单元404进行写“1”操作。
如表1所示，当对存储单元401进行写“0”操作时，选中字线WL接地，选中位线BL和选中源线SL均接收V，则存储单元401的铁电层两端的电压差为-V，且-V的绝对值大于操作电压V0＝V/3，因此存储单元401中的铁电膜层的极化状态变为负极化，从而实现对存储单元401的写“0”操作。
由于不用对存储单元402进行写“0”操作，因此与存储单元402电连接的未选中 位线Unsel BL和未选中源线Unsel SL均接收V/3，则存储单元402的铁电层两端的电压差为-V/3，即电压差绝对值小于或者等于操作电压V0＝V/3，因此不会导致存储单元402中的铁电膜层发生极化状态的改变，进而不会对存储单元404进行写“0”操作。
由于也不需要对存储单元403和存储单元404进行写“0”操作，那么，未选中字线Unsel WL接收2V/3，未选中位线Unsel BL和未选中源线Unsel SL均接收V/3，则，存储单元403的铁电层两端的电压差为-V/3，即电压差绝对值小于或者等于操作电压V0＝V/3，因此不会导致存储单元402中的铁电膜层发生极化状态的改变，进而不会对存储单元404进行写“0”操作；还有，存储单元404的铁电层两端的电压差为V/3，即电压差小于或者等于操作电压V0＝V/3，因此不会导致存储单元404中的铁电膜层发生极化状态的改变，进而不会对存储单元404进行写“0”操作。
如表1所示，当对存储单元401进行读操作时，选中字线WL接收V3(比如，V3为0，或者，V3为介于两个阈值电压之间的电压)，选中位线BL接收V2(由于选用的是NPOS管，则V2大于0)，选中源线SL接地。存储单元401的铁电场效应晶体管处于导通还是关断状态取决于存储单元401中铁电层的极化状态。
若存储单元401的铁电膜层处于正极化状态，即存储单元401中存储的数据为“1”，则存储单元401的铁电场效应晶体管处于导通状态，通过检测选中位线BL的电流来读取存储单元的“1”状态。
若存储单元401的铁电膜层处于负极化状态，即存储单元401中存储的数据为“0”，则存储单元401的铁电场效应晶体管处于关断状态，通过检测选中位线BL的电流来读取存储单元的“0”状态。
此外，由于不用对存储单元402进行读操作，因此与存储单元402电连接的未选中位线Unsel BL和未选中源线Unsel SL均接地，进而不会对存储单元402进行读操作。
还有，由于不用对存储单元403和存储单元404进行读操作，那么，未选中字线Unsel WL接收V1，以使存储单元403的铁电场效应晶体管处于关断状态，和存储单元404的铁电场效应晶体管也处于关断状态，则不会对存储单元403和存储单元404进行读操作。
下面给出了本申请给出的铁电存储器的制备方法，示例的，先在衬底上形成控制电路；再在控制电路上形成互连线；然后在互连线上形成呈阵列布设的多个存储单元，并使得通过互连线将控制电路和多个存储单元电连接，以使得通过控制电路控制存储单元的读写。
在形成存储单元时，沿与衬底相垂直的第一方向形成第一极和第二极，以及形成半导体层、栅极和铁电层，且栅极的沿第二方向相对两侧中的其中一侧具有半导体层，半导体层分别与第一极和第二极电连接，铁电层形成在栅极和半导体层之间，以形成存储单元的铁电场效应晶体管。
本申请给出了制得多种不同存储单元结构的具体制备方法，下述分别进行详细解释。
图20a至图20j给出了制得本申请涉及的一种存储单元工艺过程中每一步骤完成后的工艺结构剖面图。
如图20a，沿与衬底相垂直的第一方向Z方向依次堆叠第一极51、绝缘层561、栅极55和绝缘层562。
这里的第一极51、绝缘层561、栅极55和绝缘层562的材料上述已经进行了说明，在此不再说明。
如图20b，沿与衬底相平行的第二方向Y方向，开设多个间隔布设的第一槽101，且第一槽101贯通绝缘层562、栅极55和绝缘层561。也就是说，第一槽101不能贯通第一极51，因为这里的第一极51可以作为存储阵列的位线BL或者源线SL。
如图20c，在第一槽101内填充绝缘材料，以形成绝缘层563。
在填充绝缘材料，形成绝缘层563时，可选择物理气相沉积(physical vapor deposition，PVD)、化学气相沉积(chemical vapor deposition，CVD)或者电化学沉积(electro-chemcial deposition，ECD)等沉积工艺。
如图20d，再开设第二槽102，并且第二槽102开设在相邻的绝缘层563之间，还有第二槽102贯通绝缘层562、栅极55和绝缘层561。
如图20e，在第二槽102内形成铁电层54。
在铁电层54时，可以采用沉积、溅射等工艺形成，比如，当采用沉积法时，在第二槽102的底面、侧面，以及绝缘层562的上表面均会形成铁电层54。
如图20f，需要对第二槽102的底面，以及绝缘层562的上表面进行去除，比如，干法刻蚀，以移除第二槽102的底面，以及绝缘层562的上表面的铁电层54，以得到图20f所示的结构。
如图20g，形成半导体层53。
和形成铁电层54工艺相同，也可以采用沉积、溅射等工艺，这样的话，如图20g，在第二槽102的底面、铁电层54的侧壁面上，以及绝缘层562的上表面均会形成半导体层53。
如图20h，再将第二槽102的底面，以及绝缘层562的上表面的半导体层53去除，得到图20h所示结构。
如图20i，在第二槽102内剩余的空间内填充绝缘材料，以形成绝缘层564。
如图20j，在绝缘层562上形成第二极52。这里的第二极52形成存储阵列的源线SL或者位线BL。
基于上述各工艺步骤描述，就可以制得沿Y方向排布的多个存储单元，并且，这些存储单元的第一极51相连接，以形成位线BL或者源线SL中的一种，还有，这些存储单元的第二极52相连接，以形成位线BL或者源线SL中的另一种。
图21a至图21j给出了制得本申请涉及的另一种存储单元工艺过程中每一步骤完成后的工艺结构剖面图。
如图21a，沿与衬底相垂直的第一方向Z方向依次堆叠第一极51、绝缘层561、栅极55和绝缘层562。
如图21b，沿与衬底相平行的第二方向Y方向，开设多个间隔布设的第一槽101， 且第一槽101贯通绝缘层562、栅极55和绝缘层561。
如图21c，在第一槽101内填充绝缘材料，以形成绝缘层563。
如图21d，再开设第二槽102，并且第二槽102开设在相邻的绝缘层563之间，还有第二槽102贯通绝缘层562、栅极55和绝缘层561。
其中，图21a至图21d的工艺步骤和上述的图20a至图20d的工艺步骤相同，在每一相同的工艺步骤中，也可以采用相同的工艺手段。
如图21e，在第二槽102内依次形成铁电层54、半导体层55和绝缘层564。
和上述工艺方法不同的是，在该工艺结构中，形成铁电层54后，不需要对形成在第二槽102底面的铁电层54进行去除，而是直接在铁电层54上再形成半导体层55，这样的话，不会因为刻蚀工艺在去除第二槽102底面的铁电层54时，对第二槽102侧壁面的铁电层54造成污染，影响最终铁电层54的存储性能的现象。
如图21f，去除第二槽102底面的绝缘层564、半导体层55和铁电层53，以及绝缘层562的上表面的绝缘层564、半导体层55和铁电层53，这样就会形成图21f所示的仅在第二槽102的侧壁面依次形成有铁电层53、半导体层55和绝缘层564的结构。
如图21g，形成连接电极59，以在第二槽102的底面、绝缘层564上，以及绝缘层562上表面形成连接电极59。
如图21h，去除第二槽102底面，以及靠近第二槽102开口处的连接电极59，以及去除绝缘层562上表面形成连接电极59。这样的话，半导体层53可以通过连接电极59与第一极51电连接。
如图21i，在第二槽102内剩余的空间内填充绝缘材料，以形成绝缘层564。
如图21j，在绝缘层562上形成第二极52。
基于上述各工艺步骤，也可以制得沿Y方向排布的多个存储单元，第一极51通过半导体层53和连接电极59与第二极52电连接，并且，这些存储单元的第一极51相连接，以形成位线BL或者源线SL中的一种，还有，这些存储单元的第二极52相连接，以形成位线BL或者源线SL中的另一种。
图22a至图22j给出了制得本申请涉及的另一种存储单元工艺过程中每一步骤完成后的工艺结构剖面图。
如图22a，沿与衬底相垂直的第一方向Z方向依次堆叠导电层581、第一极51、牺牲层57、第二极52。
如图22b，沿与衬底相平行的第二方向Y方向，开设多个间隔布设的第一槽101，且第一槽101贯通第二极52、牺牲层57和第一极51，也就是说，第一槽101不能贯通导电层581，因为该导电层581最终作为存储阵列的源线SL或者位线BL。
如图22c，在第一槽101内填充绝缘材料，以形成绝缘层562，并且，再开设第二槽102，且第二槽102位于相邻两个绝缘层562之间，以及，第二槽102贯通第二极52、牺牲层57和第一极51。
如图22d，去除与绝缘层562相接触的牺牲层57，以形成图22d所示的多个凹腔103。这样的话，就可以在凹腔103内形成半导体层、铁电层和栅极。
在一些可选择的实施方式中，可以选择腐蚀工艺去除牺牲层57，比如，当牺牲层 57的材料为氧化硅时，可以采用氢氟酸腐蚀介质进行腐蚀。
如图22e，在凹腔8的壁面形成半导体层53。
由于在形成半导体层53时，可以采用PVD、CVD或者ECD等沉积工艺，这样，不仅在凹腔103的壁面形成半导体层53，在第二极52和第一极51的远离绝缘层562的侧面也会形成半导体层53。
如图22f，再形成铁电层54，该铁电层54形成在半导体层53上。在形成半导体层53和铁电层54后，凹腔103内还具有空间，该空间为了容纳栅极。
如图22g，在凹腔103剩余的空间内形成栅极55。
结合图22g，由于在形成栅极55时，沿Y方向的相邻两个存储单元的栅极55连接呈一体，进而，如图22h，开设第三槽103，以使沿Y方向的相邻两个存储单元的栅极55断开。
如图22i，在第三槽103内形成绝缘层563，以使沿Y方向的相邻两个存储单元的栅极55之间绝缘。
如图22j，在第二极52上表面形成导电层582，该导电层582作为存储阵列的源线SL或者位线BL。
基于上述形成的存储单元中，半导体层53形成有凹腔，铁电层54和栅极55均位于凹腔内。还有，通过在靠近第一极51的一侧形成源线SL(或者位线BL)，以使多个存储单元共用一条源线SL，以及，通过在靠近第二极51的一侧形成位线BL(或者源线SL)，以使多个存储单元共用一条位线BL。
图23a至图23j给出了制得本申请涉及的另一种存储单元工艺过程中每一步骤完成后的工艺结构剖面图。
如图23a，沿与衬底相垂直的第一方向Z方向依次堆叠导电层581、第一极51、牺牲层57、第二极52。
如图23b，沿与衬底相平行的第二方向Y方向，开设多个间隔布设的第一槽101，且第一槽101贯通第二极52、牺牲层57和第一极51。即第一槽101不能贯通导电层581，因为该导电层581最终作为存储阵列的源线SL或者位线BL。
如图23c，在第一槽101的侧壁面形成半导体层53，以及在第一槽101的剩余空间内形成绝缘层562，还有，再开设第二槽102，且第二槽102位于相邻两个绝缘层562之间，以及，第二槽102贯通第二极52、牺牲层57和第一极51。
如图23d，去除与半导体层53相接触的牺牲层57，以形成图23d所示的多个凹腔103。这样的话，就可以在凹腔103内形成铁电层和栅极。
如图23e，在凹腔8的壁面形成铁电层54。
由于在形成铁电层54时，可以采用PVD、CVD或者ECD等沉积工艺，这样，不仅在凹腔103的壁面形成铁电层54，在第二极52和第一极51的远离绝缘层562的侧面也会形成铁电层54。
如图23f，在凹腔103剩余的空间内形成栅极55。
结合图23f，由于在形成栅极55时，沿Y方向的相邻两个存储单元的栅极55连接呈一体，进而，如图23g，开设第三槽103，以使沿Y方向的相邻两个存储单元的 栅极55断开。
如图23h，在第三槽103内形成绝缘层563，以使沿Y方向的相邻两个存储单元的栅极55之间绝缘。
如图23i，在第二极52上表面形成导电层582，该导电层582作为存储阵列的源线SL或者位线BL。
图24a至图24g给出了制得本申请涉及的一种存储单元工艺过程中每一步骤完成后的工艺结构剖面图。
如图24a，沿与衬底相垂直的第一方向Z方向依次堆叠第二极52、牺牲层57和第一极51。
如图24b，沿与衬底相平行的第二方向Y方向，开设多个间隔布设的第一槽101，且第一槽101贯通第一极51、牺牲层57和第二极52。
如图24c，在第一槽101的侧面依次形成铁电层54和栅极55，以及在第一槽101的剩余空间内填充绝缘材料，以形成绝缘层581。并再开设第二槽102，并且第二槽102开设在相邻的具有铁电层54和栅极55的结构，还有第二槽102贯通第一极51、牺牲层57和第二极52。
如图24d，去除牺牲层57，以在第一极51和第二极52之间形成具有开口的凹腔103。
其中，第一极51的与第二极52相对的面为第一壁面，第二极52的与第一极51相对的面为第二壁面。
如图24e，在凹腔103内形成半导体层53。其中，第一极51的第一壁面、第二极52的第二壁面，和铁电层54的远离栅极55的侧面均形成有半导体层53。在形成半导体层53时，可以采用沉积等工艺形成，比如，当采用沉积法时，如图24e，会在第一极51的侧面，第二极52的侧面也分别形成有半导体层53。
如图24f，需要将第一极51的侧面、第二极52的侧面上的半导体层53进行去除，比如，干法刻蚀，以得到图24f所示的结构。
如图24g，在凹腔的剩余空间内，以及被分割开的第一极51，被分割开的第二极52之间均填充绝缘材料，以形成绝缘层582。
在一些可选择的实施方式中，在执行图24a所示工艺步骤时，可以在堆叠第二极52、牺牲层57和第一极51时，在第二极52的远离第一极51的一侧形成金属层，并且在开设第一槽101和第二槽102时，这些槽均不能贯通金属层，最终形成的存储器中，该金属层可以作为用于电连接沿Y方向排布的多个存储单元的第二极52的位线BL。
基于上述的采用不同工艺手段制得的不同结构的存储单元中，栅极的沿第二方向相对两侧中的其中一侧设置半导体层，而不是将半导体沿栅极的外围环绕，进而可以在衬底上方制得更多的存储单元，以提升该存储器的存储容量，提升该存储器的读写速度。
在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个 实施例或示例中以合适的方式结合。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种铁电存储器，其特征在于，包括：
    衬底；
    多个存储单元，形成在所述衬底上；
    每个所述存储单元包括：铁电场效应晶体管；
    其中，所述铁电场效应晶体管包括：栅极、半导体层、第一极和第二极，以及铁电层；
    所述第一极和所述第二极沿与所述衬底相垂直的第一方向排布，所述栅极位于所述第一极和所述第二极之间，所述栅极的沿第二方向相对两侧中的其中一侧具有所述半导体层，且所述半导体层分别与所述第一极和所述第二极电连接，所述栅极和所述半导体层之间被所述铁电层隔离开，所述第二方向为与所述衬底相平行的方向。
  2. 根据权利要求1所述的铁电存储器，其特征在于，所述半导体层为沿所述第一方向延伸的竖直状结构，且所述半导体层的沿所述第一方向的相对两端中的一端与所述第一极接触，另一端与所述第二极接触。
  3. 根据权利要求2所述的铁电存储器，其特征在于，在所述第一极中与所述第二极相对的面为第一壁面，在所述第二极中与所述第一极的相对的面为第二壁面；
    所述半导体层的沿所述第一方向的相对两端中的一端与所述第一壁面接触，另一端与所述第二壁面接触。
  4. 根据权利要求2所述的铁电存储器，其特征在于，在所述第一极中与所述第二极相对的面为第一壁面，在所述第一极中与所述第一壁面毗邻的为第一侧面；
    在所述第二极中与所述第一极的相对的面为第二壁面，在所述第二极中与所述第二壁面毗邻的为第二侧面，所述第一侧面和所述第二侧面处于同一侧；
    所述半导体层的沿所述第一方向的相对两端中的一端与所述第一侧面接触，另一端与所述第二侧面接触。
  5. 根据权利要求1所述的铁电存储器，其特征在于，所述半导体层包括均沿所述第二方向延伸的第一部分和第二部分，以及沿所述第一方向延伸的且与所述第一部分和所述第二部分均连接的第三部分；
    在所述第一极中与所述第二极相对的面为第一壁面，在所述第二极中与所述第一极的相对的面为第二壁面；
    所述第一部分设置在所述第一壁面上，所述第二部分设置在所述第二壁面上。
  6. 根据权利要求5所述的铁电存储器，其特征在于，所述第一部分、所述第二部分和所述第三部分连接呈一体成型结构。
  7. 根据权利要求1所述的铁电存储器，其特征在于，所述半导体层包括沿所述第二方向延伸的第一部分，和沿所述第一方向延伸且与所述第一部分连接的第三部分；
    在所述第一极中与所述第二极相对的面为第一壁面，在所述第二极中与所述第一极的相对的面为第二壁面；
    所述铁电存储器还包括连接电极，所述连接电极设置在所述第二壁面上；
    所述第三部分与所述第一壁面接触，所述第一部分与所述连接电极接触。
  8. 根据权利要求1-7中任一项所述的铁电存储器，其特征在于，在所述第一极中 与所述第二极相对的面为第一壁面，在所述第二极中与所述第一极的相对的面为第二壁面；
    所述栅极位于所述第一壁面和所述第二壁面之间的区域内。
  9. 根据权利要求1-7中任一项所述的铁电存储器，其特征在于，在所述第一极中与所述第二极相对的面为第一壁面，在所述第一极中与所述第一壁面毗邻的为第一侧面；
    在所述第二极中与所述第一极的相对的面为第二壁面，在所述第二极中与所述第二壁面毗邻的为第二侧面，所述第一侧面和所述第二侧面处于同一侧；
    所述栅极位于所述第一侧面和所述第二侧面的一侧。
  10. 根据权利要求1-9中任一项所述的铁电存储器，其特征在于，所述铁电场效应晶体管采用后道工艺制作。
  11. 根据权利要求1-10中任一项所述的铁电存储器，其特征在于，所述铁电存储器还包括：
    位线、源线和字线；
    其中，所述栅极与所述字线电连接，所述第一极与所述源线电连接，所述第二极与所述位线电连接。
  12. 根据权利要求11所述的铁电存储器，其特征在于，
    所述源线和所述位线均沿所述第二方向延伸；
    所述字线沿与所述衬底相平行的第三方向延伸，所述第二方向与所述第三方向垂直；
    沿所述第二方向排布的所述多个存储单元中的所述第一极与同一条所述源线电连接；
    沿所述第二方向排布的所述多个存储单元中的所述第二极与同一条所述位线电连接；
    沿所述第三方向排布的所述多个存储单元中的所述栅极与同一条所述字线电连接。
  13. 根据权利要求12所述的铁电存储器，其特征在于，所述多个存储单元形成沿所述第一方向排布的第一层存储阵列和第二层存储阵列；
    所述第一层存储阵列中沿所述第二方向延伸的所述源线，靠近所述第二层存储阵列中沿所述第二方向延伸的所述源线；
    其中，所述第一层存储阵列中的所述源线，与所述第二层存储阵列中的所述源线共用同一条信号线。
  14. 根据权利要求12所述的铁电存储器，其特征在于，所述多个存储单元形成沿所述第一方向排布的第一层存储阵列和第二层存储阵列；
    所述第一层存储阵列中沿所述第二方向延伸的所述源线，靠近所述第二层存储阵列中沿所述第二方向延伸的所述位线；
    其中，所述第一层存储阵列中的所述源线，与所述第二层存储阵列中的所述位线为彼此独立的信号线。
  15. 根据权利要求11-14中任一项所述的铁电存储器，其特征在于，所述铁电存储器还包括控制器，所述控制器用于：
    输出字线控制信号以控制所述字线上的电压；
    输出源线控制信号以控制所述源线上的电压；以及
    输出位线控制信号以控制所述位线上的电压。
  16. 一种电子设备，其特征在于，包括：
    处理器；和
    如权利要求1-15任一项所述的铁电存储器，所述处理器和所述铁电存储器电连接。
  17. 根据权利要求16所述的电子设备，其特征在于，
    所述处理器和所述铁电存储器被集成在同一芯片中。
  18. 一种铁电存储器的形成方法，其特征在于，包括：
    沿与衬底相垂直的第一方向形成第一极和第二极，以及形成半导体层、栅极和铁电层，且所述栅极的沿第二方向相对两侧中的其中一侧形成所述半导体层，所述半导体层分别与所述第一极和所述第二极电连接，所述铁电层形成在所述栅极和所述半导体层之间，以形成铁电场效应晶体管。
  19. 根据权利要求18所述的铁电存储器的形成方法，其特征在于，在形成所述铁电场效应晶体管之前，所述形成方法还包括：
    在所述衬底上形成控制电路；
    在所述控制电路上形成电连接所述控制电路和所述铁电场效应晶体管的互连线。
PCT/CN2021/103315 2021-06-29 2021-06-29 铁电存储器及其形成方法、电子设备 WO2023272536A1 (zh)

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