WO2024164632A1 - 三维存储阵列及其制备方法、存储器、电子设备 - Google Patents

三维存储阵列及其制备方法、存储器、电子设备 Download PDF

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Publication number
WO2024164632A1
WO2024164632A1 PCT/CN2023/133330 CN2023133330W WO2024164632A1 WO 2024164632 A1 WO2024164632 A1 WO 2024164632A1 CN 2023133330 W CN2023133330 W CN 2023133330W WO 2024164632 A1 WO2024164632 A1 WO 2024164632A1
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Prior art keywords
electrode
capacitor
substrate
memory
layer
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PCT/CN2023/133330
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English (en)
French (fr)
Inventor
林琪
范人士
卜思童
方亦陈
许俊豪
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华为技术有限公司
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Publication of WO2024164632A1 publication Critical patent/WO2024164632A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/20—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region

Definitions

  • the present application relates to the field of storage technology, and in particular to a three-dimensional storage array and a preparation method thereof, a memory, and an electronic device.
  • ferroelectric memory As a new type of memory, ferroelectric memory has the advantages of low latency, low power consumption, and miniaturization compared to traditional dynamic random access memory (DRAM), and will become the new generation of mainstream memory.
  • DRAM dynamic random access memory
  • ferroelectric memory is integrated in a two-dimensional manner within a substrate, which occupies a large area and cannot be stacked, resulting in low memory storage density and limiting the memory storage capacity.
  • Embodiments of the present application provide a three-dimensional storage array and a method for manufacturing the same, a memory, and an electronic device, for increasing the storage capacity of the three-dimensional storage array.
  • a three-dimensional storage array comprising a substrate and a plurality of storage layers formed on the substrate.
  • the plurality of storage layers are stacked in a direction perpendicular to the substrate.
  • the storage layer comprises a plurality of storage cells.
  • the storage cell comprises an electrically connected capacitor and a transistor.
  • the transistor comprises a gate, a channel, and a first pole and a second pole arranged in a direction perpendicular to the substrate and arranged around the channel.
  • the capacitor comprises a first capacitor electrode, a second capacitor electrode, and a capacitor layer arranged between the first capacitor electrode and the second capacitor electrode, and the first pole is electrically connected to the first capacitor electrode.
  • the three-dimensional storage array provided in the embodiment of the present application includes multiple storage layers of multiple storage units stacked in a direction perpendicular to the substrate, so that the formation of the storage unit does not need to rely on the substrate. Therefore, the storage unit can be prepared using a back-end process, and can achieve multi-layer stacking in a direction perpendicular to the substrate, and achieve stacking in a three-dimensional direction, thereby improving the storage density of the three-dimensional storage array and improving the storage capacity of the three-dimensional storage array.
  • the capacitors and transistors in the memory cell are arranged in a direction parallel to the substrate, so that the size of each memory cell in the vertical direction can be reduced, thereby achieving miniaturization of the memory cell.
  • the first electrode and the first capacitor electrode share the same electrode, which is easy to form and saves process steps.
  • the gate and the channel both extend in a direction perpendicular to the substrate, and the channel surrounds the gate, so that the transistor in the memory cell can be regarded as a channel-wrap transistor.
  • the gate is disposed around the channel in a direction parallel to the substrate, and the gate is located between the first electrode and the second electrode.
  • the transistor in the memory cell can be regarded as a gate-around transistor.
  • the three-dimensional storage array further includes word lines, bit lines, and plate lines; the gates are electrically connected to the word lines, the second electrodes are electrically connected to the bit lines, and the second capacitor electrodes are electrically connected to the plate lines; the word lines extend in a direction perpendicular to the substrate; in the same storage layer, the plate lines extend in a direction parallel to the substrate, and the bit lines extend in a direction parallel to the substrate.
  • the word lines extend in a direction perpendicular to the substrate
  • the plate lines extend in a direction parallel to the substrate
  • the bit lines extend in a direction parallel to the substrate.
  • the memory cell further includes a first semiconductor layer and a second semiconductor layer; the first semiconductor layer connects the first electrode and the channel; the second semiconductor layer connects the second electrode and the channel. This is conducive to forming the first electrode and the second electrode of the transistor.
  • the capacitor layer includes a first portion extending in a direction perpendicular to the substrate, and a second portion and a third portion extending in a direction parallel to the substrate; the first capacitor electrode has a first side surface opposite to the second capacitor electrode, The second capacitor electrode has a second side surface opposite to the first capacitor electrode; the first portion contacts both the first side surface and the second side surface.
  • the read/write window can be increased by changing the contact surface area between the capacitor layer and the first capacitor electrode and the second capacitor electrode.
  • the first capacitor electrode further has a first top surface and a first bottom surface adjacent to the first side surface
  • the second capacitor electrode further has a second top surface and a second bottom surface adjacent to the second side surface; the second portion contacts the first top surface, and the third portion contacts the first bottom surface.
  • the first capacitor electrode further has a first top surface and a first bottom surface adjacent to the first side surface
  • the second capacitor electrode further has a second top surface and a second bottom surface adjacent to the second side surface; the second portion contacts the second top surface, and the third portion contacts the second bottom surface.
  • the first capacitor electrode further has a first top surface and a first bottom surface adjacent to the first side surface
  • the second capacitor electrode further has a second top surface and a second bottom surface adjacent to the second side surface; the second portion contacts the first top surface, and the third portion contacts the second bottom surface.
  • the first capacitor electrode further has a first top surface and a first bottom surface adjacent to the first side surface
  • the second capacitor electrode further has a second top surface and a second bottom surface adjacent to the second side surface; the second portion contacts both the first top surface and the first top surface, and the third portion contacts both the second top surface and the second bottom surface.
  • At least one of the first side surface or the second side surface is a curved surface. In this way, the read/write window can be increased by changing the contact surface area between the capacitor layer and the first capacitor electrode and the second capacitor electrode.
  • the second capacitor electrodes of adjacent storage cells are connected, so that the size of the storage layer can be reduced, thereby improving the storage density of the three-dimensional storage array.
  • the material of the capacitor layer includes any one of ferroelectric material, insulating material, phase change material, resistive material or ferromagnetic material. In this way, different memories can be formed according to the different materials of the capacitor layer.
  • a method for preparing a three-dimensional storage array includes a substrate and a plurality of storage layers, wherein the plurality of storage layers are stacked on the substrate in a direction perpendicular to the substrate; and the storage layer includes a plurality of storage cells.
  • the method for preparing the storage cell includes: forming a dielectric layer on the substrate; forming a via hole penetrating the dielectric layer, wherein the via hole extends in a direction perpendicular to the substrate; forming a capacitor layer and a first electrode in the dielectric layer on the side wall of the via hole, and forming a second electrode spaced from the first electrode; both the first electrode and the second electrode extend in a direction parallel to the substrate; forming a channel and a gate in the via hole to form a transistor; and forming a second capacitor electrode on a side of the capacitor layer away from the first electrode to form a capacitor.
  • the formation of the storage unit does not depend on the substrate, that is, the storage unit can be prepared by a back-end process, and can realize multi-layer stacking in the vertical direction along the substrate, realize the stacking of storage units in the three-dimensional direction, improve the storage density of the three-dimensional storage array, and improve the storage capacity of the three-dimensional storage array.
  • the storage units in multiple storage layers can be formed at the same time, and the preparation cost is low.
  • the first and second poles of the transistor are formed, and the channel of the transistor is formed in steps, which can make it easier to control the formation morphology of each structure, which is conducive to improving the consistency of the transistor.
  • the preparation method before forming the channel and the gate, further includes: forming a first semiconductor layer and a second semiconductor layer in the dielectric layer on the sidewall of the via hole, which is beneficial for the subsequent preparation of the first electrode and the second electrode.
  • the preparation method further includes: forming word lines, bit lines and plate lines; the word lines are electrically connected to the gate, the bit lines are electrically connected to the second electrode, and the plate lines are electrically connected to the second capacitor electrode. In this way, by applying different voltages to the word lines, bit lines and plate lines respectively, reading and writing of multiple storage cells can be achieved.
  • a method for preparing a three-dimensional storage array includes a substrate and a plurality of storage layers, wherein the plurality of storage layers are stacked on the substrate in a direction perpendicular to the substrate; and the storage layer includes a plurality of storage cells.
  • the method for preparing the storage cell includes: forming a dielectric layer on the substrate; forming a via hole penetrating the dielectric layer, wherein the via hole extends in a direction perpendicular to the substrate; forming a capacitor layer and a first electrode in the dielectric layer on the sidewall of the via hole, and forming a gate and a second electrode spaced apart from the first electrode; the first electrode, the gate and the second electrode all extend in a direction parallel to the substrate; forming a channel in the via hole to form a transistor; and forming a second capacitor electrode on a side of the capacitor layer away from the first electrode to form a capacitor.
  • the beneficial effects of the method for preparing a three-dimensional storage array provided in the third aspect of the embodiment of the present application are the same as the beneficial effects of the method for preparing a three-dimensional storage array provided in the second aspect, and are not described in detail here.
  • a memory comprising: a controller and the three-dimensional memory array of any one of the first aspects, wherein the controller is electrically connected to the three-dimensional memory array.
  • the memory provided in the fourth aspect of the embodiment of the present application includes the three-dimensional memory array of the first aspect, and its beneficial effects are the same as those of the three-dimensional memory array, which will not be repeated here.
  • an electronic device comprising: a circuit board and a memory as in the fourth aspect, wherein the circuit board is electrically connected to the memory.
  • the electronic device provided in the fifth aspect of the embodiment of the present application includes the memory in the fourth aspect, and its beneficial effects are the same as the beneficial effects of the memory, which will not be repeated here.
  • FIG1A is a structural block diagram of an electronic device provided in an embodiment of the present application.
  • FIG1B is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application.
  • FIG2A is a structural block diagram of a memory provided in an embodiment of the present application.
  • FIG2B is a circuit diagram of a storage unit provided in an embodiment of the present application.
  • FIG3 is a schematic diagram of the structure of a storage array provided in an embodiment of the present application.
  • FIG4A is a schematic diagram of the structure of another three-dimensional storage array provided in an embodiment of the present application.
  • FIG4B is a cross-sectional view of FIG4A along the direction A1A2;
  • FIG4C is a schematic diagram of the structure of a storage unit provided in an embodiment of the present application.
  • FIG5A is a schematic diagram of the structure of another storage unit provided in an embodiment of the present application.
  • FIG5B is a schematic diagram of the structure of another storage unit provided in an embodiment of the present application.
  • FIG5C is a schematic diagram of the structure of another storage unit provided in an embodiment of the present application.
  • FIG5D is a schematic diagram of the structure of another storage unit provided in an embodiment of the present application.
  • FIG6A is a schematic diagram of the structure of another storage unit provided in an embodiment of the present application.
  • FIG6B is a schematic diagram of the structure of another storage unit provided in an embodiment of the present application.
  • FIG7 is a schematic flow chart of a method for preparing a three-dimensional storage array provided in an embodiment of the present application.
  • FIGS. 8A-8H are schematic diagrams of a process of manufacturing a three-dimensional storage array provided in an embodiment of the present application.
  • FIG9A is a schematic diagram of the structure of another three-dimensional storage array provided in an embodiment of the present application.
  • FIG9B is a cross-sectional view of FIG9A along the direction B1B2;
  • FIG9C is a schematic diagram of the structure of another storage unit provided in an embodiment of the present application.
  • FIG10 is a schematic diagram of a process of another method for preparing a three-dimensional storage array provided in an embodiment of the present application.
  • 11A-11E are schematic diagrams of another method for preparing a three-dimensional storage array provided in an embodiment of the present application.
  • the terms “second”, “first”, etc. are used only for convenience of description and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as “second”, “first”, etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, the meaning of "plurality” is two or more. Two or more.
  • directional terms such as “up”, “down”, “left” and “right” may be defined including but not limited to the orientation relative to the schematic placement of the components in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative description and clarification, and may change accordingly according to changes in the orientation of the components in the drawings.
  • connection should be understood in a broad sense.
  • connection can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium.
  • coupled can be a direct electrical connection or an indirect electrical connection through an intermediate medium.
  • contact can be a direct contact or an indirect contact through an intermediate medium.
  • a and/or B may represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B may be singular or plural.
  • the character “/” generally indicates that the associated objects are in an "or” relationship.
  • Memory In a chip, memory is a memory component used to store programs and data information. The information stored in common memory is stored in the chip in binary units, that is, it is stored in the memory as "logic 0" or “logic 1". In physical devices, it is usually achieved by high or low voltage, large or small resistance, more or less charge, etc.
  • Bit is the smallest unit of information stored in a memory.
  • n bits can represent 2n states. For example, one bit can represent two states, 0 or 1. Two bits can represent four states, 00, 01, 10, 11, and so on. In other words, if a memory stores physical information in m states, it is a log2m-bit memory.
  • Volatile memory and non-volatile memory According to whether the stored signal still exists after the external power supply of the chip is removed, the memory can be divided into volatile memory and non-volatile memory. Volatile memory is represented by static random access memory (SRAM) or dynamic random access memory (DRAM). The storage of information must have a continuous external power supply. When there is no external power supply, the stored information will no longer exist. Non-volatile memory is represented by traditional read-only memory (ROM) and flash memory, ferroelectric random-access memory (FeRAM, ferroelectric field effect transistor, FeFET), magnetic random access memory (MRAM), resistive random access memory (RRAM) and phase-change random access memory (PCRAM). These non-volatile memories all use their own unique physical principles to achieve the characteristic of not losing information when power is off.
  • ROM read-only memory
  • FeRAM ferroelectric random-access memory
  • FeFET ferroelectric field effect transistor
  • MRAM magnetic random access memory
  • RRAM resistive random access memory
  • PCRAM phase-change random access
  • the electronic device is, for example, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, or a financial terminal product.
  • consumer electronic products include mobile phones, tablet computers, laptop computers, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop displays, smart wearable products (e.g., smart watches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc.
  • Home electronic products include smart door locks, televisions, remote controls, refrigerators, rechargeable small household appliances (e.g., soybean milk machines, sweeping robots), etc.
  • Vehicle-mounted electronic products include vehicle-mounted navigation systems, vehicle-mounted DVDs, etc.
  • Financial terminal products include ATM machines, self-service terminals, etc.
  • Communication electronic products include communication equipment such as servers, storage devices, radars, and base stations.
  • the electronic device 1 includes components such as a storage device 11, a processor 12, an input device 13, and an output device 14.
  • components such as a storage device 11, a processor 12, an input device 13, and an output device 14.
  • the architecture of the electronic device 1 shown in FIG1A does not constitute a limitation on the electronic device 1 , and the electronic device 1 can include more or fewer components than those shown in FIG1A , or can combine some of the components shown in FIG1A , or can have a different arrangement of components than those shown in FIG1A .
  • the storage device 11 is used to store software programs and modules.
  • the storage device 11 mainly includes a program storage area and a data storage area, wherein the program storage area can store and back up an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc.; the data storage area can store data created according to the use of the electronic device 1 (such as audio data, image data, phone book, etc.), etc.
  • the processor 12 is the control center of the electronic device 1. It connects various parts of the entire electronic device 1 using various interfaces and lines, and runs or executes software programs and/or modules stored in the storage device 11, and calls the software programs and/or modules stored in the storage device 11.
  • the processor 12 can process data in the electronic device 1, execute various functions of the electronic device 1 and process data, thereby monitoring the electronic device 1 as a whole.
  • the processor 12 may include one or more processing units.
  • the processor 12 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), etc. Among them, different processing units may be independent devices or integrated into one or more processors.
  • AP application processor
  • GPU graphics processing unit
  • the processor 12 may integrate an application processor and a modem processor, wherein the application processor mainly processes an operating system, a user interface, and application programs, etc., and the modem processor mainly processes wireless communications. It is understandable that the above-mentioned modem processor may not be integrated into the processor 12.
  • the above-mentioned application processor may be, for example, a central processing unit (CPU).
  • the processor 12 is taken as a CPU as an example, and the CPU may include an operator 121 and a controller 122.
  • the operator 121 obtains the data stored in the internal memory 112, and processes the data stored in the internal memory 112, and the processed results are usually sent back to the internal memory 112.
  • the controller 122 can control the operator 121 to process data, and the controller 122 can also control the external memory 111 and the internal memory 112 to read or write data.
  • the input device 13 is used to receive input digital or character information, and to generate key signal input related to user settings and function control of the electronic device.
  • the input device 13 may include a touch screen and other input devices.
  • a touch screen also known as a touch panel, can collect user touch operations on or near the touch screen (such as operations performed by the user using a finger, stylus, or any other suitable object or accessory on or near the touch screen), and drive corresponding connection devices according to a pre-set program.
  • the output device 14 is used to output the input of the input device 13 and the signal corresponding to the data stored in the storage device 11. For example, the output device 14 outputs a sound signal or a video signal.
  • the controller 122 in the processor 12 can also control the output device 14 to output a signal or not output a signal.
  • the thick arrows in FIG. 1A are used to indicate data transmission, and the direction of the thick arrows indicates the direction of data transmission.
  • the single arrow between the input device 13 and the internal memory 112 indicates that the data received by the input device 13 is transmitted to the internal memory 112.
  • the double arrows between the operator 121 and the internal memory 112 indicate that the data stored in the internal memory 112 can be transmitted to the operator 121, and the data processed by the operator 121 can be transmitted to the internal memory 112.
  • the thin arrows in FIG. 1A indicate components that can be controlled by the controller 122.
  • the controller 122 can control the external memory 111, the internal memory 112, the operator 121, the input device 13, the output device 14, and the like.
  • the following is an exemplary introduction using the electronic device 1 as a mobile phone as an example.
  • the electronic device 1 may further include a middle frame 15, a rear shell 16, and a display screen 17.
  • the rear shell 16 and the display screen 17 are respectively located on opposite sides of the middle frame 15, and the middle frame 15 and the display screen 17 are disposed inside the rear shell 16.
  • the middle frame 15 includes a carrier plate 150 for carrying the display screen 17, and a frame 151 surrounding the carrier plate 150.
  • the electronic device 1 may further include a circuit board 18 , which is disposed on a side of the carrier board 150 close to the rear housing 16 .
  • the internal memory 112 in the electronic device 1 may be disposed on the circuit board 18 , and the internal memory 112 is electrically connected to the circuit board 18 .
  • the internal memory 112 may include a random access memory, a read-only memory, etc.
  • the random access memory may also include a ferroelectric random access memory (FeRAM), a dynamic random access memory (DRAM), a phase change random access memory (PCRAM), a resistive random access memory (ReRAM) or a magnetic random access memory (MRAM).
  • FeRAM ferroelectric random access memory
  • DRAM dynamic random access memory
  • PCRAM phase change random access memory
  • ReRAM resistive random access memory
  • MRAM magnetic random access memory
  • Ferroelectric memory stores data based on the ferroelectric effect of ferroelectric materials. Ferroelectric memory is expected to become a major competitor to replace DRAM due to its advantages such as ultra-high storage density, low power consumption and high speed.
  • the storage unit in the ferroelectric memory includes a ferroelectric capacitor, which includes a ferroelectric layer made of a ferroelectric material.
  • ferroelectric memory Due to the nonlinear characteristics of ferroelectric materials, the dielectric constant of ferroelectric materials can not only be adjusted, but also the difference before and after the polarization state of the ferroelectric layer is flipped is very large, which makes ferroelectric capacitors smaller than other capacitors. For example, they are much smaller than the capacitors used to store charge in DRAM.
  • ferroelectric memory has become one of the mainstream internal memories due to its non-volatility in data storage, fast access rate, low latency, low power consumption and miniaturization. At the same time, ferroelectric memory is also compatible with DRAM production lines.
  • the ferroelectric layer can be formed of common ferroelectric materials, such as ZrO2, HfO2, etc.
  • the central atom follows the electric field and stops at a low energy state.
  • the central atom moves in the crystal along the direction of the electric field and stops at another low energy state.
  • the mobile coupling forms ferroelectric domains, which form polarized charges under the action of an electric field.
  • the polarized charge formed by the reversal of the ferroelectric domain under an electric field is higher, and the polarized charge formed by the non-reversal of the ferroelectric domain under an electric field is lower.
  • This binary stable state of ferroelectric materials allows ferroelectrics to be used as memory.
  • FIG. 2A is a structural diagram of a ferroelectric memory according to some embodiments.
  • the memory 200 includes a memory array 210, a decoder 220, a driver 230, a timing controller 240, a buffer 250, and an input/output interface 260.
  • the memory array 210 includes a plurality of memory cells 300 arranged in an array.
  • the timing controller 240 is used to control the reading and writing of the memory array 210 and the memory circuit.
  • the storage density of the memory cell 300 directly affects the storage density of the memory array 210 .
  • FIG. 2B is a circuit diagram of a memory cell according to some embodiments.
  • the memory cell 300 includes a circuit architecture based on a ferroelectric capacitor, and the memory cell 300 has a 1T1C (1-transistor-1-capacitor) structure, that is, the memory cell 300 includes a transistor T and a ferroelectric capacitor C, the source of the transistor T is electrically connected to a bit line (bit line, BL), the drain is electrically connected to an electrode of the ferroelectric capacitor C, the gate is electrically connected to a word line (word line, WL), and the other electrode of the ferroelectric capacitor C is electrically connected to a plate line (plate line, PL).
  • the circuit architecture of the memory cell 300 in the embodiment of the present application is not limited thereto.
  • the transistor T may be, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET or MOS), which is a basic unit device of integrated circuits. According to the type of carriers, it is divided into N-channel type (NMOS) and P-channel type (PMOS).
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • the transistor T mainly includes a control electrode (e.g., a gate), a first input-output electrode (e.g., a source electrode), and a second input-output electrode (e.g., a drain electrode). As shown in FIG2B , for example, the control electrode of the transistor T is coupled to the word line WL, the first input-output electrode of the transistor T is coupled to the ferroelectric capacitor C, and the second input-output electrode of the transistor T is coupled to the plate line PL.
  • a control electrode e.g., a gate
  • a first input-output electrode e.g., a source electrode
  • a second input-output electrode e.g., a drain electrode
  • the resistance between the first input-output electrode and the second input-output electrode is controlled, and then the current flowing through the first input-output electrode and the second input-output electrode is controlled, so as to realize the switching characteristics of the transistor T.
  • the voltage of the transition between the on state and the off state is called the threshold voltage (Vt).
  • Vt the voltage of the transition between the on state and the off state
  • the control electrode voltage is greater than the threshold voltage
  • the transistor T is turned on, a current flows between the first input-output electrode and the second input-output electrode, and the corresponding storage unit 300 is selected.
  • the control electrode voltage is less than the threshold voltage
  • the transistor T is turned off, the current flows between the first input-output electrode and the second input-output electrode to almost zero, and the corresponding storage unit 300 is not selected.
  • transistor T can also be a P-type transistor.
  • N-type transistor is a high-on low-off transistor
  • P-type transistor is a low-on high-off transistor.
  • the turn-on voltage received by the N-type transistor and P-type transistor controllers is opposite to the threshold voltage.
  • the decoder 220 can decode according to the received address to determine the storage cell 300 in the storage array 210 that needs to be accessed.
  • the driver 230 is used to generate a control signal according to the decoding result output by the decoder 220, and the control signal is transmitted to the gate of the transistor T in the storage cell 300 through the word line WL to control the transistor T to be turned on or off, thereby achieving access to the specified storage cell 300.
  • the buffer 250 receives the data signal output by the storage cell 300 through the plate line PL, and is used to cache the data signal, for example, First-In First-Out (FIFO) can be used for caching.
  • the timing controller 240 is used to control the timing of the buffer 250, and control the driver 230 to drive the storage array 210.
  • the input and output interface 260 is used to transmit data signals, such as receiving data signals or sending data signals.
  • the storage array 210 , decoder 220 , driver 230 , timing controller 240 , buffer 250 and input/output interface 260 may be integrated into one chip or may be integrated into multiple chips.
  • FIG3 a structural diagram of a storage array 210 is shown.
  • the storage array 210 can be used in the above-mentioned memory 200.
  • the memory array 210 includes a plurality of memory cells 300.
  • Each memory cell 300 includes a transistor and a capacitor connected in series, that is, the 1T1C structure described above.
  • the transistor (T) is an access transistor, which acts as a gating device and can perform read and write operations on the capacitor (C) connected thereto.
  • the memory array 210 is integrated on the surface of a substrate, that is, the plurality of memory cells 300 are integrated on the substrate.
  • the source (S) and drain (D) of the transistor (T) are formed in the substrate, and the capacitor (C) is integrated on the source (S) or drain (D) of the transistor (T).
  • the memory cell 300 is arranged two-dimensionally on the surface of the substrate.
  • the transistor (T) in the memory cell 300 can only be made by the front-end of line (FEOL) process, resulting in the inability to achieve three-dimensional stacking of the memory cell 300.
  • the memory array 210 is integrated on the substrate, which occupies a large area, resulting in the storage density of the memory 200 being limited, limiting the improvement of the storage capacity of the memory 200, and causing the read and write speed of the memory 200 to be unable to keep up with the computing speed of the processor 12, ultimately resulting in limited improvement in the performance of electronic products such as computers and mobile phones.
  • the memory cell 300 can use a 1TnC structure, that is, n capacitors (C) are connected to the same transistor (T). By connecting multiple capacitors (C) to one transistor (T), the storage capacity of the memory cell 300 can be increased, thereby improving the storage density of the memory 200.
  • the 1TnC structured memory cell 300 brings new problems.
  • multiple capacitors (C) connected to the same transistor (T) will affect the reliability of stored data; on the other hand, due to the limitation of the read window of the memory cell 300, the number of capacitors (C) is difficult to be further increased, resulting in the storage capacity of the memory cell 300 being unable to be further increased.
  • an embodiment of the present application also provides a three-dimensional storage array.
  • the three-dimensional memory array 210 mainly includes a substrate 201 and a plurality of memory layers 202 formed on the substrate 201 .
  • FIG. 4A schematically shows a three-dimensional process structure diagram of a memory array 210
  • FIG. 4B is a cross-sectional view along the A1A2 direction in FIG. 4A .
  • the plurality of storage layers 202 are stacked along a direction z perpendicular to the substrate 201 .
  • the drawings in the embodiments of the present application take three storage layers 202 disposed on a substrate 201 as an example to schematically illustrate the storage array 210 provided in the embodiments of the present application.
  • the structure of the storage layer 202 composed of a plurality of storage cells 300 included in the storage array 210 may be the same as the structure of the storage cell 300 described in detail in the embodiments of the present application.
  • the storage array 210 may include storage cells of other structures in addition to the plurality of storage cells 300 illustrated in the embodiments of the present application, and the embodiments of the present application do not limit this.
  • a dielectric layer 400 is also filled between two adjacent storage units 300.
  • the material of the substrate 201 may be a semiconductor.
  • it may be one of bulk silicon, bulk germanium, silicon germanium, silicon carbide, silicon-on-insulator (SOI), and silicon-germanium-on-insulator (SGOI).
  • the semiconductor substrate 110 may also be doped (e.g., P-type doping, N-type doping) or undoped.
  • the semiconductor material of the substrate 201 may include any one of silicon, germanium, silicon germanium (SiGe), or a combination of several of them.
  • SOI includes a semiconductor material layer formed on an insulator layer.
  • the insulator layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc.
  • the insulator layer is disposed on a substrate 201, which is typically a silicon substrate or a glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used.
  • the substrate 201 is a wafer, such as a silicon wafer; the substrate 201 may also be a chip cut from the wafer.
  • the material of the substrate 201 may also include non-conductive materials such as glass, plastic, or sapphire.
  • the material of the dielectric layer 400 may include, for example, insulating materials such as silicon oxide (SiO x ) and nitride oxide (SiN x ), or may be doped with other insulating materials.
  • insulating materials such as silicon oxide (SiO x ) and nitride oxide (SiN x ), or may be doped with other insulating materials.
  • each memory layer 202 includes a plurality of memory cells 300 .
  • the multiple storage layers 202 included in the storage array 210 can be the same or different.
  • the embodiment of the present application assumes that the multiple storage layers 202 are the same, and the storage cells 300 in different storage layers 202 correspond to each other along the direction z perpendicular to the substrate 201. In this way, it is helpful to form bit lines, word lines and plate lines that electrically connect different storage layers 202.
  • the plurality of memory cells 300 are arranged in a direction parallel to the substrate 201 .
  • the direction parallel to the substrate 201 is recorded as the plane formed by the first direction x and the second direction y
  • the direction z perpendicular to the substrate 201 is recorded as the third direction z.
  • the first direction x and the second direction y intersect, for example, the first direction x and the second direction y are perpendicular.
  • the third direction z is perpendicular to the first direction x
  • the third direction z is also perpendicular to the second direction y.
  • any two of the first direction x, the second direction y and the third direction z are perpendicular.
  • the plurality of storage units 300 are arranged along a two-dimensional direction, that is, the plurality of storage units 300 are arranged along a first direction x and a second direction y, respectively.
  • the plurality of storage units 300 are formed in the dielectric layer 400 , and the dielectric layer 400 is filled between adjacent storage units 300 .
  • the dielectric layer 400 wraps around the periphery of the storage unit 300 .
  • FIG4C schematically shows the structure of the memory cell 300 in FIG4A and FIG4B.
  • the memory cell 300 includes a transistor 310 and a capacitor 320.
  • the transistor 310 and the capacitor 320 are electrically connected, and the capacitor 320 is formed on one side of the transistor 310.
  • the transistor 310 includes a first electrode 311 , a second electrode 312 , a gate 313 , and a channel 314 .
  • the first pole 311 and the second pole 312 are arranged along a direction z perpendicular to the substrate 201 , that is, the first pole 311 and the second pole 312 are arranged along the third direction z.
  • the first pole 311 and the second pole 312 also extend in a direction parallel to the substrate 201, that is, the first pole 311 and the second pole 312 extend in a plane formed by the first direction x and the second direction y.
  • the first pole 311 is arranged parallel to the substrate 201
  • the second pole 312 is arranged parallel to the substrate 201.
  • the materials of the first pole 311 and the second pole 312 are both conductive materials, such as metal materials.
  • the materials of the first pole 311 and the second pole 312 may include, for example, a combination of one or more conductive materials such as tungsten (W), titanium (Ti), gold (Au), molybdenum (Mo), aluminum (Al), copper (Cu), ruthenium (Ru), silver (Ag), titanium nitride (TiN), indium tin oxide (In-Ti-O, ITO), etc.
  • the material of the first pole 311 and the material of the second pole 312 may be the same or different.
  • the first pole 311 and the second pole 312 are disposed around the channel 314. That is, the first pole 311 and the second pole 312 are located at opposite ends of the channel 314.
  • the first pole 311 and the second pole 312 are disposed at the periphery of the channel 314 , that is, the first pole 311 and the second pole 312 are wrapped around the periphery of the channel 314 .
  • the channel 314 extends along a direction z perpendicular to the substrate 201 , that is, the channel 314 extends along the third direction z.
  • the material of the channel 314 may include, for example, one or more combinations of semiconductor materials such as silicon (Si), polycrystalline silicon (poly-Si, p-Si), amorphous silicon (a-Si), indium gallium zinc oxide (In-Ga-Zn-O, IGZO) multi-compound, zinc oxide (ZnO), molybdenum disulfide (MoS 2 ), and tungsten disulfide (WS 2 ).
  • semiconductor materials such as silicon (Si), polycrystalline silicon (poly-Si, p-Si), amorphous silicon (a-Si), indium gallium zinc oxide (In-Ga-Zn-O, IGZO) multi-compound, zinc oxide (ZnO), molybdenum disulfide (MoS 2 ), and tungsten disulfide (WS 2 ).
  • the channel 314 is disposed around the gate 313 of the transistor 310.
  • the channel 314 is disposed at the periphery of the gate 313, that is, the channel 314 is wrapped around the periphery of the gate 313.
  • the gate 313 also extends along a direction z perpendicular to the substrate 201 , that is, the gate 313 extends along the third direction z.
  • the gate 313 is made of a conductive material, such as a metal material.
  • the gate 313 may be made of one or more conductive materials such as tungsten, titanium, gold, molybdenum, aluminum, copper, ruthenium, silver, titanium nitride, indium tin oxide, etc.
  • first electrode 311, the second electrode 312 and the gate electrode 313 constitute three electrodes of the transistor 310.
  • the first electrode 311 and the second electrode 312 serve as the source and the drain of the transistor 310 respectively.
  • the first electrode 311 is the source of the transistor 310, and the second electrode 312 is the drain of the transistor 310.
  • the first electrode 311 is the drain of the transistor 310
  • the second electrode 312 is the source of the transistor 310.
  • the present application embodiment does not limit this, and it can be reasonably set according to actual conditions.
  • transistor 310 can be regarded as a channel all around (CAA) transistor.
  • a gate oxide layer 315 is further formed between the channel 314 and the gate 313. Since the gate 313 surrounds the channel 314, the gate oxide layer 315 also surrounds the channel 314.
  • the material of the gate oxide layer 315 may include, for example, any one of silicon nitride (SiN), silicon oxide (SiOx), or aluminum oxide (AlOx), or a combination of multiple thereof.
  • the memory cell 300 further includes a first semiconductor layer 316 and a second semiconductor layer 317.
  • the first semiconductor layer 316 is in contact with the first electrode 311.
  • the first semiconductor layer 316 is located near the second electrode 311.
  • the first semiconductor layer 316 surrounds the channel 314 and is located on the side of the second electrode 312 .
  • the second semiconductor layer 317 contacts the second electrode 312 .
  • the second semiconductor layer 317 is located on the side of the second electrode 312 close to the first electrode 311 .
  • the second semiconductor layer 317 surrounds the channel 314 .
  • the first semiconductor layer 316 and the second semiconductor layer 317 are also arranged along a direction z perpendicular to the substrate 201 , that is, the first semiconductor layer 316 and the second semiconductor layer 317 are arranged along the third direction z.
  • the first semiconductor layer 316 and the second semiconductor layer 317 also extend in a direction parallel to the substrate 201, that is, the first semiconductor layer 316 and the second semiconductor layer 317 extend in a plane formed by the first direction x and the second direction y.
  • the first semiconductor layer 316 is arranged parallel to the substrate 201
  • the second semiconductor layer 317 is arranged parallel to the substrate 201.
  • the material of the first semiconductor layer 316 and the second semiconductor layer 317 may include heavily doped polysilicon, and the type of dopant is P-type or N-type.
  • the dopant may include, for example, phosphorus (P), arsenic (As), boron (B), gallium (Ga), etc.
  • N-type doping of polysilicon may use pentavalent doping elements such as phosphorus and arsenic
  • P-type doping of polysilicon may use trivalent doping elements such as boron and gallium.
  • the first semiconductor layer 316 and the second semiconductor layer 317 function to form a first electrode 311 and a second electrode 312 .
  • the capacitor 320 includes a first capacitor electrode 321 , a second capacitor electrode 322 , and a capacitor layer 323 .
  • the capacitor layer 323 is located between the first capacitor electrode 321 and the second capacitor electrode 322 .
  • the first capacitor electrode 321 , the capacitor layer 323 , and the second capacitor electrode 322 are sequentially formed on the first electrode 311 of the transistor 310 .
  • the capacitor 320 is electrically connected to the transistor 310.
  • the capacitor 320 is electrically connected to the first electrode 311 or the second electrode 312 of the transistor 310.
  • the first capacitor electrode 321 of the capacitor 320 is electrically connected to the first electrode 311 of the transistor 310.
  • the first capacitor electrode 321 of the capacitor 320 is formed on the first electrode 311 of the transistor 310 .
  • the first capacitor electrode 321 of the capacitor 320 and the first electrode 311 of the transistor 310 may be formed separately.
  • the first capacitor electrode 321 of the capacitor 320 is electrically connected to the first electrode 311 of the transistor 310.
  • the first electrode 311 of the transistor 310 may be used as the first capacitor electrode 321 of the capacitor 320.
  • the first capacitor electrode 321 of the capacitor 320 may be used as the first electrode 311 of the transistor 310.
  • the first electrode 311 of the transistor 310 and the first capacitor electrode 321 of the capacitor 320 share the same electrode.
  • the materials of the first capacitor electrode 321 and the second capacitor electrode 322 are both conductive materials, such as metal materials.
  • the materials of the first capacitor electrode 321 and the second capacitor electrode 322 may include, for example, a combination of one or more conductive materials such as tungsten, titanium, gold, molybdenum, aluminum, copper, ruthenium (Ru), silver, titanium nitride, indium tin oxide, etc.
  • the material of the first capacitor electrode 321 and the material of the second capacitor electrode 322 may be the same or different.
  • the material of the capacitor layer 323 includes any one of ferroelectric material, insulating material, phase change material, resistive material or ferromagnetic material.
  • the ferroelectric material may include, for example, zirconium oxide ( ZrOx ), hafnium oxide ( HfOx ), zirconium hafnium oxide ( ZrHfOx ), Al-doped HfO2 , Si-doped HfO2 , Zr-doped HfO2 , La-doped HfO2 , Y-doped HfO2 , and other ferroelectric materials, or one or more of the materials doped with other elements based on the materials.
  • the insulating material is a high-K dielectric layer, and the insulating material may include, for example, at least one of aluminum oxide ( Al2O3 ), zirconium dioxide ( ZrO2 ), titanium oxide ( TiO2 ), hafnium dioxide ( HfO2 ), and lanthanum oxide ( La2O3 ).
  • the phase change material may include, for example, a chalcogenide compound film or a combination of multiple chalcogenide compound films.
  • the resistive material may include, for example, a binary transition metal oxide (TMO), such as chromium oxide ( HfOx ) and tantalum oxide ( TaOx ).
  • the ferromagnetic material may include, for example, one or a combination of iridium manganese (IrMn), platinum manganese (PtMn), iron manganese (FeMn), ruthenium manganese (RuMn), nickel manganese (NiMn) and palladium platinum manganese (PdPtMn).
  • IrMn iridium manganese
  • PtMn platinum manganese
  • FeMn iron manganese
  • RuMn ruthenium manganese
  • NiMn nickel manganese
  • PdPtMn palladium platinum manganese
  • Different materials of the capacitor layer 323 may correspond to different memories.
  • the material of the capacitor layer 323 is a ferroelectric material, and the memory may be a ferroelectric memory.
  • the material of the capacitor layer 323 is an insulating material, and the memory may be a dynamic random access memory.
  • the material of the capacitor layer 323 is a phase change material
  • the memory may be a phase change memory
  • the material of the capacitor layer 323 is a resistive material
  • the memory may be a resistive memory
  • the material of the capacitor layer 323 is a ferromagnetic material, and the memory may be a magnetic random access memory.
  • the capacitor 320 and the transistor 310 in the memory cell 300 are arranged in a direction parallel to the substrate 201. That is, the capacitor 320 and the transistor 310 are arranged in the first direction x or the second direction y.
  • the capacitor 320 is formed on one side of the transistor 310. In other words, the capacitor 320 is formed on the side wall of the first electrode 311 of the transistor 310.
  • the capacitor 320 is disposed on one side of the transistor 310 along the first direction x or the second direction y, rather than on one side of the transistor 310 along the third direction z. In this way, the size of the memory cell 300 can be reduced, and the memory cell 300 can be miniaturized.
  • the capacitor layer 323 includes a first portion 301, a second portion 302 and a third portion 303.
  • the first portion 301 extends along the third direction z
  • the second portion 302 and the third portion 303 both extend along the first direction x or the second direction y.
  • the first capacitor electrode 321 of the capacitor 320 has a first side surface a1 opposite to the second capacitor electrode 322
  • the second capacitor electrode 322 of the capacitor 320 has a second side surface a2 opposite to the first capacitor electrode 321 .
  • the first capacitor electrode 321 of the capacitor 320 further has a first top surface b1 and a first bottom surface c1 adjacent to the first side surface a1
  • the second capacitor electrode 322 of the capacitor 320 further has a second top surface b2 and a second bottom surface c2 adjacent to the second side surface a2 .
  • the first portion 301 of the capacitor layer 323 contacts both the first side surface a1 and the second side surface a2 .
  • the portion of the capacitor layer 323 between the first capacitor electrode 321 and the second capacitor electrode 322 is used as the first portion 301 of the capacitor layer 323 .
  • the second portion 302 is in contact with the first top surface b1
  • the third portion 303 is in contact with the first bottom surface c1 .
  • the second portion 302 contacts the second top surface b2
  • the third portion 303 contacts the second bottom surface c2 .
  • the capacitor layer 323 shown in FIG. 5A and FIG. 5B is in a groove shape.
  • the second portion 302 contacts the first top surface b1
  • the third portion 303 contacts the second bottom surface c2 .
  • the capacitor layer 323 shown in FIG. 5C is in a Z shape.
  • the second portion 302 contacts both the first top surface b1 and the first bottom surface c1
  • the third portion 303 contacts both the second top surface b2 and the second bottom surface c2 .
  • the capacitor layer 323 shown in FIG. 5D is in an I-shape.
  • the capacitor layer 323 is only located between the first capacitor electrode 321 and the second capacitor electrode 322 of the capacitor 320. It can also be understood that the capacitor layer 323 is the first portion 301 without the second portion 302 and the third portion 303.
  • the contact surface between the capacitor layer 323 and the first capacitor electrode 321 and the second capacitor electrode 322 is a plane.
  • the first side surface a1 and the second side surface a2 are planes.
  • At least one of the contact surfaces between the capacitor layer 323 and the first capacitor electrode 321 or the second capacitor electrode 322 is a curved surface.
  • at least one of the first side surface a1 or the second side surface a2 is a curved surface.
  • first side surface a1 and the second side surface a2 may both be curved surfaces.
  • first side surface a1 is a curved surface
  • second side surface a2 is a flat surface
  • first side surface a1 is a flat surface
  • second side surface a2 is a curved surface.
  • the area of the first portion 301 of the capacitor layer 323 can be increased, thereby increasing the storage capacity of the capacitor 320 .
  • the first side surface a1 or the second side surface a2 may also be other irregular surfaces, such as wave-shaped, sawtooth-shaped, etc. This embodiment of the present application does not limit this.
  • a plurality of memory cells 300 are arranged along a first direction x and a second direction y to form a memory layer 202.
  • a plurality of memory layers 202 are stacked along a third direction z to form a three-dimensional memory array 210.
  • the second capacitor electrodes 322 of adjacent storage units 300 are connected.
  • a dielectric layer 400 for insulation is also filled between adjacent storage units 300.
  • the three-dimensional memory array 210 further includes word lines WL, bit lines BL, and plate lines PL.
  • the second capacitor electrodes 322 of all memory cells 300 in the three-dimensional memory array 210 are electrically connected to the plate line PL.
  • the second capacitor electrodes 322 of all memory cells 300 are connected to the plate line PL constituting the memory layer 202, and the plate line PL extends in a direction parallel to the substrate 201 (the first direction x or the second direction y).
  • the plate line PL is located in the plane The surface is parallel to the substrate 201.
  • the plate lines PL between different storage layers 202 are also electrically connected.
  • the gates 313 of all memory cells 300 in the three-dimensional memory array 210 are electrically connected to the word lines WL.
  • the word lines WL extend along a direction z (third direction z) perpendicular to the substrate. That is, along the direction z (third direction z) perpendicular to the substrate, the gates 313 of each memory cell 300 are connected by the word lines WL.
  • the second electrodes 312 of all memory cells 300 in the three-dimensional memory array 210 are electrically connected to the bit line BL.
  • the second electrodes of all memory cells 300 are connected to form the bit line BL of the memory layer 202, and the bit line extends in a direction parallel to the substrate 201. In other words, the plane where the bit line BL is located is parallel to the substrate 201.
  • the three-dimensional storage array 210 provided in the first embodiment of the present application includes a substrate 201 and a plurality of storage layers 202 formed on the substrate 201.
  • the plurality of storage layers 202 are stacked along a direction z perpendicular to the substrate 201.
  • the storage layer 202 includes a plurality of storage cells 300.
  • the storage cell 300 includes an electrically connected capacitor 320 and a transistor 310.
  • the transistor 310 includes a gate 313, a channel 314, and a first pole 311 and a second pole 312 arranged along a direction perpendicular to the substrate 201 and arranged around the channel 314.
  • the capacitor 320 includes a first capacitor electrode 321, a second capacitor electrode 322, and a capacitor layer 323 arranged between the first capacitor electrode 321 and the second capacitor electrode 322, and the first capacitor electrode 321 is electrically connected to the first pole 311.
  • the solution provided in the first embodiment of the present application includes a plurality of storage layers 202 of a plurality of storage units 300 stacked in a direction perpendicular to the substrate 201, so that the formation of the storage unit 300 does not need to rely on the substrate 201.
  • the storage unit 300 can be prepared by a back-end process, and can achieve multi-layer stacking in a direction perpendicular to the substrate 201, and achieve stacking in a three-dimensional direction, thereby improving the storage density of the three-dimensional storage array 210 and improving the storage capacity of the three-dimensional storage array 210.
  • the read/write window can be increased by changing the contact surface area between the capacitor layer 323 and the first capacitor electrode 321 and the second capacitor electrode 322 .
  • the present application also provides a method for preparing the above-mentioned memory.
  • the memory provided in the embodiment of the present application and the method for preparing the same are schematically illustrated with specific examples.
  • the embodiment of the present application provides a method for manufacturing a three-dimensional memory array, wherein the three-dimensional memory array 210 includes a substrate 201 and a plurality of memory layers 202 stacked on the substrate 201 along a direction z perpendicular to the substrate 201.
  • the memory layer 202 includes a plurality of memory cells 300, and the method for manufacturing the memory cells 300 includes:
  • a method for preparing a three-dimensional memory array 210 includes:
  • a dielectric layer 400 is formed on the substrate 201 .
  • a first dielectric layer 401 , a second dielectric layer 402 , a third dielectric layer 403 and a fourth dielectric layer are sequentially formed on the substrate 201 to form the dielectric layer 400 .
  • the materials of the first dielectric layer 401, the second dielectric layer 402, the third dielectric layer 403, and the fourth dielectric layer 404 are all different, so that different dielectric layers can be selectively etched when the transistor 310 and the capacitor 320 are subsequently formed.
  • the thicknesses of the different dielectric layers can be the same or different. This embodiment of the present application does not limit this, and can be reasonably set according to the size of different structures to be formed subsequently.
  • a storage layer 202 is subsequently formed in a dielectric layer 400.
  • the number of dielectric layers 400 formed is not limited and can be reasonably set according to actual conditions.
  • the following is a schematic illustration of forming two dielectric layers 400 on the substrate 201.
  • the substrate 201 is not shown in the drawings below.
  • the via hole 410 extends along a direction z perpendicular to the substrate 201.
  • the via hole 410 may be formed by a deep hole etching process.
  • the via hole 410 penetrates all the dielectric layers 400 .
  • step S13 includes:
  • a second electrode 312 is formed.
  • the third dielectric layer 403 on the sidewall of the via hole 410 is etched and then filled with metal to form the second electrode 312 .
  • the first dielectric layer 401 on the sidewall of the via hole 410 is etched, and then filled with capacitor layer material and oxide material, followed by oxide etching back, and finally filled with metal material to form the capacitor layer 323 and the first electrode 311 .
  • a second dielectric layer 402 is provided between the first pole 311 and the second pole 312 , so the first pole 311 and the second pole 312 are arranged along a direction z perpendicular to the substrate 201 .
  • the second dielectric layer 402 on the sidewall of the via hole 410 is etched, and then filled with heavily doped polysilicon material to form a semiconductor layer.
  • the semiconductor layer covers the sidewalls of the etched second dielectric layer 402 and two opposite surfaces of the first dielectric layer 401 and the third dielectric layer 403 .
  • a dielectric layer material is filled in the area surrounded by the semiconductor layer, and the dielectric layer material filled can be the same as the material of the second dielectric layer 402.
  • the dielectric layer material is used to isolate the first semiconductor layer 316 and the second semiconductor layer 317 to be formed subsequently.
  • step S14 the semiconductor layer material formed on the sidewall of the second dielectric layer 402 after etching is not removed in step S14.
  • a channel 314 and a gate 313 are formed in the via hole 410 .
  • a channel 314, a gate oxide layer 315, and a gate 313 are sequentially formed in the via hole 410.
  • the material of the channel 314 is first filled in the via hole 410, and then the material is etched to form a through second via hole, and the side wall of the second via hole is the channel 314.
  • an oxide material is filled in the second via hole, and then the oxide material is etched to form a through third via hole and a gate oxide layer 315 located on the side wall of the third via hole.
  • the gate 313 is formed in the third via hole.
  • a transistor 310 is formed.
  • the channel 314 material on the sidewall of the fourth dielectric layer 404 is removed to disconnect the channel 314 between the adjacent storage layers 202 (dielectric layer 400).
  • the semiconductor layer material on the sidewall of the second dielectric layer 402 is removed to disconnect the first semiconductor layer 316 and the second semiconductor layer 317. In this way, the transistor 310 is formed.
  • a second capacitor electrode 322 is formed to form a capacitor 320 .
  • the first dielectric layer 401 is etched and filled with metal material to form a second capacitor electrode 322 on a side of the capacitor layer 323 away from the first electrode 311 to form a capacitor 320 .
  • the first capacitor electrode 321 of the capacitor 320 and the first electrode 311 of the transistor 310 share the same electrode.
  • the method for manufacturing the three-dimensional memory array 210 further includes: forming word lines WL, bit lines BL, and plate lines PL.
  • the gate electrodes of the plurality of memory cells 300 are electrically connected to form a word line WL.
  • the second electrodes 312 of the plurality of memory cells 300 are electrically connected to form a bit line BL.
  • the second capacitor electrodes 322 of the plurality of memory cells 300 are electrically connected to form a plate line PL.
  • step S15 when the gate electrode 313 is formed, a word line WL electrically connected to the gate electrode 313 is also formed at the same time.
  • step S13 when the second electrode 312 is formed, a bit line BL electrically connected to the second electrode 312 is also formed at the same time.
  • step S17 when the second capacitor electrode 322 is formed, a plate line PL electrically connected to the second capacitor electrode 322 is also formed at the same time.
  • Example 1 of the present application is not limited to any step sequence and can be reasonably adjusted as needed.
  • steps S11-S17 may remove some steps as needed, and are not limited to including every step. Some steps may also be added as needed, and are not limited to only including the above steps.
  • the method for preparing the three-dimensional storage array 210 provided in the first embodiment of the present application includes a substrate 201 and a plurality of storage layers 202 formed on the substrate 201.
  • the plurality of storage layers 202 are stacked along a direction z perpendicular to the substrate 201.
  • the storage layer 202 includes a plurality of storage units 300.
  • the formation method includes: forming a dielectric layer 400 on the substrate 201, and forming a via 410 extending along a direction perpendicular to the substrate 201 and penetrating the dielectric layer 400. Then, forming a capacitor layer 323 and a first pole 311, and a second pole 312 spaced from the first pole 311 in the dielectric layer 400 on the side wall of the via 410.
  • the formation of the memory cell 300 does not depend on the substrate 201, that is, the memory cell 300 can be prepared by a back-end process, and can realize multi-layer stacking in the vertical direction along the substrate 201, realize the stacking of the memory cell 300 in the three-dimensional direction, improve the storage density of the three-dimensional storage array 210, and improve the storage capacity of the three-dimensional storage array 210.
  • the memory cells 300 in multiple storage layers 202 can be formed at the same time, and the preparation cost is low.
  • the first pole 311 and the second pole 312 of the transistor 310 are formed, and the channel 314 of the transistor 310 is formed in steps, which can more easily control the formation morphology of each structure, which is conducive to improving the consistency of the transistor 310.
  • the three-dimensional memory array 210 in the embodiment of the present application can also lead out the plate line PL of each memory layer 202 at the same time without adding additional step process steps.
  • the read/write window can be increased by changing the contact surface area between the capacitor layer 323 and the first capacitor electrode 321 and the second capacitor electrode 322 .
  • the main difference between the second embodiment and the first embodiment is that the transistor 310 is different.
  • the gate 313 of the transistor 310 is arranged around the channel 314 along a direction parallel to the substrate 201 (a plane formed by the first direction x and the second direction y), and the gate 313 is located between the first pole 311 and the second pole 312.
  • the first pole 311, the gate 313 and the second pole 312 are arranged along a direction z perpendicular to the substrate 201.
  • transistor 310 can be regarded as a gate all around (GAA) transistor.
  • GAA gate all around
  • the memory cell 300 further includes a first semiconductor layer 316 and a second semiconductor layer 317.
  • the first semiconductor layer 316 is located between the first electrode 311 and the channel 314, and is disposed around the channel 314.
  • the second semiconductor layer 317 is located between the second electrode 312 and the channel 314, and is disposed around the channel 314.
  • the memory cell 300 further includes a gate oxide layer 315 .
  • the gate oxide layer 315 is located between the gate 313 and the channel 314 , and surrounds the channel 314 .
  • the word line WL extends in a direction parallel to the substrate 201. That is, the plane where the word line WL is located is parallel to the substrate 201.
  • the bit line BL also extends in a direction parallel to the substrate 201, and the leading directions of the word line WL and the bit line BL intersect, for example, the leading directions of the word line WL and the bit line BL are perpendicular.
  • Embodiment 2 of the present application further provides a method for preparing a three-dimensional storage array, as shown in FIG10 , comprising:
  • a dielectric layer 400 is formed on the substrate 201 .
  • a first dielectric layer 401 , a second dielectric layer 402 , a third dielectric layer 403 , a fourth dielectric layer 404 , a fifth dielectric layer 405 and a sixth dielectric layer 406 are sequentially formed on a substrate 201 to form a dielectric layer 400 .
  • the thickness of the second dielectric layer 402 and the thickness of the fourth dielectric layer 404 are both smaller than the thickness of the remaining dielectric layers.
  • Step S22 is the same as the above step S12, and reference may be made to the above description of S12.
  • a first electrode 311 , a second electrode 312 , a gate 313 and a capacitor layer 323 are formed.
  • a capacitor layer 323 and a first electrode 311 are formed in the first dielectric layer 401 , a gate electrode 313 is formed in the third dielectric layer 403 , and a second electrode 312 is formed in the fifth dielectric layer 405 .
  • the method of forming the first electrode 311 , the second electrode 312 and the capacitor layer 323 is the same as the method of forming in the first embodiment, and the relevant description in the first embodiment may be referred to.
  • the method for forming the gate 313 is the same as the method for forming the gate 313 in the first embodiment, and reference may be made to the relevant description in the first embodiment.
  • a gate oxide layer 315 located on one side of the gate 313 , and a first semiconductor layer 316 and a second semiconductor layer 317 located on one side of the first electrode 311 and the second electrode 312 are further formed.
  • the material of the channel 314 and the insulating material are filled in the via hole 410 , and the material of the channel 314 on the sidewall of the sixth dielectric layer 406 is removed to form the transistor 310 .
  • Step S25 is the same as the above step S17, and reference may be made to the above description of S17.
  • Example 2 of the present application is not limited to any step sequence and can be reasonably adjusted as needed.
  • steps S21-S25 may remove some steps as needed, and are not limited to include every step. Some steps may also be added as needed, and are not limited to only include the above steps.

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Abstract

本申请实施例提供一种三维存储阵列及其制备方法、存储器、电子设备，涉及存储技术领域，用于提高三维存储阵列的存储容量。三维存储阵列包括衬底以及形成在衬底上的多个存储层。多个存储层沿着与衬底相垂直的方向堆叠。存储层包括多个存储单元。存储单元包括电连接的电容器和晶体管。其中，晶体管包括栅极、沟道以及沿与衬底相垂直的方向布设、且环绕沟道设置的第一极和第二极。电容器包括第一电容电极、第二电容电极以及设置于第一电容电极和第二电容电极之间的电容层，第一电容电极与第一极电连接。

Description

三维存储阵列及其制备方法、存储器、电子设备
本申请要求于2023年02月07日提交国家知识产权局、申请号为202310132773.4、申请名称为“三维存储阵列及其制备方法、存储器、电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及存储技术领域，尤其涉及一种三维存储阵列及其制备方法、存储器、电子设备。
背景技术
铁电存储器作为一种新型存储器，相比于传统的动态随机存取存储器(dynamic random access memory，DRAM)，具有低延时、低功耗、可微缩等优势，将成为新一代主流存储器。
然而，传统的铁电存储器采用二维集成方式集成在衬底内，占用面积大，且无法堆叠，导致存储器存储密度小，且限制了存储器的存储容量。
基于此，如何减小存储单元所占区域的面积，以提高存储器的存储密度，进而提高存储器的存储容量，成为本领域亟待解决的问题。
发明内容
本申请实施例提供一种三维存储阵列及其制备方法、存储器、电子设备，用于提高三维存储阵列的存储容量。
为达到上述目的，本申请采用如下技术方案：
本申请实施例的第一方面，提供一种三维存储阵列，包括衬底以及形成在衬底上的多个存储层。多个存储层沿着与衬底相垂直的方向堆叠。存储层包括多个存储单元。存储单元包括电连接的电容器和晶体管。其中，晶体管包括栅极、沟道以及沿与衬底相垂直的方向布设、且环绕沟道设置的第一极和第二极。电容器包括第一电容电极、第二电容电极以及设置于第一电容电极和第二电容电极之间的电容层，第一极和第一电容电极电连接。
本申请实施例提供的三维存储阵列，包括多个存储单元的多个存储层沿与衬底相垂直的方向堆叠，使存储单元的形成无需依赖衬底，因此该存储单元可以采用后道工艺制备，能够实现在沿衬底垂直方向上的多层堆叠，实现三维方向上的堆叠，进而提高三维存储阵列的存储密度，提高三维存储阵列的存储容量。
在一种可能的实现方式中，存储单元中的电容器和晶体管沿着与衬底相平行的方向布设。这样一来，能够减小每个存储单元在垂直方向上的尺寸，实现存储单元的微缩。
在一种可能的实现方式中，第一极与第一电容电极共用同一电极。这样一来，易于形成，节省工艺步骤。
在一种可能的实现方式中，栅极和沟道均沿与衬底相垂直的方向延伸，且沟道环绕栅极设置。这样一来，存储单元中的晶体管可以看作沟道环绕型晶体管。
在一种可能的实现方式中，栅极沿与衬底相平行的方向环绕沟道设置，且栅极位于第一极和第二极之间。这样一来，存储单元中的晶体管可以看作栅极环绕型晶体管。
在一种可能的实现方式中，三维存储阵列还包括字线、位线以及板线；栅极均与字线电连接，第二极均与位线电连接，第二电容电极均与板线电连接；字线沿与衬底相垂直的方向延伸；同一存储层中，板线沿与衬底相平行的方向延伸，位线沿与衬底相平行的方向延伸。这样一来，通过分别在字线、位线以及板线上施加不同的电压，实现对多个存储单元的读写。同时，可以将每个存储层的板线同时引出，不会增加额外的台阶工艺步骤。
在一种可能的实现方式中，存储单元还包括第一半导体层和第二半导体层；第一半导体层连接第一极和沟道；第二半导体层连接第二极和沟道。这样一来，有利于形成晶体管的第一极和第二极。
在一种可能的实现方式中，电容层包括沿与衬底相垂直的方向延伸的第一部分，以及沿与衬底相平行的方向延伸的第二部分和第三部分；第一电容电极具有与第二电容电极相对的第一侧面， 第二电容电极具有与第一电容电极相对的第二侧面；第一部分与第一侧面和第二侧面均接触。这样一来，可以通过改变电容层与第一电容电极、第二电容电极的接触面面积，以提高读写窗口。
在一种可能的实现方式中，第一电容电极还具有与第一侧面相邻的第一顶面和第一底面，第二电容电极还具有与第二侧面相邻的第二顶面和第二底面；第二部分与第一顶面接触，第三部分与第一底面接触。这样一来，可以通过改变电容层与第一电容电极、第二电容电极的接触面面积，以提高读写窗口。
在一种可能的实现方式中，第一电容电极还具有与第一侧面相邻的第一顶面和第一底面，第二电容电极还具有与第二侧面相邻的第二顶面和第二底面；第二部分与第二顶面接触，第三部分与第二底面接触。这样一来，可以通过改变电容层与第一电容电极、第二电容电极的接触面面积，以提高读写窗口。
在一种可能的实现方式中，第一电容电极还具有与第一侧面相邻的第一顶面和第一底面，第二电容电极还具有与第二侧面相邻的第二顶面和第二底面；第二部分与第一顶面接触，第三部分与第二底面接触。这样一来，可以通过改变电容层与第一电容电极、第二电容电极的接触面面积，以提高读写窗口。
在一种可能的实现方式中，第一电容电极还具有与第一侧面相邻的第一顶面和第一底面，第二电容电极还具有与第二侧面相邻的第二顶面和第二底面；第二部分与第一顶面和第一顶面均接触，第三部分与第二顶面和第二底面均接触。这样一来，可以通过改变电容层与第一电容电极、第二电容电极的接触面面积，以提高读写窗口。
在一种可能的实现方式中，第一侧面或第二侧面中至少一个为曲面。这样一来，可以通过改变电容层与第一电容电极、第二电容电极的接触面面积，以提高读写窗口。
在一种可能的实现方式中，同一存储层中，相邻的存储单元的第二电容电极连接。这样一来，能够减小存储层的尺寸，进而提高三维存储阵列的存储密度。
在一种可能的实现方式中，电容层的材料包括铁电材料、绝缘材料、相变材料、阻变材料或者铁磁材料中的任意一种。这样一来，可以根据电容层材料的不同，形成不同的存储器。
本申请实施例的第二方面，提供一种三维存储阵列的制备方法，三维存储阵列包括衬底以及多个存储层，多个存储层沿着与衬底相垂直的方向堆叠于衬底上；存储层包括多个存储单元。存储单元的制备方法包括：在衬底上形成介质层；形成贯穿介质层的过孔，过孔沿与衬底相垂直的方向延伸；在过孔侧壁的介质层内形成电容层和第一极，以及形成与第一极具有间隔的第二极；第一极和第二极均沿与衬底相平行的方向延伸；在过孔内形成沟道和栅极，以形成晶体管；在电容层远离第一极的一侧形成第二电容电极，以形成电容器。
本申请实施例中提供的三维存储阵列的制备方法，存储单元的形成不依赖于衬底，即存储单元可以采用后道工艺制备，能够实现在沿衬底垂直方向上的多层堆叠，实现存储单元在三维方向上的堆叠，提高三维存储阵列的存储密度，提高三维存储阵列的存储容量。多个存储层中的存储单元可以同时形成，制备成本低。另外，本申请实施例提供的制备方法中形成晶体管的第一极和第二极，以及晶体管的沟道分步骤形成，能够更容易控制各个结构的形成形貌，有利于改善晶体管的一致性。
在一种可能的实现方式中，在形成沟道和栅极之前，制备方法还包括：在过孔侧壁的介质层内形成第一半导体层和第二半导体层。这样一来，有利于后续制备第一极和第二极。
在一种可能的实现方式中，制备方法还包括：形成字线、位线以及板线；字线与栅极电连接，位线与第二极电连接，板线与第二电容电极电连接。这样一来，通过分别在字线、位线以及板线上施加不同的电压，实现对多个存储单元的读写。
本申请实施例的第三方面，提供一种三维存储阵列的制备方法，三维存储阵列包括衬底以及多个存储层，多个存储层沿着与衬底相垂直的方向堆叠于衬底上；存储层包括多个存储单元。存储单元的制备方法包括：在衬底上形成介质层；形成贯穿介质层的过孔，过孔沿与衬底相垂直的方向延伸；在过孔侧壁的介质层内形成电容层和第一极，以及形成与第一极具有间隔的栅极和第二极；第一极、栅极以及第二极均沿与衬底相平行的方向延伸；在过孔内形成沟道，以形成晶体管；在电容层远离第一极的一侧形成第二电容电极，以形成电容。
本申请实施例第三方面提供的三维存储阵列的制备方法，其有益效果与第二方面提供的三维存储阵列的制备方法的有益效果相同，在此不再赘述。
本申请实施例的第四方面，提供一种存储器，包括：控制器以及第一方面任一项的三维存储阵列，控制器与三维存储阵列电连接。
本申请实施例第四方面提供的存储器，包括第一方面的三维存储阵列，其有益效果与三维存储阵列的有益效果相同，在此不再赘述。
本申请实施例的第五方面，提供一种电子设备，包括：电路板以及如第四方面的存储器，电路板与存储器电连接。
本申请实施例第五方面提供的电子设备，包括第四方面的存储器，其有益效果与存储器的有益效果相同，在此不再赘述。
附图说明
图1A为本申请实施例提供的一种电子设备的结构框图；
图1B为本申请实施例提供的一种电子设备的结构示意图；
图2A为本申请实施例提供的一种存储器的结构框图；
图2B为本申请实施例提供的一种存储单元的电路图；
图3为本申请实施例提供的一种存储阵列的结构示意图；
图4A为本申请实施例提供的另一种三维存储阵列的结构示意图；
图4B为图4A沿A1A2向的一种剖视图；
图4C为本申请实施例提供的一种存储单元的结构示意图；
图5A为本申请实施例提供的另一种存储单元的结构示意图；
图5B为本申请实施例提供的又一种存储单元的结构示意图；
图5C为本申请实施例提供的又一种存储单元的结构示意图；
图5D为本申请实施例提供的又一种存储单元的结构示意图；
图6A为本申请实施例提供的又一种存储单元的结构示意图；
图6B为本申请实施例提供的又一种存储单元的结构示意图；
图7为本申请实施例提供的一种三维存储阵列的制备方法的流程示意图；
图8A-图8H为本申请实施例提供的一种三维存储阵列的制备方法的过程示意图；
图9A为本申请实施例提供的又一种三维存储阵列的结构示意图；
图9B为图9A沿B1B2向的一种剖视图；
图9C为本申请实施例提供的又一种存储单元的结构示意图；
图10为本申请实施例提供的另一种三维存储阵列的制备方法的流程示意图；
图11A-图11E为本申请实施例提供的另一种三维存储阵列的制备方法的过程示意图。
附图标记
1-电子设备；11-存储装置；12-处理器；13-输入设备；14-输出设备；111-外存储器；112-内存
储器；121-运算器；122-控制器；15-中框；16-后壳；17-显示屏；18-电路板；150-承载板；151-边框；200-存储器；210-存储阵列；220-译码器；230-驱动器；240-时序控制器；250-缓存器；260-输入输出接口；201-衬底；202-存储层；300-存储单元；310-晶体管；320-电容器；311-第一极；312-第二极；313-栅极；314-沟道；315-栅氧化层；316-第一半导体层；317-第二半导体层；321-第一电容电极；322-第二电容电极；323-电容层；400-介质层；401-第一介质层；402-第二介质层；403-第三介质层；404-第四介质层；405-第五介质层；406-第六介质层。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，术语“第二”、“第一”等仅用于描述方便，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第二”、“第一”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或 两个以上。
此外，本申请实施例中，“上”、“下”、“左”、“右”等方位术语可以包括但不限于相对附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语可以是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件附图所放置的方位的变化而相应地发生变化。
在本申请实施例中，除非另有明确的规定和限定，术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。此外，术语“相耦接”可以是直接的电性连接，也可以通过中间媒介间接的电性连接。术语“接触”可以是直接接触，也可以是通过中间媒介间接的接触。
本申请实施例中，“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。
下面，首先对本申请实施例中的一些术语做出解释。
存储器：在芯片中，存储器是用来存储程序和数据信息的记忆部件。常见存储器存储的信息是以二进制单位存储在芯片中，也就是以“逻辑0”或者“逻辑1”保存在存储器中。在物理器件中，通常是以电压的高或者低、电阻的大或者小、电荷量的多或者少等方式得以实现。
比特：是存储器中存储信息的最小数量单位。n个比特可以表示2n种状态。例如，一个比特可以表示两种状态，0或者1。两个比特可以表示四种状态，00、01、10、11，以此类推。也就是说，如果一个存储器种存储的物理信息存在m种状态，它就是一个log2m比特的存储器。
易失性存储器和非易失性存储器(non-volatile memory，NVM)：按照存储器中所存储的信息在芯片外部供电电源移除后，存储的信号是否依旧存在，存储器可以被分为易失性存储器和非易失性存储器。易失性存储器以静态随机存储器(static random accessory memory，SRAM)或动态随机存储器(dynamic random access memory，DRAM)为代表，信息的存储必须有持续的外部供电。当无外加电源时，存储的信息也不复存在。非易失性存储器以传统的只读存储器(read-only memory，ROM)和闪存(flash)、铁电存储器(ferroelectric random-access memory，FeRAM、ferroelectric field effect transistor，FeFET)，磁性随机存储器(magnetoresistive random access memory，MRAM)、阻变式存储器(resistive random access memory，RRAM)和相变存储器(phase-change random access memory，PCRAM)为代表。这些非易失性存储器都以其各自独特的物理原理，实现掉电信息不丢失的特点。
本申请实施例提供一种的电子设备。该电子设备例如为消费性电子产品、家居式电子产品、车载式电子产品、金融终端产品。其中，消费性电子产品如为手机(mobile phone)、平板电脑(pad)、笔记本电脑、电子阅读器、个人计算机(personal computer，PC)、个人数字助理(personal digital assistant，PDA)、桌面显示器、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(virtual reality，VR)终端设备、增强现实(augmented reality，AR)终端设备、无人机等。家居式电子产品如为智能门锁、电视、遥控器、冰箱、充电家用小型电器(例如豆浆机、扫地机器人)等。车载式电子产品如为车载导航仪、车载DVD等。金融终端产品如为ATM机、自助办理业务的终端等。通信电子产品如为服务器、存储器、雷达、基站等通信设备。
示例一种电子设备，如图1A所示，电子设备1包括：存储装置11、处理器12、输入设备13、输出设备14等部件。本领域技术人员可以理解到，图1A中示出的电子设备1的架构并不构成对该电子设备1的限定，该电子设备1可以包括比如图1A所示的部件更多或更少的部件，或者可以组合如图1A所示的部件中的某些部件，或者可以与如图1A所示的部件布置不同。
其中，存储装置11用于存储软件程序以及模块。存储装置11主要包括存储程序区和存储数据区，其中，存储程序区可存储和备份操作系统、至少一个功能所需的应用程序(比如声音播放功能、图像播放功能等)等；存储数据区可存储根据电子设备1的使用所创建的数据(比如音频数据、图像数据、电话本等)等。
处理器12是该电子设备1的控制中心，利用各种接口和线路连接整个电子设备1的各个部分，通过运行或执行存储在存储装置11内的软件程序和/或模块，以及调用存储在存储装置11 内的数据，执行电子设备1的各种功能和处理数据，从而对电子设备1进行整体监控。可选的，处理器12可以包括一个或多个处理单元。例如，处理器12可以包括应用处理器(application processor，AP)，调制解调处理器，图形处理器(graphics processing unit，GPU)等。其中，不同的处理单元可以是独立的器件，也可以集成在一个或多个处理器中。例如，处理器12可集成应用处理器和调制解调处理器，其中，应用处理器主要处理操作系统、用户界面和应用程序等，调制解调处理器主要处理无线通信。可以理解的是，上述调制解调处理器也可以不集成到处理器12中。上述的应用处理器例如可以为中央处理器(central processing unit，CPU)。图1A中以处理器12为CPU为例，CPU可以包括运算器121和控制器122。运算器121获取内存储器112存储的数据，并对内存储器112存储的数据进行处理，处理后的结果通常送回内存储器112。控制器122可以控制运算器121对数据进行处理，控制器122还可以控制外存储器111和内存储器112读取或写入数据。
输入设备13用于接收输入的数字或字符信息，以及产生与电子设备的用户设置以及功能控制有关的键信号输入。示例的，输入设备13可以包括触摸屏以及其他输入设备。触摸屏，也称为触摸面板，可收集用户在触摸屏上或附近的触摸操作(比如用户使用手指、触笔等任何适合的物体或附件在触摸屏上或在触摸屏附近的操作)，并根据预先设定的程式驱动相应的连接装置。
输出设备14用于输出输入设备13的输入，和存储在存储装置11中的数据对应的信号。例如，输出设备14输出声音信号或视频信号。上述处理器12中的控制器122还可以控制输出设备14输出信号或不输出信号。
需要说明的是，图1A中的粗箭头用于表示数据的传输，粗箭头的方向表示数据传输的方向。例如，输入设备13和内存储器112之间的单箭头表示输入设备13接收到的数据向内存储器112传输。又例如，运算器121和内存储器112之间的双箭头表示内存储器112存储的数据可以向运算器121传输，且运算器121处理后的数据可以向内存储器112传输。图1A中的细箭头表示控制器122可以控制的部件。示例性地，控制器122可以对外存储器111、内存储器112、运算器121、输入设备13和输出设备14等进行控制。
为了方便进一步对电子设备1的结构进行说明，以下以电子设备1为手机为例进行示例性介绍。
参见图1B，电子设备1还可以包括中框15、后壳16以及显示屏17。后壳16和显示屏17分别位于中框15的相对两侧，且中框15和显示屏17设置于后壳16内。中框15包括用于承载显示屏17的承载板150，以及绕承载板150一周的边框151。
继续参见图1B，电子设备1还可以包括电路板18，该电路板18设置于承载板150的靠近后壳16的一侧，电子设备1中的内存储器112可以设置于电路板18上，内存储器112与电路板18电连接。
根据前文所述，内存储器112可以包括随机存储器、只读存储器等，按照工作原理进行划分，随机存储器还可以包括铁电存储器(ferroelectric random access memory，FeRAM)、动态随机存取存储器(dynamic random access memory，DRAM)、相变存储器(phase change random access memory，PCRAM)、阻变存储器(resistive random access memory，ReRAM)或磁性随机存储器(magnetoresistive random access memory，MRAM)。铁电存储器是基于铁电材料的铁电效应来存储数据。铁电存储器因其超高的存储密度、低功耗和高速度等优势，有望成为替代DRAM的主要竞争者。铁电存储器中的存储单元包含铁电电容，铁电电容包括由铁电材料制得的铁电层。由于铁电材料的非线性特性，铁电材料的介电常数不仅可以调节，而且在铁电层极化状态翻转前后的差值非常大，这使得铁电电容与其他电容相比体积较小，比如，比DRAM中的用于存储电荷的电容体积小很多。目前，铁电存储器凭借其存储数据非易失性、存取速率快、低延时、低功耗以及可微缩等特点，同时铁电存储器还能与DRAM的产线兼容，成为主流的内存储器之一。
在铁电存储器中，铁电层可以采用常见的铁电材料形成，比如，ZrO2，HfO2等。当一个电场被施加到铁电层时，中心原子顺着电场停在低能量状态，反之，当电场反转被施加到该铁电层时，中心原子顺着电场的方向在晶体里移动并停在另一低能量状态。大量中心原子在晶体单胞中 移动耦合形成铁电畴(ferroelectric domains)，铁电畴在电场作用下形成极化电荷。铁电畴在电场下反转所形成的极化电荷较高，铁电畴在电场下无反转所形成的极化电荷较低，这种铁电材料的二元稳定状态使得铁电可以作为存储器。
本文的以下实施例以内存储器112为铁电存储器为例进行介绍，图2A为根据一些实施例的铁电存储器的架构图。
参见图2A，存储器200包括存储阵列210、译码器220、驱动器230、时序控制器240、缓存器250和输入输出接口260。存储阵列210包括阵列式排布的多个存储单元300。
时序控制器240用于控制存储阵列210和存储电路的读取和写入。存储单元300的存储密度直接影响着存储阵列210的存储密度。
图2B为根据一些实施例的存储单元的电路图。
参见图2B，存储单元300包括基于铁电电容的电路架构，该存储单元300具有1T1C(1-transistor-1-capacitor)结构，即存储单元300包括一个晶体管T和一个铁电电容C，晶体管T的源极与位线(bit line，BL)电连接，漏极与铁电电容C的一个电极电连接，栅极与字线(word line，WL)电连接，铁电电容C的另一个电极与板线(plate line，PL)电连接，本申请的实施例中的存储单元300的电路架构不限于此。
晶体管T例如可以是金属氧化物半导体场效应管(metal–oxide–semiconductor field-effect transistor，MOSFET或者MOS)，MOSFET是现在集成电路的基本单元器件。根据其载流子类型的不同，分为N沟道型(NMOS)和P沟道型(PMOS)。
晶体管T主要包括控制极(例如栅极)、第一输入输出极(例如源极)、以及第二输入输出极(例如漏极)。如图2B所示，例如晶体管T的控制极与字线WL耦接，晶体管T的第一输入输出极与铁电电容器C耦接，晶体管T的第二输入输出极与板线PL耦接。通过改变控制极的电压，来控制第一输入输出极和第二输入输出极之间的电阻，进而控制第一输入输出极和第二输入输出极流过的电流，实现晶体管T的开关特性。
以晶体管T为N型晶体管为例，开态和关态转变的电压被称为阈值电压(Vt)，当控制极电压大于阈值电压时，晶体管T打开，第一输入输出极和第二输入输出极之间存在电流，对应的存储单元300被选中。当控制极电压小于阈值电压时，晶体管T关闭，第一输入输出极和第二输入输出极之间电流几乎为0，对应的存储单元300未被选中。
当然，晶体管T也可以为P型晶体管。N型晶体管为高开低关型晶体管，P型晶体管是低开高关型晶体管，N型晶体管和P型晶体管控制器接收的开启电压与阈值电压的大小相反。当存储单元300被选中时，会向铁电电容器C中施加一个电场(电压)，此时铁电材料内部的极化电荷相对移动，会产生电极化强度。
基于此，上述译码器220可根据接收到的地址进行译码，以确定需要访问的存储阵列210中的存储单元300。驱动器230用于根据译码器220输出的译码结果生成控制信号，该控制信号通过字线WL传输至存储单元300中晶体管T的栅极，以控制晶体管T导通或截止，从而实现对指定存储单元300的访问。缓存器250通过板线PL接收存储单元300输出的数据信号，用于将数据信号进行缓存，例如可以采用先入先出(First-In First-Out，简称：FIFO)来进行缓存。时序控制器240用于控制缓存器250的时序，以及控制驱动器230驱动存储阵列210。输入输出接口260用于传输数据信号，例如接收数据信号或发送数据信号。
上述存储阵列210、译码器220、驱动器230、时序控制器240、缓存器250和输入输出接口260可以集成于一个芯片中，也可以分别集成于多个芯片中。
基于此，如图3所示，示意一种存储阵列210的结构图。该存储阵列210可用于上述存储器200中。
存储阵列210包括多个存储单元300。每个存储单元300包括串联的晶体管和电容，即上述的1T1C结构。晶体管(T)为访问晶体管，访问晶体管作为选通器件，可与其连接的电容(C)进行读写操作。
如图3所示，以多个存储单元300组成的存储阵列为例，存储阵列210集成在衬底表面，也就是多个存储单元300均集成在衬底上。
其中，在衬底内形成晶体管(T)的源极(S)和漏极(D)，电容(C)集成在晶体管(T)的源极(S)或者漏极(D)上。也就是说，存储单元300在衬底的表面进行二维排布。
由于晶体管(T)的源极(S)和漏极(D)均需要在衬底中掺杂得到，因此该存储单元300中的晶体管(T)只能采用前道工艺(front end of line，FEOL)制作，导致存储单元300无法实现三维堆叠。另外，存储阵列210集成于衬底上，占用面积大，导致存储器200的存储密度受到限制，限制了存储器200存储容量的提升，导致存储器200的读写速度跟不上处理器12的运算速度，最终导致计算机，手机等电子产品性能的提升受限。
基于此，为了提高存储器的存储密度，存储单元300可以利用1TnC结构，即n个电容(C)连接同一个晶体管(T)。通过多个电容(C)共同连接一个晶体管(T)，可以提高存储单元300的存储容量，进而提高存储器200的存储密度。
然而，1TnC结构的存储单元300又会带来新的问题。一方面，多个电容(C)连接同一个晶体管(T)会影响存储数据的可靠性；另一方面，受限于存储单元300的读取窗口，电容(C)的数量难以得到进一步提升，导致存储单元300的存储容量无法得到进一步提升。
基于此，为了能够进一步提高存储器中存储阵列的存储容量，且不影响数据可靠性，本申请实施例还提供一种三维存储阵列。
以下提供两个具体实施例，对三维存储阵列进行示例性说明。
实施例一
如图4A和图4B所示，三维存储阵列210主要包括衬底201以及形成于衬底201上的多个存储层202。
图4A示意出一种存储阵列210的三维工艺结构图，图4B为图4A中沿A1A2向的剖面图。
其中，多个存储层202沿着与衬底201相垂直的方向z堆叠。
为了便于示意，本申请实施例中的附图以设置在衬底201上的三个存储层202为例，对本申请实施例提供的存储阵列210进行示意性说明。存储阵列210包括的多个存储单元300组成的存储层202的结构可以与本申请实施例重点描述的存储单元300的结构相同。当然，存储阵列210在包括本申请实施例示意的多个存储单元300的基础上，还可以包括其他结构的存储单元，本申请实施例对此不做限定。
如图4A和图4B所示，相邻的两个存储层202之间通过介质层400相隔开。同一存储层202中，相邻的两个存储单元300之间也填充有介质层400。
衬底201的材料可以是半导体。例如，可以为体硅、体锗、硅锗、碳化硅、绝缘体上硅(silicon-on-insulator，SOI)、绝缘体上锗硅(SiGe-on-insulator，SGOI)中的一种。半导体衬底110还可以是掺杂的(例如，P型掺杂、N型掺杂)或者未掺杂的。
其中，衬底201的半导体材料可包括硅、锗、硅锗(SiGe)中任意一种或者几种的组合。
SOI包括在绝缘体层上形成的半导体材料层。绝缘体层可以是例如掩埋氧化物(BOX)层、氧化硅层等。绝缘体层设置在衬底201上，衬底201通常是硅基底或玻璃基底。也可以使用其他基底，例如，多层或梯度基底。
或者，示例性的，衬底201是晶圆，例如，硅晶圆；衬底201也可以是从晶圆切割下来的晶片。
衬底201的材料还可以包括诸如玻璃、塑料或蓝宝石等的非导电材料。
介质层400的材料例如可以包括氧化硅(SiOx)、氧化氮(SiNx)等绝缘材料，或者掺杂其他绝缘材料。
继续参考图4A和图4B，每个存储层202包括多个存储单元300。
此处释明的是，存储阵列210中包括的多个存储层202可以相同，也可以不同。为了方便示意，本申请实施例以多个存储层202相同，且沿与衬底201相垂直的方向z，不同存储层202中的存储单元300对应。这样一来，有助于形成电连接不同存储层202的位线、字线以及板线。
关于多个存储单元300的排布方式，如图4A所示，多个存储单元300沿与衬底201相平行的方向排布。
为了方便示意，将与衬底201相平行的方向记为第一方向x与第二方向y组成的平面，将与衬底201垂直的方向z记为第三方向z。其中，第一方向x和第二方向y相交，例如，第一方向x和第二方向y垂直。也就是说，第三方向z与第一方向x垂直，第三方向z还与第二方向y垂直。例如，第一方向x、第二方向y以及第三方向z中任意两个方向垂直。
也就是说，同一存储层202中，多个存储单元300沿二维方向排布。即，多个存储单元300分别沿第一方向x和第二方向y排布。
其中，多个存储单元300形成于介质层400内，且相邻的存储单元300之间填充有介质层400。也就是说，介质层400包裹于存储单元300的外围。
关于存储单元300的结构，图4C示意出图4A和图4B中存储单元300的结构。如图4C所示，存储单元300包括晶体管310和电容器320。其中，晶体管310和电容器320电连接，且电容器320形成于晶体管310一侧。
晶体管310包括第一极311、第二极312、栅极313以及沟道314。
其中，第一极311和第二极312沿与衬底201相垂直的方向z布设，也就是说，第一极311和第二极312沿第三方向z布设。
第一极311和第二极312还沿与衬底201平行的方向延伸，即第一极311和第二极312沿第一方向x和第二方向y组成的平面延伸。也就是说，第一极311与衬底201平行设置，第二极312与衬底201平行设置。
第一极311和第二极312的材料均为导电材料，例如金属材料。示例性的，第一极311和第二极312的材料例如可以包括钨(W)、钛(Ti)、金(Au)、钼(Mo)、铝(Al)、铜(Cu)、钌(Ru)、银(Ag)、氮化钛(TiN)、氧化铟锡(In-Ti-O，ITO)等导电材料中的一种或多种的组合。第一极311的材料和第二极312的材料可以相同，也可以不不同。
第一极311和第二极312环绕沟道314设置。也就是说，第一极311和第二极312位于沟道314相对的两端。
第一极311和第二极312设置于沟道314的外围，也就是说，第一极311和第二极312包裹在沟道314的外围。
如图4B所示，沟道314沿与衬底201相垂直的方向z延伸，也就是说，沟道314沿第三方向z延伸。
沟道314的材料例如可以包括硅(Si)、多晶硅(poly-Si，p-Si)、非晶硅(amorphous-Si，a-Si)、铟镓锌氧化物(In-Ga-Zn-O，IGZO)多元化合物、氧化锌(ZnO)、二硫化钼(MoS2)、二硫化钨(WS2)等半导体材料中的一种或多种的组合。
关于晶体管310的栅极313，如图4A-图4C所示，沟道314环绕晶体管310的栅极313设置。也就是说，沟道314设置于栅极313的外围，即沟道314包裹在栅极313的外围。
栅极313也沿与衬底201相垂直的方向z延伸，也就是说，栅极313沿第三方向z延伸。
栅极313的材料为导电材料，例如金属材料。示例性的，栅极313的材料例如可以包括钨、钛、金、钼、铝、铜、钌、银、氮化钛、氧化铟锡等导电材料中的一种或多种的组合。
此处释明的是，第一极311、第二极312以及栅极313构成晶体管310的三个电极。第一极311和第二极312分别作为晶体管310的源极和漏极。
示例性的，第一极311为晶体管310的源极，第二极312为晶体管310的漏极。或者，示例性的，第一极311为晶体管310的漏极，第二极312为晶体管310的源极。本申请实施例对此不做限定，根据实际情况合理设置即可。
这时，晶体管310可以看作沟道环绕型(channel all around，CAA)晶体管。
在一些实施例中，如图4C所示，沟道314和栅极313之间还形成有栅氧化层315。由于栅极313环绕沟道314一圈设置，因此栅氧化层315也环绕沟道314一圈设置。
栅氧化层315的材料例如可以包括氮化硅(SiN)、氧化硅(SiOx)或者氧化铝(AlOx)等中的任意一种或者多种的组合。
在一些实施例中，如图4C所示，存储单元300还包括第一半导体层316和第二半导体层317。其中，第一半导体层316与第一极311接触，第一半导体层316位于第一极311靠近第二 极312一侧，且第一半导体层316环绕沟道314设置。第二半导体层317与第二极312接触，第二半导体层317位于第二极312靠近第一极311一侧，且第二半导体层317环绕沟道314设置。
第一半导体层316和第二半导体层317也沿与衬底201相垂直的方向z布设，也就是说，第一半导体层316和第二半导体层317沿第三方向z布设。
第一半导体层316和第二半导体层317还沿与衬底201平行的方向延伸，即第一半导体层316和第二半导体层317沿第一方向x和第二方向y组成的平面延伸。也就是说，第一半导体层316与衬底201平行设置，第二半导体层317与衬底201平行设置。
示例性的，第一半导体层316和第二半导体层317的材料可以包括重掺杂的多晶硅，掺杂物的类型为P型或者N型。掺杂物例如可以包括磷(P)、砷(As)、硼(B)、镓(Ga)等。例如，对多晶硅进行N型掺杂可以采用5价掺杂元素磷、砷等，对多晶硅进行P型掺杂可以采用3价掺杂元素硼、镓等。
此处释明的是，多晶硅材料的掺杂组分和浓度可以根据实际需要进行调节，以实现需要的性能。
第一半导体层316和第二半导体层317的作用是为了形成第一极311和第二极312。
关于电容器320，继续参考图4C，电容器320包括第一电容电极321、第二电容电极322以及电容层323。电容层323位于第一电容电极321和第二电容电极322之间。
如图4C所示，第一电容电极321、电容层323和第二电容电极322依次形成于晶体管310的第一极311上。
其中，电容器320与晶体管310电连接。示例性的，电容器320与晶体管310的第一极311或者第二极312电连接。例如，电容器320的第一电容电极321与晶体管310的第一极311电连接。
示例性的，电容器320的第一电容电极321形成于晶体管310的第一极311上。
其中，电容器320的第一电容电极321和晶体管310的第一极311可以分别形成。这时，电容器320的第一电容电极321与晶体管310的第一极311电连接。或者，还可以将晶体管310的第一极311作为电容器320的第一电容电极321。或者，还可以将电容器320的第一电容电极321作为将晶体管310的第一极311。
也就是说，晶体管310的第一极311与电容器320的第一电容电极321共用同一电极，
第一电容电极321和第二电容电极322的材料均为导电材料，例如金属材料。示例性的，第一电容电极321和第二电容电极322的材料例如可以包括钨、钛、金、钼、铝、铜、钌(Ru)、银、氮化钛、氧化铟锡等导电材料中的一种或多种的组合。第一电容电极321的材料与第二电容电极322的材料可以相同，也可以不同。
电容层323的材料包括铁电材料、绝缘材料、相变材料、阻变材料或者铁磁材料中的任意一种。
铁电材料例如可以包括氧化锆(ZrOx)、氧化铪(HfOx)、氧化锆铪(ZrHfOx)、Al掺杂HfO2、Si掺杂HfO2、Zr参杂HfO2、La掺杂HfO2、Y掺杂HfO2等铁电材料或者基于该材料的进行其他元素掺杂的材料中的一种或者多种。绝缘材料为高K介质层，绝缘材料例如可以包括氧化铝(Al2O3)、二氧化锆(ZrO2)、氧化钛(TiO2)、二氧化铪(HfO2)和氧化镧(La2O3)中的至少一种。相变材料例如可以包括硫系化合物薄膜或者多种硫系化合物薄膜的组合。阻变材料例如可以包括二元过渡金属氧化物(TMO)，例如：氧化铬(HfOx)和氧化钽(TaOx)等。铁磁材料例如可以包括铱锰(IrMn)、铂锰(PtMn)、铁锰(FeMn)、钌锰(RuMn)、镍锰(NiMn)和钯铂锰(PdPtMn)中的一种或者多种的组合。
其中，根据电容层323的材料不同，可对应不同的存储器。
示例性的，电容层323的材料为铁电材料，上述存储器可为铁电存储器。
或者，示例性的，电容层323的材料为绝缘材料，上述存储器可为动态随机存取存储器。
或者，示例性的，电容层323的材料为相变材料，上述存储器可为相变存储器。
或者，示例性的，电容层323的材料为阻变材料，上述存储器可为阻变存储器。
或者，示例性的，电容层323的材料为铁磁材料，上述存储器可为磁性随机存储器。
继续参考图4B，存储单元300中的电容器320和晶体管310沿着与衬底201相平行的方向布设。也就是说，电容器320和晶体管310沿第一方向x或者第二方向y布设，
或者说是，沿第一方向x或者第二方向y，电容器320形成于晶体管310的一侧。也就是说，电容器320形成于晶体管310的第一极311的侧壁上。
本申请实施例中，电容器320设置于晶体管310沿第一方向x或第二方向y的一侧，而不是设置于晶体管310沿第三方向z的一侧。这样一来，能够减小存储单元300的尺寸，实现存储单元300的微缩。
在一些实施例中，如图5A所示，电容层323包括第一部分301、第二部分302以及第三部分303。其中，第一部分301沿第三方向z延伸，第二部分302和第三部分303均沿第一方向x或者第二方向y延伸。
继续参考图5A，电容器320的第一电容电极321具有与第二电容电极322相对的第一侧面a1，电容器320的第二电容电极322具有与第一电容电极321相对的第二侧面a2。
电容器320的第一电容电极321还具有与第一侧面a1相邻的第一顶面b1和第一底面c1，电容器320的第二电容电极322还具有与第二侧面a2相邻的第二顶面b2和第二底面c2。
其中，电容层323的第一部分301与第一侧面a1和第二侧面a2均接触。也就是说，将位于第一电容电极321和第二电容电极322之间电容层323的部分作为电容层323的第一部分301。
关于第二部分302和第三部分303，示例性的，如图5A所示，第二部分302与第一顶面b1接触，第三部分303与第一底面c1接触。
或者，示例性的，如图5B所示，第二部分302与第二顶面b2接触，第三部分303与第二底面c2接触。
这时，图5A和图5B所示的电容层323成凹槽形。
或者，示例性的，如图5C所示，第二部分302与第一顶面b1接触，第三部分303与第二底面c2接触。
这时，图5C所示的电容层323成Z形。
或者，示例性的，如图5D所示，第二部分302与第一顶面b1和第一底面c1均接触，第三部分303与第二顶面b2和第二底面c2均接触。
这时，图5D所示的电容层323成工字形。
在另一些实施例中，如图6A所示，电容层323仅位于电容器320的第一电容电极321和第二电容电极322之间。也可以理解为，电容层323为上述第一部分301，没有上述第二部分302和上述第三部分303。
在一些实施例中，如图6A所示，电容层323与第一电容电极321、第二电容电极322的接触面为平面。也就是说，第一侧面a1和第二侧面a2为平面。
在另一些实施例中，如图6B所示，电容层323与第一电容电极321、第二电容电极322的接触面中至少一个为曲面。也就是说，第一侧面a1或第二侧面a2中至少一个为曲面。
例如，第一侧面a1和第二侧面a2可以均为曲面。或者，第一侧面a1为曲面，第二侧面a2为平面。或者，第一侧面a1为平面，第二侧面a2为曲面。
这样一来，能够增大电容层323的第一部分301的面积，进而增大电容器320的存储容量。
其中，第一侧面a1或第二侧面a2也可以是其他不规则的面。例如，波浪形、锯齿形等。本申请实施例对此不做限定。
继续参考图4A，多个存储单元300沿第一方向x和第二方向y排布，构成存储层202。多个存储层202沿第三方向z层叠设置，构成三维存储阵列210。
其中，同一存储层202中，相邻的存储单元300的第二电容电极322连接。相邻的存储单元300之间还填充有用于绝缘的介质层400。
如图4A所示，三维存储阵列210还包括字线WL、位线BL以及板线PL。
三维存储阵列210中所有存储单元300的第二电容电极322均与板线PL电连接。对于同一存储层202中，所有存储单元300的第二电容电极322连接构成该存储层202的板线PL，且板线PL沿与衬底201相平行的方向(第一方向x或第二方向y)延伸。也就是说，板线PL所在平 面与衬底201平行。不同存储层202之间的板线PL还存在电连接。
三维存储阵列210中所有存储单元300的栅极313均与字线WL电连接。字线WL沿与衬底相垂直的方向z(第三方向z)延伸。也就是说，沿与衬底相垂直的方向z(第三方向z)，通过字线WL将每一个存储单元300的栅极313连接。
三维存储阵列210中所有存储单元300的第二极312均与位线BL电连接。对于同一存储层202中，所有存储单元300的第二极连接构成该存储层202的位线BL，且位线沿与衬底201相平行的方向延伸。也就是说，位线BL所在平面与衬底201平行。
本申请实施例一提供的三维存储阵列210，包括衬底201以及形成在衬底201上的多个存储层202。多个存储层202沿着与衬底201相垂直的方向z堆叠。存储层202包括多个存储单元300。存储单元300包括电连接的电容器320和晶体管310。其中，晶体管310包括栅极313、沟道314以及沿与衬底201相垂直的方向布设、且环绕沟道314设置的第一极311和第二极312。电容器320包括第一电容电极321、第二电容电极322以及设置于第一电容电极321和第二电容电极322之间的电容层323，第一电容电极321与第一极311电连接。本申请实施例一提供的方案，包括多个存储单元300的多个存储层202沿与衬底201相垂直的方向堆叠，使存储单元300的形成无需依赖衬底201，因此该存储单元300可以采用后道工艺制备，能够实现在沿衬底201垂直方向上的多层堆叠，实现三维方向上的堆叠，进而提高三维存储阵列210的存储密度，提高三维存储阵列210的存储容量。
另外，本申请实施例中可以通过改变电容层323与第一电容电极321、第二电容电极322的接触面面积，以提高读写窗口。
本申请还提供了上述存储器的制备方法，下面，以具体的示例对本申请实施例提供的存储器及其制备方法进行示意说明。
本申请实施例提供一种三维存储阵列的制备方法，三维存储阵列210包括衬底201以及沿着与衬底201相垂直的方向z堆叠于衬底201上的多个存储层202。存储层202包括多个存储单元300，存储单元300的制备方法包括：
在一些实施例中，如图7所示，三维存储阵列210的制备方法包括：
S11、如图8A所示，在衬底201上形成介质层400。
示例性的，在衬底201上形成多层绝缘材料，构成介质层400，例如，在衬底201上依次形成第一介质层401、第二介质层402、第三介质层403以及第四介质层，以构成介质层400。
其中，第一介质层401的材料、第二介质层402的材料、第三介质层403的材料以及第四介质层404的材料均不同，以使后续形成晶体管310和电容器320时可以对不同介质层进行选择性刻蚀。不同介质层的厚度可以相同，也可以不同。本申请实施例对此不做限定，根据后续形成不同结构的尺寸合理设置即可。
本申请实施例中，在一个介质层400中后续形成一个上述存储层202。本申请实施例中对形成介质层400的数量不做限定，根据实际情况合理设置即可。以下以在衬底201上形成两个介质层400进行示意说明。
此处释明的是，以下为了方便示意，附图中均不示意出衬底201。
S12、如图8B所示，形成贯穿介质层400的过孔410。
如图8B所示，过孔410沿与衬底201相垂直的方向z延伸。示例性的，可以通过深孔刻蚀工艺形成过孔410。
此处释明的是，过孔410贯穿所有的介质层400。
S13、形成第一极311、第二极312以及电容层323。
示例性的，步骤S13包括：
S131、如图8C所示，形成第二极312。
示例性的，刻蚀过孔410侧壁的第三介质层403，然后填充金属，形成第二极312。
S132、如图8D所示，形成电容层323和第一极311。
示例性的，刻蚀过孔410侧壁的第一介质层401，然后填充电容层材料和氧化物材料，接着回刻氧化物，最后填充剂金属材料，以形成电容层323和第一极311。
第一极311和第二极312之间间隔有第二介质层402，因此第一极311和第二极312沿与衬底201相垂直的方向z布设。
S14、如图8E所示，形成半导体层。
示例性的，刻蚀过孔410侧壁的第二介质层402，然后填充重掺杂的多晶硅材料，形成半导体层。
其中，半导体层覆盖刻蚀后的第二介质层402的侧壁，以及第一介质层401和第三介质层403相对的两个表面。
然后，在半导体层围成的区域填充介质层材料，填充的介质层材料可以与第二介质层402的材料相同。上述介质层材料用于隔离后续形成的第一半导体层316和第二半导体层317。
此处释明的是，为了避免后续工艺过程中电容层323和第一极311被损坏，步骤S14不去除形成于刻蚀后的第二介质层402侧壁上的半导体层材料。
S15、如图8F所示，在过孔410内形成沟道314和栅极313。
示例性的，在过孔内410依次形成沟道314、栅氧化层315以及栅极313。例如，先在过孔内410填充沟道314的材料，接着刻蚀该材料，形成贯穿的第二过孔，第二过孔的侧壁为沟道314。然后，在第二过孔内填充氧化材料，接着刻蚀该氧化材料，形成贯穿的第三过孔和位于第三过孔侧壁的栅氧化层315。最后在第三过孔内形成栅极313。
S16、如图8G所示，形成晶体管310。
去除第四介质层404侧壁的沟道314材料，以断开相邻存储层202(介质层400)之间的沟道314。去除第二介质层402侧壁的半导体层的材料，以断形成第一半导体层316和第二半导体层317。这样一来，形成晶体管310。
S17、如图8H所示，形成第二电容电极322，以形成电容器320。
示例性的，刻蚀第一介质层401，并填充金属材料，以在电容层323远离第一极311的一侧形成第二电容电极322，以形成电容器320。
其中，电容器320的第一电容电极321与晶体管310的第一极311共用同一电极。
在一些实施例中，三维存储阵列210的制备方法还包括：形成字线WL、位线BL以及板线PL。
示例性的，电连接多个存储单元300的栅极，以形成字线WL。电连接多个存储单元300的第二极312，以形成位线BL。电连接多个存储单元300的第二电容电极322，以形成板线PL。
此处释明的是，在步骤S15中，形成栅极313时，还同时形成电连接栅极313的字线WL。在步骤S13中，形成第二极312时，还同时形成电连接第二极312的位线BL。在步骤S17中，形成第二电容电极322时，还同时形成电连接第二电容电极322的板线PL。
本申请实施例一提供的上述制备方法，并不做任何步骤顺序的限制，可以根据需要合理调整。
此外，上述S11-S17的步骤，可以根据需要去除其中的某些步骤，并不限定为每个步骤都必须包含。也可以根据需要增加某些步骤，不限定为仅包含上述步骤。
本申请实施例一提供的三维存储阵列210的制备方法，包括衬底201以及形成在衬底201上的多个存储层202。多个存储层202沿着与衬底201相垂直的方向z堆叠。存储层202包括多个存储单元300。形成方法包括：在衬底201上形成介质层400，并形成沿与衬底201相垂直方向延伸、贯穿介质层400的过孔410。然后，在过孔410侧壁的介质层400内形成电容层323和第一极311、以及与第一极311间隔的第二极312。接着，在过孔410内形成沟道314和栅极313，以形成晶体管310。最后，在电容层323远离第一极311的一侧形成第二电容电极322，以形成电容器320。本申请实施例中，存储单元300的形成不依赖于衬底201，即存储单元300可以采用后道工艺制备，能够实现在沿衬底201垂直方向上的多层堆叠，实现存储单元300在三维方向上的堆叠，提高三维存储阵列210的存储密度，提高三维存储阵列210的存储容量。多个存储层202中的存储单元300可以同时形成，制备成本低。另外，本申请实施例提供的制备方法中形成晶体管310的第一极311和第二极312，以及晶体管310的沟道314分步骤形成，能够更容易控制各个结构的形成形貌，有利于改善晶体管310的一致性。
另外，本申请实施例中的三维存储阵列210，还可以将每个存储层202的板线PL同时引出，不会增加额外的台阶工艺步骤。
此外，本申请实施例中可以通过改变电容层323与第一电容电极321、第二电容电极322的接触面面积，以提高读写窗口。
实施例二
实施例二与实施例一的主要不同之处在于：晶体管310不同。
如图9A和图9B所示，晶体管310的栅极313沿与衬底201相平行的方向(第一方向x和第二方向y组成的平面)环绕沟道314设置，且栅极313位于第一极311和第二极312之间。也就是说，第一极311、栅极313以及第二极312沿与衬底201相垂直的方向z布设。
这时，晶体管310可以看作为栅极环绕型(gate all around，GAA)晶体管。
在一些实施例中，如图9C所示，存储单元300还包括第一半导体层316和第二半导体层317。第一半导体层316位于第一极311和沟道314之间，且环绕沟道314设置。第二半导体层317位于第二极312和沟道314之间，且环绕沟道314设置。
在一些实施例中，如图9C所示，存储单元300还包括栅氧化层315。栅氧化层315位于栅极313和沟道314之间，且环绕沟道314设置。
同一存储层202中，字线WL沿与衬底201相平行的方向延伸。也就是说，字线WL所在平面与衬底201平行。位线BL也沿与衬底201相平行的方向延伸，且字线WL与位线BL的引出方向相交，例如，字线WL与位线BL的引出方向垂直。
本申请实施例二还提供一种三维存储阵列的制备方法，如图10所示，包括：
S21、如图11A所示，在衬底201上形成介质层400。
与实施例一不同在于，实施例二中在衬底201上依次形成第一介质层401、第二介质层402、第三介质层403、第四介质层404、第五介质层405以及第六介质层406，以构成介质层400。
其中，第二介质层402的厚度和第四介质层404的厚度均小于其余介质层的厚度。
S22、如图11B所示，形成贯穿介质层400的过孔410。
步骤S22与上述步骤S12相同，可参考上述关于S12的相关描述。
S23、如图11C所示，形成第一极311、第二极312、栅极313以及电容层323。
示例性的，在第一介质层401内形成电容层323和第一极311，在第三介质层403内形成栅极313，在第五介质层405内形成第二极312。
形成第一极311、第二极312以及电容层323的方法与实施例一中的形成方法相同，可参考实施例一中的相关描述。
形成栅极313的方法与实施例一中的形成方法相同，可参考实施例一中的相关描述。
在一些实施例中，还形成位于栅极313一侧的栅氧化层315、位于第一极311和第二极312一侧的第一半导体层316和第二半导体层317。
S24、如图11D所示，在过孔410内形成沟道314，以形成晶体管310。
示例性的，在过孔内410填充沟道314的材料以及绝缘材料，并去除第六介质层406侧壁的沟道314材料，形成晶体管310。
S25、如图11E所示，形成第二电容电极322，以形成电容器320。
步骤S25与上述步骤S17相同，可参考上述关于S17的相关描述。
本申请实施例二提供的上述制备方法，并不做任何步骤顺序的限制，可以根据需要合理调整。
此外，上述S21-S25的步骤，可以根据需要去除其中的某些步骤，并不限定为每个步骤都必须包含。也可以根据需要增加某些步骤，不限定为仅包含上述步骤。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种三维存储阵列，其特征在于，包括：
    衬底；
    形成在所述衬底上的多个存储层，所述多个存储层沿与所述衬底相垂直的方向堆叠；
    每一个所述存储层包括多个存储单元；
    每一个所述存储单元包括电连接的电容器和晶体管；所述电容器形成于所述晶体管一侧；
    其中，所述晶体管包括第一极、第二极、栅极和沟道，所述沟道沿与所述衬底相垂直的方向延伸，所述第一极和所述第二极沿与所述衬底相垂直的方向布设，且所述第一极和所述第二极环绕所述沟道设置；
    所述电容器包括第一电容电极、第二电容电极以及设置于所述第一电容电极和所述第二电容电极之间的电容层；所述第一电容电极与所述第一极电连接。
  2. 根据权利要求1所述的三维存储阵列，其特征在于，所述存储单元中的所述电容器和所述晶体管沿着与所述衬底相平行的方向布设。
  3. 根据权利要求1或2所述的三维存储阵列，其特征在于，所述第一极与所述第一电容电极共用同一电极。
  4. 根据权利要求1-3任一项所述的三维存储阵列，其特征在于，所述栅极和所述沟道均沿与所述衬底相垂直的方向延伸，且所述沟道环绕所述栅极设置。
  5. 根据权利要求1-3任一项所述的三维存储阵列，其特征在于，所述栅极沿与所述衬底相平行的方向环绕所述沟道设置，且所述栅极位于所述第一极和所述第二极之间。
  6. 根据权利要求1-5任一项所述的三维存储阵列，其特征在于，所述三维存储阵列还包括字线、位线以及板线；所述栅极均与所述字线电连接，所述第二极均与所述位线电连接，所述第二电容电极均与所述板线电连接；所述字线沿与所述衬底相垂直的方向延伸；同一所述存储层中，所述板线沿与所述衬底相平行的方向延伸，所述位线沿与所述衬底相平行的方向延伸。
  7. 根据权利要求1-6任一项所述的三维存储阵列，其特征在于，所述存储单元还包括第一半导体层和第二半导体层；所述第一半导体层连接所述第一极和所述沟道；所述第二半导体层连接所述第二极和所述沟道。
  8. 根据权利要求1-7任一项所述的三维存储阵列，其特征在于，所述电容层包括沿与所述衬底相垂直的方向延伸的第一部分，以及沿与所述衬底相平行的方向延伸的第二部分和第三部分；
    所述第一电容电极具有与所述第二电容电极相对的第一侧面，所述第二电容电极具有与所述第一电容电极相对的第二侧面；所述第一部分与所述第一侧面和所述第二侧面均接触。
  9. 根据权利要求8所述的三维存储阵列，其特征在于，所述第一电容电极还具有与所述第一侧面相邻的第一顶面和第一底面，所述第二电容电极还具有与所述第二侧面相邻的第二顶面和第二底面；
    所述第二部分与所述第一顶面接触，所述第三部分与所述第一底面接触；
    或，
    所述第二部分与所述第二顶面接触，所述第三部分与所述第二底面接触；
    或，
    所述第二部分与所述第一顶面接触，所述第三部分与所述第二底面接触；
    或，
    所述第二部分与所述第一顶面和所述第一顶面均接触，所述第三部分与所述第二顶面和所述第二底面均接触。
  10. 根据权利要求8或9所述的三维存储阵列，其特征在于，所述第一侧面或所述第二侧面中至少一个为曲面。
  11. 根据权利要求1-10任一项所述的三维存储阵列，其特征在于，同一所述存储层中，相邻的所述存储单元的所述第二电容电极连接。
  12. 根据权利要求1-11任一项所述的三维存储阵列，其特征在于，所述电容层的材料包括铁电材料、绝缘材料、相变材料、阻变材料或者铁磁材料中的任意一种。
  13. 一种三维存储阵列的制备方法，其特征在于，所述三维存储阵列包括衬底以及多个存储层，所述多个存储层沿着与所述衬底相垂直的方向堆叠于所述衬底上；所述存储层包括多个存储单元；
    所述存储单元的制备方法包括：
    在所述衬底上形成介质层；
    形成贯穿所述介质层的过孔，所述过孔沿与所述衬底相垂直的方向延伸；
    在所述过孔侧壁的所述介质层内形成电容层和第一极，以及形成与所述第一极具有间隔的第二极；所述第一极和所述第二极均沿与所述衬底相平行的方向延伸；
    在所述过孔内形成沟道和栅极，以形成晶体管；
    在所述电容层远离所述第一极的一侧形成第二电容电极，以形成电容器。
  14. 根据权利要求13所述的三维存储阵列的制备方法，其特征在于，在形成所述沟道和所述栅极之前，所述制备方法还包括：
    在所述过孔侧壁的所述介质层内形成第一半导体层和第二半导体层。
  15. 根据权利要求13或14所述的三维存储阵列的制备方法，其特征在于，所述制备方法还包括：
    形成字线、位线以及板线；所述字线与所述栅极电连接，所述位线与所述第二极电连接，所述板线与所述第二电容电极电连接。
  16. 一种三维存储阵列的制备方法，其特征在于，所述存储器包括衬底以及多个存储层，所述多个存储层沿着与所述衬底相垂直的方向堆叠于所述衬底上；所述存储层包括多个存储单元；
    所述存储单元的制备方法包括：
    在所述衬底上形成介质层；
    形成贯穿所述介质层的过孔，所述过孔沿与所述衬底相垂直的方向延伸；
    在所述过孔侧壁的所述介质层内形成电容层和第一极，以及形成与所述第一极具有间隔的栅极和第二极；所述第一极、所述栅极以及所述第二极均沿与所述衬底相平行的方向延伸；
    在所述过孔内形成沟道，以形成晶体管；
    在所述电容层远离所述第一极的一侧形成第二电容电极，以形成电容。
  17. 一种存储器，其特征在于，包括：
    控制器以及如权利要求1-12任一项所述的三维存储阵列，所述控制器与所述三维存储阵列电连接。
  18. 一种电子设备，其特征在于，包括：
    电路板以及如权利要求17所述的存储器，所述电路板与所述存储器电连接。
PCT/CN2023/133330 2023-02-07 2023-11-22 三维存储阵列及其制备方法、存储器、电子设备 WO2024164632A1 (zh)

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