WO2024060021A1 - 一种三维存储阵列、存储器及电子设备 - Google Patents

一种三维存储阵列、存储器及电子设备 Download PDF

Info

Publication number
WO2024060021A1
WO2024060021A1 PCT/CN2022/119960 CN2022119960W WO2024060021A1 WO 2024060021 A1 WO2024060021 A1 WO 2024060021A1 CN 2022119960 W CN2022119960 W CN 2022119960W WO 2024060021 A1 WO2024060021 A1 WO 2024060021A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
electrode
capacitor
substrate
memory
Prior art date
Application number
PCT/CN2022/119960
Other languages
English (en)
French (fr)
Inventor
景蔚亮
孙莹
黄凯亮
王正波
廖恒
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2022/119960 priority Critical patent/WO2024060021A1/zh
Publication of WO2024060021A1 publication Critical patent/WO2024060021A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components

Definitions

  • the present application relates to the field of semiconductor memory technology, and in particular to a three-dimensional memory array, a memory including the three-dimensional memory array, a method for forming the three-dimensional memory array, and an electronic device including the memory.
  • DRAM dynamic random access memory
  • CPU central processing unit
  • the read and write speed of the memory has been continuously improved.
  • the storage density of the memory has also continued to increase to meet people's needs for data processing in the information age.
  • 1T1C memory cells As memory develops toward higher density and larger bandwidth, many types of memory cells have been developed, such as 1T1C memory cells or 1TnC memory cells, where T stands for transistor and C stands for capacitor.
  • Figure 1 shows a process structure diagram of a planar 1T1C memory cell.
  • the source and drain are formed by doping in the substrate, and the gate and capacitor are formed on the substrate, and Word line (WL), bit line (BL) and plate line (PL) electrode lines.
  • WL Word line
  • BL bit line
  • PL plate line
  • the gate is electrically connected to the word line WL
  • the drain is electrically connected to the bit line BL
  • the source is electrically connected to the plate line PL through a capacitor.
  • the planar memory unit shown in Figure 1 occupies a large area, which limits the improvement of storage density.
  • the projected area of the capacitor on the substrate is getting smaller and smaller.
  • the capacitor needs to be made higher (such as the size along the P direction as shown in Figure 1 getting bigger).
  • the 2D memory unit shown in Figure 1 will encounter physical size limits if it is scaled below 10nm.
  • the present application provides a three-dimensional storage array, a memory including the three-dimensional storage array, a method for forming the three-dimensional storage array, and an electronic device including the memory.
  • the main purpose is to provide a three-dimensional memory array structure that can not only increase storage density, but also pose no major challenges to the process.
  • this application provides a three-dimensional storage array.
  • the three-dimensional storage array can be used in dynamic random access memory (dynamic random access memory, DRAM).
  • DRAM dynamic random access memory
  • the three-dimensional storage array includes a substrate and multiple storage layers formed on the substrate.
  • the multiple storage layers are stacked along a direction perpendicular to the substrate to form a three-dimensional stacked storage structure.
  • Each storage layer includes multiple storage layers.
  • Each memory unit includes a transistor and a capacitor electrically connected to the transistor.
  • the memory unit may be a 1T1C memory unit.
  • the transistor includes a first electrode, a second electrode, a gate electrode and a channel layer; the capacitor includes a first capacitor electrode, a capacitor layer and a second capacitor electrode; the first electrode of the transistor is electrically connected to the first capacitor electrode; each storage layer includes A first metal layer and a second metal layer stacked in a direction perpendicular to the substrate, the first metal layer and the second metal layer are electrically isolated by a dielectric layer; the first electrode of the transistor and the capacitor are formed on the first metal layer , the second electrode of the transistor is formed in the second metal layer; at least part of the gate electrode and at least part of the channel layer are formed in the dielectric layer, and the channel layer surrounds the periphery of the gate electrode; the first capacitor electrode, the capacitor layer and the second capacitor electrode are stacked in a direction parallel to the substrate, the capacitor layer surrounds the periphery of the first capacitor electrode, and the second capacitor electrode may surround the periphery of the capacitor layer.
  • the memory cell provided in the present application may be a 1T1C memory cell.
  • the first electrode and the second electrode electrically connected to the channel layer are stacked in the corresponding first metal layer and the second metal layer in a direction perpendicular to the substrate, and the channel layer surrounds the periphery of the gate, that is, the transistor is a field effect transistor with a ring channel structure.
  • the capacitor layer surrounds the periphery of the first capacitor electrode, that is, the capacitor is a ring capacitor structure.
  • the present application reduces the size of the memory cell, so that more memory cells can be integrated on a unit area parallel to the substrate, so that the integration density of the three-dimensional memory array is higher.
  • the stacked first metal layer, dielectric layer and second metal layer are used to realize the integration of transistors and capacitors.
  • this application can reduce the number of metal layers laid out and achieve 3D stacking of more storage layers to increase the storage density of the memory.
  • the capacitor belongs to a ring capacitor structure.
  • the ring capacitor structure can increase the storage capacity without giving any problems.
  • the etching process poses greater challenges, thus making the memory array a high-density, large-storage, and low-cost memory array.
  • multiple layers of dielectric layers can be stacked first, and then processed on the stacked dielectric layer structures, and multiple layers of storage layers can be processed simultaneously.
  • two layers of storage layers can be produced at the same time. That is to say, the multi-layer storage layers of this application can be processed at the same time, that is, a multi-layer device can be formed at one time without the need to produce it first.
  • the first layer of storage layer is then used to manufacture the second layer of storage layer, the third layer of storage layer, etc. layer by layer using the same process.
  • the process flow can be simplified and manufacturing costs can be reduced.
  • the process complexity and manufacturing costs will be significantly reduced.
  • it can also avoid the The memory layer is produced layer by layer, resulting in poor alignment accuracy of the memory cells.
  • one end of the gate extends into the first metal layer, the first electrode surrounds the periphery of the gate and is electrically isolated from the gate through the gate dielectric layer; the other end of the gate extends to In the second metal layer, the second electrode surrounds the periphery of the gate electrode and is electrically isolated from the gate electrode through the gate dielectric layer.
  • a through hole can be penetrated in a multi-layer stacked dielectric layer, and a columnar gate structure can be formed in the through hole.
  • one end of the channel layer extends into the second metal layer, and the second pole surrounds the periphery of the channel layer.
  • the channel layer surrounding the gate electrode extends into the metal layer where the second electrode is located, so that the second electrode surrounds the channel, this increases the contact area between the second electrode and the channel layer, achieving a larger area. electrical contact, inhibiting the increase in leakage current and lower electron mobility.
  • the other end of the channel layer extends into the first metal layer; the first electrode and the first capacitor electrode share the same electrode; and the first capacitor electrode surrounds the periphery of the channel layer.
  • the channel layer can also extend into the metal layer where the first electrode of the transistor is located, and the first electrode is surrounded by the outer periphery of the channel layer. Similarly, a larger area of electrical contact between the channel and the electrode is achieved, which suppresses the increase of leakage current and lowers the electron mobility.
  • first electrode of the transistor and the first capacitor electrode of the capacitor share the same electrode, which can simplify the process structure of the memory cell.
  • the channel layer located in the dielectric layer includes a surrounding channel and a first planar channel connected to the surrounding channel.
  • the first planar channel is parallel to the substrate; the surrounding channel surrounds the gate.
  • the periphery of the pole; the surface of the second pole facing the first pole is in contact with the first planar channel.
  • the channel layer not only includes a surrounding channel surrounding the gate electrode, but also includes a planar channel parallel to the substrate, the contact area with the second electrode is increased.
  • the channel layer located in the dielectric layer also includes a second planar channel parallel to the substrate and opposite to the first planar channel, the first planar channel and the second planar channel Connected by a surrounding channel; the second planar channel is in contact with the first pole.
  • the channel layer also includes a second planar channel in ohmic contact with the first pole to increase the ohmic relationship between the channel layer and the first pole of the transistor. Contact area.
  • the first capacitance electrode includes a surrounding electrode surrounding the gate electrode, and a planar electrode connected to the surrounding electrode and arranged parallel to the substrate, so that the first capacitance electrode is formed in contact with the substrate.
  • a capacitive layer is formed on both the horizontal contact surface and the vertical contact surface.
  • the capacitor area of the capacitor layer can be increased to increase the capacitor capacity, thereby improving the The storage performance of this storage unit.
  • the planar electrode includes a first planar electrode and a second planar electrode arranged oppositely, and the first planar electrode and the second planar electrode are connected through a surrounding electrode, so that a capacitor with an opening is formed in the first capacitor electrode.
  • the groove has an opening facing away from the gate, and the capacitor layer and the second capacitor electrode are sequentially disposed on the inner wall of the groove to form a capacitor layer having a first notch and the first notch facing away from the gate.
  • the capacitive area of the capacitive layer is increased by designing the planar electrode to include a first planar electrode and a second planar electrode.
  • each storage layer further includes a first electrode line, the second capacitance electrode of the capacitor is electrically connected to the first electrode line; the first electrode line extends in a direction perpendicular to the substrate, and the An electrode line is disposed close to the first notch; in the plurality of storage layers, the second capacitance electrodes of the plurality of capacitors arranged perpendicularly to the substrate are electrically connected to the same first electrode line.
  • the first capacitor electrode includes a first planar electrode and a second planar electrode
  • the second capacitor electrode in the capacitor is far away from the gate of the transistor.
  • the first electrode line (such as a PL line) electrically connected to the second capacitor electrode of the capacitor can be extended in a direction perpendicular to the substrate to electrically connect the second capacitor electrodes of multiple capacitors arranged perpendicular to the substrate.
  • the planar electrode has a plate-like structure and is connected to the surrounding electrode to form a capacitor layer with a second gap and the second gap faces the gate electrode, and the second capacitor electrode is disposed on the capacitor layer away from the third gap. on the surface of a capacitor electrode.
  • each storage layer further includes a first electrode line, and the second capacitance electrode of the capacitor is electrically connected to the first electrode line; the first electrode line has a plate-like structure and is arranged parallel to the substrate. , and the first electrode line is arranged away from the second gap; in each storage layer, the second capacitance electrodes of multiple capacitors are electrically connected to the same first electrode line.
  • the first electrode line (such as the PL line) can be designed in a plate shape to electrically connect the second capacitance electrodes of all capacitors in a storage layer.
  • each storage layer further includes a second electrode line and a third electrode line; the gate electrode of the transistor is electrically connected to the second electrode line; and the second electrode of the transistor is electrically connected to the third electrode line.
  • the second electrode line is the word line WL
  • the third electrode line is the bit line BL.
  • the second electrode line extends in a direction perpendicular to the substrate; in multiple storage layers, the gates of multiple transistors arranged perpendicular to the substrate are connected to the same second electrode line. Electrical connection.
  • the third electrode line extends in a direction parallel to the substrate; in each storage layer, the second electrodes of multiple transistors arranged parallel to the substrate and the same third electrode Wire connection.
  • the second electrode line and the third electrode line can both have a strip structure and can be perpendicular to each other.
  • the second electrode line is electrically connected to the gates of a plurality of transistors arranged perpendicularly to the substrate, and the third electrode line is electrically connected to the substrate. Connect the second electrodes of a plurality of transistors arranged parallel to the substrate.
  • the first metal layer is disposed close to the substrate, and the second metal layer is disposed far away from the substrate.
  • the capacitor is placed close to the substrate, and the transistor is placed far away from the substrate.
  • the first metal layer is disposed far away from the substrate, and the second metal layer can be disposed close to the substrate. That is, the capacitor is placed far away from the substrate, and the transistor is placed close to the substrate.
  • the memory array is a DRAM memory array, or the memory array is a ferroelectric memory array.
  • the plurality of storage layers are formed on the substrate using a back-end process.
  • the transistors and capacitors in the memory unit are manufactured using back-end processes, while the controller can be manufactured through front-end processes.
  • the controller may include one or more circuits of a decoder, a driver, a timing controller, a buffer, or an input-output driver, and may also include other functional circuits.
  • the controller can control the first electrode line, the second electrode line and the third electrode line in the embodiment of the present application.
  • the interconnection lines and the memory array are all manufactured through the back-end process BEOL. It can make the circuit density per unit area greater, thereby improving the storage performance per unit area.
  • this application also provides a memory, which includes a controller and a storage array in any of the above implementations.
  • the controller is electrically connected to the storage array, and the controller is used to control reading and writing of the storage array.
  • the memory array in the above-mentioned implementation method since the memory array in the above-mentioned implementation method is included, in the memory array, transistors and capacitors are arranged in a direction parallel to the substrate. In this way, the memory cells of this structure can be stacked in a direction perpendicular to the substrate and in a direction parallel to the substrate to achieve three-dimensional stacking, high-density integration, and improved storage capacity.
  • the storage array and the controller are integrated into the same chip, and the chip is disposed on the substrate.
  • the storage array is integrated in the first chip
  • the controller is integrated in the second chip
  • both the first chip and the second chip are disposed on the substrate through electrical connection structures.
  • the storage array is integrated in a first chip
  • the controller is integrated in a second chip
  • the first chip is stacked with the second chip, and integrated on the substrate.
  • this application also provides an electronic device, including a processor and a memory in any of the above implementations.
  • the processor is electrically connected to the memory, and the memory is used to store data generated by the processor.
  • the electronic device provided by the embodiment of the present application includes the memory in any of the above implementations. Therefore, the electronic device provided by the embodiment of the present application and the memory of the above technical solution can solve the same technical problem and achieve the same expected effect.
  • the present application also provides a method for forming a memory array.
  • the forming method includes:
  • a multi-layer dielectric layer is stacked on the substrate.
  • the multi-layer dielectric layer includes a plurality of groups of functional dielectric layers and an electrically isolated dielectric layer located between two adjacent groups of functional dielectric layers.
  • Each group of functional dielectric layers includes a first layer stacked in sequence.
  • Each storage layer includes a first metal layer patterned with a first functional dielectric layer, and a third functional dielectric layer patterned with a metal layer. a second metal layer, and a second functional dielectric layer located between the first metal layer and the second metal layer, each storage layer including a plurality of storage units, each storage unit including a transistor and a capacitor;
  • the transistor includes a first electrode, a second electrode, a gate electrode and a channel layer;
  • the capacitor includes a first capacitor electrode, a capacitor layer and a second capacitor electrode; the first electrode of the transistor and the capacitor are formed in the first metal layer, and the transistor
  • the second electrode is formed in the second metal layer; at least part of the gate electrode and at least part of the channel layer are formed in the second functional dielectric layer, and the channel layer surrounds the periphery of the gate electrode; the first capacitor electrode, the capacitor layer and the second capacitor electrode are stacked in a direction parallel to the substrate, and the capacitor layer surrounds the periphery of the first capacitor electrode.
  • multiple dielectric layers are stacked on a substrate, and some of the dielectric layers are patterned into storage layers, thereby forming multi-layer storage layers arranged perpendicularly to the substrate.
  • seven dielectric layers can be stacked first.
  • the dielectric layer located in the middle layer among the seven dielectric layers serves as an electrically isolated dielectric layer.
  • the three layers above it and the three layers below it can respectively form a storage layer. layer.
  • multiple storage layers can be formed at the same time, instead of stacking one storage layer and then stacking another storage layer. In this way, not only can the preparation process be simplified, but also This avoids the problem of difficult alignment process caused by multi-layer stacking.
  • the channel of the transistor is a ring channel structure
  • the capacitance of the capacitor is a ring capacitance structure, so that the area occupied by the memory cell of this structure is close to 4F. 2.
  • the size of the memory unit is reduced.
  • the capacitor belongs to a ring capacitor structure, compared with the columnar capacitor extending in a direction perpendicular to the substrate in related technologies, the ring capacitor structure does not require any suggestions for the etching process on the basis of increasing the storage capacity. Therefore, the storage array is a high-density, large-storage, and low-cost storage array.
  • forming the gate includes: opening a first through hole through the multi-layer dielectric layer in a direction perpendicular to the substrate, and filling the first through hole with conductive material to form a transistor. gate.
  • this formation method can be used to produce a columnar gate perpendicular to the substrate.
  • the forming method further includes: filling the first through hole with a semiconductor material to A channel layer of the transistor is formed on the inner wall surface of the first through hole.
  • a ring-gate channel structure can be formed.
  • the channel layer of this structure can also increase the contact area with the source and drain of the transistor to avoid the short channel effect.
  • forming the first capacitance electrode, the capacitance layer and the second capacitance electrode of the capacitor includes: filling the first through hole with conductive material, and before forming the gate electrode, opening a hole in the first functional dielectric layer.
  • a first groove, the opening of the first groove faces the first through hole, and a first capacitor electrode, a capacitor layer and a second capacitor electrode are formed in the first groove to form a capacitor with a notch and the notch faces the first through hole. layer.
  • the formed capacitor layer includes not only a portion perpendicular to the substrate, but also a portion parallel to the substrate, thereby increasing the capacitance of the capacitor.
  • forming the first capacitance electrode, the capacitance layer and the second capacitance electrode of the capacitor includes:
  • a second through hole is opened through the multi-layer dielectric layer in a direction perpendicular to the substrate;
  • a second groove is opened in the first functional dielectric layer, the opening of the second groove faces the second through hole, the bottom surface of the second groove penetrates to the first through hole, and a first capacitor electrode is formed in the second groove. the capacitor layer and the second capacitor electrode to form a capacitor layer with a gap, and the gap is away from the first through hole.
  • the capacitor layer formed in this way includes not only a portion perpendicular to the substrate, but also a portion parallel to the substrate, so as to increase the capacitance of the capacitor.
  • the forming method further includes:
  • a third groove is formed in the second functional medium layer, the opening of the third groove faces the second through hole, and a semiconductor material is filled in the third groove to form a channel layer of the transistor on the inner wall surface of the third groove.
  • the formed channel layer not only includes a surrounding portion surrounding the periphery of the gate electrode, but also includes a planar portion parallel to the substrate to increase the contact area with the source and drain of the transistor.
  • Figure 1 is a process structure diagram of a 1T1C memory cell in the prior art
  • Figure 2 is a circuit diagram of an electronic device provided by an embodiment of the present application.
  • Figure 3 is a circuit diagram of a memory provided by an embodiment of the present application.
  • Figure 4a is a package structure diagram of a storage array and a controller provided by an embodiment of the present application
  • FIG4b is a packaging structure diagram of a storage array and a controller provided in an embodiment of the present application.
  • Figure 4c is a package structure diagram of a storage array and controller provided by an embodiment of the present application.
  • Figure 5 is a schematic three-dimensional structural diagram of a memory provided by an embodiment of the present application.
  • Figure 6 is a simple circuit diagram of a memory provided by an embodiment of the present application.
  • Figure 7 is a circuit diagram of a storage unit in a memory provided by an embodiment of the present application.
  • Figure 8 is a circuit diagram of a memory array provided by an embodiment of the present application.
  • Figure 9 is a simple structural diagram of a storage array provided by an embodiment of the present application.
  • Figure 10 is a three-dimensional process structure diagram of a memory array provided by an embodiment of the present application.
  • Figure 11 is a three-dimensional process structure diagram of a memory array provided by an embodiment of the present application.
  • Figure 12 is an enlarged view of point A in Figure 11;
  • Figure 13 is a projection structural diagram of multiple memory cells on a substrate provided by an embodiment of the present application.
  • Figure 14 is a cross-sectional view of a memory unit provided by an embodiment of the present application.
  • Figure 15 is a cross-sectional view including two storage layers provided by an embodiment of the present application.
  • Figure 16 is a cross-sectional view including two storage layers provided by an embodiment of the present application.
  • Figure 17 is a three-dimensional process structure diagram of a memory array provided by an embodiment of the present application.
  • Figures 18a to 18e are cross-sectional views of the corresponding process structures after completion of each step in a memory array manufacturing method provided by an embodiment of the present application;
  • Figure 19 is a three-dimensional process structure diagram of a memory array provided by an embodiment of the present application.
  • Figure 20 is a three-dimensional process structure diagram of a memory array provided by an embodiment of the present application.
  • Figure 21 is a structural diagram of a storage unit provided by an embodiment of the present application.
  • Figure 22 is a cross-sectional view of a memory unit provided by an embodiment of the present application.
  • Figure 23 is a three-dimensional process structure diagram of a memory array provided by an embodiment of the present application.
  • 24a to 24h are cross-sectional views of corresponding process structures after each step in a memory array manufacturing method provided by an embodiment of the present application is completed;
  • Figure 25 is a flow chart of a storage array manufacturing method provided by an embodiment of the present application.
  • Figures 26a to 26n are cross-sectional views of the corresponding process structures after completion of each step in a memory manufacturing method provided by an embodiment of the present application;
  • Figures 27a to 27h are cross-sectional views of the corresponding process structures after completion of each step in a memory manufacturing method provided by an embodiment of the present application.
  • Tr - transistor Tr - transistor
  • FIG. 2 is a circuit block diagram of an electronic device 200 provided by an embodiment of the present application.
  • the electronic device 200 can be a terminal device, such as a mobile phone, a tablet, a smart bracelet, or a personal computer (PC), Servers, workstations, etc.
  • PC personal computer
  • the electronic device 200 may include a bus 205, and a system on chip (SOC) 210 connected to the bus 205.
  • SOC210 can be used to process data, such as processing application data, processing image data, and caching temporary data.
  • the SOC 210 may include an application processor (AP) 211 for processing applications, a graphics processing unit (GPU) 212 for processing image data, and a cache cache.
  • the first RAM 213 may be static random access memory (static random access memory, SRAM) or embedded flash memory (embedded flash, eflash), etc.
  • the above-mentioned AP211, GPU212 and first RAM213 may be integrated into one bare chip (die), or may be respectively provided in multiple dies.
  • the electronic device 200 may also include a second RAM 220 connected to the SOC 210 through the bus 205 .
  • the second RAM 220 may be a dynamic random access memory (DRAM).
  • the second RAM 220 may be used to save volatile data, such as temporary data generated by the SOC 210 .
  • the storage capacity of the second RAM 220 is usually larger than that of the first RAM 213, but the reading speed is usually slower than that of the first RAM 213.
  • the electronic device 200 may also include a communication chip 230 and a power management chip 240 connected to the SOC 210 via the bus 205.
  • the communication chip 230 can be used for processing the protocol stack, or amplifying and filtering analog radio frequency signals, or realizing the above functions at the same time.
  • the power management chip 240 can be used to power other chips.
  • the SOC 210 and the second RAM 220 can be packaged in a packaging structure, such as using 2.5D (dimension) or 3D packaging, etc., to obtain a faster data transmission rate between chips.
  • FIG. 3 is a circuit block diagram of a memory 300 that can be applied in an electronic device according to an embodiment of the present application.
  • the memory 300 may be ferroelectric random access memory (Ferroelectric Random Access Memory, FeRAM or FRAM), or may be dynamic random access memory (dynamic random access memory, DRAM). This application does not limit the application scenarios of the memory 300.
  • the memory 300 includes a storage array 31 and a controller 32 for accessing the storage array 31 , where the controller 32 is used to control read and write operations of the storage array 31 .
  • the storage array 31 and the controller 32 shown in FIG. 3 have a variety of package structures that can be implemented.
  • package structures that can be implemented are given below.
  • Figure 4a is one of the packaging structures of the storage array 31 and the controller 32 given in the embodiment of the present application. That is, the storage array 31 and the controller 32 are two independent chips. The storage array 31 and the controller 32 are respectively integrated on the substrate 33. For example, the storage array 31 and the controller 32 can be electrically connected through metal traces arranged on the substrate 33 . In this structure, since the storage array 31 and the controller 32 are two independent chips, the storage array 31 may be called a stand-alone memory.
  • Figure 4b is another packaging structure of the storage array 31 and the controller 32 according to the embodiment of the present application.
  • the storage array 31 and the controller 32 are two independent chips, so the storage array 31 can also be called an independent memory.
  • the storage array 31 and the controller 32 are stacked.
  • the storage array 31 and the controller 32 can be connected through a through silicon via (TSV) or a rewiring layer. (redistribution layer, RDL) realizes interconnection.
  • TSV through silicon via
  • RDL rewiring layer
  • Fig. 4c is another packaging structure of the memory array 31 and the controller 32 provided in the embodiment of the present application.
  • the memory array 31 and the controller 32 are integrated into the same chip 3, and the chip 3 is integrated on the substrate 33. Therefore, the memory array 31 can be called an embedded memory.
  • the controller 32 can be integrated on the substrate through the front end of line (FEOL) process, and the interconnection lines and the memory array pass through the back end of line (FEOL) process. end of line, BEOL) process is integrated on the controller 32.
  • the controller here can be used to generate control signals. These control signals can be read and write control signals for controlling the read and write operations of data in the storage array.
  • the controller here can also include analog circuit parts, such as sense amplifiers.
  • the memory array 31 can be a single memory layer or multiple memory layers stacked along the Z direction perpendicular to the substrate. When two or more memory layers are included, such a memory can be called a three-dimensional integrated memory structure to increase the storage capacity.
  • the memory array 31 in the memory may include a plurality of memory cells 400 arranged in an array as shown in FIG6 , wherein each memory cell 400 may be used to store 1 bit (bit) or multiple bits of data.
  • the memory array 31 may also include electrode lines such as word lines (WL) and bit lines (BL).
  • Each memory cell 400 is electrically connected to the corresponding word line WL and bit line BL.
  • Different memory cells 400 may be electrically connected via WL and BL.
  • One or more of the above WL and BL are used to select the memory cell 400 to be read or written in the memory array by receiving the control level output by the control circuit, thereby realizing the data read and write operation.
  • the controller 32 in the memory may include one or more circuit structures among the decoder 320, the driver 330, the timing controller 340, the buffer 350 or the input and output driver 360 shown in FIG. 6 .
  • the decoder 320 is used to decode according to the received address to determine the storage unit 400 that needs to be accessed.
  • the driver 330 is used to control the level of the signal line according to the decoding result generated by the decoder 320, thereby achieving access to the designated storage unit 400.
  • the buffer 350 is used to cache the read data. For example, first-in first-out (FIFO) may be used for caching.
  • the timing controller 340 is used to control the timing of the buffer 350 and control the driver 330 to drive the signal lines in the memory array 310 .
  • the input and output driver 360 is used to drive transmission signals, such as driving received data signals and driving data signals to be sent, so that the data signals can be transmitted over long distances.
  • decoder 320 decoder 320
  • driver 330 driver 330
  • timing controller 340 buffer 350
  • input and output driver 360 can be integrated into one chip, or can be integrated into multiple chips respectively.
  • the memory 300 involved in the embodiment of this application may be a dynamic random access memory (dynamic random access memory, DRAM).
  • DRAM dynamic random access memory
  • it may be a DRAM including 1T1C memory cells.
  • the memory 300 involved in the embodiment of the present application may also be a ferroelectric random access memory (FeRAM).
  • FeRAM ferroelectric random access memory
  • it may also be a FeRAM including 1T1C memory cells.
  • FIG. 7 is a circuit diagram of a storage unit 400 in the memory 300 according to the embodiment of the present application.
  • the memory unit 400 belongs to a 1T1C gain-cell memory unit structure, that is, a memory unit 400 includes a transistor Tr and a capacitor C.
  • the transistor Tr can choose a thin film transistor (TFT) structure.
  • the first electrode of the transistor Tr is electrically connected to the first capacitor electrode of the capacitor C
  • the second electrode of the transistor Tr is electrically connected to the bit line (BL)
  • the gate electrode of the transistor Tr is electrically connected to the word line (WL).
  • the second capacitance electrode of the capacitor C is electrically connected to the plate line (PL).
  • the plate line (PL) can be called the first electrode line
  • the word line (WL) can be called the second electrode line
  • the bit line (bit line, BL) may be called the third electrode line.
  • the memory unit shown in FIG. 7 is a FeRAM memory unit, that is, the capacitor layer formed between the first capacitor electrode and the second capacitor electrode is a ferroelectric material layer.
  • the memory unit shown in Figure 7 may also be a DRAM memory unit.
  • the word line WL is used to receive the word line control signal to turn on the transistor Tr
  • the bit line BL is used to receive the bit line control signal
  • the ferroelectric The plate line PL electrically connected to the capacitor is used to receive the plate line control signal.
  • the voltage difference between the bit line control signal and the plate line control signal causes the ferroelectric layer of the selected ferroelectric capacitor to be positively or negatively polarized, so that the selected ferroelectric capacitor is polarized.
  • Different logic information is written into the ferroelectric capacitor. For example, when the ferroelectric layer is positively polarized, a logic signal "0" is written. For another example, when the ferroelectric layer is negatively polarized, a logic signal "1" is written.
  • the transistor Tr shown in Figure 7 above can be an NMOS (N-channel metal oxide semiconductor, N-channel metal oxide semiconductor) tube, or a PMOS (P-channel metal oxide semiconductor) tube can be selected. semiconductor, P-channel metal oxide semiconductor) tube.
  • NMOS N-channel metal oxide semiconductor, N-channel metal oxide semiconductor
  • PMOS P-channel metal oxide semiconductor
  • one of the drain or source of the transistor Tr is called the first electrode, and the corresponding other electrode is called the second electrode.
  • the control of the transistor terminal is the gate.
  • the drain and source of a transistor can be determined based on the direction of current flow.
  • FIG8 illustrates a circuit diagram of the memory cells 400 shown in FIG7 arranged in an array.
  • the gates of the transistors Tr of the plurality of memory cells arranged in the same direction may be electrically connected to the same word line WL; and the second electrodes of the transistors Tr of the plurality of memory cells arranged in the same direction may be electrically connected to the same bit line BL; and the second capacitor electrodes of the plurality of capacitors C may be electrically connected to the same plate line PL, for example, the plate line PL may be grounded.
  • embodiments of the present application provide some memory unit process structures that can improve storage density, as detailed below.
  • the memory array provided by the embodiment of the present application includes multiple memory layers, and these multiple memory layers are stacked along a direction perpendicular to the substrate 100 . Wherein, two adjacent storage layers are electrically isolated by an electrical isolation dielectric layer. In each memory layer, a stack of multiple metal layers may be included, and two adjacent metal layers are electrically isolated by a dielectric layer, and memory cells may be formed in these metal layers.
  • Figures 10 and 11 are three-dimensional process structure diagrams of a memory array according to an embodiment of the present application.
  • the memory array 31 can be stacked on the substrate 100 through a front-end process, or integrated on the substrate 100 through a back-end process. on the substrate 100.
  • the storage array 31 includes three storage layers, namely storage layer 501 , storage layer 502 and storage layer 503 .
  • the storage layer 501 and the storage layer 502, and the storage layer 502 and the storage layer 503 are electrically isolated by the dielectric layer 500.
  • each storage layer includes a first metal layer 50A1 and a second metal layer 50A2, and a dielectric layer 51 located between the first metal layer 50A1 and the second metal layer 50A2.
  • the memory cell shown in FIG. 7 can be formed in the first metal layer 50A1, the second metal layer 50A2 and the dielectric layer 51.
  • the specific process structure that can be implemented can be seen below.
  • Figure 12 is an enlarged view of point A in Figure 11.
  • the transistor Tr and the capacitor C are integrated in the first metal layer 50A1, the second metal layer 50A2 and the dielectric layer 51.
  • the first electrode 11 of the transistor Tr is formed in the first metal layer 50A1
  • the second electrode 12 of the transistor Tr is formed in the second metal layer 50A2
  • at least part of the gate electrode 13 of the transistor Tr and the channel layer 14 at least partially penetrates the dielectric layer 51
  • the first capacitor electrode 21, the capacitor layer 23 and the second capacitor electrode 22 of the capacitor C are all formed in the first metal layer 50A1.
  • a memory cell array is integrated using the stacked first metal layer 50A1, the second metal layer 50A2, and the dielectric layer 51.
  • the memory array provided in this application can significantly reduce the number of stacked metal layers.
  • the present application can integrate more memory layers and more memory units to increase the storage capacity of the memory.
  • the gate 13 has a columnar structure penetrating through the dielectric layer 51 , and the channel layer 14 surrounds the periphery of the gate 13 . That is, the channel of the transistor Tr has a ring channel structure.
  • the first capacitor electrode 21 , the capacitor layer 23 and the second capacitor electrode 22 are stacked on the first capacitor in a direction parallel to the substrate 100 .
  • the capacitor layer 23 surrounds the periphery of the first capacitor electrode 21, and the second capacitor electrode 22 surrounds the periphery of the capacitor layer 23. That is, the capacitor is a ring capacitor structure.
  • the ring capacitor structure can increase the capacitor area to increase the capacitor capacity and improve the storage performance of the memory.
  • FIGS. 11 and 12 The memory unit structure shown in FIGS. 11 and 12 provided by the embodiments of the present application can not only achieve three-dimensional stacking, but also occupy a smaller area for each memory unit, thereby correspondingly increasing the storage density.
  • FIG. 13 shows the area of the orthographic projection on the substrate 100 of the plurality of memory cells 400 located in a memory layer in FIG. 11 .
  • more memory units 400 can be integrated per unit area.
  • the ring capacitor structure needs to have a higher depth-to-width ratio in order to meet the high capacitance. This will pose process challenges to the opening of through holes to form the columnar capacitor.
  • the ring-shaped capacitor can be implemented using a deposition process, which will not increase the process difficulty too much.
  • multiple dielectric layers can be stacked in a direction perpendicular to the substrate. For example, when two memory layers need to be prepared, seven dielectric layers can be stacked. These media layers are then patterned to produce two storage layers at the same time, that is, the three media layers are patterned into one storage layer, and the other three media layers are patterned into another storage layer. The two storage layers are then patterned together. Layers of media are separated, rather than making one storage layer and then making another storage layer. Therefore, the memory array provided in the embodiments of the present application can simplify the preparation process and reduce the complexity of the process during preparation. The specific achievable process methods will be introduced later, and how to use one process to prepare multiple processes at the same time based on the process method. storage layer, which will not be described here.
  • one end of the gate electrode 13 penetrating the dielectric layer 51 may extend into the first metal layer 50A1 and be electrically isolated from the first electrode 11 through the gate dielectric layer 15 .
  • the other end of the gate electrode 13 can also extend into the second metal layer 50A2 and be electrically isolated from the second electrode 12 through the gate dielectric layer 15 .
  • the first electrode 11 of the transistor Tr and the capacitor C are both formed in the first metal layer 50A1
  • the first electrode of the transistor Tr can be The pole 11 and the first capacitor electrode 21 of the capacitor C share the same electrode to simplify the process structure. That is, the formed metal layer can not only serve as the first electrode 11 of the transistor Tr, but also serve as the first capacitor electrode 21 of the capacitor C.
  • Figures 11 and 12 also show an achievable structure of the channel layer 14.
  • the channel layer 14 that runs through the dielectric layer 51 and surrounds the gate electrode 13 can extend into the first metal layer 50A1 and make ohmic contact with the first pole 11 in the first metal layer 50A1.
  • the first pole 11 surrounds the periphery of the channel layer 14 . In this way, the contact area between the channel layer 14 and the first electrode 11 can be increased, thereby avoiding short channel effects, such as suppressing an increase in leakage current and lower electron mobility.
  • the channel layer 14 that runs through the dielectric layer 51 and surrounds the gate 13 can also extend into the second metal layer 50A2 and make ohmic contact with the second pole 12 in the second metal layer 50A2, and the second pole 12 surrounding the periphery of the channel layer 14 . Similar to the above-mentioned first electrode 11 , the contact area between the second electrode 12 and the channel layer 14 can also be increased to increase the electron mobility in the channel layer 14 .
  • Figure 14 shows a cross-sectional view along X-Z of one of the memory cells of Figures 11 and 12.
  • the first capacitor electrode 21 not only includes a surrounding electrode 211 surrounding the periphery of the channel layer 14, but also includes a planar electrode 212 connected to the surrounding electrode 211 and arranged parallel to the substrate.
  • the planar electrode 212 has an annular structure and surrounds the surrounding electrode 211. around the periphery of electrode 211.
  • the first capacitor electrode 21 of this structure not only has a horizontal contact surface N2 in contact with the capacitor layer 23 , but also has a vertical contact surface in contact with the capacitor layer 23 .
  • N1 The horizontal contact surface N2 is a surface parallel to the substrate, and the vertical contact surface N1 is a surface perpendicular to the substrate.
  • the first capacitor electrode 21 provided in the embodiment of the present application can increase the contact area with the capacitor layer 23, that is, the capacitor area of the capacitor layer 23 can be increased, thereby increasing the capacitance of the capacitor C. .
  • the capacitor layer 23 is formed on the horizontal contact surface N2 and the vertical contact surface N1 of the first capacitor electrode 21 .
  • the second capacitor electrode 22 is formed on the capacitor layer 23 so that the capacitor layer 23 is sandwiched between the first capacitor electrode 21 and the second capacitor electrode 22 .
  • FIG. 15 and 16 respectively provide cross-sectional views of the memory array including the memory layer 501 and the memory layer 502 along the X-Z section.
  • FIG. 15 there is a dielectric layer 500 between the storage layer 501 and the storage layer 502, that is, the storage layer 501 and the storage layer 502 are electrically isolated by a dielectric layer.
  • the channel layer 14 in the storage layer 501 and The channel layer 14 in the storage layer 502 is separated at the dielectric layer 500 .
  • the channel layer 14 of the storage layer 501 can extend to the two dielectric layers close to the storage layer.
  • 501 in the dielectric layer 500a, and the channel layer 14 in the storage layer 501 and the channel layer 14 in the storage layer 502 are separated at the dielectric layer 500b.
  • FIGS. 10 and 11 In the memory array shown in FIGS. 10 and 11 , not only the memory cells (including transistors Tr and capacitors C) in each memory layer are shown, but also the achievable process structures of the word lines WL, bit lines BL and plate lines PL for controlling the reading and writing of the memory cells are shown.
  • Figure 17 shows the layout of word lines WL, bit lines BL and plate lines PL in the embodiments of Figures 10 and 11.
  • the word line WL extends in a direction perpendicular to the substrate 100 and electrically connects the gate electrodes 13 of a plurality of transistors Tr in a plurality of storage layers arranged in a direction perpendicular to the substrate. That is, the gate electrodes 13 of a plurality of transistors Tr arranged in a direction perpendicular to the substrate are electrically connected to the same word line WL.
  • the word line WL extends along the Z direction, and the gates 13 of the plurality of transistors Tr arranged along the Z direction in the storage layer 501, the storage layer 502, and the storage layer 503 are electrically connected to the same word line WL.
  • the word line WL runs through multiple storage layers and the media layer between each two adjacent storage layers.
  • a word line WL layer is formed above multiple memory layers to interconnect the multiple word lines WL shown in FIG. 10 .
  • the bit line BL extends in a direction parallel to the substrate, and electrically connects the second electrodes 12 of the plurality of transistors Tr in each storage layer arranged in a direction parallel to the substrate. . That is, the second electrodes 12 of the plurality of transistors Tr arranged in a direction parallel to the substrate are electrically connected to the same bit line BL.
  • the bit line BL extends along the Y direction.
  • the second electrodes 12 of the plurality of transistors Tr arranged along the Y direction are electrically connected to the same bit line BL.
  • two adjacent bit lines BL are electrically isolated by a dielectric layer.
  • the plate line PL has a plate-like structure.
  • the plate line PL is located in the first metal layer 50A1, and the capacitor C is located in the first metal layer 50A1.
  • the second capacitor electrodes 22 are all electrically connected to the plate-shaped plate line PL.
  • the plate line PL located in the first metal layer 50A1 is electrically connected to the second capacitor electrodes 22 of all capacitors C in the storage layer 501.
  • the plate line PL can be grounded.
  • a through hole 61 penetrating through the multiple dielectric layers can be opened in the stacked dielectric layers, and the through hole 61 can be used to fill the channel layer 14 and the gate electrode 13 .
  • these dielectric layers are used as functional dielectric layers to form storage layers, and the other part are used as electrical isolation layers to electrically isolate two adjacent storage layers.
  • these functional media layers include a first functional media layer 500a1, a second functional media layer 500a2, and a third functional media layer 500a3 stacked in sequence.
  • the first functional media layer 500a1, the second functional media layer 500a2 And the third functional medium layer 500a3 can be used to form a storage layer.
  • the through hole 61 penetrates these functional dielectric layers and electrically isolated dielectric layers.
  • a groove 71 connected to the through hole 61 can be opened in the first functional dielectric layer 500a1, and then a metal layer is formed on the inner wall of the groove 71, and then the part of the groove 71 close to the through hole 61 is carved back. the metal layer on the edge to form the second capacitor electrode 22 .
  • the capacitor layer 23 is formed in the groove 71 , and then a capacitor layer structure with a notch facing the through hole 61 is formed as shown in FIG. 18c .
  • the groove 71 is then filled with a metal layer to form the first capacitor electrode 21 of the capacitor C, thereby manufacturing the capacitor C.
  • the remaining dielectric layer of the dielectric layer where the capacitor C is located is etched away, and then filled with a metal layer to form a plate-shaped plate line PL, so that the plate line PL is in contact and electrically connected to the second capacitor electrode 22 of the capacitor C.
  • the metal layer close to the edge of the through hole is etched back to prevent the formed plate line PL and capacitor layer from contacting the channel layer 14, so that the circuit structure shown in Figure 7 cannot be formed. storage unit.
  • the produced capacitor layer 23 not only includes parts perpendicular to the substrate, but also includes parts parallel to the substrate. Therefore, the area of the capacitor layer can be increased to improve the capacitor capacity.
  • the first metal layer 50A1 forming the capacitor C in each memory layer is disposed close to the substrate, and the second metal layer 50A2 is disposed far away from the substrate. That is, the capacitor C is closer to the substrate than the transistor Tr.
  • the first metal layer 50A1 forming the capacitor C can also be arranged away from the substrate, and the second metal layer 50A2 is arranged close to the substrate.
  • the embodiment of the present application also provides another memory cell structure containing 1T1C, as shown in Figures 19 and 20.
  • Figures 19 and 20 also show memory arrays containing multiple 1T1C memory cells.
  • the 1T1C memory unit shown in Figure 19 may be a 1T1C memory unit of FeRAM, or it may be a 1T1C memory unit of DRAM.
  • the storage array process structure shown in FIG20 is similar to the storage array process structure shown in FIG11 in that: it also belongs to a three-dimensional stacked storage array, and the three-dimensional stacked storage array also includes multiple storage layers, for example, storage layer 501, storage layer 502 and storage layer 503 shown in FIG20; and, in FIG20, each storage layer also includes a first metal layer 50A1 and a second metal layer 50A2, and a dielectric layer 51 located between the first metal layer 50A1 and the second metal layer 50A2.
  • Figure 21 shows an enlarged view of a memory cell of Figure 20, in which the first electrode 11 of the transistor Tr is formed in the first metal layer 50A1, and the The second electrode 12 is formed in the second metal layer 50A2; the first capacitor electrode 21, the capacitor layer 23 and the second capacitor electrode 22 of the capacitor C are all formed in the first metal layer 50A1.
  • the gate electrode 13 of the transistor Tr extends to the first metal layer 50A1 and the second metal layer 50A2.
  • the channel layer 14 of the transistor Tr is only formed in the dielectric layer 51 and is not Extending into the first metal layer 50A1 and the second metal layer 50A2.
  • Fig. 22 shows a cross-sectional view of a memory cell cut along the X-Z line in Fig. 20.
  • the channel layer 14 includes a surrounding channel 141 surrounding the gate 13, and also includes a first planar channel 142a connected to the surrounding channel 141 and parallel to the substrate 100.
  • the first planar channel 142a is in ohmic contact with the second electrode 12 of the transistor Tr to achieve electrical connection.
  • the channel layer 14 further includes a second planar channel 142b connected to the surrounding channel 141 and parallel to the substrate 100 .
  • the first planar channel 142a and the second planar channel 142b are arranged opposite to each other.
  • the second planar channel 142b is in ohmic contact with the first electrode 11 of the transistor Tr to achieve electrical connection.
  • the process structure of the first capacitor electrode 21 and the capacitor layer 23 in the capacitor C in the structure shown in Figure 22 is also different from the structure shown in Figure 10.
  • the first capacitive electrode 21 includes a surrounding electrode 211, a first planar electrode 212a and a second planar electrode 212b.
  • the first planar electrode 212a and the second planar electrode 212b are both parallel to the substrate, and the first planar electrode 212a and the second planar electrode 212b are connected through the surrounding electrode 211, so that a cavity with an opening is formed in the first capacitor electrode 21, and the opening of the cavity is away from the columnar gate 13.
  • the capacitor layer 23 is formed on the inner wall surface of the cavity, and the second capacitor electrode 22 is formed on the capacitor layer 23 .
  • the first electrode 11 of the transistor Tr and the first capacitor electrode 21 of the capacitor C also share the same electrode.
  • first planar channel 142a of the channel layer 14 is in ohmic contact with the second electrode 12 of the transistor Tr, and the second planar channel 142b of the channel layer 14 is in ohmic contact with the first planar electrode 212a of the capacitor C.
  • the capacitor layer 23 formed is a capacitor structure with the notch facing the gate electrode 13, while in Figure 22, the capacitor layer 23 formed is a capacitor structure with the notch facing away from the gate electrode 13. structure.
  • the capacitor layer 23 shown in FIG. 14 or FIG. 22 includes not only a vertical part perpendicular to the substrate, but also a horizontal part parallel to the substrate. Through the layout of vertical and horizontal parts, the capacitor area can be increased to improve the capacitor capacity.
  • Figure 23 shows the layout of word lines WL, bit lines BL and plate lines PL in the memory array of Figure 20.
  • the specific achievable process structure is as follows.
  • the word line WL extends in a direction perpendicular to the substrate 100, and electrically connects the gates 13 of the plurality of transistors Tr arranged in a direction perpendicular to the substrate in the plurality of storage layers. That is, the gates 13 of the plurality of transistors Tr arranged in a direction perpendicular to the substrate are electrically connected to the same word line WL.
  • the word line WL extends in the Z direction, and the gates 13 of the plurality of transistors Tr arranged in the Z direction in the plurality of storage layers are electrically connected to the same word line WL.
  • bit line BL structure shown in Figure 23 it is the same as the bit line BL structure shown in Figure 17 above.
  • the bit line BL extends in a direction parallel to the substrate, and the edge of each storage layer is parallel to the substrate.
  • the second poles 12 of the plurality of transistors Tr arranged in parallel directions are electrically connected. That is, the second electrodes 12 of the plurality of transistors Tr arranged in a direction parallel to the substrate are electrically connected to the same bit line BL.
  • the bit line BL extends along the Y direction, and the second electrodes 12 of the plurality of transistors Tr arranged along the Y direction in each storage layer are electrically connected to the same bit line BL.
  • the plate line PL extends in a direction perpendicular to the substrate, and the first transistor Tr of the plurality of memory layers is arranged in a direction perpendicular to the substrate.
  • Two poles 12 are electrically connected. That is, the second capacitance electrodes 22 of the plurality of capacitors C arranged along the direction perpendicular to the substrate are electrically connected to the same plate line PL.
  • the plate line PL extends along the Z direction, and the second poles 12 of the plurality of transistors Tr arranged along the Z direction in the plurality of storage layers are electrically connected to the same plate line PL.
  • the second capacitance electrodes 22 of two adjacent capacitors C along the same direction may be electrically connected to the same plate line PL.
  • the second capacitance electrodes 22 of two adjacent capacitors C arranged along the X direction are electrically connected to the same plate line PL.
  • a first through hole 611 penetrating through these dielectric layers can be opened in the stacked multi-layer dielectric layer, and the first through hole 611 can be used to fill the gate electrode 13 .
  • these dielectric layers are used as a functional dielectric layer to form a storage layer, and the other part is used as an electrical isolation layer to electrically isolate two adjacent storage layers.
  • these functional media layers include a first functional media layer 500a1, a second functional media layer 500a2, and a third functional media layer 500a3 stacked in sequence.
  • the first functional media layer 500a1, the second functional media layer 500a2 And the third functional medium layer 500a3 can be used to form a storage layer.
  • a groove 711 connected to the first through hole 611 is opened in the third functional dielectric layer 500a3, and then a metal layer is filled in the groove 711 to form the second electrode 12 of the transistor Tr.
  • the gate dielectric layer 15 and the gate electrode 13 are formed in the first through hole 611.
  • second through holes 612 penetrating through these dielectric layers are then opened in the stacked multi-layer dielectric layers, and the second through holes 612 are located between two adjacent first through holes 611 .
  • a groove 712 parallel to the substrate and connected to the second through hole 612 is opened in the second functional dielectric layer 500a2.
  • the groove 712 penetrates to the gate dielectric layer 15.
  • the inner wall surface of the groove 712 produced in Figure 24e is filled with semiconductor material to form a channel layer 14 on the inner wall surface of the groove 712, and the gap of the channel layer 14 is away from the formed gate electrode 13 .
  • a groove 713 parallel to the substrate and connected to the second through hole 612 is opened in the first functional dielectric layer 500a1.
  • the first capacitor electrode of the capacitor C is sequentially formed on the inner wall of the groove 713. 21.
  • the prepared channel layer 14 includes not only the surrounding channel but also the planar channel; and the prepared capacitor layer 23 includes not only the portion perpendicular to the substrate but also the portion parallel to the substrate.
  • each functional layer of the transistor Tr there are many materials that can be selected for each functional layer of the transistor Tr, each functional layer of the capacitor C, as well as the word line WL, the bit line BL and the plate line PL. The following is given. Some materials to choose from.
  • the materials of the first electrode, the second electrode, the gate electrode of the transistor Tr, the word line WL, the bit line BL and the plate line PL are all conductive materials, such as metal materials.
  • it can be TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide),
  • One or more conductive materials such as Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), etc.
  • the channel layer 14 of the transistor Tr can select Si (silicon), poly-Si (p-Si, polysilicon), amorphous-Si (a-Si, amorphous silicon), In-Ga-Zn -O (IGZO, indium gallium zinc oxide) multicomponent, ZnO (zinc oxide), ITO (indium tin oxide), TiO 2 (titanium dioxide), MoS 2 (molybdenum disulfide), WS 2 (tungsten disulfide), graphite
  • Si silicon
  • p-Si polysilicon
  • amorphous-Si a-Si, amorphous silicon
  • In-Ga-Zn -O IGZO, indium gallium zinc oxide multicomponent
  • ZnO zinc oxide
  • ITO indium tin oxide
  • TiO 2 titanium dioxide
  • MoS 2 molybdenum disulfide
  • WS 2 tungsten disulfide
  • graphite One or more semiconductor materials such as en
  • the material of the gate dielectric layer of the above-mentioned transistor Tr can be SiO 2 (silicon dioxide), Al 2 O 3 (aluminum oxide), HfO 2 (hafnium dioxide), ZrO 2 (zirconia), TiO 2 (titanium dioxide), Y 2 One or more of insulating materials such as O 3 (yttrium trioxide) and Si 3 N 4 (silicon nitride).
  • Both the first capacitor electrode 21 and the second capacitor electrode 22 in the capacitor C are conductive materials.
  • the materials that can be selected they can be TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver) and other conductive materials.
  • the capacitance layer 23 in the capacitor C can be made of SiO2, Al2O3, HfO2, ZrO2, TiO2, Y2O3, Si3N4, HAO and other insulating materials, or it can be ZrO2, HfO2, Al-doped HfO2, Si-doped HfO2, Zr-doped Ferroelectric materials such as HfO2, La-doped HfO2, Y-doped HfO2, or materials doped with other elements based on this material, and any combination thereof.
  • Figure 25 exemplifies a flow chart for preparing a memory array.
  • Step S1 Stack multiple dielectric layers on the substrate.
  • the multi-layer dielectric layers include multiple groups of functional dielectric layers and an isolation dielectric layer located between two adjacent groups of functional dielectric layers.
  • Each group of functional dielectric layers includes sequentially stacked A first functional medium layer, a second functional medium layer and a third functional medium layer.
  • the materials of two adjacent dielectric layers in these multi-layer dielectric layers may be different.
  • one of the two adjacent dielectric layers is made of one of insulating materials such as SiO 2 (silicon dioxide), Al 2 O 3 (aluminum oxide), HfO 2 (hafnium dioxide), ZrO 2 (zirconium oxide), TiO 2 (titanium dioxide), Y 2 O 3 (yttrium trioxide) and Si 3 N 4 (silicon nitride
  • the other dielectric layer may be made of another insulating material such as SiO 2 (silicon dioxide), Al 2 O 3 (aluminum oxide), HfO 2 (hafnium dioxide), ZrO 2 (zirconium oxide), TiO 2 (titanium dioxide), Y 2 O 3 (yttrium trioxide) and Si 3 N 4 (silicon nitride).
  • eleven dielectric layers can be stacked on the substrate, and every three dielectric layers are used to produce one memory layer.
  • One dielectric layer between every three dielectric layers serves as an electrical isolation layer between two adjacent storage layers.
  • Step S2 Pattern multiple sets of functional dielectric layers to form multiple stacked storage layers.
  • Each storage layer includes a first metal layer patterned with a first functional dielectric layer, and a third functional dielectric layer patterned.
  • the transistor includes a first electrode, a second electrode, a gate electrode and a channel layer;
  • the capacitor includes a first capacitor electrode, a capacitor layer and a second capacitor electrode; the first electrode of the transistor and the capacitor are formed in the first metal layer, and the transistor
  • the second electrode is formed in the second metal layer; at least part of the gate electrode and at least part of the channel layer are formed in the second dielectric layer, and the channel layer surrounds the periphery of the gate electrode; the first capacitor electrode, the capacitor layer and The second capacitor electrodes are stacked in a direction parallel to the substrate, and the capacitor layer surrounds the periphery of the first capacitor electrode.
  • Figures 26a to 26n show the process structure after each step is completed in the process of manufacturing a memory array according to the embodiment of the present application.
  • a plurality of dielectric layers are stacked on a substrate, the plurality of dielectric layers comprising a plurality of groups of functional dielectric layers, and an electrically isolating dielectric layer 500b located between two adjacent groups of functional dielectric layers, each group of functional dielectric layers comprising a first functional dielectric layer 500a1, a second functional dielectric layer 500a2 and a third functional dielectric layer 500a3 stacked in sequence.
  • FIG. 26a shows two sets of functional dielectric layers, thereby making two stacked storage layers.
  • two adjacent dielectric layers can use different dielectric materials.
  • the various dielectric materials that can be selected are introduced above and will not be described again here.
  • FIG. 26a shows two electrically isolating dielectric layers 500b between two sets of functional dielectric layers.
  • each opening K1 penetrates multiple dielectric layers.
  • multiple openings K may be spaced apart along the X direction parallel to the substrate.
  • a plurality of spaced through holes 61 are opened between every two adjacent openings K1.
  • the plurality of through holes 61 between two adjacent openings K1 can also be arranged along the Y direction perpendicular to the X direction. Orientation arrangement.
  • each through hole 61 penetrates these multi-layer dielectric layers.
  • the through hole 61 is used to fill the conductive material to form the word line WL.
  • the third functional dielectric layer 500a3 is selectively etched to form a plurality of grooves 711 on the third dielectric layer 500a3, and the plurality of grooves 711 are formed in the third functional dielectric layer 500a3 at intervals, and two adjacent grooves 711 are isolated by the dielectric layer.
  • the groove 711 surrounds the periphery of the through hole 61 produced in FIG. 26d because the groove 711 is for forming the second pole 12 of the transistor Tr.
  • the groove 711 opened in Figure 26e is filled with metal to prepare the second electrode 12 of the transistor Tr.
  • metal may also be deposited in the through hole 61. Based on this, the metal in the through hole 61 needs to be etched back.
  • the first functional dielectric layer 500a1 is selectively etched to form a plurality of grooves 712 on the first functional dielectric layer 500a1, and the positions of these grooves 712 are consistent with the grooves 711 opened in Figure 26e. The location corresponds.
  • Figure 26h shows a partial structural diagram of Figure 26g.
  • the metal layer at the edge of the groove 712 close to the through hole 61 is carved back.
  • the capacitor material is filled to form the capacitor layer 23 on the metal layer produced in Figure 26i and at the edge of the groove 712 close to the through hole 61.
  • the capacitor material will be formed in the through hole 61, furthermore, the capacitor material in the through hole 61 needs to be etched away.
  • the remaining space of the groove 712 is filled with metal material to form the first capacitor electrode 21 of the capacitor C.
  • the metal material in the filled through hole 61 needs to be etched away.
  • the gate dielectric layer 15, the channel layer 14 and the metal layer are sequentially stacked on the inner wall surface of the through hole 61.
  • the metal layer forms the word line WL of the memory array.
  • the dielectric layer between the two adjacent second poles 12 on each third functional dielectric layer 500a3 is etched away, so that along the Y direction parallel to the substrate A plurality of second poles 12 are electrically connected to form a bit line BL.
  • the electrical isolation dielectric layer 500b is etched away, so that the channel layer formed in Figure 26l and located in the electrical isolation dielectric layer 500b perpendicular to the substrate is isolated, forming the structure shown in Figure 26m.
  • the second functional dielectric layer 500a2 is selectively etched and filled with metal PL so that the second capacitor electrodes of the capacitor layer on the same layer are interconnected through the plate line PL to form the final 3D 1T1C storage array.
  • Figures 26h to 26n show partial structural diagrams during the formation process of the memory array.
  • a memory is produced by stacking one layer of memory array and then stacking another layer of memory array, as the storage density continues to increase, the number of stacked layers will also increase, and the requirements for photolithography alignment accuracy will also increase. High, if the alignment accuracy of the next-level storage array structure and the upper-level storage array structure is low, the read and write performance may be affected.
  • using the memory array preparation method provided by the embodiments of the present application requires lower photolithography alignment accuracy and does not pose higher challenges to the process. In this way, it can not only simplify the process and reduce the difficulty of the process, but also Improve the product quality rate, improve the read and write performance of the memory, and also reduce the manufacturing cost of the memory.
  • Figures 27a to 27h show the process structure after each step is completed in the process of manufacturing a memory array according to the embodiment of the present application.
  • the multi-layer dielectric layer includes multiple groups of functional dielectric layers, and an electrically isolated dielectric layer 500 located between two adjacent groups of functional dielectric layers.
  • Each group of functional dielectric layers It includes a first functional medium layer 500a1, a second functional medium layer 500a2 and a third functional medium layer 500a3 stacked in sequence.
  • Figure 27a shows two sets of functional media layers, whereby two stacked storage layers can be produced.
  • the two adjacent dielectric layers can use different dielectric materials.
  • the various dielectric materials that can be selected are introduced above and will not be described again here.
  • a plurality of first through holes 611 arranged at intervals are opened, and each first through hole 611 penetrates these multi-layer dielectric layers.
  • the first through hole 611 is used to fill the conductive material to form the word line WL.
  • the third functional dielectric layer 500a3 is selectively etched to form a plurality of grooves on the third dielectric layer 500a3, and these grooves are formed at intervals in the third functional dielectric layer 500a3. Two adjacent grooves are separated by a dielectric layer.
  • the groove surrounds the periphery of the first through hole 611 produced in FIG. 27b because the groove is for forming the second pole 12 of the transistor Tr.
  • metal may also be deposited in the first through hole 611. Based on this, the metal in the first through hole 611 needs to be etched back.
  • a gate dielectric layer and a metal layer are sequentially formed on the inner wall surface of the first through hole 611, and the metal layer forms the word line WL of the memory array.
  • each second through hole 612 penetrates these dielectric layers.
  • the second functional dielectric layer 500a2 is selectively etched to form a plurality of grooves 712 on the second functional dielectric layer 500a2.
  • the grooves 712 surround the periphery of the second through hole 612, and the grooves 712 stay on The gate dielectric layer 15 in the first through hole 611.
  • semiconductor material is deposited on the inner wall surface of the groove 712 , and the semiconductor material at the outer edge of the groove 712 near the second through hole 612 is etched back to form a channel layer 14 , and then the dielectric material is continuously filled to fill the groove 712 .
  • the first functional dielectric layer 500a1 is selectively etched to form a plurality of grooves 713 on the first functional dielectric layer 500a1.
  • the grooves 713 surround the periphery of the second through hole 612, and the grooves 712 stay on The gate dielectric layer 15 in the first through hole 611.
  • a metal layer is formed on the inner wall surface of the groove 713, and the metal layer located at the outer edge of the groove 713 near the second through hole 612 is etched back to form the first capacitor electrode of the capacitor C.
  • the capacitor material will be formed in the second through hole 612, furthermore, the capacitor material in the second through hole 612 needs to be etched away.
  • the remaining space of the groove 713 is filled with metal material to form the first capacitor electrode 21 of the capacitor C.
  • the second through hole 612 is filled with metal material to form a strip-shaped plate line PL.
  • the final 3D 1T1C storage array can be formed.
  • a storage layer can be produced, in which one dielectric layer is patterned as the first A metal layer, another dielectric layer is patterned into a second metal layer, and another dielectric layer is disposed between the two metal layers. And, the first electrodes of the capacitor and the transistor in the memory cell are formed in the first metal layer, and the second electrodes of the transistors are formed in the second metal layer.
  • the first electrode of the capacitor and the transistor is formed in the first metal layer” referred to in the embodiment of the present application can be understood as: during the process, a film layer (for example, a dielectric layer) parallel to the substrate In the structure, by performing a patterning process, the first electrodes of the capacitor and the transistor can be formed so that the first electrodes of the capacitor and the transistor are in the first metal layer parallel to the substrate, instead of the two capacitor electrodes in the capacitor. , the capacitor layer and the first electrode of the transistor are stacked in a direction perpendicular to the substrate.
  • the second electrode of the transistor is formed in the second metal layer
  • a film layer such as a dielectric layer
  • the second electrode of the transistor can be formed by performing a patterning process, so that the second electrode of the transistor is in the second metal layer parallel to the substrate.

Abstract

一种三维存储阵列（31）、存储器（300）、存储阵列的形成方法，以及电子设备。涉及半导体存储器技术领域。主要用于提升存储单元（400）的集成密度，简化制备方法。该存储器（300）包括衬底（100）、多个存储层（501，502，503），每一个存储层（501，502，503）包括沿与衬底（100）相垂直方向堆叠的第一金属层（50A1）和第二金属层（50A2），第一金属层（50A1）和第二金属层（50A2）之间被介质层（51）电隔离开；每一个存储层（501，502，503）中的一个存储单元（400）包括晶体管（Tr）和电容器（C），即就是存储单元（400）中的晶体管（Tr）和电容器（C）被集成在堆叠的第一金属层（50A1）、介质层（51）和第二金属层（50A2）中。该存储阵列（31）在实现三维集成的基础上，还可以减小每一个存储单元（400）的面积，以提升集成密度，另外，还不会给工艺提出较大的挑战。

Description

一种三维存储阵列、存储器及电子设备 技术领域
本申请涉及半导体存储技术领域，尤其涉及一种三维存储阵列、包含该三维存储阵列的存储器、三维存储阵列的形成方法，以及包含有该存储器的电子设备。
背景技术
随着集成电路技术的不断演进，计算机，手机等电子设备中芯片上单位面积的晶体管数量不断增加，从而让电子设备的性能得到不断的优化。比如，动态随机存取存储器(dynamic random access memory，DRAM)，它作为一种内存结构，可以用于暂存中央处理器(central processing unit，CPU)的运算数据。为了适配处理器的运算速度，存储器的读写速度不断的被提升，从而，存储器的存储密度也不断增长，以满足信息时代下人们对于数据处理的需求。
随着存储器往更高密度，更大带宽的发展，催生出许多种结构的存储单元，比如，1T1C存储单元或者1TnC存储单元等，这里的T代表晶体管transistor，C代表电容器capacitor。
存储器快速地向高密度、高容量的方向发展的同时，给存储单元的工艺尺寸微缩带来了挑战和限制。示例的，见图1所示，图1示出的是一种平面1T1C存储单元的工艺结构图，通过在衬底中掺杂形成源漏极，且在衬底上形成栅极和电容器，以及字线(word line，WL)、位线(bit line，BL)和板线(plate line，PL)电极线。其中，栅极与字线WL电连接，漏极与位线BL电连接，源极通过电容器与板线PL电连接。
图1所示的平面存储单元所占据的面积较大，限制了存储密度的提升。与此同时，随着晶体管尺寸的微缩，电容器在衬底上的投影面积也越来越小，为了保证1T1C存储器能够稳定运行，电容器需要做的更高(如沿图1所示的P方向尺寸越来越大)。随着电容器高度的不断扩大及投影面积的不断微缩，对蚀刻工艺也造成了极大的挑战。因此，图1所示的2D存储单元微缩到10nm以下就会遇到物理尺寸极限。
发明内容
本申请提供一种三维存储阵列、包含该三维存储阵列的存储器、三维存储阵列的形成方法，以及包含有该存储器的电子设备。主要目的提供一种不仅可以提升存储密度，还基本不会给工艺提出较大挑战的三维存储阵列结构。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，本申请提供了一种三维存储阵列，比如，该三维存储阵列可以用于动态随机存取存储器(dynamic random access memory，DRAM)中。
该三维存储阵列包括衬底，和形成在衬底上的多个存储层，多个存储层沿着与衬底相垂直的方向堆叠，以形成三维堆叠存储结构，每一个存储层包括多个存储单元，每一个存储单元包括晶体管和与晶体管电连接的电容器，比如，该存储单元可以是 1T1C存储单元。晶体管包括第一极、第二极、栅极和沟道层，电容器包括第一电容电极、电容层和第二电容电极，晶体管的第一极与第一电容电极电连接；每一个存储层包括沿与衬底相垂直方向堆叠的第一金属层和第二金属层，第一金属层和第二金属层之间被介质层电隔离开；晶体管的第一极和电容器形成在第一金属层中，晶体管的第二极形成在第二金属层中；栅极的至少部分和沟道层的至少部分形成在介质层中，沟道层环绕在栅极的外围；第一电容电极、电容层和第二电容电极沿与衬底相平行的方向堆叠，电容层环绕在第一电容电极的外围，第二电容电极可以环绕在电容层的外围。
本申请给出的存储单元，可以是1T1C存储单元。在该存储单元中，与沟道层电连接的第一极和第二极沿与衬底相垂直的方向堆叠在相对应的第一金属层中和第二金属层中，且沟道层环绕在栅极的外围，即该晶体管是一种环沟道结构的场效应晶体管。还有，存储单元的电容器中，电容层是环绕在第一电容电极的外围，也就是该电容器是一种环电容结构。相比平面2D存储单元，本申请缩小了存储单元尺寸，因此，在与衬底相平行的单位面积上，可以集成更多的存储单元，以使得该三维存储阵列的集成密度更高。
另外，利用堆叠的第一金属层、介质层和第二金属层，就实现了晶体管和电容器的集成，相比采用更多的金属层集成存储单元，本申请可以减少金属层布设的数量，实现更多存储层的3D堆叠，以提升存储器的存储密度。
还有，在本申请中，电容器属于一种环电容结构，相比相关技术中的沿与衬底相垂直方向延伸的柱状电容，环电容结构在实现增加存储容量的基础上，还不会给刻蚀工艺提出较大的挑战，从而，使得该存储阵列为高密度、大存储、低成本的存储阵列。
除此之外，本申请给出的存储阵列在制备时，可以先堆叠多层介质层，然后，在堆叠的这些介质层结构上进行加工，可以同时加工出多层存储层，比如，当堆叠7层介质层时，完成一道加工工艺后，可以同时制得两层存储层，也就是说，本申请的多层存储层可以同时进行加工，即一次性形成多层器件，而不需要先制得第一层存储层，再利用相同的工艺逐层制得第二层存储层、第三层存储层等。如此一来，从工艺角度讲，可以简化工艺流程，降低制造成本，尤其是对于三维堆叠层数较多的存储阵列，工艺繁琐性和制造成本均会被明显的降低，另外，还可以避免由于逐层制得存储层，造成的存储单元对准精度差的现象。
在一种可能的实现方式中，栅极的一端延伸至第一金属层内，第一极环绕在栅极的外围，并通过栅介质层与栅极电隔离开；栅极的另一端延伸至第二金属层内，第二极环绕在栅极的外围，并通过栅介质层与栅极电隔离开。
从工艺角度讲，便于制造该栅极结构，比如，可以在多层堆叠的介质层内贯通通孔，并在该通孔内形成柱状的该栅极结构。
在一种可能的实现方式中，沟道层的一端延伸至第二金属层内，且第二极环绕在沟道层的外围。
由于环绕在栅极外围的沟道层延伸至第二极所处的金属层内，以使得第二极环绕沟道，这样，可以增加第二极与沟道层的接触面积，实现更大面积的电学接触，抑制漏电流增大，电子迁移率较低等。
在一种可能的实现方式中，沟道层的另一端延伸至第一金属层内；第一极和第一 电容电极共用同一电极；第一电容电极环绕在沟道层的外围。
和上述沟道层与第二极的位置类似，沟道层还可以延伸至晶体管的第一极所在的金属层内，并使得第一极环绕在沟道层的外围。同样的，实现了沟道与电极更大面积的电学接触，抑制漏电流增大，电子迁移率较低等。
另外，将晶体管的第一极和电容器的第一电容电极共用同一电极，可以简化该存储单元的工艺结构。
在一种可能的实现方式中，位于介质层中的沟道层包括环绕沟道、与环绕沟道连接的第一平面沟道，第一平面沟道平行于衬底；环绕沟道环绕在栅极的外围；第二极的朝向第一极的面与第一平面沟道接触。
此种实施例中，由于沟道层不仅包括环绕在栅极外围的环绕沟道，还包括与衬底相平行的平面沟道，以增加与第二极的接触面积。
在一种可能的实现方式中，位于介质层中的沟道层还包括平行于衬底的且与第一平面沟道相对的第二平面沟道，第一平面沟道和第二平面沟道通过环绕沟道连接；第二平面沟道与第一极接触。
沟道层除包括上述的与第二极欧姆接触的第一平面沟道之外，还包括与第一极欧姆接触的第二平面沟道，以增加沟道层与晶体管的第一极的欧姆接触面积。
在一种可能的实现方式中，第一电容电极包括环绕在栅极外围的环绕电极，和与环绕电极连接且与衬底相平行布设的平面电极，以使得第一电容电极形成与衬底相平行的水平接触面，和与衬底相垂直的垂直接触面，水平接触面和垂直接触面上均形成有电容层。
通过将第一电容电极设计为不仅包括与电容层接触的垂直接触面，还包括与电容层接触的水平接触面，这样的话，可以增加电容层的电容面积，以提升电容容量，从而，可以提升该存储单元的存储性能。
在一种可能的实现方式中，平面电极包括相对设置的第一平面电极和第二平面电极，第一平面电极和第二平面电极通过环绕电极连接，以使得第一电容电极内形成具有开口的凹槽，且凹槽的开口背离栅极，电容层和第二电容电极依次设置在凹槽的内壁面上，以形成具有第一缺口且第一缺口背离栅极的电容层。
在此种实施例中，通过将平面电极设计为包括第一平面电极和第二平面电极，以增加电容层的电容面积。
在一种可能的实现方式中，每一个存储层还包括第一电极线，电容器的第二电容电极与第一电极线电连接；第一电极线沿与衬底相垂直的方向延伸，且第一电极线靠近第一缺口设置；多个存储层中，沿与衬底相垂直布设的多个电容器的第二电容电极与同一条第一电极线电连接。
当第一电容电极包括第一平面电极和第二平面电极时，电容器中的第二电容电极远离晶体管的栅极，那么，可以将与电容器的第二电容电极电连接的第一电极线(比如PL线)沿着与衬底相垂直的方向延伸，以电连接沿与衬底相垂直布设的多个电容器的第二电容电极。
在一种可能的实现方式中，平面电极呈板状结构，并与环绕电极连接，以形成具有第二缺口且第二缺口朝向栅极的电容层，第二电容电极设置在电容层的背离第一电 容电极的表面上。
在一种可能的实现方式中，每一个存储层还包括第一电极线，电容器的第二电容电极与第一电极线电连接；第一电极线呈板状结构，且与衬底相平行布设，且第一电极线背离第二缺口设置；每一个存储层中，多个电容器的第二电容电极与同一个第一电极线电连接。
可以将第一电极线(比如PL线)呈板状设计，以电连接一个存储层中所有电容器的第二电容电极。
在一种可能的实现方式中，每一个存储层还包括第二电极线和第三电极线；晶体管的栅极与第二电极线电连接；晶体管的第二极与第三电极线电连接。
例如，该第二电极线为字线WL，第三电极线为位线BL。
在一种可能的实现方式中，第二电极线沿与衬底相垂直的方向延伸；多个存储层中，沿与衬底相垂直布设的多个晶体管的栅极与同一条第二电极线电连接。
在一种可能的实现方式中，第三电极线沿与衬底相平行的方向延伸；每一个存储层中，沿与衬底相平行布设的多个晶体管的第二极与同一条第三电极线电连接。
即就是，该第二电极线和第三电极线可以均为条状结构，并且可以相互垂直，第二电极线电连接与衬底相垂直布设的多个晶体管的栅极，第三电极线电连接与衬底相平行布设的多个晶体管的第二极。
在一种可能的实现方式中，第一金属层靠近衬底设置，第二金属层远离衬底设置。
即为电容器靠近衬底设置，晶体管远离衬底设置。
在另外一些实现结构中，第一金属层远离衬底设置，第二金属层可以靠近衬底设置。则就是电容器远离衬底设置，晶体管靠近衬底设置。
在另外一些实现结构中，存储阵列为DRAM存储阵列，或者，存储阵列为铁电存储阵列。
在一些实现结构中，所述多个存储层采用后道工艺形成在所述衬底上。
存储单元中的晶体管和电容器均为采用后道工艺制作，控制器可以通过前道工艺制作。该控制器可以包括译码器、驱动器、时序控制器、缓冲器或输入输出驱动中的一个或多个电路，还可以包括其他功能电路。该控制器可以控制本申请实施例中的第一电极线、第二电极线和第三电极线。
在完成前道工艺FEOL后，互连线，以及存储阵列均通过后道工艺BEOL制作。可以使得单位面积内的电路密度更大，从而提升单位面积的存储性能。
第二方面，本申请还提供了一种存储器，该存储器包括控制器和上述任一实现方式中的存储阵列，控制器与存储阵列电连接，控制器用于控制存储阵列的读写。
在本申请提供的存储器中，由于包括了上述实现方式中的存储阵列，在存储阵列中，晶体管和电容器沿与衬底相平行的方向排布，这样，可以将此种结构的存储单元沿着与衬底相垂直的方向，以及与衬底相平行的方向进行堆叠，实现三维堆叠，实现高密度集成，提升存储容量。
在一种可能的实现方式中，存储阵列和控制器被集成在同一个芯片中，且该芯片设置在基板上。
在一种可能的实现方式中，存储阵列被集成在第一芯片中，控制器被集成在第二 芯片中，且第一芯片和第二芯片均通过电连接结构设置在基板上。
在一种可能的实现方式中，存储阵列被集成在第一芯片中，控制器被集成在第二芯片中，第一芯片与第二芯片堆叠，并集成在基板上。
第三方面，本申请还提供了一种电子设备，包括处理器和上述任一实现方式中的存储器，处理器与存储器电连接，存储器用于存储处理器产生的数据。
本申请实施例提供的电子设备包括上述任一实现方式中的存储器，因此本申请实施例提供的电子设备与上述技术方案的存储器能够解决相同的技术问题，并达到相同的预期效果。
第四方面，本申请还提供了一种存储阵列的形成方法，该形成方法包括：
在衬底上堆叠多层介质层，多层介质层包括多组功能介质层，和位于相邻两组功能介质层之间的电隔离介质层，每一组功能介质层包括依次堆叠的第一功能介质层、第二功能介质层和第三功能介质层；
对多组功能介质层进行图案化处理，以形成堆叠的多个存储层，每一个存储层包括将第一功能介质层图案化后的第一金属层、将第三功能介质层图案化后的第二金属层，以及位于第一金属层和第二金属层之间的第二功能介质层，每一个存储层包括多个存储单元，每一个存储单元包括晶体管和电容器；
其中，晶体管包括第一极、第二极、栅极和沟道层；电容器包括第一电容电极、电容层和第二电容电极；晶体管的第一极和电容器形成在第一金属层中，晶体管的第二极形成在第二金属层中；栅极的至少部分和沟道层的至少部分形成在第二功能介质层中，沟道层环绕在栅极的外围；第一电容电极、电容层和第二电容电极沿与衬底相平行的方向堆叠，电容层环绕在第一电容电极的外围。
本申请提供的存储阵列的形成方法中，在衬底上堆叠多层介质层，其中一些介质层图案化为存储层，从而形成沿与衬底相垂直布设的多层存储层。例如，当需要制备两个存储层时，可以先堆叠七层介质层，七层介质层中的位于中间层的介质层作为电隔离介质层，其上三层和其下三层可以分别形成存储层。可以理解为在衬底上堆叠多层介质层后，可以同时形成多个存储层，而不是堆叠一层存储层后，再堆叠另一层存储层，这样的话，不仅可以简化制备工艺，还可以避免多层堆叠时，引起的对准工艺难度较大的问题。
另外，利用本申请给出的形成方法制得的存储阵列的存储单元，晶体管的沟道是环沟道结构，电容器的电容是环电容结构，从而使得该种结构的存储单元占据的面积接近4F 2，相比平面2D存储单元，缩小了存储单元尺寸。
还有，由于电容器属于一种环电容结构，相比相关技术中的沿与衬底相垂直方向延伸的柱状电容，环电容结构在实现增加存储容量的基础上，还不会给刻蚀工艺提出较大的挑战，从而，使得该存储阵列为高密度、大存储、低成本的存储阵列。
在一种可能的实现方式中，形成栅极包括：沿与衬底相垂直的方向，开设贯通多层介质层的第一通孔，并在第一通孔内填充导电材料，以形成晶体管的栅极。
即利用该形成方法可以制得与衬底相垂直的柱状栅极。
在一种可能的实现方式中，开设贯通多层介质层的第一通孔之后，在第一通孔内填充导电材料之前，形成方法还包括：在第一通孔内填充半导体材料，以在第一通孔 的内壁面上形成晶体管的沟道层。
从而，可以形成环栅的沟道结构，除外，该种结构的沟道层还可以增加与晶体管的源漏极的接触面积，以避免短沟道效应。
在一种可能的实现方式中，形成电容器的第一电容电极、电容层和第二电容电极，包括：在第一通孔内填充导电材料，形成栅极之前，在第一功能介质层内开设第一凹槽，第一凹槽的开口朝向第一通孔，在第一凹槽内形成第一电容电极、电容层和第二电容电极，以形成具有缺口且缺口朝向第一通孔的电容层。
这样，形成的电容层不仅包括与衬底相垂直的部分，还包括与衬底相平行的部分，进而，可以增加该电容器的电容容量。
在一种可能的实现方式中，形成电容器的第一电容电极、电容层和第二电容电极，包括：
在第一通孔内填充导电材料，形成栅极之后，沿与衬底相垂直的方向，开设贯通多层介质层的第二通孔；
在第一功能介质层内开设第二凹槽，第二凹槽的开口朝向第二通孔，第二凹槽的底面贯通至第一通孔，在第二凹槽内形成第一电容电极、电容层和第二电容电极，以形成具有缺口且缺口背离第一通孔的电容层。
这样形成的电容层也不仅包括与衬底相垂直的部分，还包括与衬底相平行的部分，以可以增加该电容器的电容容量。
在一种可能的实现方式中，开设贯通多层介质层的第二通孔之后，形成方法还包括：
在第二功能介质层内形成第三凹槽，第三凹槽的开口朝向第二通孔，在第三凹槽内填充半导体材料，以在第三凹槽的内壁面上形成晶体管的沟道层。
形成的沟道层不仅包括环绕在栅极外围的环绕部分，还包括与衬底平行的平面部分，以增加与晶体管的源漏极的接触面积。
附图说明
图1为现有技术中一种1T1C存储单元的工艺结构图；
图2为本申请实施例提供的一种电子设备中的电路图；
图3为本申请实施例提供的一种存储器的电路图；
图4a为本申请实施例提供的一种存储阵列和控制器的封装结构图；
图4b为本申请实施例提供的一种存储阵列和控制器的封装结构图；
图4c为本申请实施例提供的一种存储阵列和控制器的封装结构图；
图5为本申请实施例提供的一种存储器的三维结构示意图；
图6为本申请实施例提供的一种存储器的简易电路图；
图7为本申请实施例提供的一种存储器中一个存储单元的电路图；
图8为本申请实施例提供的一种存储阵列的电路图；
图9为本申请实施例提供的一种存储阵列的简易结构图；
图10为本申请实施例提供的一种存储阵列的三维工艺结构图；
图11为本申请实施例提供的一种存储阵列的三维工艺结构图；
图12为图11的A处放大图；
图13为本申请实施例提供的多个存储单元在衬底上的投影结构图；
图14为本申请实施例提供的一种存储单元的剖面图；
图15为本申请实施例提供的一种包括两个存储层的剖面图；
图16为本申请实施例提供的一种包括两个存储层的剖面图；
图17为本申请实施例提供的一种存储阵列的三维工艺结构图；
图18a至图18e为本申请实施例提供的一种存储阵列制作方法中各步骤完成后对应的工艺结构剖面图；
图19为本申请实施例提供的一种存储阵列的三维工艺结构图；
图20为本申请实施例提供的一种存储阵列的三维工艺结构图；
图21为本申请实施例提供的一个存储单元的结构图；
图22为本申请实施例提供的一种存储单元的剖面图；
图23为本申请实施例提供的一种存储阵列的三维工艺结构图；
图24a至图24h为本申请实施例提供的一种存储阵列制作方法中各步骤完成后对应的工艺结构剖面图；
图25为本申请实施例提供的一种存储阵列制作方法的流程框图；
图26a至图26n为本申请实施例提供的一种存储器制作方法中各步骤完成后对应的工艺结构剖面图；
图27a至图27h为本申请实施例提供的一种存储器制作方法中各步骤完成后对应的工艺结构剖面图。
附图标记：
100-衬底；
200-电子设备；
300-存储器；
31-存储阵列；
32-控制器；
33-基板；
400-存储单元；
Tr-晶体管；
11–第一极；
12–第二极；
13–栅极；
14–沟道层；141–环绕沟道；142a–第一平面沟道；142b–第二平面沟道；
15–栅介质层；
C-电容器；
21–第一电容电极；211–环绕电极；212–平面电极；212a–第一平面电极；212b–第二平面电极；
22–第二电容电极；
23–电容层；
500a1–第一功能介质层、500a2–第二功能介质层、500a3–第三功能介质层；500、500a、500b–介质层；
501、502、503-存储层；
50A1–第一金属层；
50A2–第二金属层；
51–介质层；
61–通孔；611–第一通孔；612–第二通孔；
71、711、712、713–凹槽；
8–金属层。
具体实施方式
下面结合附图介绍本申请给出的实施例。
本申请实施例提供一种电子设备。图2为本申请实施例提供的一种电子设备200中的电路框图，该电子设备200可以是终端设备，例如手机，平板电脑，智能手环，也可以是个人电脑(personal computer，PC)、服务器、工作站等。
如图2，电子设备200可以包括总线205，以及与总线205连接的片上系统(system on chip，SOC)210。SOC210可以用于处理数据，例如处理应用程序的数据，处理图像数据，以及缓存临时数据。在一种实施方式中，SOC210可以包括用于处理应用程序的应用处理器(application processor，AP)211，用于处理图像数据的图像处理单元(graphics processing unit，GPU)212，以及用于缓存高速数据的第一随机存取存储器(random access memory，RAM)213。该第一RAM213可以是静态随机存取存储器(static random access memory，SRAM)或嵌入式闪存(embedded flash，eflash)等。上述AP211、GPU212和第一RAM213可以被集成于一个裸片(die)中，也可以被分别设置在多个die中。
再如图2所示，电子设备200还可以包括通过总线205与SOC210连接的第二RAM220。该第二RAM220可以是动态随机存取存储器(dynamic random access memory，DRAM)。第二RAM220可以用于保存易失性数据，例如SOC210产生的临时数据。第二RAM220的存储容量通常大于第一RAM213，但读取速度通常慢于第一RAM213。
此外，电子设备200还可以包括通过总线205与SOC210连接的通信芯片230和电源管理芯片240。通信芯片230可以用于协议栈的处理，或对模拟射频信号进行放大、滤波等处理，或同时实现上述功能。电源管理芯片240可以用于对其他芯片进行供电。在一种实施方式中，SOC210和第二RAM220可以被封装在一个封装结构中，例如采用2.5D(dimension)或3D封装等，以获得更快的芯片间数据传输速率。
图3为本申请实施例提供的一种可以被应用在电子设备中的存储器300的电路框图。在一种实施方式中，存储器300可以铁电随机存取存储器(Ferroelectric Random Access Memory，FeRAM或FRAM)，或者，可以是动态随机存取存储器(dynamic random access memory，DRAM)。本申请对存储器300的应用场景不做限定。
如图3所示，存储器300包括存储阵列31和用于访问存储阵列31的控制器32，其中，控制器32用于控制存储阵列31的读写操作。
其中，图3所示的存储阵列31和控制器32具有多种可以实现的封装结构，比如，下述给出了几种可以实现的封装结构。
图4a是本申请实施例给出的存储阵列31和控制器32的其中一种封装结构，即是，存储阵列31和控制器32是两个彼此独立的芯片，存储阵列31和控制器32分别被集成在基板33上。比如，存储阵列31和控制器32可以通过布设在基板33上的金属走线实现电导通。在此种结构中，由于存储阵列31和控制器32为两个相独立的芯片，因此该存储阵列31可以被称为独立(stand-alone)存储器。
图4b是本申请实施例给出的存储阵列31和控制器32的另一种封装结构。此结构中，和上述图4a类似的是，存储阵列31和控制器32是两个彼此独立的芯片，因而该存储阵列31也可以被称为独立存储器。和上述图4a不同的是，在图4b中，存储阵列31和控制器32相堆叠，比如，存储阵列31和控制器32之间可以通过硅通孔(through silicon via，TSV)或者重布线层(redistribution layer，RDL)实现互连。
图4c是本申请实施例给出的存储阵列31和控制器32的又一种封装结构。在此种示例的结构中，将存储阵列31和控制器32集成到同一芯片3，芯片3被集成在基板33上，因此，该存储阵列31可以被称为嵌入式存储器。
在上述图4c所示的结构中，如图5所示，控制器32可以通过前道(front end of line，FEOL)制程被集成在衬底上，互连线和存储阵列通过后道(back end of line，BEOL)制程集成在控制器32上。利用这里的控制器可以产生控制信号，这些控制信号可以是读写控制信号，用于控制存储阵列中数据的读写操作，除外，这里的控制器也可以包括模拟电路部分，例如灵敏放大器等。
还有，再参阅图5，上述的存储阵列31可以是一个存储层，也可以是沿与衬底垂直的Z方向堆叠的多个存储层。当包含两层或者更多层存储层的情况下，这样的存储器可以被称为三维集成存储器结构，以提升存储容量。
在一种实施方式中，存储器中的存储阵列31可以包括图6所示的多个阵列排布的存储单元400，其中每个存储单元400都可以用于存储1比特(bit)或者多bit的数据。存储阵列31还可以包括字线(word line，WL)和位线(bit line，BL)等电极线。每一个存储单元400都与对应的字线WL和位线BL电连接。不同的存储单元400可以通过WL和BL电连接。上述WL和BL中的一个或多个用于通过接收控制电路输出的控制电平，选择存储阵列中待读写的存储单元400，从而实现数据的读写操作。
存储器中的控制器32可以包括图6所示的译码器320、驱动器330、时序控制器340、缓存器350或输入输出驱动360中的一个或多个电路结构。
在图6所示存储器300结构中，译码器320用于根据接收到的地址进行译码，以确定需要访问的存储单元400。驱动器330用于根据译码器320产生的译码结果来控制信号线的电平，从而实现对指定存储单元400的访问。缓存器350用于将读取的数据进行缓存，例如可以采用先入先出(first-in first-out，FIFO)来进行缓存。时序控制器340用于控制缓存器350的时序，以及控制驱动器330驱动存储阵列310中的信号线。输入输出驱动360用于驱动传输信号，例如驱动接收的数据信号和驱动需要发送的数据信号，使得数据信号可以被远距离传输。
上述存储阵列31、译码器320、驱动器330、时序控制器340、缓存器350和输入 输出驱动360可以集成于一个芯片中，也可以分别集成于多个芯片中。
本申请实施例涉及的存储器300可以是动态随机存取存储器(dynamic random access memory，DRAM)。比如，可以是包括1T1C存储单元的DRAM。
另外，本申请实施例涉及的存储器300也可以是铁电随机存取存储器(ferroelectric random access memory，FeRAM)，比如，也可以是包含1T1C存储单元的FeRAM。
图7是本申请实施例给出的存储器300中的一个存储单元400的电路图。如图7，该存储单元400属于1T1C的gain-cell的存储单元结构，也就是在一个存储单元400中包括一个晶体管Tr和一个电容器C。比如，晶体管Tr可以选择薄膜晶体管(Thin film transistor，TFT)结构。
其中，晶体管Tr的第一极与电容器C的第一电容电极电连接，晶体管Tr的第二极与位线(bit line，BL)电连接，晶体管Tr的栅极与字线(word line，WL)电连接；以及，电容器C的第二电容电极与板线(plate line，PL)电连接。
在图7所示的存储单元中，板线(plate line，PL)可以被称为第一电极线，字线(word line，WL)可以被称为第二电极线，位线(bit line，BL)可以被称为第三电极线。
示例的，当图7所示存储单元为FeRAM存储单元，即形成在第一电容电极和第二电容电极之间的电容层为铁电材料层。当然，图7所示存储单元也可以是DRAM存储单元。
比如，当图7所示存储单元为FeRAM存储单元时，在写入阶段，字线WL用于接收字线控制信号，使得晶体管Tr导通，位线BL用于接收位线控制信号，铁电电容电连接的板线PL用于接收板线控制信号，位线控制信号和板线控制信号的电压差使被选中的铁电电容的铁电层发生正极化或者发生负极化，以在被选中的铁电电容中写入不同的逻辑信息。比如，当铁电层发生正极化时，写入逻辑信号“0”，再比如，当铁电层发生负极化时，写入逻辑信号“1”。
在本申请所涉及的实施例中，例如上述图7所示的晶体管Tr可以选择NMOS(N-channel metal oxide semiconductor，N沟道金属氧化物半导体)管，或者可以选择PMOS(P-channel metal oxide semiconductor，P沟道金属氧化物半导体)管。
另外，在本申请所涉及的实施例中，晶体管Tr的漏极(drain)或源极(source)中的一极称为第一极，相应的另一极称为第二极，晶体管的控制端为栅极。晶体管的漏极和源极可以根据电流的流向而确定。
图8示例的是图7所示存储单元400呈阵列排布的电路图。见图8，沿同一方向排布的多个存储单元的晶体管Tr的栅极可以与同一条字线WL电连接；以及，沿同一方向排布的多个存储单元的晶体管Tr的第二极可以与同一条位线BL电连接；这些多个电容器C的第二电容电极可以与同一板线PL电连接，比如，该板线PL可以接地。
在诸如上述图7所示的DRAM存储单元或者FeRAM存储单元中，本申请实施例给出了一些可以提高存储密度的存储单元工艺结构，具体见下述。
本申请实施例提供的存储阵列中，如图9所示，包括了多个存储层，且这些多个存储层沿着与衬底100相垂直的方向堆叠。其中，相邻两个存储层之间被电隔离介质层电隔离开。在每一个存储层中，可以包括堆叠的多层金属层，并且相邻两层金属层 之间被介质层电隔离开，存储单元可以被形成在这些金属层中。
图10和图11是本申请实施例给出的一种存储阵列的三维工艺结构图，具体的，可以通过前道制程将存储阵列31堆叠在衬底100上，或者，通过后道制程集成在衬底100上。
如图11，示例性的给出了存储阵列31包括三个存储层，分别为存储层501、存储层502和存储层503。存储层501和存储层502之间，以及存储层502和存储层503之间，均被介质层500电隔离开。
继续参阅图11，每一个存储层包括第一金属层50A1和第二金属层50A2，以及位于第一金属层50A1和第二金属层50A2之间的介质层51。
图7所示的存储单元可以被形成在第一金属层50A1、第二金属层50A2和介质层51中，具体可以实现的工艺结构可以见下述。
再参阅图11和图12，图12是图11的A处放大图。一并结合图11和图12，晶体管Tr和电容器C被集成在第一金属层50A1、第二金属层50A2和介质层51中。例如，晶体管Tr的第一极11被形成在第一金属层50A1中，晶体管Tr的第二极12被形成在第二金属层50A2中，晶体管Tr的栅极13的至少部分和沟道层14的至少部分贯穿在介质层51中；以及，电容器C的第一电容电极21、电容层23和第二电容电极22均被形成在第一金属层50A1中。
也就是，利用堆叠的第一金属层50A1、第二金属层50A2和介质层51集成了一层存储单元阵列。
如图11和图12所示的晶体管Tr的栅极13的至少部分和沟道层14的至少部分贯穿在介质层51中，可以理解为，栅极13的至少部分和沟道层14的至少部分，沿与衬底相垂直的方向贯穿介质层51。
相比一些相关技术中，利用三层、四层甚至更多层的金属层集成一层存储单元阵列，本申请给出的存储阵列可以明显的减少金属层的堆叠层数。这样的话，在具有相等金属层的存储阵列中，本申请可以集成更多的存储层，集成更多的存储单元，以提升该存储器的存储容量。
继续参阅图11和图12，在此实施例的存储单元的晶体管Tr中，栅极13呈柱状结构贯穿于介质层51中，沟道层14环绕在栅极13的外围。即就是该晶体管Tr的沟道为一种环沟道结构。
还有，见图11和图12，在此实施例的存储单元的电容器C中，第一电容电极21、电容层23和第二电容电极22沿与衬底100相平行的方向堆叠在第一金属层50A1中，并且，电容层23环绕在第一电容电极21的外围，第二电容电极22环绕在电容层23的外围。即为该电容器为一种环电容结构。环电容结构可以增加电容面积，以增加电容容量，提升该存储器的存储性能。
本申请实施例给出的见图11和图12所示的存储单元结构，不仅可以实现三维堆叠，且每一个存储单元所占据的面积较小，从而，也可以相对应的提升存储密度。比如，图13示出的是图11位于一个存储层中的多个存储单元400在衬底100上的正投影的面积。其中，每一个存储单元400所占的区域基本为2F×2F＝4F 2，占用面积小，进而，可以在单位面积上集成更多的存储单元400。
除此之外，环电容结构相比柱状的电容结构，为了满足高电容时，需要使得柱状的电容结构的深宽比较高，这样，会给形成柱状电容的通孔的开设提出工艺挑战。然而，在本申请实施例中，环状电容可以采用沉积工艺实现，不会过大的增加工艺难度。
以及，关于图11和图12所示存储阵列在制备过程中，可以沿着与衬底相垂直的方向堆叠多层介质层，比如，需要制备两个存储层时，可以堆叠7层介质层，然后对这些介质层进行图案化处理，同时制得两个存储层，即将三层介质层图案化为一个存储层，另外三层介质层图案化为另一个存储层，两层存储层再被一层介质层隔离开，而不是在制得一层存储层后，又再制得另一层存储层。所以，本申请实施例给出的存储阵列在制备时，可以简化制备工艺流程，降低工艺繁琐性，具体的可以实现的工艺方法后续进行介绍，以及结合工艺方法介绍如何利用一次工艺，同时制备多个存储层，在此不予描述。
继续参阅图12，贯穿介质层51的栅极13的一端可以延伸至第一金属层50A1中，并通过栅介质层15与第一极11电隔离开。
栅极13的另一端也可以延伸至第二金属层50A2中，并通过栅介质层15与第二极12电隔离开。
再如图12所示，由于晶体管Tr的第一极11和电容器C均形成在第一金属层50A1中，从而，在一些可以选择的实施例中，如图12，可以使得晶体管Tr的第一极11和电容器C的第一电容电极21共用同一电极，以简化工艺结构。即就是形成的金属层，不仅可以作为晶体管Tr的第一极11，还可以作为电容器C的第一电容电极21。
图11和图12还给出了沟道层14的一种可以实现的结构。如图11和图12，贯穿在介质层51的、且环绕栅极13的沟道层14可以延伸至第一金属层50A1中，并与第一金属层50A1中的第一极11欧姆接触，且第一极11环绕在沟道层14的外围。这样，可以增加沟道层14与第一极11的接触面积，从而可以避免短沟道效应，比如抑制漏电流增大，电子迁移率较低等。
类似的，贯穿在介质层51的环绕栅极13的沟道层14还可以延伸至第二金属层50A2中，并与第二金属层50A2中的第二极12欧姆接触，且第二极12环绕在沟道层14的外围。和上述第一极11类似，也同样可以增加第二极12与沟道层14的接触面积，以提升沟道层14中的电子迁移率。
上述结合图11和图12介绍了晶体管Tr的第一极11、第二极12、栅极13和沟道层14可以实现的一些工艺结构，下面再介绍附图介绍电容器C可以实现的工艺结构。
图14给出了图11和图12中一个存储单元的沿X-Z剖切的剖面图。其中，第一电容电极21不仅包括环绕在沟道层14外围的环绕电极211，还包括与环绕电极211连接的，且与衬底相平行布设的平面电极212，平面电极212呈环形结构，围绕在环绕电极211的外围。
如图14所示的引出平面电极212的情况下，会使得该种结构的第一电容电极21不仅具有与电容层23接触的水平接触面N2，还具有与电容层23接触的竖直接触面N1。该水平接触面N2是与衬底相平行的面，竖直接触面N1是与衬底相垂直的面。
相比仅具有环绕电极211，本申请实施例给出的第一电容电极21可以增加与电容层23的接触面积，即可以增加电容层23的电容面积，从而，可以提升该电容器C的 电容量。
继续参阅图14，电容层23形成在第一电容电极21的水平接触面N2和竖直接触面N1上。第二电容电极22形成在电容层23上，以使得电容层23被夹持在第一电容电极21和第二电容电极22之间。
图15和图16分别给出了包括存储层501和存储层502的存储阵列沿X-Z剖切的剖面图。在图15中，存储层501和存储层502之间具有一层介质层500，即通过一层介质层将存储层501和存储层502电隔离开，存储层501中的沟道层14，与存储层502中的沟道层14在介质层500处被分断开。而在图16中，存储层501和存储层502之间具有两层介质层，分别为介质层500a和介质层500b，存储层501的沟道层14可以延伸至两层介质层中靠近存储层501的介质层500a内，并且，存储层501中的沟道层14，与存储层502中的沟道层14在介质层500b处被分断开。
在图10和图11所示的存储阵列中，不仅示出了每一个存储层中的存储单元(包括晶体管Tr和电容器C)，还示出了控制存储单元读写的字线WL、位线BL和板线PL的可实现的工艺结构。
图17给出了图10和图11实施例中字线WL、位线BL和板线PL的布设方式。具体见图17，字线WL沿与衬底100相垂直的方向延伸，并且，将多个存储层中的沿与衬底相垂直方向布设的多个晶体管Tr的栅极13电连接。即就是，沿与衬底相垂直方向布设的多个晶体管Tr的栅极13与同一条字线WL电连接。比如，字线WL沿Z方向延伸，存储层501、存储层502和存储层503中，沿Z方向布设的多个晶体管Tr的栅极13与同一条字线WL电连接于一起。
也就是说，字线WL贯穿了多个存储层，以及贯穿每相邻两个存储层之间的介质层。当然，在该存储阵列中，在位于多个存储层上方的位置会形成字线WL层，以将图10所示的多个字线WL进行互连。
图17所示实施例中，位线BL沿与衬底相平行的方向延伸，并且，将每一个存储层中的沿与衬底相平行方向布设的多个晶体管Tr的第二极12电连接。即为，沿与衬底相平行方向布设的多个晶体管Tr的第二极12与同一条位线BL电连接。比如，位线BL沿Y方向延伸，存储层501中，沿Y方向布设的多个晶体管Tr的第二极12与同一条位线BL电连接于一起。且相邻两个位线BL之间被介质层电隔离开。
关于板线PL的布设方式，具有多种可以实现的结构，见图17，板线PL呈板状结构，板线PL位于第一金属层50A1中，且位于第一金属层50A1中的电容器C的第二电容电极22均与该板状的板线PL电连接。比如，存储层501中，位于第一金属层50A1中的板线PL电连接存储层501中的所有电容器C的第二电容电极22。一种示例的，该板线PL可以接地。
在制得上述实施例涉及的存储单元结构的工艺流程中，可以采用下述工艺方式：
如图18a，可以在堆叠的多个介质层内开设贯通这些介质层的通孔61，该通孔61可以用于填充沟道层14和栅极13。
这些介质层中的一部分作为功能介质层，用于形成存储层，另一部分作为电隔离层，用于将相邻两个存储层电隔离开。比如，图18a所示的，这些功能介质层包括依次堆叠的第一功能介质层500a1、第二功能介质层500a2和第三功能介质层500a3，第 一功能介质层500a1、第二功能介质层500a2和第三功能介质层500a3可以用于形成一个存储层。
并且，该通孔61贯通这些功能介质层和电隔离的介质层。
如图18b，可以在第一功能介质层500a1内开设与通孔61相连通的凹槽71，然后在凹槽71的内壁面上形成金属层，再回刻掉凹槽71的靠近通孔61的边缘的金属层，以形成第二电容电极22。
如图18c，再在凹槽71内形成电容层23，进而，就会形成图18c所示的具有缺口，且缺口朝向通孔61的电容层结构。
如图18d，再在凹槽71内填充金属层，以形成电容器C的第一电容电极21，从而，制得电容器C。
如图18e，将电容器C所处介质层的其余介质层刻蚀掉，再填充金属层，以形成板状的板线PL，使得板线PL与电容器C的第二电容电极22接触电连接。
见上述图18b所示，回刻掉凹槽的靠近通孔的边缘的金属层，是为了避免形成的板线PL和电容层与沟道层14接触，以无法形成图7所示电路结构的存储单元。
由图18a至图18e所示，制得的电容层23不仅包括与衬底相垂直的部分，还包括与衬底相平行的部分，从而，可以增加电容层的面积，以提升电容容量。
在上述涉及的存储阵列中，每一个存储层中的形成电容器C的第一金属层50A1靠近衬底设置，第二金属层50A2远离衬底设置，也就是电容器C相对晶体管Tr更加靠近衬底。
当然，在另外一些工艺结构中，也可以是形成电容器C的第一金属层50A1远离衬底设置，而第二金属层50A2靠近衬底设置。
本申请实施例还给出了另外一种包含1T1C的存储单元结构，见图19和图20所示，图19和图20示出的也是包含多个1T1C存储单元的存储阵列。
图19所示的1T1C存储单元，可以是FeRAM的1T1C存储单元，或者，也可以是DRAM的1T1C存储单元。
图20所示存储阵列工艺结构和上述图11所示存储阵列工艺结构相比，相同之处在于：也属于三维堆叠存储阵列，三维堆叠存储阵列也是包含多个存储层，例如，图20示出的存储层501、存储层502和存储层503；以及，在图20中，每一个存储层也包括第一金属层50A1和第二金属层50A2，以及位于第一金属层50A1和第二金属层50A2之间的介质层51。
相同之处还包括：如图21所示，图21示出的是图20的一个存储单元的放大图，其中，晶体管Tr的第一极11被形成在第一金属层50A1中，晶体管Tr的第二极12被形成在第二金属层50A2中；电容器C的第一电容电极21、电容层23和第二电容电极22均被形成在第一金属层50A1中。
下述介绍图20所示实施例与图11所示实施例的不同之处。
如图21所示的存储单元，晶体管Tr的栅极13均延伸至第一金属层50A1和第二金属层50A2中，但是，晶体管Tr的沟道层14仅形成在介质层51中，并未延伸至第一金属层50A1和第二金属层50A2中。
图22给出了图20中一个存储单元沿X-Z剖切的剖面图。其中，沟道层14包括 环绕在栅极13外围的环绕沟道141，还包括与环绕沟道141相连接且平行衬底100的第一平面沟道142a，第一平面沟道142a与晶体管Tr的第二极12欧姆接触，实现电连接。
继续参阅图22，沟道层14还包括与环绕沟道141相连接且平行衬底100的第二平面沟道142b，第一平面沟道142a与第二平面沟道142b相对布设，第二平面沟道142b与晶体管Tr的第一极11欧姆接触，实现电连接。
图22所示结构中的电容器C中的第一电容电极21、电容层23的工艺结构也和上述图10所示结构不一样。
如图22，第一电容电极21包括环绕电极211、第一平面电极212a和第二平面电极212b，第一平面电极212a和第二平面电极212b均与衬底相平行，且第一平面电极212a和第二平面电极212b通过环绕电极211连接，以使得第一电容电极21内形成具有开口的凹腔，且该凹腔的开口背离柱状的栅极13。电容层23形成在凹腔的内壁面上，以及，第二电容电极22形成在电容层23上。
依照图22工艺结构，晶体管Tr的第一极11和电容器C的第一电容电极21也共用同一电极。
并且，沟道层14的第一平面沟道142a与晶体管Tr的第二极12欧姆接触，沟道层14的第二平面沟道142b与电容器C的第一平面电极212a欧姆接触。
对比图14和图22，可以理解为，在图14中，形成的电容层23为缺口朝向栅极13的电容结构，而在图22中，形成的电容层23为缺口背离栅极13的电容结构。
无论是图14，还是图22所示电容层23结构，均不仅包括与衬底垂直的竖直部分，还包括与衬底相平行的水平部分。通过竖直部分和水平部分的布设，可以增加电容面积，以提升电容容量。
图23给出了图20存储阵列中字线WL、位线BL和板线PL的布设方式，具体可实现的工艺结构如下。
图23所示字线WL结构中，和上述实施例图17所示字线WL结构一样，字线WL沿与衬底100相垂直的方向延伸，并且，将多个存储层中的沿与衬底相垂直方向布设的多个晶体管Tr的栅极13电连接。即就是，沿与衬底相垂直方向布设的多个晶体管Tr的栅极13与同一条字线WL电连接。比如，字线WL沿Z方向延伸，多个存储层中沿Z方向布设的多个晶体管Tr的栅极13与同一条字线WL电连接于一起。
图23所示位线BL结构中，和上述图17所示位线BL结构也一样，位线BL沿与衬底相平行的方向延伸，并且，将每一个存储层中的沿与衬底相平行方向布设的多个晶体管Tr的第二极12电连接。即就是，沿与衬底相平行方向布设的多个晶体管Tr的第二极12与同一条位线BL电连接。比如，位线BL沿Y方向延伸，每一个存储层中沿Y方向布设的多个晶体管Tr的第二极12与同一条位线BL电连接于一起。
关于板线PL的布设方式，在图23中，板线PL沿与衬底相垂直的方向延伸，并且，将多个存储层中的沿与衬底相垂直方向布设的多个晶体管Tr的第二极12电连接。也即为，沿与衬底相垂直方向布设的多个电容器C的第二电容电极22与同一条板线PL电连接。比如，板线PL沿Z方向延伸，多个存储层中沿Z方向布设的多个晶体管Tr的第二极12与同一条板线PL电连接于一起。
还有，继续参阅图23，在每一个存储层中，沿同一方向的相邻的两个电容器C的第二电容电极22可以与同一条板线PL电连接。例如，沿X方向排布的相邻的两个电容器C的第二电容电极22与同一条板线PL电连接。
在制得图21和图22所示结构的工艺流程中，可以采用下述工艺方式：
如图24a，可以在堆叠的多层介质层内开设贯通这些介质层的第一通孔611，该第一通孔611可以用于填充栅极13。
和上述图18a所示工艺流程类似，这些介质层中的一部分作为功能介质层，用于形成存储层，另一部分作为电隔离层，用于将相邻两层存储层电隔离开。比如，图24a所示的，这些功能介质层包括依次堆叠的第一功能介质层500a1、第二功能介质层500a2和第三功能介质层500a3，第一功能介质层500a1、第二功能介质层500a2和第三功能介质层500a3可以用于形成一个存储层。
如图24b，在第三功能介质层500a3内开设与该第一通孔611相连通的凹槽711，然后在凹槽711内填充金属层，以形成晶体管Tr的第二极12。
如图24c，再在第一通孔611内形成栅介质层15和栅极13。
如图24d，然后在堆叠的多层介质层内开设贯通这些介质层的第二通孔612，并且第二通孔612位于相邻两个第一通孔611之间。
如图24e，在第二功能介质层500a2内开设平行衬底且与第二通孔612相连通的凹槽712，该凹槽712贯通至栅介质层15。
如图24f，在如图24e制得的凹槽712的内壁面上填充半导体材料，以在凹槽712的内壁面上形成沟道层14，且沟道层14的缺口背离形成的栅极13。
如图24g和图24h，在第一功能介质层500a1内开设平行衬底且与第二通孔612相连通的凹槽713，该凹槽713的内壁面上依次形成电容器C的第一电容电极21、电容层23和第二电容电极22。
这样的话，制得的沟道层14不仅包括环绕沟道，还包括平面沟道；以及，制得的电容层23不仅包括与衬底相垂直的部分，还包括与衬底相平行的部分。
上述各个实施例提供的1T1C存储单元中，晶体管Tr的各个功能层、电容器C的各个功能层，以及字线WL、位线BL和板线PL可以选择的材料具有多种，下述给出了可以选择的部分材料。
在可选择的材料中，晶体管Tr的第一极、第二极、栅极、字线WL、位线BL和板线PL的材料均为导电材料，例如金属材料。在可选择的实施方式中，可以为TiN(氮化钛)、Ti(钛)、Au(金)、W(钨)、Mo(钼)、In-Ti-O(ITO，氧化铟锡)、Al(铝)、Cu(铜)、Ru(钌)、Ag(银)等导电材料中的一种或多种。
在可选择的材料中，晶体管Tr的沟道层14可以选择Si(硅)、poly-Si(p-Si，多晶硅)、amorphous-Si(a-Si，非晶硅)、In-Ga-Zn-O(IGZO，铟镓锌氧化物)多元化合物、ZnO(氧化锌)、ITO(氧化铟锡)、TiO 2(二氧化钛)、MoS 2(二硫化钼)、WS 2(二硫化钨)、石墨烯、黑磷等半导体材料中的一种或多种。
上述的晶体管Tr栅介质层的材料可以SiO 2(二氧化硅)、Al 2O 3(氧化铝)、HfO 2(二氧化铪)、ZrO 2(氧化锆)、TiO 2(二氧化钛)、Y 2O 3(三氧化二钇)和Si 3N 4(氮化硅)等绝缘材料中的一种或多种。
电容器C中的第一电容电极21和第二电容电极22均为导电材料。在可以选择的材料中，可以为TiN(氮化钛)、Ti(钛)、Au(金)、W(钨)、Mo(钼)、In-Ti-O(ITO，氧化铟锡)、Al(铝)、Cu(铜)、Ru(钌)、Ag(银)等导电材料中的一种或多种。
电容器C中的电容层23可以选择可以为SiO2、Al2O3、HfO2、ZrO2、TiO2、Y2O3、Si3N4、HAO等绝缘材料，也可以为ZrO2,HfO2,Al掺杂HfO2，Si掺杂HfO2，Zr参杂HfO2，La掺杂HfO2，Y掺杂HfO2等铁电材料，或者基于该材料的进行其他元素掺杂的材料以及它们的任意组合。
上述结合附图介绍了本申请实施给出的可以实现的包括1T1C存储单元的三维存储阵列，下面结合附图详细介绍本申请实施例给出的制备方法，以制得包含有1T1C存储单元的三维存储阵列，具体见下述。
图25示例性的给出了制备存储阵列的流程框图。
步骤S1：在衬底上堆叠多层介质层，多层介质层包括多组功能介质层，和位于相邻两组功能介质层之间的隔离介质层，每一组功能介质层包括依次堆叠的第一功能介质层、第二功能介质层和第三功能介质层。
这些多层介质层中的相邻两层介质层的材料可以不同。比如，相邻两层介质层中的一层选择SiO 2(二氧化硅)、Al 2O 3(氧化铝)、HfO 2(二氧化铪)、ZrO 2(氧化锆)、TiO 2(二氧化钛)、Y 2O 3(三氧化二钇)和Si 3N 4(氮化硅)等绝缘材料中的一种时，另一层可以选择SiO 2(二氧化硅)、Al 2O 3(氧化铝)、HfO 2(二氧化铪)、ZrO 2(氧化锆)、TiO 2(二氧化钛)、Y 2O 3(三氧化二钇)和Si 3N 4(氮化硅)等绝缘材料中的另外一种。
示例的，当需要制得三个存储层时，可以在衬底上堆叠十一层介质层，每三层介质层用来制得一个存储层。每三层介质层之间的一层介质层作为相邻两个存储层之间的电隔离层。
依照如此设计，当需要制得N个存储层时，就需要依次堆叠3N+(N-1)层介质层。
步骤S2：对多组功能介质层进行图案化处理，以形成堆叠的多个存储层，每一个存储层包括将第一功能介质层图案化后的第一金属层、将第三功能介质层图案化后的第二金属层，以及位于第一金属层和第二金属层之间的第二功能介质层，每一个存储层包括多个存储单元，每一个存储单元包括晶体管和电容器；
其中，晶体管包括第一极、第二极、栅极和沟道层；电容器包括第一电容电极、电容层和第二电容电极；晶体管的第一极和电容器形成在第一金属层中，晶体管的第二极形成在第二金属层中；栅极的至少部分和沟道层的至少部分形成在第二介质层中，沟道层环绕在栅极的外围；第一电容电极、电容层和第二电容电极沿与衬底相平行的方向堆叠，电容层环绕在第一电容电极的外围。
利用本申请实施例给出的制备方法制得三维存储阵列时，是先在衬底上堆叠多层介质层，然后在这些多层介质层上进行图案化处理，以同时制得多个存储层，而不是制得一个存储层后，再制得另一个存储层。这样的话，从工艺角度讲，可以简化制备工艺，降低制造成本，还可以避免堆叠多个存储层时，对准精度逐渐降低的现象。
下面结合附图对上述步骤S1和步骤S2所涉及的具体工艺流程进行介绍。
图26a至图26n给出了制得本申请实施例一种存储阵列的工艺过程中每一步骤完成后的工艺结构。
如图26a，在衬底上堆叠多层介质层，多层介质层包括多组功能介质层，和位于相邻两组功能介质层之间的电隔离介质层500b，每一组功能介质层包括依次堆叠的第一功能介质层500a1、第二功能介质层500a2和第三功能介质层500a3。
比如，图26a示出了两组功能介质层，从而，可以制得堆叠的两个存储层。
另外，相邻两层介质层可以采用不同的介质材料，上述介绍了可以选择的多种介质材料，在此不再赘述。
还有，在图26a示例的给出了两组功能介质层之间具有两层电隔离介质层500b。
如图26b，开设多个开口K1，且每一个开口K1贯通多层介质层。
比如，多个开口K可以沿着与衬底相平行的X方向间隔排布。
如图26c，在每一个开口K1内填充介质材料，以将开口K1填满。
如图26d，在每相邻两个开口K1之间开设多个间隔排布的通孔61，位于相邻两个开口K1之间的多个通孔61也可以沿着与X方向垂直的Y方向排布。
并且，每一个通孔61贯通这些多层介质层。该通孔61是用于填充导电材料，形成字线WL。
如图26e，选择性刻蚀第三功能介质层500a3，以在第三介质层500a3上形成多个凹槽711，且这些多个凹槽711间隔形成在第三功能介质层500a3中。相邻两个凹槽711之间被介质层隔离开。
以及，凹槽711环绕在图26d制得的通孔61的外围，因为该凹槽711是为了形成晶体管Tr的第二极12。
如图26f，在图26e开设的凹槽711内填充金属，以制得晶体管Tr的第二极12。
除此之外，在采用沉积工艺制得图26f的第二极12时，可能会在通孔61内也沉积金属，基于此，需要将通孔61内的金属回刻掉。
如图26g，选择性刻蚀第一功能介质层500a1，以在第一功能介质层500a1上形成多个凹槽712，且这些多个凹槽712的位置与如图26e开设的凹槽711的位置相对应。
如图26h，在凹槽712的壁面上形成金属层8。其中，为了清楚显示局部图，图26h示出的是图26g的部分结构图。
如图26i，将凹槽712的靠近通孔61的边缘位置处的金属层回刻掉。
如图26j，填充电容材料，以在图26i制得的金属层上，以及凹槽712的靠近通孔61的边缘位置形成电容层23。
由于电容材料会形成在通孔61内，进而，需要将通孔61内的电容材料刻蚀掉。
如图26k，在凹槽712的剩余空间内填充金属材料，以形成电容器C的第一电容电极21。
类似的，需要将填充的通孔61内的金属材料刻蚀掉。
如图26l，在通孔61的内壁面上依次堆叠栅介质层15、沟道层14和金属层，该金属层形成该存储阵列的字线WL。
沿与衬底相平行的Y方向，将每一个第三功能介质层500a3上的位于相邻两个第 二极12之间的介质层刻蚀掉，以使得沿与衬底相平行的Y方向的多个第二极12电连接，形成位线BL。
另外，将电隔离介质层500b刻蚀掉，以使得图26l形成的沿与衬底相垂直的，位于电隔离介质层500b中的沟道层被隔断，形成图26m所示结构。
如图26n，选择性刻蚀第二功能介质层500a2，填充金属PL使得位于同一层上的电容层的第二电容电极通过板线PL互联在一起，即可形成最终的3D 1T1C存储阵列。
其中，为了清楚显示局部图，图26h至图26n示出的是存储阵列形成过程中的部分结构图。
基于上述的3D 1T1C存储阵列制备方法可以看出：堆叠多层介质层后，可以利用刻蚀开口、选择性刻蚀、沉积等工艺，同时制得多个存储层。而不是制得一个存储层后，再制得另一个存储层。
若采用堆叠一层存储阵列后，再堆叠另一层存储阵列的方式制得存储器时，随着存储密度不断增加，堆叠层数也随之增加，进而对光刻对准精度要求也越来越高，如果下一层存储阵列结构与上一层存储阵列结构对准精度较低时，可能会影响读写性能。然而，采用本申请实施例提供的存储阵列制备方法，对光刻对准精度要求较低，也不会给工艺提出较高的挑战，这样的话，不仅可以简化工艺制程，降低工艺难度，还会提升产品优良率，提升存储器的读写性能，另外，也会降低该存储器的制造成本。
图27a至图27h给出了制得本申请实施例一种存储阵列的工艺过程中每一步骤完成后的工艺结构。
如图27a，在衬底100上堆叠多层介质层，多层介质层包括多组功能介质层，和位于相邻两组功能介质层之间的电隔离介质层500，每一组功能介质层包括依次堆叠的第一功能介质层500a1、第二功能介质层500a2和第三功能介质层500a3。
比如，图27a示出了两组功能介质层，从而，可以制得堆叠的两个存储层。
相邻两层介质层可以采用不同的介质材料，上述介绍了可以选择的多种介质材料，在此不再赘述。
继续如图27a，开设多个间隔排布的第一通孔611，并且，每一个第一通孔611贯通这些多层介质层。该第一通孔611是用于填充导电材料，形成字线WL。
如图27b，选择性刻蚀第三功能介质层500a3，以在第三介质层500a3上形成多个凹槽，且这些多个凹槽间隔形成在第三功能介质层500a3中。相邻两个凹槽之间被介质层隔离开。
以及，凹槽环绕在图27b制得的第一通孔611的外围，因为该凹槽是为了形成晶体管Tr的第二极12。
在开设的凹槽内填充金属，以制得晶体管Tr的第二极12。
除此之外，在采用沉积工艺制得图27b的第二极12时，可能会在第一通孔611内也沉积金属，基于此，需要将第一通孔611内的金属回刻掉。
如图27c，在第一通孔611的内壁面上依次形成栅介质层和金属层，该金属层形成该存储阵列的字线WL。
以及，开设多个间隔排布的第二通孔612，第二通孔612位于相邻两个第一通孔611之间。且每一个第二通孔612贯通这些介质层。
如图27d，选择性刻蚀第二功能介质层500a2，以在第二功能介质层500a2上形成多个凹槽712，凹槽712环绕在第二通孔612的外围，且凹槽712停留在第一通孔611内的栅介质层15。
如图27e，在凹槽712的内壁面上沉积半导体材料，回刻位于凹槽712的靠近第二通孔612的外缘处的半导体材料，以形成沟道层14，再继续将填充介质材料，以将凹槽712填满。
如图27f，选择性刻蚀第一功能介质层500a1，以在第一功能介质层500a1上形成多个凹槽713，凹槽713环绕在第二通孔612的外围，且凹槽712停留在第一通孔611内的栅介质层15。
如图27g，在凹槽713的内壁面上形成金属层，回刻位于凹槽713的靠近第二通孔612的外缘处的金属层，以制得电容器C的第一电容电极。
填充电容材料，以在图27g制得的金属层上，以凹槽713的靠近第二通孔612的边缘位置形成电容层23。
由于电容材料会形成在第二通孔612内，进而，需要将第二通孔612内的电容材料刻蚀掉。
如图27h，在凹槽713的剩余空间内填充金属材料，以形成电容器C的第一电容电极21。在第二通孔612内填充金属材料，以制得条状的板线PL。即可形成最终的3D 1T1C存储阵列。
基于上述对存储阵列工艺结构、形成方法的描述，可以得知：通过对相毗邻的三层介质层进行图案化处理，就可以制得一个存储层，其中，一个介质层被图案化为第一金属层，另一个介质层被图案化为第二金属层，又一个介质层被设置在该两个金属层之间。以及，存储单元中的电容器和晶体管的第一极被形成在第一金属层中，晶体管的第二极被形成在第二金属层中。
本申请实施例涉及的“电容器和晶体管的第一极被形成在第一金属层中”，可以被理解为：在工艺制程中，在与衬底相平行的一个膜层(比如，介质层)结构中，进行图案化处理，就可以形成电容器和晶体管的第一极，以使得电容器和晶体管的第一极处于与衬底相平行的第一金属层中，而不是电容器中的两个电容电极、电容层和晶体管的第一极沿着与衬底相垂直的方向堆叠。
类似的，本申请实施例涉及的“晶体管的第二极被形成在第二金属层中”，可以被理解为：在工艺制程中，在与衬底相平行的一个膜层(比如，介质层)结构中，进行图案化处理，就可以形成晶体管的第二极，以使得晶体管的第二极处于与衬底相平行的第二金属层中。
在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (25)

  1. 一种存储阵列，其特征在于，包括：
    衬底；
    形成在所述衬底上的多个存储层，所述多个存储层沿着与所述衬底相垂直的方向堆叠；
    每一个所述存储层包括多个存储单元，每一个所述存储单元包括晶体管和与所述晶体管电连接的电容器；
    所述晶体管包括第一极、第二极、栅极和沟道层；
    所述电容器包括第一电容电极、电容层和第二电容电极；
    所述第一极与所述第一电容电极电连接；
    每一个所述存储层包括沿与所述衬底相垂直方向堆叠的第一金属层和第二金属层，所述第一金属层和所述第二金属层之间被介质层电隔离开；
    所述晶体管的所述第一极和所述电容器形成在所述第一金属层中，所述晶体管的所述第二极形成在所述第二金属层中；
    所述栅极的至少部分和所述沟道层的至少部分贯穿在所述介质层中，所述沟道层环绕在所述栅极的外围；
    所述第一电容电极、所述电容层和所述第二电容电极沿与所述衬底相平行的方向堆叠，所述电容层环绕在所述第一电容电极的外围。
  2. 根据权利要求1所述的存储阵列，其特征在于，
    所述栅极的一端延伸至所述第一金属层内，所述第一极环绕在所述栅极的外围，并通过栅介质层与所述栅极电隔离开；
    所述栅极的另一端延伸至所述第二金属层内，所述第二极环绕在所述栅极的外围，并通过栅介质层与所述栅极电隔离开。
  3. 根据权利要求1或2所述的存储阵列，其特征在于，所述沟道层的一端延伸至所述第二金属层内，且所述第二极环绕在所述沟道层的外围。
  4. 根据权利要求1-3中任一项所述的存储阵列，其特征在于，所述沟道层的另一端延伸至所述第一金属层内；
    所述第一极和所述第一电容电极共用同一电极；
    所述第一电容电极环绕在所述沟道层的外围。
  5. 根据权利要求1或2所述的存储阵列，其特征在于，位于所述介质层中的所述沟道层包括环绕沟道、与所述环绕沟道连接的第一平面沟道，所述第一平面沟道平行于所述衬底；
    所述环绕沟道环绕在所述栅极的外围；
    所述第二极的朝向所述第一极的面与所述第一平面沟道接触。
  6. 根据权利要求5所述的存储阵列，其特征在于，位于所述介质层中的所述沟道层还包括平行于所述衬底的且与所述第一平面沟道相对的第二平面沟道，所述第一平面沟道和所述第二平面沟道通过所述环绕沟道连接；
    所述第二平面沟道与所述第一极接触。
  7. 根据权利要求1-6中任一项所述的存储阵列，其特征在于，所述第一电容电极包 括环绕在所述栅极外围的环绕电极，和与所述环绕电极连接且与所述衬底相平行布设的平面电极，以使得所述第一电容电极形成与所述衬底相平行的水平接触面，和与所述衬底相垂直的垂直接触面，所述水平接触面和所述垂直接触面上均形成有所述电容层。
  8. 根据权利要求7所述的存储阵列，其特征在于，
    所述平面电极包括相对设置的第一平面电极和第二平面电极，所述第一平面电极和所述第二平面电极通过所述环绕电极连接，以使得所述第一电容电极内形成具有开口的凹槽，且所述凹槽的开口背离所述栅极，所述电容层和所述第二电容电极依次设置在所述凹槽的内壁面上，以形成具有第一缺口且所述第一缺口背离所述栅极的所述电容层。
  9. 根据权利要求8所述的存储阵列，其特征在于，每一个所述存储层还包括第一电极线，所述电容器的所述第二电容电极与所述第一电极线电连接；
    所述第一电极线沿与所述衬底相垂直的方向延伸，且所述第一电极线靠近所述第一缺口设置；
    所述多个存储层中，沿与所述衬底相垂直布设的多个所述电容器的所述第二电容电极与同一条所述第一电极线电连接。
  10. 根据权利要求7所述的存储阵列，其特征在于，所述平面电极呈板状结构，并与所述环绕电极连接，以形成具有第二缺口且所述第二缺口朝向所述栅极的所述电容层，所述第二电容电极设置在所述电容层的背离所述第一电容电极的表面上。
  11. 根据权利要求10所述的存储阵列，其特征在于，每一个所述存储层还包括第一电极线，所述电容器的所述第二电容电极与所述第一电极线电连接；
    所述第一电极线呈板状结构，且与所述衬底相平行布设，且所述第一电极线背离所述第二缺口设置；
    每一个所述存储层中，多个所述电容器的所述第二电容电极与同一个所述第一电极线电连接。
  12. 根据权利要求1-11中任一项所述的存储阵列，其特征在于，每一个所述存储层还包括第二电极线和第三电极线；
    所述晶体管的所述栅极与所述第二电极线电连接；
    所述晶体管的所述第二极与所述第三电极线电连接。
  13. 根据权利要求12所述的存储阵列，其特征在于，所述第二电极线沿与所述衬底相垂直的方向延伸；
    所述多个存储层中，沿与所述衬底相垂直布设的多个所述晶体管的所述栅极与同一条所述第二电极线电连接。
  14. 根据权利要求12或13所述的存储阵列，其特征在于，所述第三电极线沿与所述衬底相平行的方向延伸；
    每一个所述存储层中，沿与所述衬底相平行布设的多个所述晶体管的所述第二极与同一条所述第三电极线电连接。
  15. 根据权利要求1-14中任一项所述的存储阵列，其特征在于，所述第一金属层靠近所述衬底设置，所述第二金属层远离所述衬底设置。
  16. 根据权利要求1-15中任一项所述的存储阵列，其特征在于，所述存储阵列为DRAM存储阵列，或者，所述存储阵列为铁电存储阵列。
  17. 根据权利要求1-16中任一项所述的存储阵列，其特征在于，所述多个存储层采用后道工艺形成在所述衬底上。
  18. 一种存储器，其特征在于，包括：
    如权利要求1-17中任一项所述的存储阵列；
    控制器，所述控制器与所述存储阵列电连接，所述控制器用于控制所述存储阵列的读写。
  19. 一种电子设备，其特征在于，包括：
    处理器；
    如权利要求18所述的存储器，所述处理器与所述存储器电连接，所述存储器用于存储所述处理器产生的数据。
  20. 一种存储阵列的形成方法，其特征在于，所述形成方法包括：
    在衬底上堆叠多层介质层，所述多层介质层包括多组功能介质层，和位于相邻两组所述功能介质层之间的电隔离介质层，每一组所述功能介质层包括依次堆叠的第一功能介质层、第二功能介质层和第三功能介质层；
    对所述多组功能介质层进行图案化处理，以形成堆叠的多个存储层，每一个存储层包括将所述第一功能介质层图案化后的第一金属层、将所述第三功能介质层图案化后的第二金属层，以及位于所述第一金属层和所述第二金属层之间的所述第二功能介质层，每一个存储层包括多个存储单元，每一个所述存储单元包括晶体管和电容器；
    其中，所述晶体管包括第一极、第二极、栅极和沟道层；
    所述电容器包括第一电容电极、电容层和第二电容电极；
    所述晶体管的所述第一极和所述电容器形成在所述第一金属层中，所述晶体管的所述第二极形成在所述第二金属层中；
    所述栅极的至少部分和所述沟道层的至少部分形成在所述第二功能介质层中，所述沟道层环绕在所述栅极的外围；
    所述第一电容电极、所述电容层和所述第二电容电极沿与所述衬底相平行的方向堆叠，所述电容层环绕在所述第一电容电极的外围。
  21. 根据权利要求20所述的存储阵列的形成方法，其特征在于，形成所述栅极包括：
    沿与所述衬底相垂直的方向，开设贯通所述多层介质层的第一通孔，并在所述第一通孔内填充导电材料，以形成所述晶体管的所述栅极。
  22. 根据权利要求21所述的存储阵列的形成方法，其特征在于，所述开设贯通所述多层介质层的第一通孔之后，在所述第一通孔内填充导电材料之前，所述形成方法还包括：
    在所述第一通孔内填充半导体材料，以在所述第一通孔的内壁面上形成所述晶体管的所述沟道层。
  23. 根据权利要求21所述的存储阵列的形成方法，其特征在于，形成所述电容器 的所述第一电容电极、所述电容层和所述第二电容电极，包括：
    在所述第一通孔内填充所述导电材料，形成所述栅极之前，在所述第一功能介质层内开设第一凹槽，所述第一凹槽的开口朝向所述第一通孔，在所述第一凹槽内形成所述第一电容电极、所述电容层和所述第二电容电极，以形成具有缺口且所述缺口朝向所述第一通孔的所述电容层。
  24. 根据权利要求21所述的存储阵列的形成方法，其特征在于，形成所述电容器的所述第一电容电极、所述电容层和所述第二电容电极，包括：
    在所述第一通孔内填充所述导电材料，形成所述栅极之后，沿与所述衬底相垂直的方向，开设贯通所述多层介质层的第二通孔；
    在所述第一功能介质层内开设第二凹槽，所述第二凹槽的开口朝向所述第二通孔，所述第二凹槽的底面贯通至所述第一通孔，在所述第二凹槽内形成所述第一电容电极、所述电容层和所述第二电容电极，以形成具有缺口且所述缺口背离所述第一通孔的所述电容层。
  25. 根据权利要求24所述的存储阵列的形成方法，其特征在于，所述开设贯通所述多层介质层的第二通孔之后，所述形成方法还包括：
    在所述第二功能介质层内形成第三凹槽，所述第三凹槽的开口朝向所述第二通孔，在所述第三凹槽内填充半导体材料，以在所述第三凹槽的内壁面上形成所述晶体管的所述沟道层。
PCT/CN2022/119960 2022-09-20 2022-09-20 一种三维存储阵列、存储器及电子设备 WO2024060021A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/119960 WO2024060021A1 (zh) 2022-09-20 2022-09-20 一种三维存储阵列、存储器及电子设备

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/119960 WO2024060021A1 (zh) 2022-09-20 2022-09-20 一种三维存储阵列、存储器及电子设备

Publications (1)

Publication Number Publication Date
WO2024060021A1 true WO2024060021A1 (zh) 2024-03-28

Family

ID=90453709

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/119960 WO2024060021A1 (zh) 2022-09-20 2022-09-20 一种三维存储阵列、存储器及电子设备

Country Status (1)

Country Link
WO (1) WO2024060021A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160308042A1 (en) * 2014-07-03 2016-10-20 Broadcom Corporation Semiconductor Device with a Vertical Channel Formed Through a Plurality of Semiconductor Layers
CN106298679A (zh) * 2016-09-30 2017-01-04 中国科学院微电子研究所 存储器件及其制造方法及包括该存储器件的电子设备
CN109863575A (zh) * 2016-08-26 2019-06-07 日升存储公司 三维阵列中电容耦接非易失性薄膜晶体管串
CN110349967A (zh) * 2019-06-28 2019-10-18 长江存储科技有限责任公司 一种三维存储器的形成方法及三维存储器
CN112331672A (zh) * 2020-11-05 2021-02-05 长江存储科技有限责任公司 三维存储器及其制造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160308042A1 (en) * 2014-07-03 2016-10-20 Broadcom Corporation Semiconductor Device with a Vertical Channel Formed Through a Plurality of Semiconductor Layers
CN109863575A (zh) * 2016-08-26 2019-06-07 日升存储公司 三维阵列中电容耦接非易失性薄膜晶体管串
CN106298679A (zh) * 2016-09-30 2017-01-04 中国科学院微电子研究所 存储器件及其制造方法及包括该存储器件的电子设备
CN110349967A (zh) * 2019-06-28 2019-10-18 长江存储科技有限责任公司 一种三维存储器的形成方法及三维存储器
CN112331672A (zh) * 2020-11-05 2021-02-05 长江存储科技有限责任公司 三维存储器及其制造方法

Similar Documents

Publication Publication Date Title
CN111223863B (zh) 动态随机存取存储器结构
US20240121942A1 (en) Memory and forming method thereof, and electronic device
US20230064388A1 (en) Memory devices having vertical transistors and methods for forming the same
US20230066312A1 (en) Memory devices having vertical transistors and methods for forming the same
WO2024060021A1 (zh) 一种三维存储阵列、存储器及电子设备
US20230069096A1 (en) Memory devices having vertical transistors and methods for forming the same
US20230062524A1 (en) Memory devices having vertical transistors and methods for forming the same
US20230060149A1 (en) Memory devices having vertical transistors and methods for forming the same
US20230065806A1 (en) Memory devices having vertical transistors and methods for forming the same
WO2024031438A1 (zh) 一种三维存储阵列、存储器及电子设备
WO2023004598A1 (zh) 铁电存储器及其形成方法、电子设备
WO2023272536A1 (zh) 铁电存储器及其形成方法、电子设备
US20230380136A1 (en) Memory devices having vertical transistors and methods for forming the same
CN117750777A (zh) 一种三维存储阵列、存储器及电子设备
US20230380137A1 (en) Memory devices having vertical transistors and methods for forming the same
WO2023221925A1 (en) Memory devices having vertical transistors and methods for forming the same
WO2023077314A1 (zh) 存储器、存储器的控制方法和形成方法、电子设备
WO2024066560A1 (zh) 一种存储阵列、存储器及电子设备
US20230062141A1 (en) Memory devices having vertical transistors and methods for forming the same
US20230062083A1 (en) Memory devices having vertical transistors and methods for forming the same
WO2023029142A1 (en) Memory devices having vertical transistors and methods for forming thereof
CN117678333A (zh) 具有垂直晶体管的存储器装置及其形成方法
CN117598039A (zh) 具有垂直晶体管的存储器装置及其形成方法
CN117397040A (zh) 具有垂直晶体管的存储器装置及其制造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22959033

Country of ref document: EP

Kind code of ref document: A1