WO2024031438A1 - 一种三维存储阵列、存储器及电子设备 - Google Patents

一种三维存储阵列、存储器及电子设备 Download PDF

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Publication number
WO2024031438A1
WO2024031438A1 PCT/CN2022/111458 CN2022111458W WO2024031438A1 WO 2024031438 A1 WO2024031438 A1 WO 2024031438A1 CN 2022111458 W CN2022111458 W CN 2022111458W WO 2024031438 A1 WO2024031438 A1 WO 2024031438A1
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electrode
transistor
layer
electrode line
channel layer
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PCT/CN2022/111458
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English (en)
French (fr)
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黄凯亮
景蔚亮
孙莹
王正波
廖恒
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华为技术有限公司
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Priority to PCT/CN2022/111458 priority Critical patent/WO2024031438A1/zh
Publication of WO2024031438A1 publication Critical patent/WO2024031438A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components

Definitions

  • the present application relates to the field of semiconductor memory technology, and in particular to a three-dimensional memory array, a memory including the three-dimensional memory array, a method for forming the three-dimensional memory array, and an electronic device including the memory.
  • DRAM dynamic random access memory
  • CPU central processing unit
  • hard disks external devices
  • DRAM dynamic random access memory
  • the area occupied by the transistor process structure can affect the integration density of the memory unit, thereby affecting the storage capacity of the memory.
  • transistors have many different process structures.
  • the layout of many transistors poses challenges to the manufacturing process, which will also limit the improvement of the integration density of memory cells.
  • the present application provides a three-dimensional storage array, a memory including the three-dimensional storage array, a method for forming the three-dimensional storage array, and an electronic device including the memory.
  • the main purpose is to provide a memory array that can increase storage density and simplify the manufacturing process.
  • this application provides a three-dimensional storage array.
  • the three-dimensional storage array can be used in dynamic random access memory (dynamic random access memory, DRAM).
  • DRAM dynamic random access memory
  • the three-dimensional memory array includes a substrate, a plurality of storage layers formed on the substrate, the plurality of storage layers are stacked along a direction perpendicular to the substrate, and each storage layer includes a first electrode line and a second electrode line, And a plurality of memory cells; each memory unit includes a first transistor and a second transistor that are electrically connected.
  • the memory unit may be a 2TOC memory cell structure, and the first transistor and the second transistor each include a gate, a third transistor, and a gate. The first and second poles, and the channel layer.
  • the first electrode of the first transistor is electrically connected to the first electrode line, the first electrode of the second transistor is connected to the second electrode line; the gate electrode of the first transistor may be electrically connected to the third electrode line, and the second electrode of the second transistor is electrically connected to the first electrode line.
  • the electrode line can be electrically connected to the fourth electrode line; for example, when the memory cell is a 2T0C memory cell in DRAM, the first electrode line here can be the write bit line, the second electrode line can be the read bit line, and the third electrode line is the writing word line, and the fourth electrode line is the reading word line.
  • each storage layer includes a first metal layer and a first dielectric layer stacked in a direction perpendicular to the substrate; a first electrode line, a second electrode line, and a third transistor of each of the first transistor and the second transistor. At least part of the first pole, the second pole, and the channel layer are located in the first metal layer.
  • This application provides that in each memory unit of a plurality of memory cells, the first electrode, the second electrode and the channel layer of each transistor of the first transistor and the second transistor are located on the first metal layer parallel to the substrate. , that is, the first transistor and the second transistor are arranged in a direction parallel to the substrate.
  • the memory unit of this structure can be arranged in a direction perpendicular to the substrate and in a direction parallel to the substrate. Stacking is carried out to achieve three-dimensional stacking, achieve high-density integration, and increase storage capacity to adapt to the amount of computing data of the processor.
  • the first electrode line such as WBL
  • the second electrode line such as RBL
  • the first electrode, the second electrode of the transistor, and the channel layer are at a third level parallel to the substrate.
  • the first electrode line and the second electrode line are located in another metal layer.
  • Multi-layer devices can be processed at the same time, that is, multi-layer devices are formed at one time without the need to first prepare the first-layer memory array, and then use the same process to manufacture the second-layer memory array, third-layer memory array, etc. layer by layer.
  • the process flow can be simplified and manufacturing costs can be reduced.
  • the process complexity and manufacturing costs will be significantly reduced.
  • it can also avoid the The memory array is fabricated layer by layer, resulting in poor alignment accuracy of the memory cells.
  • part of the channel layer of each transistor of the first transistor and the second transistor is located in the first metal layer, and the other part extends to the first dielectric layer.
  • the channel layer of each of the first transistor and the second transistor is entirely located in the first metal layer.
  • the memory array further includes a third electrode line and a fourth electrode line; both the third electrode line and the fourth electrode line extend in a direction perpendicular to the substrate; the third electrode line is electrically connected to each The gate electrodes of the first transistors in two adjacent storage layers; the fourth electrode line is electrically connected to the second electrode of the second transistor in each two adjacent storage layers.
  • the first electrode line and the second electrode line extend in a direction parallel to the substrate, and the third electrode line and the fourth electrode line extend in a direction perpendicular to the substrate.
  • the channel layer of the first transistor is the first channel layer
  • the channel layer of the second transistor is the second channel layer; the first channel layer is perpendicular to the second channel layer. Layout; the extension direction of the first electrode line and the second electrode line is consistent with the extension direction of the second channel layer.
  • the first channel layer extends along a first direction
  • the second channel layer, first electrode line, and second electrode line all extend along a second direction perpendicular to the first direction.
  • the extension of the first channel layer along the first direction can be understood to mean that the current direction in the first channel layer is the first direction
  • the extension of the second channel layer along the second direction can be understood to mean that the current direction in the second channel layer is the third direction. Two directions.
  • one end of the first channel layer close to the second channel layer passes through the gate dielectric layer formed at the interface between the first channel layer and the second channel layer and the second channel layer. electrically isolated.
  • the first channel layer not only serves as the channel of the first transistor, but also serves as the gate of the second transistor. In this way, the process structure can be simplified and the storage density can be further improved.
  • a cavity is formed in the second channel layer close to the first channel layer, one end of the first channel layer is disposed in the cavity, and is formed on the inner wall of the cavity
  • the gate dielectric layer is electrically isolated from the second channel layer.
  • the area occupied by the memory unit can be further reduced, thereby further increasing the storage density and improving the storage density.
  • the storage capacity of the array By utilizing the cavity provided on the second channel layer and disposing the first channel layer in the cavity, the area occupied by the memory unit can be further reduced, thereby further increasing the storage density and improving the storage density.
  • the storage capacity of the array By utilizing the cavity provided on the second channel layer and disposing the first channel layer in the cavity, the area occupied by the memory unit can be further reduced, thereby further increasing the storage density and improving the storage density.
  • the storage capacity of the array can be utilizing the cavity provided on the second channel layer and disposing the first channel layer in the cavity.
  • a gate of a second transistor is formed at an end of the first channel layer embedded in the cavity, and the gate of the second transistor is connected to the third transistor through a gate dielectric layer formed on the inner wall of the cavity.
  • the two channel layers are electrically isolated, and the gate electrode of the second transistor and the second electrode of the first transistor share the same electrode.
  • a gate structure of the second transistor is also introduced, and the gate of the second transistor passes through the gate dielectric layer. electrically insulated from the second channel layer.
  • the memory array further includes a fifth electrode line
  • each memory unit further includes at least one ferroelectric capacitor
  • the ferroelectric capacitor includes a first ferroelectric electrode, a ferroelectric film layer and a second ferroelectric electrode.
  • the first ferroelectric electrode is electrically connected to the second electrode of the first transistor and the gate electrode of the second transistor respectively
  • the second ferroelectric electrode is electrically connected to the fifth electrode
  • the first electrode, the second electrode and the channel layer of each transistor are located in the same metal layer parallel to the substrate
  • the fifth electrode line extends in a direction perpendicular to the substrate.
  • the memory unit also includes at least one capacitor, a 2TnC memory unit can be formed, and the 2TnC memory unit can be applied in ferroelectric random access memory (FeRAM).
  • FeRAM ferroelectric random access memory
  • the first ferroelectric electrode, the first electrode, the second electrode and the channel layer of each transistor of the first transistor and the second transistor are located in the same metal layer parallel to the substrate,
  • the memory array of the present application can be processed simultaneously, that is, multi-layer devices can be formed at one time.
  • the extending direction of the first ferroelectric electrode is consistent with the extending direction of the first channel layer, and the first ferroelectric electrode is formed at an end of the first channel layer close to the second channel layer. , and is electrically isolated from the second channel layer by the gate dielectric layer; the second ferroelectric electrode is disposed on the side of the first ferroelectric electrode, and is electrically isolated from the first ferroelectric electrode by the ferroelectric film layer.
  • a cavity is formed in the second channel layer close to the first ferroelectric electrode, and one end of the first ferroelectric electrode is disposed in the cavity and is formed on the inner wall of the cavity.
  • the gate dielectric layer is electrically isolated from the second channel layer.
  • the area occupied by the memory unit can be further reduced, so that more memory units can be integrated within a unit area and the storage capacity can be increased.
  • each memory cell includes a plurality of ferroelectric capacitors; the plurality of ferroelectric capacitors are arranged at intervals along a direction parallel to the extending direction of the first channel layer.
  • the memory cell is called a 2TnC memory cell including multiple ferroelectric capacitors.
  • a third channel perpendicular to an extension direction of the first channel layer and electrically connected to the first channel layer is formed at an end of the first channel layer away from the second channel layer.
  • the first electrode line here may not only serve as the WBL, but also may serve as the source or drain of the first transistor.
  • a third electrode line perpendicular to the substrate is formed on the side of the first channel layer, and the third electrode line is electrically isolated from the first channel layer by a gate dielectric layer.
  • the third electrode line here can not only serve as the WWL, but also serve as the gate of the first transistor.
  • the gate of the first transistor may be a double gate structure, a single gate structure or a gate-all-around structure.
  • the first pole and the second pole of the second transistor are formed at opposite ends of the second channel layer.
  • the second electrode line is located on a side of the second channel layer away from the first channel layer; the memory unit further includes a conductive connection part, and the first electrode of the second transistor is connected to the first electrode through the conductive connection part.
  • the second electrode wire is electrically connected.
  • the first electrode of the second transistor is drawn out using a conductive connection portion to be electrically connected to the second electrode line.
  • the first electrode, the second electrode line and the conductive connection part of the second transistor are all made in the semiconductor layer through a doping process.
  • first electrode, the second electrode line and the conductive connection part can also be made of metal materials.
  • a fourth electrode line extending in a direction perpendicular to the substrate is in contact with the other of two opposite ends of the second channel layer.
  • the fourth electrode line can not only serve as the RWL, but also serve as the second electrode of the second transistor.
  • the plurality of memory units include a first memory unit and a second memory unit; the first memory unit and the second memory unit are arranged in a direction parallel to the substrate; the first memory unit and the second memory unit are arranged in a direction parallel to the substrate; In any of the two memory cells, the first electrode of the first transistor is electrically connected to the first electrode line, and the first electrode of the second transistor is electrically connected to the second electrode line.
  • the first electrode line and the second electrode line may be shared.
  • the plurality of memory units include a first memory unit and a third memory unit; the first memory unit and the third memory unit are stacked in a direction perpendicular to the substrate, and the first memory unit and the third memory unit are stacked in a direction perpendicular to the substrate.
  • the gate electrode of the first transistor is electrically connected to the third electrode line
  • the second electrode of the second transistor is electrically connected to the fourth electrode line.
  • the first memory unit and the second memory unit arranged perpendicularly to the substrate may share the third electrode line and the fourth electrode line.
  • a plurality of memory cells, first electrode lines, second electrode lines, third electrode lines and fourth electrode lines are all formed on the substrate using a subsequent process.
  • the first transistor and the second transistor are both manufactured by a back-end process, and the controller can be manufactured by a front-end process.
  • the controller may include one or more circuits of a decoder, a driver, a timing controller, a buffer, or an input-output driver, and may also include other functional circuits.
  • the controller can control the first electrode line, the second electrode line, the third electrode line and the fourth electrode line in the embodiment of the present application.
  • the interconnection lines and the memory array are all manufactured through the back-end process BEOL. It can make the circuit density per unit area greater, thereby improving the storage performance per unit area.
  • the storage array is a DRAM storage array.
  • the memory cell is understood to be a 2T0C memory cell in the DRAM memory array.
  • the first electrode line is a write bit line
  • the second electrode line is a read bit line
  • the third electrode line is a write word line
  • the fourth electrode line is the read word line.
  • the memory array is a ferroelectric memory array.
  • the memory array further includes a fifth electrode line
  • each memory unit further includes at least one ferroelectric capacitor
  • the ferroelectric capacitor includes a first ferroelectric electrode, a ferroelectric film layer and a second ferroelectric electrode.
  • the first ferroelectric electrode is electrically connected to the second electrode of the first transistor and the gate of the second transistor respectively
  • the second ferroelectric electrode is electrically connected to the fifth electrode line
  • the first electrode line is the write bit line
  • the second electrode line is The first line is the read bit line
  • the third electrode line is the precharge line
  • the fourth electrode line is the source line
  • the fifth electrode line is the word line.
  • this application also provides a memory, which includes a controller and a storage array in any of the above implementations.
  • the controller is electrically connected to the storage array, and the controller is used to control reading and writing of the storage array.
  • the first transistor and the second transistor are arranged in a direction parallel to the substrate.
  • the structure of this structure can be
  • the memory cells are stacked in a direction perpendicular to the substrate and in a direction parallel to the substrate to achieve three-dimensional stacking, achieve high-density integration, and increase storage capacity.
  • the storage array and the controller are integrated into the same chip, and the chip is disposed on the substrate.
  • the storage array is integrated in the first chip
  • the controller is integrated in the second chip
  • both the first chip and the second chip are disposed on the substrate through electrical connection structures.
  • the storage array is integrated in a first chip
  • the controller is integrated in a second chip
  • the first chip is stacked with the second chip, and integrated on the substrate.
  • this application also provides an electronic device, including a processor and a memory in any of the above implementations.
  • the processor is electrically connected to the memory, and the memory is used to store data generated by the processor.
  • the electronic device provided by the embodiment of the present application includes the memory in any of the above implementations. Therefore, the electronic device provided by the embodiment of the present application and the memory of the above technical solution can solve the same technical problem and achieve the same expected effect.
  • the present application also provides a method for forming a memory array.
  • the forming method includes:
  • each semiconductor layer to form a first electrode line, a second electrode line, and a memory cell including a first transistor and a second transistor;
  • the first transistor and the second transistor each include a first electrode, a second electrode, a gate electrode and a channel layer.
  • the first electrode of the first transistor is electrically connected to the first electrode line
  • the first electrode of the second transistor is electrically connected to the third electrode line.
  • Two electrode lines, and the first electrode line, the second electrode line, and at least part of the first electrode, the second electrode and the channel layer of each transistor of the first transistor and the second transistor are located parallel to the substrate.
  • the first metal layer is parallel to the dielectric layer.
  • firstly multiple layers of alternately arranged semiconductor layers and dielectric layers are stacked, and then patterning is performed on each semiconductor layer to form the first electrode and the second electrode of the first transistor and the second transistor. pole, channel layer, and first electrode line and second electrode line.
  • multi-layer memory cells can be produced at the same time without stacking memory cells layer by layer. In this way, the preparation process can not only be simplified, but also the alignment process caused by multi-layer stacking can be avoided. question.
  • the forming method before patterning each semiconductor layer to form the first electrode line, the second electrode line, and the memory unit including the first transistor and the second transistor, the forming method further includes: opening A plurality of first through holes, the plurality of first through holes are arranged at intervals along the first direction, and any first through hole penetrates the multi-layer semiconductor layer and the multi-layer dielectric layer along the direction perpendicular to the substrate; in the third A through hole is filled with an insulating layer.
  • the insulating layer is formed to electrically isolate two adjacent memory cells.
  • patterning is performed on each semiconductor layer to form a first electrode line, a second electrode line, and a memory unit including a first transistor and a second transistor, including: in each semiconductor layer A first groove is formed on the first groove, and the first groove includes a first part extending along the first direction, and a second part located between two adjacent insulating layers; a gate dielectric layer is formed on the wall of the first groove; A semiconductor material is filled in the first part to form a channel layer of the first transistor; a conductive material is filled in the first part to form a first electrode line extending in the first direction.
  • a first groove is opened on each semiconductor layer.
  • the first groove includes a first part extending along a first direction, and a second part located between two adjacent insulating layers. The portion extends beyond a side of the insulating layer away from the first portion to form a cavity in the semiconductor layer, so that the channel layer of the first transistor is disposed in the cavity.
  • the channel layer of the first transistor is embedded in the channel layer of the second transistor, thereby further reducing the area of the memory unit and increasing the storage density.
  • patterning on each semiconductor layer to form a first electrode line, a second electrode line, and a memory unit including a first transistor and a second transistor also includes: opening an opening on each semiconductor layer.
  • the second groove includes a third portion extending along the first direction and a fourth portion located between the channel layers of two adjacent first transistors; both the third portion and the fourth portion are filled with insulation. layer.
  • the forming method further includes: doping a third portion of the semiconductor layer extending along the first direction and adjacent to the second trench. to form a second electrode line extending along the first direction, and doping the semiconductor layer adjacent to the channel layer of the first transistor to form a first electrode of the second transistor electrically connected to the second electrode line .
  • the semiconductor layer is doped to form the second electrode and the second electrode line of the second transistor. In this way, the process can be simplified.
  • forming the fourth electrode line includes: opening a second through hole on the semiconductor layer on opposite sides of the fourth part, so that the second through hole is along a direction perpendicular to the substrate. Penetrate the multi-layer semiconductor layer and the multi-layer dielectric layer; fill the second through hole with conductive material to form a fourth electrode line.
  • forming the third electrode line includes: opening a third through hole on the side of the channel layer of the first transistor, so that the third through hole penetrates multiple times in a direction perpendicular to the substrate. a semiconductor layer and a multi-layer dielectric layer; and a conductive material is filled in the third through hole to form a third electrode line.
  • a third via hole may be opened on both opposite sides of the first channel layer to form a first transistor with a gate all around, or a third via hole may be opened on one of the opposite sides of the first channel layer , to form a single-gate first transistor.
  • Figure 1 is a circuit diagram of an electronic device provided by an embodiment of the present application.
  • Figure 2 is a circuit diagram of a memory provided by an embodiment of the present application.
  • Figure 3a is a package structure diagram of a storage array and a controller provided by an embodiment of the present application
  • Figure 3b is a package structure diagram of a storage array and controller provided by an embodiment of the present application.
  • Figure 3c is a package structure diagram of a storage array and controller provided by an embodiment of the present application.
  • Figure 4 is a schematic three-dimensional structural diagram of a memory provided by an embodiment of the present application.
  • Figure 5 is a simple circuit diagram of a memory provided by an embodiment of the present application.
  • Figure 6 is a circuit diagram of a storage unit in a memory provided by an embodiment of the present application.
  • Figure 7 is a circuit diagram of a storage unit in a memory provided by an embodiment of the present application.
  • Figure 8 is a positional relationship diagram between a memory unit and a substrate in a memory provided by an embodiment of the present application.
  • Figure 9 is a simple three-dimensional schematic diagram of a memory provided by an embodiment of the present application.
  • Figure 10 is a cross-sectional view of the process structure of a memory unit in a memory provided by an embodiment of the present application.
  • Figure 11 is a three-dimensional view of a storage unit in a memory provided by an embodiment of the present application.
  • Figure 12 is a top view of Figure 11;
  • Figure 13a is a simple two-dimensional schematic diagram of a memory provided by an embodiment of the present application.
  • Figure 13b is a simple three-dimensional schematic diagram of a memory provided by an embodiment of the present application.
  • Figure 14 is a cross-sectional view of the process structure of a memory unit in a memory provided by an embodiment of the present application.
  • Figure 15 is a cross-sectional view of the process structure of a second transistor of a memory unit in a memory provided by an embodiment of the present application;
  • Figure 16 is a cross-sectional view of the process structure of a memory unit in a memory provided by an embodiment of the present application.
  • Figure 17 is a cross-sectional view of the process structure of a memory unit in a memory provided by an embodiment of the present application.
  • Figure 18 is a three-dimensional view of a memory array formed by multiple memory cells in a memory provided by an embodiment of the present application;
  • Figure 19 is a cross-sectional view of the process structure of a memory array formed by multiple memory cells in a memory provided by an embodiment of the present application;
  • Figure 20 is a three-dimensional view of a multi-layer storage array in a memory provided by an embodiment of the present application.
  • Figure 21 is a cross-sectional view of the process structure of a memory unit in a memory provided by an embodiment of the present application.
  • Figure 22 is a cross-sectional view of the process structure of a memory unit in a memory provided by an embodiment of the present application.
  • Figure 23 is a cross-sectional view of the process structure of a memory unit in a memory provided by an embodiment of the present application.
  • Figure 24 is a cross-sectional view of the process structure of a memory unit in a memory provided by an embodiment of the present application.
  • Figure 25 is a cross-sectional view of the process structure of a memory array formed by multiple memory cells in a memory provided by an embodiment of the present application;
  • Figure 26 is a flow chart of a storage array manufacturing method provided by an embodiment of the present application.
  • Figures 27a to 27m are cross-sectional views of the corresponding process structures after completion of each step in a memory manufacturing method provided by an embodiment of the present application.
  • 61-First electrode wire 62-Second electrode wire; 63-Third electrode wire; 64-Fourth electrode wire; 65-Fifth electrode wire;
  • FIG. 1 is a circuit block diagram of an electronic device 200 provided by an embodiment of the present application.
  • the electronic device 200 can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), Servers, workstations, etc.
  • a terminal device such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), Servers, workstations, etc.
  • the electronic device 200 may include a bus 205, and a system on chip (SOC) 210 connected to the bus 205.
  • SOC210 can be used to process data, such as processing application data, processing image data, and caching temporary data.
  • the SOC 210 may include an application processor (AP) 211 for processing applications, a graphics processing unit (GPU) 212 for processing image data, and a cache cache.
  • the first RAM 213 may be static random access memory (static random access memory, SRAM) or embedded flash memory (embedded flash, eflash), etc.
  • the above-mentioned AP211, GPU212 and first RAM213 may be integrated into one bare chip (die), or may be respectively provided in multiple dies.
  • the electronic device 200 may also include a second RAM 220 connected to the SOC 210 through the bus 205 .
  • the second RAM 220 may be a dynamic random access memory (DRAM).
  • the second RAM 220 may be used to save volatile data, such as temporary data generated by the SOC 210 .
  • the storage capacity of the second RAM 220 is usually larger than that of the first RAM 213, but the reading speed is usually slower than that of the first RAM 213.
  • the electronic device 200 may also include a communication chip 230 and a power management chip 240 connected to the SOC 210 through the bus 205.
  • the communication chip 230 can be used to process the protocol stack, or to amplify and filter analog radio frequency signals, or to implement the above functions at the same time.
  • the power management chip 240 can be used to power other chips.
  • the SOC 210 and the second RAM 220 may be packaged in a packaging structure, such as using 2.5D (dimension) or 3D packaging, etc., to obtain faster inter-chip data transmission rate.
  • FIG. 2 is a circuit block diagram of a memory 300 that can be applied in an electronic device according to an embodiment of the present application.
  • the memory 300 may be the first RAM 213 as shown in FIG. 1 or the second RAM 220.
  • the application scenarios of the memory 300 in this application are not limited.
  • the memory 300 includes a storage array 31 and a controller 32 for accessing the storage array 31 , where the controller 32 is used to control read and write operations of the storage array 31 .
  • the storage array 31 and the controller 32 shown in FIG. 2 have a variety of package structures that can be implemented.
  • package structures that can be implemented are given below.
  • Figure 3a is one of the packaging structures of the storage array 31 and the controller 32 given in the embodiment of the present application. That is, the storage array 31 and the controller 32 are two independent chips.
  • the storage array 31 and the controller 32 are respectively Integrated on the substrate 33 , for example, the storage array 31 and the controller 32 can achieve electrical conduction through metal traces arranged on the substrate 33 .
  • the storage array 31 since the storage array 31 and the controller 32 are two independent chips, the storage array 31 may be called a stand-alone memory.
  • Figure 3b is another packaging structure of the storage array 31 and the controller 32 according to the embodiment of the present application.
  • the storage array 31 and the controller 32 are two independent chips, so the storage array 31 can also be called an independent memory.
  • the storage array 31 and the controller 32 are stacked.
  • the storage array 31 and the controller 32 can be connected through a through silicon via (TSV) or a rewiring layer. (redistribution layer, RDL) phase conduction.
  • TSV through silicon via
  • RDL rewiring layer
  • Figure 3c is another packaging structure of the storage array 31 and the controller 32 provided in the embodiment of the present application.
  • the memory array 31 and the controller 32 are integrated into the same chip 3, and the chip 3 is integrated on the substrate 33. Therefore, the memory array 31 can be called an embedded memory.
  • the controller 32 can be integrated on the substrate through the front end of line (FEOL) process, and the interconnection lines and the memory array pass through the back end of line (FEOL) process. end of line, BEOL) process is integrated on the controller 32.
  • the controller here can be used to generate control signals. These control signals can be read and write control signals for controlling the read and write operations of data in the storage array.
  • the controller here can also include analog circuit parts, such as sense amplifiers.
  • the above-mentioned memory array 31 may be a one-layer memory array, or may include a first-layer memory array and a second-layer memory array stacked along the Z direction perpendicular to the substrate as shown in FIG. 4 , or, in some alternative implementations, more layers of storage arrays may be included. When two or more layers of storage arrays are included, such a memory can be called a three-dimensional integrated memory structure to increase storage capacity.
  • the storage array 31 in the memory may include multiple storage units 400 arranged in an array as shown in FIG. 5 , where each storage unit 400 may be used to store 1 bit or multiple bits. data.
  • the memory array 31 may also include signal lines such as word lines (WL) and bit lines (BL).
  • WL word lines
  • BL bit lines
  • Each memory cell 400 is electrically connected to the corresponding word line WL and bit line BL.
  • Different memory cells 400 may be electrically connected through WL and BL.
  • One or more of the above-mentioned WL and BL are used to select the memory unit 400 to be read and written in the memory array by receiving the control level output by the control circuit, thereby realizing data read and write operations.
  • the controller 32 in the memory may include one or more circuit structures among the decoder 320, the driver 330, the timing controller 340, the buffer 350 or the input and output driver 360 shown in FIG. 5 .
  • the decoder 320 is used to decode according to the received address to determine the storage unit 400 that needs to be accessed.
  • the driver 330 is used to control the level of the signal line according to the decoding result generated by the decoder 320, thereby achieving access to the designated storage unit 400.
  • the buffer 350 is used to cache the read data. For example, first-in first-out (FIFO) may be used for caching.
  • the timing controller 340 is used to control the timing of the buffer 350 and control the driver 330 to drive the signal lines in the memory array 310 .
  • the input and output driver 360 is used to drive transmission signals, such as driving received data signals and driving data signals to be sent, so that the data signals can be transmitted over long distances.
  • the above-mentioned memory array 310, decoder 320, driver 330, timing controller 340, buffer 350 and input/output driver 360 can be integrated into one chip, or can be integrated into multiple chips respectively.
  • the memory 300 involved in the embodiment of the present application may be a dynamic random access memory (dynamic random access memory, DRAM).
  • DRAM dynamic random access memory
  • it can be a DRAM including a 2T0C storage unit.
  • a gain-cell memory including a 2T0C storage unit structure can achieve nanosecond-level read and write speeds and millisecond-level storage times, and its area is only that of a static random access memory (static random access memory). random access memory, one-third of SRAM) because of its wide range of applications.
  • the memory 300 involved in the embodiment of the present application may also be a ferroelectric random access memory (FeRAM).
  • FeRAM ferroelectric random access memory
  • it may be a FeRAM including 2TnC memory cells.
  • n here may be equal to 1, or may be greater than Or equal to 2, such as FeRAM including 2T1C memory cells, or FeRAM including 2T2C memory cells.
  • FIG. 6 is a circuit diagram of a storage unit 400 in the memory 300 according to the embodiment of the present application.
  • the memory unit 400 belongs to the 2T0C gain-cell memory unit structure, that is, a memory unit 400 includes a write transistor T1 (also called the first transistor T1) and a read transistor T2 (also called the first transistor T1). may be called the second transistor T2).
  • the first transistor T1 and the second transistor T2 can select a thin film transistor (TFT) structure.
  • TFT thin film transistor
  • the first electrode of the write transistor T1 is electrically connected to the write bit line (WBL)
  • the second electrode of the write transistor T1 is electrically connected to the gate of the read transistor T2
  • the gate of the write transistor T1 is electrically connected to the write bit line (WBL).
  • write word line, WWL write word line electrical connection.
  • the first electrode of the read transistor T2 is electrically connected to the read bit line (RBL)
  • the second electrode of the read transistor T2 is electrically connected to the read word line (RWL).
  • the write bit line WBL may also be referred to as the first electrode line for loading a signal to the first electrode of the write transistor T1
  • the read bit line RBL may also be referred to as the first electrode line for loading the signal to the first electrode of the write transistor T1.
  • the first electrode of the transistor T2 is a second electrode line that loads a signal.
  • the write word line WWL may also be called a third electrode line that is used to load a signal to the gate of the write transistor T1.
  • the read word line RWL may also be called a third electrode line that is used to load a signal to the gate of the write transistor T1.
  • the write operation process During the write operation, the voltage of the read bit line RBL is 0, and the read transistor T2 does not work; the first write word line control signal is provided to the write word line WWL, and the first write word line control signal controls the write transistor T1 to turn on.
  • the first logic information for example, "0" is written
  • a first write bit line control signal is provided to the write bit line WBL (or read word line RWL)
  • the first write bit line control signal is written through the write transistor T1 Node N.
  • second logic information such as "1”
  • a second write bit line control signal is provided to the write bit line WBL (or read word line RWL), and the second write bit line control signal is written through the write transistor T1.
  • the read transistor T2 does not work; the second write word line control signal is provided to the write word line WWL, and the second write word line control signal controls the write transistor T1 to turn off. At this time, the potential stored in the node is not affected by external influences.
  • Read operation process Provide a second write word line control signal to the write word line WWL, and the second write word line control signal controls the write transistor T1 to turn off; provide a read word line control signal to the read word line RWL (or write bit line WBL), and according to the read The level of current on bit line RBL determines the stored logic information of the memory cell.
  • the node stores the first write bit line control signal
  • since the first write bit line control signal can control the read transistor T2 to turn on
  • the read word line RWL (or write bit line WBL) provides the read word line control signal
  • the read word line RWL (or the write bit line WBL) charges the read bit line RBL through the read transistor T2, and the voltage on the read bit line RBL increases.
  • the storage unit stores logical information "0".
  • the node stores the second write bit line control signal
  • the second write bit line control signal can control the read transistor T2 to turn off
  • the read word line RWL or write bit line WBL
  • the read word line RWL or the write bit line WBL
  • the read bit line RBL maintains a voltage of 0V. In this way, when a small current on the read bit line RBL is detected, it can The read memory cell stores logical information "1".
  • FIG. 7 is a circuit diagram of another memory unit 400 provided by an embodiment of the present application.
  • the memory unit 400 includes a first transistor T1, a second transistor T2, a ferroelectric capacitor C1 and a ferroelectric capacitor C2, that is, it is a 2T2C memory unit.
  • the gate electrode of the first transistor T1 is electrically connected to the precharge line CL
  • the second electrode of the first transistor T1 is electrically connected to the gate electrode of the second transistor T2
  • the first electrode of the first transistor T1 is electrically connected to the write bit line (write bit line).
  • bit line, WBL are electrically connected
  • the first pole of the ferroelectric capacitor C1 and the ferroelectric capacitor C2 are electrically connected to the gate of the second transistor T2
  • the second pole of the ferroelectric capacitor C1 and the second pole of the ferroelectric capacitor C2 are electrically connected respectively.
  • Electrically connected to word line WL The second electrode of the second transistor T2 is electrically connected to the source line SL
  • the first electrode of the second transistor T2 is electrically connected to the read bit line (RBL).
  • the write bit line WBL may also be referred to as a first electrode line for loading a signal to the first electrode of the first transistor T1
  • the read bit line RBL may also be referred to as a first electrode line for loading a signal to the first electrode of the first transistor T1
  • the first electrode of the second transistor T2 is a second electrode line for loading a signal.
  • the precharge line CL may also be called a third electrode line for loading a signal on the first transistor T1.
  • the source line SL may also be called a third electrode line for loading a signal on the first electrode of the second transistor T2.
  • the precharge line CL is used to receive the first precharge control signal to turn on the first transistor T1
  • the write bit line WBL is used to receive the first write bit line control signal
  • the word line WL is used to
  • the voltage difference between the first word line control signal and the first write bit line control signal causes the ferroelectric film layer of the ferroelectric capacitor to be positively or negatively polarized to write in the ferroelectric capacitor.
  • different logical information For example, when the ferroelectric film layer is positively polarized, a logic signal "0" is written. For another example, when the ferroelectric film layer is negatively polarized, a logic signal "1" is written.
  • the precharge line CL is used to receive the first precharge control signal, so that the first transistor T1 is turned on, and the write bit line WBL is used to To receive the second write bit line control signal, the word WL line is used to receive the second word line control signal.
  • the voltage difference between the second word line control signal and the second write bit line control signal causes the ferroelectric film layer of the ferroelectric capacitor to be in half state.
  • the polarity of the ferroelectric film layer does not flip, that is, the polarization state remains unchanged; in the second reading stage, the precharge line CL is used to receive the second precharge control signal, causing the first transistor T1 to turn off, The read bit line RBL is used to receive the first read bit line control signal, and the word line WL is used to receive the word line control signal with a voltage smaller than the second word line control signal, so that the ferroelectric capacitor is flipped from positive polarization to negative polarization.
  • the precharge line CL is used to receive the first precharge control signal, so that the first transistor T1 is turned on, and the write bit line WBL is used to receive the first write bit line control signal, the word line WL is used to receive the first word line control signal, and the voltage difference between the first word line control signal and the first write bit line control signal causes the ferroelectric film layer of the ferroelectric capacitor to be positively polarized. And read "0" according to the read bit line potential signal.
  • the precharge line CL is used to receive the first precharge control signal, so that the first transistor T1 is turned on, and the write bit line WBL is used to receive the second write
  • the word line WL is used to receive the second word line control signal, the voltage difference between the second word line control signal and the second write bit line control signal makes the ferroelectric film layer of the ferroelectric capacitor in a half-selected state, and the iron The polarity of the electric film layer does not flip, and the polarization state remains unchanged;
  • the precharge line CL is used to receive the second precharge control signal, so that the first transistor T1 is turned off, and the read bit line RBL is used to
  • the word line WL is used to receive the word line control signal with a voltage smaller than the second word line control signal, so that the negative polarity state of the ferroelectric capacitor remains unchanged, and the second transistor T2 is turned on.
  • the precharge line CL is used to receive the first precharge control signal to turn on the first transistor T1
  • the write bit line WBL is used to receive the first write bit line control signal
  • the word line WL is used to The first word line control signal is received, and the voltage difference between the first word line control signal and the first write bit line control signal causes the ferroelectric film layer of the ferroelectric capacitor to be negatively polarized. And read as "1" according to the read bit line potential signal.
  • the first transistor T1 and the second transistor T2 shown in the above-mentioned Figures 6 and 7 can be NMOS (N-channel metal oxide semiconductor) tubes, Or you can choose PMOS (P-channel metal oxide semiconductor, P-channel metal oxide semiconductor) tube.
  • NMOS N-channel metal oxide semiconductor
  • PMOS P-channel metal oxide semiconductor, P-channel metal oxide semiconductor
  • one of the drain or source of any one of the first transistor T1 and the second transistor T2 is called the first pole, and accordingly The other pole is called the second pole, and the control end of the transistor is the gate.
  • the drain and source of the transistor can be determined according to the flow direction of the current. For example, in the writing transistor T1 in Figure 6, when the current flows from left to right, the left end is the drain and the right end is the source; conversely, when the current flows from When turning from right to left, the right end is the drain and the left end is the source.
  • embodiments of the present application provide some memory unit process structures that can improve storage density, as detailed below.
  • Figure 8 simply shows the layout of the first transistor T1 and the second transistor T2 in the memory unit 400. See Figure 8.
  • T2 is arranged in a direction parallel to the substrate 100 instead of being stacked and arranged in a direction perpendicular to the substrate 100 .
  • the memory array provided by the embodiment of the present application, as shown in Figure 9, includes multiple memory layers, and these multiple memory layers are stacked in a direction perpendicular to the substrate 100.
  • One memory layer shown in Figure 9 can be understood as the one-layer storage array shown in Figure 4 above.
  • each memory layer includes a stacked first metal layer and a first dielectric layer, and the first metal layer and the first dielectric layer are stacked along a direction perpendicular to the substrate 100 . Two adjacent first metal layers are electrically isolated by a first dielectric layer.
  • the first transistor T1 and the second transistor T2 shown in FIG. 8 may be formed in the first metal layer shown in FIG. 9.
  • the specific layout method that can be implemented is as follows.
  • all layer structures such as electrodes, channels in the storage layer etc.
  • all layer structures may be located above the surface of the substrate; alternatively, part of the layer may be located in the storage layer (eg, electrode), and the other part may be located in the substrate close to the surface (eg, channel).
  • FIG. 10 is a sectional view of an achievable process structure of the first transistor T1 and the second transistor T2 according to the embodiment of the present application.
  • FIG. 11 is a three-dimensional view of FIG. 10
  • FIG. 12 is a top view of FIG. 11 .
  • the first pole 11 and the second pole 12 of the first transistor T1 and the first pole 21 and the second pole 22 of the second transistor T2 are located at In the first metal layer as shown in Figure 9, which is parallel to the substrate. That is, it can be understood that during the process flow, the first electrode 11 and the second electrode 12 of the first transistor T1 can be formed by performing a patterning process in a film layer (for example, a semiconductor layer) structure parallel to the substrate. , and, the first pole 21 and the second pole 22 of the second transistor T2, so that the first pole 11 and the second pole 12, and the first pole 21 and the second pole 22 are in the first metal parallel to the substrate. Instead of these electrodes being stacked in a direction perpendicular to the substrate. The following will describe how to fabricate the first electrode 11 and the second electrode 12 of the first transistor T1 and the first electrode 21 and the second electrode 22 of the second transistor T2 on the same film layer in combination with the preparation process flow.
  • a film layer for example, a semiconductor layer
  • the first electrode line 61 electrically connected to the first electrode 11 of the first transistor T1 and the second electrode line 62 electrically connected to the first electrode 21 of the second transistor T2 are connected to the first electrode line 62 mentioned above.
  • the first pole 11 and the second pole 12 of the transistor T1 and the first pole 21 and the second pole 22 of the second transistor T2 are located in the first metal layer shown in FIG. 9 .
  • first electrode lines 61 and the second electrode lines 62 are consistent.
  • the first electrode lines 61 and the second electrode lines 62 extend in the Y direction parallel to the substrate.
  • At least part of the channel layer 13 of the first transistor T1 and at least part of the channel layer 23 of the second transistor T2 are also located on the metal layer where the first electrode line 61 and the second electrode line 62 are located. middle.
  • At least part of the first electrode, the second electrode, and the channel layer of any of the first electrode line 61, the second electrode line 62, the first transistor T1, and the second transistor T2 are located in the same metal layer.
  • “at least part of the channel layer of any one of the first transistor T1 and the second transistor T2 is located in the first metal layer” involved in the embodiment of the present application it can be understood as follows, as shown in Figures 13a and 13b. 13a and 13b take the channel layer 23 of the second transistor T2 as an example. See Figure 13a.
  • the first electrode 21 and the second electrode 22 are located in the first metal layer, and A part of the channel layer 23 electrically connecting the first pole 21 and the second pole 22 is located in the first metal layer, and a part extends into the first dielectric layer adjacent to the first metal layer.
  • the first electrode 21 and the second electrode 22 are located in the first metal layer, and the entire channel layer 23 electrically connected to the first electrode 21 and the second electrode 22 is located in the first metal layer. In the first metal layer, it does not extend into the first dielectric layer.
  • the arrangement of the channel layer of the first transistor T1 is similar to the arrangement of the channel layer of the second transistor T2 shown in FIGS. 13a and 13b. For example, it may be entirely located in the first metal layer, or may be partially located in the first metal layer. Located in the first metal layer and partially located in the first dielectric layer.
  • the second electrode 12 can not only serve as the second electrode of the first transistor T1, but also serve as the gate electrode 42 of the second transistor T2, that is, the second electrode of the first transistor T1, and the second electrode of the first transistor T1.
  • the gates of the two transistors T2 share the same electrode.
  • the first electrode 11 of the first transistor T1 may share the same electrode line with the first electrode line 61 .
  • the first electrode line 61 in FIGS. 10 to 12 may be the write bit line WBL in the 2TOC memory cell shown in FIG. 6
  • the second electrode line 62 may be the write bit line WBL in the 2TOC memory cell shown in FIG. 6 Read bit line RBL.
  • the first electrode line 61 in FIGS. 10 to 12 may be the write bit line WBL in the 2T2C memory unit shown in FIG. 7
  • the second electrode line 62 may be the write bit line WBL in the 2T2C memory unit shown in FIG. 7 of read bit line RBL.
  • the third electrode line 63 and the fourth electrode line 64 both extend in a direction perpendicular to the substrate, for example, as shown in Figure 6
  • Both the write word line WWL and the read word line RWL in the 2T0C memory cell extend along the Z direction perpendicular to the substrate.
  • the memory cells including the first transistor T1 and the second transistor T2 involved in the embodiment of the present application can be arranged in a direction parallel to the substrate and perpendicular to the substrate. Realize three-dimensional stacking, achieve high-density integration, and increase the storage capacity of the storage array.
  • the first electrode, the second electrode and the channel layer of each of the first transistor T1 and the second transistor T2 are formed in the same metal layer, rather than stacking two layers in a direction perpendicular to the substrate, or stacking more layers.
  • multiple memory cells stacked in a direction perpendicular to the substrate can be simultaneously prepared on stacked multi-layer semiconductor layers, or in other words, a multi-layer memory array can be manufactured at the same time, instead of manufacturing one After forming one layer of memory array, another layer of memory array is produced. Therefore, when preparing the memory array provided in the embodiment of the present application, the preparation process can be simplified and the process complexity can be reduced. The specific achievable process method will be carried out later. The introduction, as well as the introduction of how to use one process to prepare multi-layer devices at the same time based on the process method, will not be described here.
  • the channel layer 13 of the first transistor T1 and the channel layer 23 of the second transistor T2 are arranged vertically.
  • the channel layer 13 in the X-Y plane extends along the X direction
  • the channel layer 23 extends along the The Y direction extends perpendicular to the X direction.
  • the current direction in the channel layer 13 of the first transistor T1 is perpendicular to the current direction in the channel layer 23 of the second transistor T2.
  • FIG. 14 is another implementable structure of the first transistor T1 and the second transistor T2 provided by the embodiment of the present application.
  • the second electrode 12 or the gate electrode 42 is omitted.
  • the channel layer 13 of the first transistor T1 is electrically isolated from the channel layer 23 of the second transistor T2 through the gate dielectric layer 51 .
  • the channel layer 13 not only serves as the channel of the first transistor T1, but can also serve as the gate 42 of the second transistor T2 or the second electrode 12 of the first transistor. In this case, by simplifying the process structure , which can also increase storage density.
  • a cavity 231 can be formed in the channel layer 23 close to the channel layer 13, and the channel layer 13 can be One end extends into the cavity 231.
  • a gate dielectric layer 51 can be formed on the wall of the cavity 231 , and the second electrode 12 extending into the cavity 231 is electrically isolated from the channel layer 13 through the gate dielectric layer 51 located in the cavity 231 . open.
  • one end of the channel layer 13 is extended into the cavity 231 , and is electrically isolated from the channel layer 13 by the gate dielectric layer 51 located in the cavity 231 .
  • Figure 16 exemplarily shows yet another structure that can be implemented of the memory unit.
  • a cavity is not formed in the channel layer 23 close to the channel layer 13 , but the surface of the channel layer 23 opposite to the channel layer 13 is a plane, and the channel layer 13 is formed on this surface.
  • the gate dielectric layer 51 on the plane is electrically isolated from the channel layer 23 .
  • the surface of the channel layer 23 opposite to the channel layer 13 is a plane, and the end of the channel layer 13 forms the second pole 12 of the first transistor T2, and the second pole 12 passes through
  • the gate dielectric layer 5 is electrically isolated from the channel layer 23 .
  • the first transistor T1 also includes a gate 41 .
  • the gate 41 of the first transistor T1 may have a single gate structure, a double gate structure, or a gate-all-around structure as shown in FIG. 12 .
  • the gate 41 of the first transistor T1 is electrically isolated from the channel layer 13 by the gate dielectric layer 51 .
  • the gate 41 of the first transistor T1 may belong to the same metal layer as the third electrode line 63 , that is, the third electrode line 63 is electrically isolated from the channel layer 13 through the gate dielectric layer 51 .
  • a first electrode 11 is formed on one end of the channel layer 13 away from the channel layer 23 .
  • one end of the opposite ends of the channel layer 23 forms the first electrode 21, and the other end forms the second electrode 22.
  • a first electrode line 61 (such as a write bit line WBL) and a second electrode line 62 (such as a read bit line RBL) are formed.
  • the first electrode line 61 and the second electrode line 62 extend in the same direction.
  • the first electrode line 61 and the second electrode line 62 may extend along the Y direction parallel to the substrate.
  • the first electrode 11 of the first transistor T1 and the first electrode line 61 share the same metal layer, that is, the first electrode line 61 can be directly connected to the channel shown in Figure 17 Layer 13 contacts, achieving electrical connection.
  • the fourth electrode line 64 extending in the direction perpendicular to the substrate may share the same metal layer with the second pole of the second transistor T2 , that is, the fourth electrode line 64 may directly contact the channel layer 23 , realizing the electrical connection between the second transistor T2 and the fourth electrode line 64.
  • the second electrode line 62 extends along the Y direction, and the second electrode line 62 is located on a side of the channel layer 23 away from the first transistor T1. In order to electrically connect the first pole 21 of the second transistor T2 to the second electrode line 62, see FIG. The two electrode lines 62 are electrically connected.
  • the first electrode line 61 , the first pole 21 , the second pole 22 of the second transistor T2 , the conductive connection portion 7 and the second electrode line 61 may all be metal layers. Or, in some other embodiments, part of the first electrode line 61 , the first pole 21 , the second pole 22 of the second transistor T2 , the conductive connecting part 7 and the second electrode line 61 are metal layers, and part of them are metal layers. A conductive layer formed in a semiconductor material through a doping process.
  • the first electrode line 61 and the second electrode 22 are metal layers, while the first electrode 21, the conductive connection part 7 and the second transistor T2
  • the two electrode lines 61 are conductive layers formed in semiconductor materials through a doping process.
  • the following will be introduced in the preparation method of the memory array.
  • Figure 18 shows a diagram containing four memory cells as shown above.
  • the four memory cells form a 2 ⁇ 2 memory array.
  • the four memory cells in the 2 ⁇ 2 memory array are respectively called memory cells. 400A, storage unit 400B, storage unit 400C and storage unit 400D.
  • the memory unit 400A and the memory unit 400B are arranged along the Y direction parallel to the substrate, and the memory unit 400A and the memory unit 400B are arranged mirror-symmetrically along the X direction parallel to the substrate. It can be understood that the second pole 22 of the second transistor T2 in the memory unit 400A is disposed close to the second pole 22 of the second transistor T2 in the memory unit 400B.
  • the second electrode 22 of the second transistor T2 in the memory unit 400A is electrically isolated from the second electrode 22 of the second transistor T2 in the memory unit 400B by an insulating layer.
  • the second electrode line 62 extends in the Y direction, and the memory cells 400A and 400B arranged in the Y direction are electrically connected to the same second electrode line 62 .
  • the memory cells 400A and 400C are arranged along the X direction parallel to the substrate, and the memory cells 400A and 400C are mirror-symmetrically arranged along the Y direction parallel to the substrate.
  • the channel layer of the first transistor T1 in the memory unit 400A and the channel layer of the first transistor T1 in the memory unit 400C are electrically connected to the same first electrode line 61, that is, they share the same first electrode line 61. .
  • Figure 19 If the structure shown in Figure 18 is arranged in the X-Y plane parallel to the substrate, a one-layer memory array shown in Figure 19 can be obtained. Figure 19 also exemplarily shows a part of this layer of memory array.
  • the three-dimensional memory array shown in Figure 20 can be obtained.
  • the memory array shown in Figure 20 can be electrically connected to the controller through interconnection lines.
  • the interconnection lines can be formed on a side of the memory array away from the substrate using a subsequent process.
  • the interconnection lines formed on the substrate and electrically connected to the memory array include a plurality of write word line interconnection lines arranged in parallel, such as WWL0, WWL1, WWL2, WWL3, WWL4, as shown in Figure 20 WWL5, WWL6 and WWL7, among which any WWL can be connected to the writing line located in the X-Y plane through a conductive channel.
  • the interconnection lines also include multiple parallel read word line interconnection lines, such as RWL0, RWL1, RWL2, RWL3, RWL4, RWL5 and RWL6 shown in Figure 20, and any RWL can be connected through a conductive channel Reading word lines located in the X-Y plane.
  • the interconnection lines also include a plurality of read bit line interconnection lines shown in Figure 20, such as RBLc0 to RBLc13 shown in Figure 20. Each read bit line interconnection line connects the read bit lines located in the X-Y plane through a conductive channel.
  • the interconnection lines also include a plurality of write bit line interconnection lines shown in FIG. 20 , such as WBLc0 to WBLc13 shown in FIG. 20 . Each write bit line interconnection line connects the write bit lines located in the X-Y plane through a conductive channel.
  • the memory cells to be read can be selected through the interconnection lines shown in Figure 20.
  • the specific read and write processes have been introduced above and will not be repeated here.
  • the first transistor T1, the second transistor T2, the first electrode line 61, the second electrode line 62, the third electrode line 63 and the fourth electrode line 64 can be selected from a variety of materials. Some of the materials you can choose from are given below.
  • any channel in the channel layer 13 and the channel layer 23 can select Si (silicon), poly-Si (p-Si, polysilicon), amorphous-Si (a-Si, amorphous silicon). Silicon), In-Ga-Zn-O (IGZO, indium gallium zinc oxide) multicomponent compound, ZnO (zinc oxide), ITO (indium tin oxide), TiO 2 (titanium dioxide), MoS 2 (molybdenum disulfide), WS 2.
  • One or more of semiconductor materials such as tungsten disulfide, graphene, and black phosphorus.
  • the above-mentioned gate dielectric layer 51 can be made of SiO 2 (silicon dioxide), Al 2 O 3 (aluminum oxide), HfO 2 (hafnium dioxide), ZrO 2 (zirconia), TiO 2 (titanium dioxide), Y 2 O 3 (yttrium trioxide) and Si 3 N 4 (silicon nitride) and other insulating materials.
  • the materials of the first and second electrodes, the first and second electrode lines, and the third and fourth electrode lines of any one of the above-mentioned first transistor T1 and second transistor T2 are conductive.
  • the materials of the first pole 51 and the second pole 52 may be TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In- One or more of conductive materials such as Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver).
  • FIG. 21 exemplarily shows a process structure diagram of a 2T2C memory cell.
  • the memory cells can be used in FeRAM memory arrays.
  • the 2TnC memory cell provided in the embodiment of the present application is similar to the above-mentioned 2TOC memory cell in that it includes a first transistor T1 and a second transistor T2. The difference is that the 2TnC memory cell also includes an iron Electric capacitor C.
  • one ferroelectric capacitor C may be included, or as shown in FIG. 21 , two ferroelectric capacitors C may be included, or more ferroelectric capacitors C may be included.
  • the 2TnC memory cell shown in Figure 21 is the same as the 2T0C memory cell shown above.
  • the first electrode 21, the second electrode 22 and the channel layer 23, as well as the first electrode line 61 and the second electrode line 62 are located in the same metal layer parallel to the substrate, and the first electrode line 61 and the second electrode
  • the extension directions of the lines 62 are consistent, and the third electrode line 63 and the fourth electrode line 64 extend in a direction perpendicular to the substrate.
  • one process can be used to prepare multiple memory cells stacked in a direction perpendicular to the substrate at the same time. In this way, the preparation process can be simplified. , reducing the complexity of the process.
  • the first electrode line 61 in Figure 21 is the write bit line WBL shown in Figure 7.
  • the second electrode line 62 is the read bit line RBL shown in FIG. 7
  • the third electrode line 63 is the source line SL shown in FIG. 7
  • the fourth electrode line 64 is the precharge line CL shown in FIG. 7 .
  • the channel layer 13 of the first transistor T1 and the channel layer 23 of the second transistor T2 shown in FIG. 21, and the extending directions of the first electrode line 61 and the second electrode line 62 please refer to the above-mentioned 2TnC memory device. unit.
  • the channel layer 13 of the first transistor T1 is arranged perpendicularly to the channel layer 23 of the second transistor T2 , and the extension direction of the first electrode line 61 and the second electrode line 62 is in the same direction as the channel layer 23 The extension direction is the same.
  • the ferroelectric capacitor C of the 2TnC memory cell includes a first ferroelectric electrode 81 , a ferroelectric film layer 82 and a second ferroelectric electrode 82 , wherein the ferroelectric film layer 82 is stacked on the first ferroelectric electrode 81 and the second ferroelectric electrode 82.
  • the first ferroelectric electrode 81 is also located in the metal layer where the first and second electrodes of the first transistor T1 and the second transistor T2 are located. That is to say, the first pole 11, the first pole 12, the second pole 22, at least part of the channel layer 13, at least part of the channel layer 23 and the first ferroelectric electrode 81 in Figure 21 are all located in the same metal layer. .
  • a cavity 231 is formed in the channel layer 23 of the second transistor T2 close to the first transistor T1 , and a first ferroelectric electrode 81 is formed at an end of the channel layer 13 of the first transistor T1 .
  • a portion of a ferroelectric electrode 81 extends into the cavity 231 , and the first ferroelectric electrode 81 is electrically isolated from the channel layer 23 by the ferroelectric film layer 82 .
  • the first ferroelectric electrode 81 can not only serve as the first electrode of the ferroelectric capacitor, but also can serve as the gate electrode of the second transistor, or can also serve as the electrode of the first transistor.
  • the second ferroelectric electrode 83 can be electrically connected to the fifth electrode line 65, for example, to the word line WL shown in Figure 7.
  • the first ferroelectric electrode serves as an electrode of the ferroelectric capacitor and is connected to the word line WL.
  • the voltage difference on line WL completes the writing of stored information.
  • both the precharge line CL and the word line WL extend in a direction perpendicular to the substrate.
  • the two word lines WL and the precharge line CL are parallel and arranged in a direction perpendicular to the substrate.
  • the word line WL and the precharge line CL are electrically isolated from each other, and the word line WL and the word line WL are also electrically isolated from each other.
  • Figure 22 is a process structure diagram of another 2TnC memory cell according to the embodiment of the present application.
  • the gate 42 of the second transistor T2 is shown.
  • the gate 42 is electrically connected to the first ferroelectric electrode 81 and at least part of the gate 42 is embedded in the cavity 231 of the channel layer 23 .
  • the first ferroelectric electrode 81 can be made of at least one of tungsten W, titanium nitride TiN, polysilicon, cobalt Co, nickel Ni, and copper Cu.
  • the pole 42 can also be made of at least one of tungsten W, titanium nitride TiN, polysilicon, cobalt Co, nickel Ni, and copper Cu.
  • Figure 23 is a process structure diagram of another 2TnC memory cell according to the embodiment of the present application.
  • the 2TnC memory cell includes multiple ferroelectric capacitors C
  • these multiple ferroelectric capacitors C are arranged at intervals, and the arrangement direction is consistent with the extending direction of the channel layer 13 of the first transistor T1
  • the plurality of second ferroelectric electrodes 83 included in the plurality of ferroelectric capacitors C are insulated from each other.
  • an insulating layer can be used to electrically isolate two adjacent second ferroelectric electrodes 83 .
  • the ferroelectric film layer 82 that electrically isolates the first ferroelectric electrode 81 and the second ferroelectric electrode 83 can be combined with the gate dielectric layer 51 that electrically isolates the first ferroelectric electrode 81 and the channel layer 23 .
  • the ferroelectric film layer 82 that electrically isolates the first ferroelectric electrode 81 and the second ferroelectric electrode 83 can be combined with the gate dielectric layer 51 that electrically isolates the first ferroelectric electrode 81 and the channel layer 23 .
  • ferroelectric materials such as hybrid HfO 2 or materials doped with other elements based on this material.
  • the ferroelectric film layer 82 that electrically isolates the first ferroelectric electrode 81 and the second ferroelectric electrode 83 can be combined with the gate dielectric layer 51 that electrically isolates the channel layer 13 and the first electrode line 61 . As an integrated structure.
  • the ferroelectric film layer 82 that electrically isolates the first ferroelectric electrode 81 and the second ferroelectric electrode 83 and the second ferroelectric electrode 83 can be electrically isolated.
  • the gate dielectric layer 51 and the channel layer 23 and the gate dielectric layer 51 that electrically isolates the channel layer 13 and the first electrode line 61 form an integrated structure.
  • ZrO 2 zirconia
  • HfO 2 hafnium dioxide
  • Al-doped HfO 2 Al-doped HfO 2
  • Si-doped HfO 2 Al-doped HfO 2
  • Zr-doped HfO 2 Al-doped HfO 2
  • Si-doped HfO 2 zir-doped HfO 2
  • Zr-doped HfO 2 La-doped HfO 2
  • Y-doped HfO 2 Y-doped HfO 2
  • One or more of the electrical materials or materials doped with other elements based on the material.
  • a cavity 231 is formed on the channel layer 23, and at least part of the first ferroelectric electrode 81 or at least part of the gate electrode 42 is embedded in the cavity 231. , in this way, the size of the memory unit can be further reduced and the integration density of the 2TnC memory unit can be increased.
  • Figure 24 is a process structure diagram of yet another 2TnC memory cell according to an embodiment of the present application.
  • this memory cell no cavity is formed on the side of the channel layer 23 , that is, the surface of the channel layer 23 opposite to the first ferroelectric electrode 81 is a plane, and the first ferroelectric electrode 81 passes through the ferroelectric film layer 82 electrically isolated from channel layer 23.
  • the materials that can be selected for the remaining structures can refer to the materials for the corresponding structures in the above-mentioned 2TOC memory cells.
  • a three-dimensional memory array can be obtained by arranging any of the memory cells in Figures 21 to 24 in the X, Y and Z directions that are perpendicular to each other.
  • FIG. 25 is a simple example of a memory array formed in the X-Y plane when the 2TnC memory cell shown in FIG. 21 is used.
  • the first electrode line 61 and the second electrode line 62 extend in the same direction, for example, along the Y direction parallel to the substrate, and the third electrode line 63, the fourth electrode line 64 and the fifth electrode line 65 extend along the Y direction parallel to the substrate.
  • the substrate extends in a direction perpendicular to the substrate.
  • the first electrode line 61 is WBL
  • the second electrode line 62 is RBL
  • the third electrode line is CL
  • the fourth electrode line is SL
  • the fifth electrode line is WL.
  • Figure 26 exemplifies a flow chart for preparing a memory array.
  • Step S1 Form multiple semiconductor layers and multiple dielectric layers on the substrate, and stack the multiple semiconductor layers and multi-layer dielectric layers alternately in a direction perpendicular to the substrate.
  • 5 semiconductor layers and 5 dielectric layers can be stacked on the substrate, and the 5 semiconductor layers and 5 dielectric layers are stacked alternately, that is, two adjacent semiconductor layers are separated by a dielectric layer.
  • the semiconductor layer here can be Si (silicon), poly-Si (p-Si, polysilicon), amorphous-Si (a-Si, amorphous silicon), In-Ga-Zn-O (IGZO, indium gallium zinc oxide ) one or more of the multi-component compounds, ZnO (zinc oxide), ITO (indium tin oxide), TiO 2 (titanium dioxide), MoS 2 (molybdenum disulfide), WS 2 (tungsten disulfide) and other semiconductor materials.
  • the dielectric layer can choose SiO 2 (silicon dioxide), Al 2 O 3 (aluminum oxide), HfO 2 (hafnium dioxide), ZrO 2 (zirconia), TiO 2 ( titanium dioxide), Y 2 O 3 (dioxide trioxide).
  • insulating materials such as yttrium) and Si 3 N 4 (silicon nitride).
  • Step S2 Pattern each semiconductor layer to form a first electrode line, a second electrode line, and a memory unit including a first transistor and a second transistor; both the first transistor and the second transistor include a first electrode, the second electrode, the gate electrode and the channel layer, the first electrode of the first transistor is electrically connected to the first electrode line, the first electrode of the second transistor is electrically connected to the second electrode line, and the first electrode line and the second electrode line, And at least part of the first electrode, the second electrode, and the channel layer of each transistor of the first transistor and the second transistor are located in the first metal layer, and the first metal layer is parallel to the dielectric layer.
  • the embodiment of the present application does not limit the order of preparation of the first electrode line, the second electrode line, the first transistor, and the second transistor.
  • the first transistor and the first electrode line can be prepared first, and then A second transistor and a second electrode line are produced.
  • the first transistor and the second transistor each include a first electrode, a second electrode, a gate electrode and a channel layer.
  • the first electrode of the first transistor is electrically connected to the first electrode line
  • the first electrode of the second transistor is electrically connected to the third electrode line. Two electrode wires.
  • the gate electrode of the first transistor is electrically connected to the third electrode line
  • the second electrode of the second transistor is electrically connected to the fourth electrode line.
  • first electrode line, the second electrode line, and the first electrode, the second electrode and the channel layer of each transistor of the first transistor and the second transistor are located in the same metal layer parallel to the substrate. That is to say, the patterning process can be performed on the same semiconductor layer, and the first electrode, the second electrode, the channel layer, the first electrode line and the second electrode line can be produced.
  • Figures 27a to 27l show the process structure after each step is completed in the process of manufacturing a memory array according to the embodiment of the present application.
  • multi-layer semiconductor layers 10 and multi-layer dielectric layers 20 are formed on a substrate (not shown in the figure), and the multi-layer semiconductor layers 10 and multi-layer dielectric layers 20 alternate along the direction perpendicular to the substrate. Stacked.
  • the materials that can be selected for the semiconductor layer and the dielectric layer are introduced above and will not be described here.
  • multiple through holes 301 are opened along the direction parallel to the substrate.
  • these multiple through holes 301 can be arranged at intervals along the Y direction parallel to the substrate.
  • each through hole 301 penetrates the multi-layer semiconductor layer 10 and the multi-layer dielectric layer 20 .
  • each through hole 301 is filled with insulating material to form an insulating layer 401.
  • the insulating layer 401 in Figure 27c can be selected from SiO 2 (silicon dioxide), Al 2 O 3 (aluminum oxide), HfO 2 (hafnium dioxide), ZrO 2 (zirconia), TiO 2 (titanium dioxide), Y 2 O 3 (yttrium trioxide) and Si 3 N 4 (silicon nitride) and other insulating materials.
  • a first groove 201 is opened on any semiconductor layer 10 .
  • the first groove 201 includes a first part 201A extending along the Y direction, and a second part 201B located between two adjacent insulating layers 401 .
  • an etching process can be used.
  • the second portion 201B of the first trench 201 can exceed the side of the insulating layer 401 away from the first portion, so as to connect the semiconductor A cavity 231 is formed in layer 10 .
  • the cavity 231 formed in this structure can form the cavity 231 shown in FIG. 21. This cavity 231 is used to extend the channel layer 13 of the first transistor T1 to reduce the area occupied by the memory cell. .
  • a first groove 201 is opened on each semiconductor layer 10 .
  • an etching process can be used to etch the first grooves 201 on multiple semiconductor layers 10 at the same time. That is, multiple semiconductor layers are patterned at the same time to form multiple stacked memory cells at the same time.
  • a gate dielectric layer 51 is formed on the wall surface of the first trench 201.
  • each semiconductor layer 10 has a first trench 201 , the gate dielectric layer 51 can be formed on the walls of these multiple first trenches 201 at the same time.
  • the second part 201B of the first trench 201 is filled with a semiconductor material to form the channel layer 13 of the first transistor T1; and, the first part of the first trench is filled with a conductive material, such as a metal material, To form the first electrode line 61 extending along the Y direction.
  • the channel layer 13 may be formed in the second part of each of the plurality of semiconductor layers, and the first electrode line 61 may be formed in the first part of each semiconductor layer. That is, the channel layers 13 of multiple first transistors are formed at the same time, and the multiple first electrode lines 61 are formed at the same time.
  • a through hole 302 is opened on the side of the channel layer 13 of the first transistor T1 formed in Figure 27f, and the through hole 302 penetrates the multi-layer semiconductor layer 10 and the multi-layer dielectric layer in a direction perpendicular to the substrate. 20.
  • through holes 302 can be opened on opposite sides of the channel layer 13 .
  • a through hole may be opened on only one side of the opposite sides of the channel layer 13.
  • the first transistor formed is a single-gate transistor.
  • the through hole 302 is filled with conductive material, such as metal, to form a third electrode line 63 electrically connected to the gate of the first transistor.
  • conductive material such as metal
  • the third electrode line 63 is the write word line WWL.
  • the third electrode line 63 is the precharge line CL.
  • a second groove 202 is opened on each semiconductor layer 10.
  • the second groove 202 includes a third portion 202A extending along the Y direction, and a third portion 202A located between the channel layers 13 of the two adjacent first transistors T1. Part IV 202B.
  • insulating material is filled in both the third part 202A and the fourth part 202B to form an insulating layer 402.
  • the third portion of the semiconductor layer extending along the Y direction and adjacent to the second trench is doped to form a second electrode line 62 extending along the Y direction, and the third portion adjacent to the first transistor is doped.
  • the semiconductor layer of the channel layer is doped to form the first electrode 21 of the second transistor electrically connected to the second electrode line 62 .
  • the semiconductor layer is doped to form the second electrode line and the first electrode of the second transistor.
  • a groove can also be made on each semiconductor layer shown in FIG. 27j, and metal material is filled in the groove to form the second electrode line and the first electrode of the second transistor.
  • through holes 303 are opened in the semiconductor layers on opposite sides of the fourth part of the second groove, so that the through holes 303 penetrate the multi-layer semiconductor layer 10 and the multi-layer dielectric in a direction perpendicular to the substrate. layer 20;
  • the through hole 303 opened in Figure 27l is filled with conductive material to form the fourth electrode line 64.
  • a memory is produced by stacking one layer of memory array and then stacking another layer of memory array, as the storage density continues to increase, the number of stacked layers will also increase, and the requirements for photolithography alignment accuracy will also increase. High, if the alignment accuracy of the next-level storage array structure and the upper-level storage array structure is low, the read and write performance may be affected.
  • using the memory array preparation method provided by the embodiments of the present application requires lower photolithography alignment accuracy and does not pose higher challenges to the process. In this way, it can not only simplify the process and reduce the difficulty of the process, but also Improve the product quality rate, improve the read and write performance of the memory, and also reduce the manufacturing cost of the memory.

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Abstract

本申请实施例提供一种三维存储阵列、存储器、存储阵列的形成方法，以及电子设备。涉及半导体存储器技术领域。主要用于提升存储单元的集成密度。该存储器包括衬底、多个存储层，每一个存储层包括第一电极线和第二电极线，以及多个存储单元，每一个存储单元包括电连接的第一晶体管和第二晶体管，每一个存储层包括沿与衬底相垂直方向堆叠的第一金属层和第一介质层；第一电极线、第二电极线，以及第一晶体管和第二晶体管的每一个晶体管的第一极、第二极、沟道层的至少部分位于第一金属层中。通过将这些结构集成在同一金属层中，可以同时制造多层存储单元，以简化制备工艺。

Description

一种三维存储阵列、存储器及电子设备 技术领域
本申请涉及半导体存储技术领域，尤其涉及一种三维存储阵列、包含该三维存储阵列的存储器、三维存储阵列的形成方法，以及包含有该存储器的电子设备。
背景技术
在计算系统中，比如，动态随机存取存储器(dynamic random access memory，DRAM)作为一种内存结构，可以用于暂存中央处理器(central processing unit，CPU)的运算数据，以及与硬盘等外部存储器交换数据，是计算系统中非常重要的组成部分。
随着存储器往更高密度，更大带宽的发展，催生出许多种结构的存储单元，比如，DRAM中的2T0C存储单元，铁电存储器中的1T1C存储单元或者2TnC存储单元等，这里的T代表晶体管transistor，C代表电容器capacitor。
在诸如包含至少两个晶体管的存储单元中，晶体管工艺结构所占据的面积，可以影响存储单元的集成密度，从而，影响存储器的存储容量。
目前，为了提升存储密度，晶体管出现许多种不同工艺结构。然而，许多晶体管的布设方式又给制造工艺提出了挑战，如此一来，也会限定存储单元集成密度的提升。
发明内容
本申请提供一种三维存储阵列、包含该三维存储阵列的存储器、三维存储阵列的形成方法，以及包含有该存储器的电子设备。主要目的提供一种可以提升存储密度，也可以简化制造工艺的存储阵列。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，本申请提供了一种三维存储阵列，比如，该三维存储阵列可以用于动态随机存取存储器(dynamic random access memory，DRAM)中。
该三维存储阵列包括衬底、形成在衬底上的多个存储层，多个存储层沿着与衬底相垂直的方向堆叠，且每一个存储层包括第一电极线和第二电极线，以及多个存储单元；每一个存储单元包括电连接的第一晶体管和第二晶体管，例如，该存储单元可以是一种2T0C的存储单元结构，第一晶体管和第二晶体管均包括栅极、第一极和第二极，以及沟道层。
第一晶体管的第一极与第一电极线电连接，第二晶体管的第一极与第二电极线连接；第一晶体管的栅极可以与第三电极线电连接，第二晶体管的第二极可以与第四电极线电连接；比如，当该存储单元为DRAM中的2T0C存储单元时，这里的第一电极线可以为写位线，第二电极线为读位线，第三电极线为写字线，第四电极线为读字线。
其中，每一个存储层包括沿与衬底相垂直方向堆叠的第一金属层和第一介质层；第一电极线、第二电极线，以及第一晶体管和第二晶体管的每一个晶体管的第一极、第二极、沟道层的至少部分位于第一金属层中。
本申请给出多个存储单元的每一个存储单元中，第一晶体管和第二晶体管的每一个晶体管的第一极、第二极和沟道层，位于与衬底相平行的第一金属层中，即第一晶体管和第二晶体管沿与衬底相平行的方向排布，这样的话，可以将此种结构的存储单元沿着与衬底相垂直的方向，以及与衬底相平行的方向进行堆叠，实现三维堆叠，实现高密度集成，提升存储容量，以与处理器的运算数据量适配。
另外，在本申请中，由于第一电极线(比如WBL)、第二电极线(比如RBL)、晶体管的第一极、第二极、沟道层的至少部分处于与衬底相平行的第一金属层中，而不是第一极、第二极和沟道层位于一层金属层中，而第一电极线和第二电极线位于另一层金属层中。
那么，在制得本申请的存储阵列时，可以先堆叠交替布设多层介质层和多层半导体层，然后，在堆叠的这些层结构上进行加工，可以同时加工出多层存储单元，比如，当交替堆叠10层介质层和10层半导体层时，完成一道加工工艺后，可以同时制得10层存储单元，以及同时制得第一电极线和第二电极线，也就是说，本申请的多层器件可以同时进行加工，即一次性形成多层器件，而不需要先制得第一层存储阵列，再利用相同的工艺逐层制得第二层存储阵列、第三层存储阵列等。如此一来，从工艺角度讲，可以简化工艺流程，降低制造成本，尤其是对于三维堆叠层数较多的存储阵列，工艺繁琐性和制造成本均会被明显的降低，另外，还可以避免由于逐层制得存储阵列，造成的存储单元对准精度差的现象。
在一种可能的实现方式中，第一晶体管和第二晶体管的每一个晶体管的沟道层，一部分位于第一金属层中，另一部分延伸至第一介质层中。
或者，第一晶体管和第二晶体管的每一个晶体管的沟道层全部位于第一金属层中。
在一种可能的实现方式中，存储阵列还包括第三电极线和第四电极线；第三电极线和第四电极线均沿与衬底相垂直的方向延伸；第三电极线电连接每相邻两层存储层中的第一晶体管的栅极；第四电极线电连接每相邻两层存储层中的第二晶体管的第二极。
即在本申请给出的实施例中，第一电极线和第二电极线沿与衬底相平行的方向延伸，而第三电极线和第四电极线沿与衬底相垂直的方向延伸。在一种可能的实现方式中，第一晶体管的沟道层为第一沟道层，第二晶体管的沟道层为第二沟道层；第一沟道层与第二沟道层相垂直布设；第一电极线和第二电极线的延伸方向与第二沟道层的延伸方向一致。
比如，第一沟道层沿第一方向延伸，第二沟道层、第一电极线和第二电极线均沿与第一方向相垂直的第二方向延伸。
第一沟道层沿第一方向延伸可以理解为第一沟道层中的电流方向为第一方向，第二沟道层沿第二方向延伸可以理解为第二沟道层的电流方向为第二方向。
在一种可能的实现方式中，第一沟道层的靠近第二沟道层的一端，通过形成在第一沟道层和第二沟道层界面处的栅介质层与第二沟道层电隔离开。
在此实施例中，第一沟道层不仅作为第一晶体管的沟道，还可以作为第二晶体管的栅极。这样，可以简化工艺结构，可以进一步的提升存储密度。
在一种可能的实现方式中，第二沟道层的靠近第一沟道层的位置处形成有凹腔， 第一沟道层的一端设置在凹腔内，并通过形成在凹腔内壁上的栅介质层与第二沟道层电隔离开。
利用在第二沟道层上设置的凹腔，以将第一沟道层设置在该凹腔内，可以进一步的减小该存储单元所占用的面积，以进一步的提升存储密度，提高该存储阵列的存储容量。
在一种可能的实现方式中，嵌入凹腔的第一沟道层的端部形成有第二晶体管的栅极，第二晶体管的栅极，通过形成在凹腔内壁上的栅介质层与第二沟道层电隔离开，且第二晶体管的栅极和第一晶体管的第二极共用同一电极。
相比上述的直接将第一沟道层通过栅介质层与第二沟道层电绝缘，本实现方式中，还引入了第二晶体管的栅极结构，第二晶体管的栅极通过栅介质层与第二沟道层电绝缘。
在一种可能的实现方式中，存储阵列还包括第五电极线，每一个存储单元还包括至少一个铁电电容；铁电电容包括第一铁电电极、铁电膜层和第二铁电电极，第一铁电电极与第一晶体管的第二极和第二晶体管的栅极分别电连接，第二铁电电极与第五电极线电连接；第一铁电电极、第一晶体管和第二晶体管的每一个晶体管的第一极、第二极和沟道层，位于与衬底相平行的同一金属层中；第五电极线沿与衬底相垂直的方向延伸。
由于存储单元还包括了至少一个电容，从而可以形成2TnC存储单元，该2TnC存储单元可以被应用在铁电随机存取存储器(ferroelectric random access memory，FeRAM)中。
并且，在2TnC存储单元中，第一铁电电极、第一晶体管和第二晶体管的每一个晶体管的第一极、第二极和沟道层，位于与衬底相平行的同一金属层中，这样的话，本申请的存储阵列可以同时进行加工，即一次性形成多层器件。
在一种可能的实现方式中，第一铁电电极的延伸方向与第一沟道层的延伸方向一致，且第一铁电电极形成在第一沟道层的靠近第二沟道层的一端，并通过栅介质层与第二沟道层电隔离开；第二铁电电极设置在第一铁电电极的侧面，并通过铁电膜层与第一铁电电极电隔离开。
在一种可能的实现方式中，第二沟道层的靠近第一铁电电极的位置处形成有凹腔，第一铁电电极的一端设置在凹腔内，并通过形成在凹腔内壁上的栅介质层与第二沟道层电隔离开。
通过将第一铁电电极设置在第二沟道层的凹腔内，可以进一步的减小存储单元所占的面积，以在单位面积内集成更多的存储单元，提升存储容量。
在一种可能的实现方式中，每一个存储单元包括多个铁电电容；多个铁电电容沿着与第一沟道层延伸方向相平行的方向间隔排布。
从而，使得该存储单元称为包括多个铁电电容的2TnC存储单元。
在一种可能的实现方式中，在第一沟道层的远离第二沟道层的一端，形成与第一沟道层的延伸方向相垂直的并与第一沟道层接触电连接的第一电极线。
在一些示例中，这里的第一电极线不仅可以作为WBL，还可以作为第一晶体管的源极或者漏极。
在一种可能的实现方式中，在第一沟道层的侧面，形成与衬底相垂直的第三电极线，且第三电极线与第一沟道层之间被栅介质层电隔离开。
在一些示例中，这里的第三电极线不仅可以作为WWL，还可以作为第一晶体管的栅极。该第一晶体管的栅极可以是双栅结构、单栅结构或者环栅结构。
在一种可能的实现方式中，第二沟道层的相对的两端形成有第二晶体管的第一极和第二极。
在一种可能的实现方式中，第二电极线位于第二沟道层的远离第一沟道层的一侧；存储单元还包括导电连接部，第二晶体管的第一极通过导电连接部与第二电极线电连接。
利用导电连接部将第二晶体管的第一极引出，以与第二电极线电连接。
在一种可能的实现方式中，第二晶体管的第一极、第二电极线和导电连接部均在半导体层中通过掺杂工艺制得。
当然，第一极、第二电极线和导电连接部也可以采用金属材料制得。
在一种可能的实现方式中，沿与衬底相垂直方向延伸的第四电极线，与第二沟道层的相对的两端中的另一端接触。
在一些示例中，该第四电极线不仅可以作为RWL，还可以作为第二晶体管的第二极。
在一种可能的实现方式中，多个存储单元包括第一存储单元和第二存储单元；第一存储单元和第二存储单元沿与衬底相平行的方向排布；第一存储单元和第二存储单元的任一存储单元中，第一晶体管的第一极均与第一电极线电连接，第二晶体管的第一极均与第二电极线连接。
也就是，沿与衬底相平行布设的第一存储单元和第二存储单元中，可以共用第一电极线和第二电极线。
在一种可能的实现方式中，多个存储单元包括第一存储单元和第三存储单元；第一存储单元和第三存储单元沿与衬底相垂直的方向堆叠，第一存储单元和第三存储单元的任一存储单元中，第一晶体管的栅极均与第三电极线电连接，第二晶体管的第二极均与第四电极线电连接。
沿与衬底相垂直布设的第一存储单元和第二存储单元，可以共用第三电极线和第四电极线。
在一种可能的实现方式中，多个存储单元、第一电极线、第二电极线、第三电极线和第四电极线均采用后道工艺形成在衬底上。
第一晶体管和第二晶体管均为采用后道工艺制作，控制器可以通过前道工艺制作。该控制器可以包括译码器、驱动器、时序控制器、缓冲器或输入输出驱动中的一个或多个电路，还可以包括其他功能电路。该控制器可以控制本申请实施例中的第一电极线、第二电极线、第三电极线和第四电极线。在完成前道工艺FEOL后，互连线，以及存储阵列均通过后道工艺BEOL制作。可以使得单位面积内的电路密度更大，从而提升单位面积的存储性能。
在一种可能的实现方式中，存储阵列为DRAM存储阵列。
这样的话，该存储单元理解为DRAM存储阵列中的2T0C存储单元。
在一种可能的实现方式中，当该存储单元理解为DRAM存储阵列中的2T0C存储单元时，第一电极线为写位线，第二电极线为读位线，第三电极线为写字线，第四电极线为读字线。
在一种可能的实现方式中，存储阵列为铁电存储阵列。
在一种可能的实现方式中，存储阵列还包括第五电极线，每一个存储单元还包括至少一个铁电电容；铁电电容包括第一铁电电极、铁电膜层和第二铁电电极，第一铁电电极与第一晶体管的第二极和第二晶体管的栅极分别电连接，第二铁电电极与第五电极线电连接；第一电极线为写位线，第二电极线为读位线，第三电极线为预充电线，第四电极线为源线，第五电极线为字线。
第二方面，本申请还提供了一种存储器，该存储器包括控制器和上述任一实现方式中的存储阵列，控制器与存储阵列电连接，控制器用于控制存储阵列的读写。
在本申请提供的存储器中，由于包括了上述实现方式中的存储阵列，在存储阵列中，第一晶体管和第二晶体管沿与衬底相平行的方向排布，这样，可以将此种结构的存储单元沿着与衬底相垂直的方向，以及与衬底相平行的方向进行堆叠，实现三维堆叠，实现高密度集成，提升存储容量。
在一种可能的实现方式中，存储阵列和控制器被集成在同一个芯片中，且该芯片设置在基板上。
在一种可能的实现方式中，存储阵列被集成在第一芯片中，控制器被集成在第二芯片中，且第一芯片和第二芯片均通过电连接结构设置在基板上。
在一种可能的实现方式中，存储阵列被集成在第一芯片中，控制器被集成在第二芯片中，第一芯片与第二芯片堆叠，并集成在基板上。
第三方面，本申请还提供了一种电子设备，包括处理器和上述任一实现方式中的存储器，处理器与存储器电连接，存储器用于存储处理器产生的数据。
本申请实施例提供的电子设备包括上述任一实现方式中的存储器，因此本申请实施例提供的电子设备与上述技术方案的存储器能够解决相同的技术问题，并达到相同的预期效果。
第四方面，本申请还提供了一种存储阵列的形成方法，该形成方法包括：
在衬底上形成多层半导体层和多层介质层，且多层半导体层和多层介质层沿着与衬底相垂直的方向交替堆叠；
对每一个半导体层进行图形化处理，以形成第一电极线、第二电极线、包含第一晶体管和第二晶体管的存储单元；
其中，第一晶体管和第二晶体管均包含第一极、第二极、栅极和沟道层，第一晶体管的第一极电连接第一电极线，第二晶体管的第一极电连接第二电极线，且第一电极线、第二电极线，以及第一晶体管和第二晶体管的每一个晶体管的第一极、第二极和沟道层的至少部分，位于与衬底相平行的第一金属层中，第一金属层与介质层平行。
本申请提供的存储阵列的形成方法中，首先是堆叠了多层交替布设的半导体层和介质层，然后在每一个半导体层上构图，形成第一晶体管和第二晶体管的第一极、第二极、沟道层，以及第一电极线和第二电极线。也可以理解为，可以同时制得多层存储单元，不需要一层一层堆叠存储单元，这样的话，不仅可以简化制备工艺，还可以 避免多层堆叠时，引起的对准工艺难度较大的问题。
在一种可能的实现方式中，对每一个半导体层进行图形化处理，以形成第一电极线、第二电极线、包含第一晶体管和第二晶体管的存储单元之前，形成方法还包括：开设多个第一通孔，多个第一通孔沿第一方向间隔排布，且任一第一通孔沿着与衬底相垂直的方向贯通多层半导体层和多层介质层；在第一通孔内填充绝缘层。形成的该绝缘层是为了电隔离相邻的两个存储单元。
在一种可能的实现方式中，对每一个半导体层进行图形化处理，以形成第一电极线、第二电极线、包含第一晶体管和第二晶体管的存储单元，包括：在每一个半导体层上开设第一槽，第一槽包括沿第一方向延伸的第一部分，和位于相邻两个绝缘层之间的第二部分；在第一槽的壁面上形成栅介质层；在第二部分内填充半导体材料，以形成第一晶体管的沟道层；在第一部分内填充导电材料，以形成沿第一方向延伸的第一电极线。
在一种可能的实现方式中，在每一个半导体层上开设第一槽，第一槽包括沿第一方向延伸的第一部分，和位于相邻两个绝缘层之间的第二部分，第二部分超出绝缘层的远离第一部分的侧面，以在半导体层内形成凹腔，以使得第一晶体管的沟道层设置在凹腔内。
这样形成的存储单元中，第一晶体管的沟道层是嵌入至第二晶体管的沟道层中，从而，可以进一步的减小存储单元的面积，提升存储密度。
在一种可能的实现方式中，在每一个半导体层上构图，形成第一电极线、第二电极线、包含第一晶体管和第二晶体管的存储单元，还包括：在每一个半导体层上开设第二槽，第二槽包括沿第一方向延伸的第三部分，和位于相邻两个第一晶体管的沟道层之间的第四部分；在第三部分和第四部分内均填充绝缘层。
在一种可能的实现方式中，在每一个半导体层上开设第二槽之后，形成方法还包括：对沿第一方向延伸的，且临接第二槽的第三部分的半导体层进行掺杂，以形成沿第一方向延伸的第二电极线，以及，对临接第一晶体管的沟道层的半导体层进行掺杂，以形成与第二电极线电连接的第二晶体管的第一极。
在此种实现方式中，是通过对半导体层进行掺杂，以形成第二晶体管的第二极和第二电极线，如此的话，可以简化工艺。
在一种可能的实现方式中，形成第四电极线，包括：在第四部分相对的两侧的半导体层上开设第二通孔，以使第二通孔沿着与衬底相垂直的方向贯通多层半导体层和多层介质层；在第二通孔内填充导电材料，以形成第四电极线。
在一种可能的实现方式中，形成第三电极线，包括：在第一晶体管的沟道层的侧面开设第三通孔，以使第三通孔沿着与衬底相垂直的方向贯通多层半导体层和多层介质层；在第三通孔内填充导电材料，以形成第三电极线。
可以在第一沟道层的相对的两侧均开设第三通孔，以形成环栅的第一晶体管，或者，可以在第一沟道层的相对两侧中的一侧开设第三通孔，以形成单栅的第一晶体管。
附图说明
图1为本申请实施例提供的一种电子设备中的电路图；
图2为本申请实施例提供的一种存储器的电路图；
图3a为本申请实施例提供的一种存储阵列和控制器的封装结构图；
图3b为本申请实施例提供的一种存储阵列和控制器的封装结构图；
图3c为本申请实施例提供的一种存储阵列和控制器的封装结构图；
图4为本申请实施例提供的一种存储器的三维结构示意图；
图5为本申请实施例提供的一种存储器的简易电路图；
图6为本申请实施例提供的一种存储器中一个存储单元的电路图；
图7为本申请实施例提供的一种存储器中一个存储单元的电路图；
图8为本申请实施例提供的一种存储器中一个存储单元和衬底的位置关系图；
图9为本申请实施例提供的一种存储器中三维简单示意图；
图10为本申请实施例提供的一种存储器中一个存储单元的工艺结构的剖面图；
图11为本申请实施例提供的一种存储器中一个存储单元的三维视图；
图12为图11的俯视图；
图13a为本申请实施例提供的一种存储器中二维简单示意图；
图13b为本申请实施例提供的一种存储器中三维简单示意图；
图14为本申请实施例提供的一种存储器中一个存储单元的工艺结构的剖面图；
图15为本申请实施例提供的一种存储器中一个存储单元的第二晶体管的工艺结构的剖面图；
图16为本申请实施例提供的一种存储器中一个存储单元的工艺结构的剖面图；
图17为本申请实施例提供的一种存储器中一个存储单元的工艺结构的剖面图；
图18为本申请实施例提供的一种存储器中多个存储单元形成的存储阵列的三维视图；
图19为本申请实施例提供的一种存储器中多个存储单元形成的存储阵列的工艺结构的剖面图；
图20为本申请实施例提供的一种存储器中多层存储阵列的三维视图；
图21为本申请实施例提供的一种存储器中一个存储单元的工艺结构的剖面图；
图22为本申请实施例提供的一种存储器中一个存储单元的工艺结构的剖面图；
图23为本申请实施例提供的一种存储器中一个存储单元的工艺结构的剖面图；
图24为本申请实施例提供的一种存储器中一个存储单元的工艺结构的剖面图；
图25为本申请实施例提供的一种存储器中多个存储单元形成的存储阵列的工艺结构的剖面图；
图26为本申请实施例提供的一种存储阵列制作方法的流程框图；
图27a至图27m为本申请实施例提供的一种存储器制作方法中各步骤完成后对应的工艺结构剖面图。
附图标记：
100-衬底；
200-电子设备；
300-存储器；
31-存储阵列；
32-控制器；
33-基板；
400、400A、400B、400C、400D、401、402、403、404-存储单元；
T1-第一晶体管、写晶体管；
T2-第二晶体管、读晶体管；
11、21-第一极；12、22-第二极；13、23-沟道层；
41、42-栅极；
51-栅介质层；
61-第一电极线；62-第二电极线；63-第三电极线；64-第四电极线；65-第五电极线；
7-导电连接部；
81-第一铁电电极；82-铁电膜层；82-第二铁电电极；
10-半导体层；
20-介质层；
201-第一槽；201A-第一部分；201B-第二部分；
301、302、303-通孔；
401、402-绝缘层。
具体实施方式
下面结合附图介绍本申请给出的实施例。
本申请实施例提供一种电子设备。图1为本申请实施例提供的一种电子设备200中的电路框图，该电子设备200可以是终端设备，例如手机，平板电脑，智能手环，也可以是个人电脑(personal computer，PC)、服务器、工作站等。
如图1，电子设备200可以包括总线205，以及与总线205连接的片上系统(system on chip，SOC)210。SOC210可以用于处理数据，例如处理应用程序的数据，处理图像数据，以及缓存临时数据。在一种实施方式中，SOC210可以包括用于处理应用程序的应用处理器(application processor，AP)211，用于处理图像数据的图像处理单元(graphics processing unit，GPU)212，以及用于缓存高速数据的第一随机存取存储器(random access memory，RAM)213。该第一RAM213可以是静态随机存取存储器(static random access memory，SRAM)或嵌入式闪存(embedded flash，eflash)等。上述AP211、GPU212和第一RAM213可以被集成于一个裸片(die)中，也可以被分别设置在多个die中。
再如图1所示，电子设备200还可以包括通过总线205与SOC210连接的第二RAM220。该第二RAM220可以是动态随机存取存储器(dynamic random access memory，DRAM)。第二RAM220可以用于保存易失性数据，例如SOC210产生的临时数据。第二RAM220的存储容量通常大于第一RAM213，但读取速度通常慢于第一RAM213。
此外，电子设备200还可以包括通过总线205与SOC210连接的通信芯片230和电源管理芯片240。通信芯片230可以用于协议栈的处理，或对模拟射频信号进行放大、滤波等处理，或同时实现上述功能。电源管理芯片240可以用于对其他芯片进行 供电。在一种实施方式中，SOC210和第二RAM220可以被封装在一个封装结构中，例如采用2.5D(dimension)或3D封装等，以获得更快的芯片间数据传输速率。
图2为本申请实施例提供的一种可以被应用在电子设备中的存储器300的电路框图。在一种实施方式中，存储器300可以是如图1所示的第一RAM213，也可以是第二RAM220。本申请存储器300的应用场景不做限定。
如图2所示，存储器300包括存储阵列31和用于访问存储阵列31的控制器32，其中，控制器32用于控制存储阵列31的读写操作。
其中，图2所示的存储阵列31和控制器32具有多种可以实现的封装结构，比如，下述给出了几种可以实现的封装结构。
图3a是本申请实施例给出的存储阵列31和控制器32的其中一种封装结构，即是，存储阵列31和控制器32是两个彼此独立的芯片，存储阵列31和控制器32分别被集成在基板33上，比如，存储阵列31和控制器32可以通过布设在基板33上的金属走线实现电导通。在此种结构中，由于存储阵列31和控制器32为两个相独立的芯片，因此该存储阵列31可以被称为独立(stand-alone)存储器。
图3b是本申请实施例给出的存储阵列31和控制器32的另一种封装结构。此结构中，和上述图3a类似的是，存储阵列31和控制器32是两个彼此独立的芯片，因而该存储阵列31也可以被称为独立存储器。和上述图3a不同的是，在图3b中，存储阵列31和控制器32相堆叠，比如，存储阵列31和控制器32之间可以通过硅通孔(through silicon via，TSV)或者重布线层(redistribution layer，RDL)相导通。
图3c是本申请实施例给出的存储阵列31和控制器32的又一种封装结构。在此种示例的结构中，将存储阵列31和控制器32集成到同一芯片3，芯片3被集成在基板33上，因此，该存储阵列31可以被称为嵌入式存储器。
在上述图3c所示的结构中，如图4所示，控制器32可以通过前道(front end of line，FEOL)制程被集成在衬底上，互连线和存储阵列通过后道(back end of line，BEOL)制程集成在控制器32上。利用这里的控制器可以产生控制信号，这些控制信号可以是读写控制信号，用于控制存储阵列中数据的读写操作，除外，这里的控制器也可以包括模拟电路部分，例如灵敏放大器等。
还有，再参阅图4，上述的存储阵列31可以是一层存储阵列，也可以是图4所示的包括沿与衬底垂直的Z方向堆叠的第一层存储阵列和第二层存储阵列，或者，在另外一些可选择的实施方式中，可以包括更多层的存储阵列。当包含两层或者更多层存储阵列的情况下，这样的存储器可以被称为三维集成存储器结构，以提升存储容量。
在一种实施方式中，存储器中的存储阵列31可以包括图5所示的多个阵列排布的存储单元400，其中每个存储单元400都可以用于存储1比特(bit)或者多bit的数据。存储阵列31还可以包括字线(word line，WL)和位线(bit line，BL)等信号线。每一个存储单元400都与对应的字线WL和位线BL电连接。不同的存储单元400可以通过WL和BL电连接。上述WL和BL中的一个或多个用于通过接收控制电路输出的控制电平，选择存储阵列中待读写的存储单元400，从而实现数据的读写操作。
存储器中的控制器32可以包括图5所示的译码器320、驱动器330、时序控制器340、缓存器350或输入输出驱动360中的一个或多个电路结构。
在图5所示存储器300结构中，译码器320用于根据接收到的地址进行译码，以确定需要访问的存储单元400。驱动器330用于根据译码器320产生的译码结果来控制信号线的电平，从而实现对指定存储单元400的访问。缓存器350用于将读取的数据进行缓存，例如可以采用先入先出(first-in first-out，FIFO)来进行缓存。时序控制器340用于控制缓存器350的时序，以及控制驱动器330驱动存储阵列310中的信号线。输入输出驱动360用于驱动传输信号，例如驱动接收的数据信号和驱动需要发送的数据信号，使得数据信号可以被远距离传输。
上述存储阵列310、译码器320、驱动器330、时序控制器340、缓存器350和输入输出驱动360可以集成于一个芯片中，也可以分别集成于多个芯片中。
本申请实施例涉及的存储器300可以是动态随机存取存储器(dynamic random access memory，DRAM)。比如，可以是包括2T0C存储单元的DRAM，包含2T0C存储单元结构的gain-cell存储器能实现纳秒级的读写速度以及毫秒级的存储时间，且其占用面积仅为静态随机存取存储器(static random access memory，SRAM)的三分之一，因为应用范围很广。
另外，本申请实施例涉及的存储器300也可以是铁电随机存取存储器(ferroelectric random access memory，FeRAM)，比如，可以是包含2TnC存储单元的FeRAM，这里的n可以等于1，或者，可以大于或者等于2，比如包括2T1C存储单元的FeRAM，或者，包括2T2C存储单元的FeRAM。
图6是本申请实施例给出的存储器300中的一个存储单元400的电路图。如图6，该存储单元400属于2T0C的gain-cell的存储单元结构，也就是在一个存储单元400中包括一个写晶体管T1(也可以被称为第一晶体管T1)和一个读晶体管T2(也可以被称为第二晶体管T2)。比如，第一晶体管T1和第二晶体管T2可以选择薄膜晶体管(Thin film transistor，TFT)结构。
其中，写晶体管T1的第一极与写位线(write bit line，WBL)电连接，写晶体管T1的第二极与读晶体管T2的栅极电连接，写晶体管T1的栅极与写字线(write word line，WWL)电连接。读晶体管T2的第一极与读位线(read bit line，RBL)电连接，读晶体管T2的第二极与读字线(read word line，RWL)电连接。
在图6所示的存储单元中，写位线WBL也可以被称为用于向写晶体管T1的第一极加载信号的第一电极线，读位线RBL也可以被称为用于向读晶体管T2的第一极加载信号的第二电极线，写字线WWL也可以被称为用于向写晶体管T1的栅极加载信号的第三电极线，读字线RWL也可以被称为用于向读晶体管T2的第二极加载信号的第四电极线。
下述对上述图6所示2T0C存储单元400的写操作过程和读操作过程分别进行说明。
写操作过程：在写操作过程中，读位线RBL的电压为0，读晶体管T2不工作；给写字线WWL提供第一写字线控制信号，第一写字线控制信号控制写晶体管T1导通。当写入第一逻辑信息，例如为“0”时，给写位线WBL(或者读字线RWL)，提供第一写位线控制信号，第一写位线控制信号通过写晶体管T1写入节点N。当写入第二逻辑信息，例如为“1”时，给写位线WBL(或者读字线RWL)提供第二写位线控制信号， 第二写位线控制信号通过写晶体管T1写入。
应当理解到，在写操作完成之后，读晶体管T2不工作；给写字线WWL提供第二写字线控制信号，第二写字线控制信号控制写晶体管T1断开，此时，节点存储的电位不受外界影响。
读操作过程：给写字线WWL提供第二写字线控制信号，第二写字线控制信号控制写晶体管T1断开；给读字线RWL(或者写位线WBL)提供读字线控制信号，根据读位线RBL上电流的高低判断存储单元的存储的逻辑信息。当节点存储的是第一写位线控制信号时，由于第一写位线控制信号可以控制读晶体管T2导通，因而在读字线RWL(或者写位线WBL)提供读字线控制信号时，读字线RWL(或者写位线WBL)通过读晶体管T2对读位线RBL充电，读位线RBL上的电压升高，这样一来，当检测到读位线RBL上的电流较大时，则可以读出存储单元存储的是逻辑信息“0”。当节点存储的是第二写位线控制信号时，由于第二写位线控制信号可以控制读晶体管T2关断，因此在读字线RWL(或者写位线WBL)提供读字线控制信号时，读字线RWL(或者写位线WBL)不会通过读晶体管T2对读位线RBL充电，读位线RBL维持0V电压，这样一来，当检测到读位线RBL上电流较小时，则可以读出存储单元存储的是逻辑信息“1”。
图7为本申请实施例提供的另一种存储单元400的电路图。该存储单元400包括第一晶体管T1，第二晶体管T2、铁电电容C1和铁电电容C2，即就是2T2C存储单元。其中，第一晶体管T1的栅极与预充电线CL电连接，第一晶体管T1的第二极与第二晶体管T2的栅极电连接，第一晶体管T1的第一极与写位线(write bit line，WBL)电连接，铁电电容C1和铁电电容C2的第一极分别第二晶体管T2的栅极电连接，铁电电容C1的第二极和铁电电容C2的第二极分别与字线WL电连接。第二晶体管T2的第二极与源线SL电连接，第二晶体管T2的第一极与读位线(read bit line，RBL)电连接。
在图7所示的存储单元中，写位线WBL也可以被称为用于向第一晶体管T1的第一极加载信号的第一电极线，读位线RBL也可以被称为用于向第二晶体管T2的第一极加载信号的第二电极线，预充电线CL也可以被称为用于向第一晶体管T1加载信号的第三电极线，源线SL也可以被称为用于向第二晶体管T2的第二极加载信号的第四电极线。
下述对上述图7所示2T2C存储单元400的写操作过程和读操作过程分别进行说明。
写操作过程：在写入阶段，预充电线CL用于接收第一预充电控制信号，使得第一晶体管T1导通，写位线WBL用于接收第一写位线控制信号，字线WL用于接收第一字线控制信号，第一字线控制信号和第一写位线控制信号的电压差使铁电电容的铁电膜层发生正极化或者发生负极化，以在铁电电容中写入不同的逻辑信息。比如，当铁电膜层发生正极化时，写入逻辑信号“0”，再比如，当铁电膜层发生负极化时，写入逻辑信号“1”。
读操作过程：若读取的数据为“0”时，在第一读取阶段，预充电线CL用于接收第一预充电控制信号，使得第一晶体管T1导通，写位线WBL用于接收第二写位线控 制信号，字WL线用于接收第二字线控制信号，第二字线控制信号和第二写位线控制信号的电压差使得铁电电容的铁电膜层处于半选状态，铁电膜层极性不发生翻转，即极化状态保持不变；在第二读取阶段，预充电线CL用于接收第二预充电控制信号，使得第一晶体管T1断开，读位线RBL用于接收第一读位线控制信号，字线WL用于接收比第二字线控制信号的电压小的字线控制信号，使得铁电电容由正极化翻转为负极化，以使第二晶体管T2断开；在第三读取阶段，预充电线CL用于接收第一预充电控制信号，使得第一晶体管T1导通，写位线WBL用于接收第一写位线控制信号，字线WL用于接收第一字线控制信号，第一字线控制信号和第一写位线控制信号的电压差使得铁电电容的铁电膜层发生正极化。并根据读位线电位信号读取为“0”。
若读取的数据为“1”时，在第一读取阶段，预充电线CL用于接收第一预充电控制信号，使得第一晶体管T1导通，写位线WBL用于接收第二写位线控制信号，字线WL用于接收第二字线控制信号，第二字线控制信号和第二写位线控制信号的电压差使得铁电电容的铁电膜层处于半选状态，铁电膜层极性不发生翻转，极化状态保持不变；在第二读取阶段，预充电线CL用于接收第二预充电控制信号，使得第一晶体管T1断开，读位线RBL用于接收第一读位线控制信号，字线WL用于接收比第二字线控制信号的电压小的字线控制信号，使铁电电容的负极性状态保持不变，第二晶体管T2导通；在第三读取阶段，预充电线CL用于接收第一预充电控制信号，使得第一晶体管T1导通，写位线WBL用于接收第一写位线控制信号，字线WL用于接收第一字线控制信号，第一字线控制信号和第一写位线控制信号的电压差使得铁电电容的铁电膜层发生负极化。并根据读位线电位信号读取为“1”。
在本申请所涉及的实施例中，例如上述图6和图7所示的第一晶体管T1和第二晶体管T2可以选择NMOS(N-channel metal oxide semiconductor，N沟道金属氧化物半导体)管，或者可以选择PMOS(P-channel metal oxide semiconductor，P沟道金属氧化物半导体)管。
另外，在本申请所涉及的实施例中，第一晶体管T1和第二晶体管T2中的任一晶体管的漏极(drain)或源极(source)中的一极称为第一极，相应的另一极称为第二极，晶体管的控制端为栅极。晶体管的漏极和源极可以根据电流的流向而确定，比如，在图6的写晶体管T1中，电流从左至右时，则左端为漏极，右端为源极；相反的，当电流从右向左时，右端为漏极，左端为源极。
在诸如上述图6和图7所示的存储单元400中，本申请实施例给出了一些可以提高存储密度的存储单元工艺结构，具体见下述。
图8简易示出了存储单元400的中第一晶体管T1和第二晶体管T2的布设方式，见图8，本申请实施例给出的任一存储单元400中的第一晶体管T1和第二晶体管T2沿与衬底100相平行的方向布设，而不是沿与衬底100相垂直的方向堆叠布设。
本申请实施例提供的存储阵列中，如图9所示，包括了多个存储层，且这些多个存储层沿着与衬底100相垂直的方向堆叠，图9所示的一层存储层，可以理解为上述图4所示的一层存储阵列。
其中，继续见图9，每一个存储层包括堆叠的第一金属层和第一介质层，并且，第一金属层和第一介质层沿着与衬底100相垂直的方向叠层设置。相邻两层第一金属 层之间被第一介质层电隔离开。
关于图8所示的第一晶体管T1和第二晶体管T2可以被形成在图9所示的第一金属层中，具体的可以实现的布设方式见下述。
另外，形成在衬底上，且沿与衬底相垂直方向堆叠的多个存储层中，在最靠近衬底的一层存储层中，存储层中的全部层结构(比如，电极、沟道等)可以位于衬底表面之上；或者，可以一部分位于存储层中(比如，电极)，另一部分是在衬底中靠近表面的位置(比如，沟道)。
图10是本申请实施例给出的第一晶体管T1和第二晶体管T2的一种可以实现的工艺结构剖面图，图11是图10的三维视图，图12是图11的俯视图。
一并结合图10、图11和图12，在该实施例中，第一晶体管T1的第一极11和第二极12，以及，第二晶体管T2的第一极21和第二极22位于与衬底相平行的如图9所示的第一金属层中。即可以理解为，工艺流程中，在与衬底相平行的一个膜层(比如，半导体层)结构中，进行图案化处理，就可以形成第一晶体管T1的第一极11和第二极12，以及，第二晶体管T2的第一极21和第二极22，以使得第一极11和第二极12，以及第一极21和第二极22处于与衬底相平行的第一金属层中，而不是这些电极沿着与衬底相垂直的方向堆叠。下面会结合制备工艺流程介绍如何在同一膜层上制得第一晶体管T1的第一极11、第二极12，以及第二晶体管T2的第一极21、第二极22。
继续参阅图10，与第一晶体管T1的第一极11电连接的第一电极线61，和与第二晶体管T2的第一极21电连接的第二电极线62，与上述涉及的第一晶体管T1的第一极11、第二极12，以及第二晶体管T2的第一极21、第二极22位于图9所示的第一金属层中。
并且，第一电极线61和第二电极线62的延伸方向是一致的，比如，如图10，第一电极线61和第二电极线62沿与衬底相平行的Y方向延伸。
继续参阅图10，第一晶体管T1的沟道层13的至少部分，和第二晶体管T2的沟道层23的至少部分，也位于与第一电极线61和第二电极线62所在的金属层中。
总之，第一电极线61、第二电极线62、第一晶体管T1和第二晶体管T2的任一晶体管的第一极、第二极、沟道层的至少部分位于同一金属层中。关于本申请实施例涉及的“第一晶体管T1和第二晶体管T2的任一晶体管的沟道层的至少部分位于第一金属层中”，可以这样理解，如图13a和图13b所示，图13a和图13b是以第二晶体管T2的沟道层23为例来说明的，见图13a，在第二晶体管T2中，第一极21和第二极22位于第一金属层中，而与第一极21和第二极22电连接的沟道层23的一部分位于第一金属层中，一部分延伸至与第一金属层相邻的第一介质层中。然而在图13b中，在第二晶体管T2中，第一极21和第二极22位于第一金属层中，而与第一极21和第二极22电连接的沟道层23的全部位于第一金属层中，并未延伸至第一介质层中。
关于第一晶体管T1的沟道层的设置方式，与图13a和图13b所示的第二晶体管T2的沟道层的设置方式类似，比如，可以全部位于第一金属层中，或者，可以部分位于第一金属层中，部分位于第一介质层中。
在图10所示的结构中，第二极12不仅可以作为第一晶体管T1的第二极，还可以 作为第二晶体管T2的栅极42，也就是第一晶体管T1的第二极，和第二晶体管T2的栅极共用同一电极。
还有，继续见图10，第一晶体管T1的第一极11，可以与第一电极线61共用同一电极线。
在一些实施例中，图10至图12中的第一电极线61可以是图6所示2T0C存储单元中的写位线WBL，第二电极线62可以是图6所示2T0C存储单元中的读位线RBL。在另外一些实施例中，图10至图12中的第一电极线61可以是图7所示2T2C存储单元中的写位线WBL，第二电极线62可以是图7所示2T2C存储单元中的读位线RBL。
关于第三电极线63和第四电极线64的设置方式，如图11所示，第三电极线63和第四电极线64均沿与衬底相垂直的方向延伸，比如，图6所示2T0C存储单元中的写字线WWL和读字线RWL均沿与衬底垂直的Z方向延伸。
基于上述描述得知：利用本申请实施例涉及的包含第一晶体管T1和第二晶体管T2的存储单元，可以沿着与衬底相平行的，和与衬底相垂直的方向排布，就可以实现三维堆叠，实现高密度的集成，提升该存储阵列的存储容量。
除此之外，由于每一个存储单元中，第一晶体管T1和第二晶体管T2的每一个晶体管的第一极、第二极和沟道层，以及第一电极线61和第二电极线62被形成在同一金属层中，而不是沿着与衬底相垂直的方向堆叠两层，或者堆叠更多层。
从工艺方法角度讲，可以通过在堆叠的多层半导体层上，同时制备沿与衬底相垂直方向堆叠的多个存储单元，或者说，同时制得多层存储阵列，而不是在制得一层存储阵列后，又再制得另一层存储阵列，所以，本申请实施例给出的存储阵列在制备时，可以简化制备工艺流程，降低工艺繁琐性，具体的可以实现的工艺方法后续进行介绍，以及结合工艺方法介绍如何利用一次工艺，同时制备多层器件，在此不予描述。
继续参阅图10，第一晶体管T1的沟道层13和第二晶体管T2的沟道层23相垂直布设，比如，处于X-Y平面内的沟道层13沿X方向延伸，而沟道层23沿与X方向相垂直的Y方向延伸。
即就是，第一晶体管T1的沟道层13中的电流方向，与第二晶体管T2的沟道层23中的电流方向是相垂直的。
图14是本申请实施例给出的第一晶体管T1和第二晶体管T2的另外一种可以实现的结构。相比图14和图10，在图14所示的实施例中，省略了第二极12或者栅极42。而是第一晶体管T1的沟道层13通过栅介质层51与第二晶体管T2的沟道层23电隔离开。进而，在该实施例中，沟道层13不仅作为第一晶体管T1的沟道，也可以作为第二晶体管T2的栅极42或者第一晶体管的第二极12，这样的话，通过简化工艺结构，也可以提升存储密度。
为了进一步的减小存储单元所占据面积，进一步的提升存储密度，如图14和图15，可以在沟道层23的靠近沟道层13的位置处形成凹腔231，并将沟道层13的一端伸入至凹腔231内。这样设计，可以减小该存储单元在X方向上的尺寸，从而可以提升存储单元的集成密度，即在X-Y平面内，沿着与沟道层13平行的方向上可以集成更多的存储单元。
比如，如图10，可以在凹腔231的壁面上形成栅介质层51，伸入至凹腔231内的 第二极12通过位于凹腔231内的栅介质层51与沟道层13电隔离开。再比如，如图14，将沟道层13的一端伸入至凹腔231内，通过位于凹腔231内的栅介质层51与沟道层13电隔离开。
在另一些可以实现的结构中，如图16，图16示例性的给出的存储单元的又一种可以实现的结构。如图16，沟道层23的靠近沟道层13的位置处并未形成凹腔，而是沟道层23与沟道层13相对的面为平面，以及，沟道层13通过形成在该平面上的栅介质层51与沟道层23电隔离开。
或者，如图17，和图15类似的，沟道层23与沟道层13相对的面为平面，沟道层13的端部形成第一晶体管T2的第二极12，第二极12通过栅介质层5与沟道层23电隔离开。
继续参阅图10至图17，在第一晶体管T1中，还包括栅极41。第一晶体管T1的栅极41可以是单栅结构，或者可以是双栅结构，又或者可以是图12所示的环栅结构。
在一些结构中，如图16和图17，第一晶体管T1的栅极41通过栅介质层51与沟道层13电隔离开。第一晶体管T1的栅极41可以与第三电极线63属于同一金属层，即第三电极线63通过栅介质层51与沟道层13电隔离开。
再次结合图17，在第一晶体管T1中，沟道层13的远离沟道层23的一端形成有第一极11。在第二晶体管T2中，沟道层23的相对两端中的一端形成第一极21，另一端形成第二极22。
由于在第一晶体管T1的第一极11、第二极12、沟道层13，和第二晶体管T2的第一极21、第二极22和沟道层23所处的金属层中，还形成第一电极线61(比如写位线WBL)和第二电极线62(比如读位线RBL)。第一电极线61和第二电极线62的延伸方向一致，比如，第一电极线61和第二电极线62可以沿着与衬底相平行的Y方向延伸。
在可以选择的工艺结构中，如图17，第一晶体管T1的第一极11与第一电极线61共用同一金属层，也就是该第一电极线61可以直接与图17所示的沟道层13接触，实现电连接。
继续参阅图17，沿与衬底相垂直方向延伸的第四电极线64可以与第二晶体管T2的第二极共用同一金属层，也就是该第四电极线64可以直接与沟道层23接触，实现第二晶体管T2与第四电极线64的电连接。
继续参阅图17，第二电极线62沿Y方向延伸，且第二电极线62位于沟道层23的远离第一晶体管T1的一侧。为了使得第二晶体管T2的第一极21与第二电极线62电连接，见图17，该存储单元还包括导电连接部7，第二晶体管T2的第一极21通过导电连接部7与第二电极线62电连接。
在一些实施例中，如图17，第一电极线61、第二晶体管T2的第一极21、第二极22、导电连接部7和第二电极线61均可以是金属层。或者，在另外一些实施例中，第一电极线61、第二晶体管T2的第一极21、第二极22、导电连接部7和第二电极线61中的部分是金属层，部分是在半导体材料中通过掺杂工艺形成的导电层，比如，在图17中，第一电极线61和第二极22是金属层，而第二晶体管T2的第一极21、导电连接部7和第二电极线61是在半导体材料中通过掺杂工艺形成的导电层。关于如何在半 导体材料中通过掺杂工艺形成导电层，下述会在存储阵列的制备方法中介绍。
如图18，图18示出了包含4个上述所示的存储单元，该4个存储单元形成2×2的存储阵列，2×2的存储阵列中的四个存储单元分别被称为存储单元400A，存储单元400B、存储单元400C和存储单元400D。
存储单元400A和存储单元400B沿与衬底相平行的Y方向排布，并且，存储单元400A和存储单元400B沿与衬底相平行的X方向镜像对称布设。可以理解为，存储单元400A中第二晶体管T2的第二极22，靠近存储单元400B中第二晶体管T2的第二极22设置。存储单元400A中第二晶体管T2的第二极22，与存储单元400B中第二晶体管T2的第二极22之间是被绝缘层电隔离开。
还有，第二电极线62沿Y方向延伸，沿Y方向排布的存储单元400A和存储单元400B与同一条第二电极线62电连接。
再次参阅图18，存储单元400A和存储单元400C沿与衬底相平行的X方向排布，并且，存储单元400A和存储单元400C沿与衬底相平行的Y方向镜像对称布设。还有，存储单元400A中第一晶体管T1的沟道层，与存储单元400C中第一晶体管T1的沟道层与同一个第一电极线61电连接，即就是共用同一个第一电极线61。
若将图18所示的结构在与衬底相平行的X-Y平面内排布，就可以得到图19所示的一层存储阵列，图19也是示例性的给出了该层存储阵列的部分。
将图19所示的结构，沿着与衬底相垂直的Z方向排布，就可以得到图20所示的三维存储阵列。图20所示的存储阵列可以通过互连线与控制器电连接，示例的，如图20，可以采用后道工艺将互连线形成在该存储阵列的远离衬底的一侧。
继续参照图20，形成在衬底上的与存储阵列电连接的互连线包括多条平行布设的写字线互连线，比如，如图20所示的WWL0、WWL1、WWL2、WWL3、WWL4、WWL5、WWL6和WWL7，其中，任一条WWL可以通过导电通道连接位于X-Y平面内的写字线。另外，互连线还包括多条平行布设的读字线互连线，比如，图20所示的RWL0、RWL1、RWL2、RWL3、RWL4、RWL5和RWL6，并且，任一条RWL可以通过导电通道连接位于X-Y平面内的读字线。
还有，互连线还包括图20所示的多条读位线互连线，如图20所示的RBLc0至RBLc13。每一读位线互连线通过导电通道连接位于X-Y平面内的读位线。以及，该互连线还包括图20所示的多条写位线互连线，如图20所示的WBLc0至WBLc13。每一写位线互连线通过导电通道连接位于X-Y平面内的写位线。
在进行读写操作时，可以通过图20所示的这些互连线选择所要读取的存储单元，具体的读写过程上述已经进行了介绍，在此不再赘述。
上述实施例提供的存储单元中，第一晶体管T1、第二晶体管T2、第一电极线61、第二电极线62、第三电极线63和第四电极线64可以选择的材料具有多种，下述给出了可以选择的部分材料。
在可选择的材料中，沟道层13和沟道层23中的任一沟道可以选择Si(硅)、poly-Si(p-Si，多晶硅)、amorphous-Si(a-Si，非晶硅)、In-Ga-Zn-O(IGZO，铟镓锌氧化物)多元化合物、ZnO(氧化锌)、ITO(氧化铟锡)、TiO 2(二氧化钛)、MoS 2(二硫化钼)、WS 2(二硫化钨)、石墨烯、黑磷等半导体材料中的一种或多种。
上述的栅介质层51的材料可以SiO 2(二氧化硅)、Al 2O 3(氧化铝)、HfO 2(二氧化铪)、ZrO 2(氧化锆)、TiO 2(二氧化钛)、Y 2O 3(三氧化二钇)和Si 3N 4(氮化硅)等绝缘材料中的一种或多种。
上述的第一晶体管T1和第二晶体管T2中的任一晶体管的第一极、第二极，第一电极线和第二电极线，以及第三电极线和第四电极线的材料均为导电材料，例如金属材料。在可选择的实施方式中，第一极51和第二极52的材料可以为TiN(氮化钛)、Ti(钛)、Au(金)、W(钨)、Mo(钼)、In-Ti-O(ITO，氧化铟锡)、Al(铝)、Cu(铜)、Ru(钌)、Ag(银)等导电材料中的一种或多种。
上述给出的是包含第一晶体管T1和第二晶体管T2的2T0C存储单元的工艺结构图。另外，本申请实施例还给出了包含第一晶体管T1和第二晶体管T2的2TnC存储单元的工艺结构图，比如，图21示例性的示出了2T2C存储单元的工艺结构图，示例的2T2C存储单元可以被应用在FeRAM存储阵列中。
参照图21，本申请实施例给出的2TnC存储单元中，和上述的2T0C存储单元类似的是均包含第一晶体管T1和第二晶体管T2，不同的是，在2TnC存储单元中，还包括铁电电容C。在一些实施例中，可以包括一个铁电电容C，或者如图21的包括两个铁电电容C，又或者，包括更多的铁电电容C。
从工艺结构方面讲，图21所示的2TnC存储单元，和上述所示的2T0C存储单元一样，第一晶体管T1的第一极11、第二极12和沟道层13，第二晶体管T2的第一极21、第二极22与沟道层23，以及第一电极线61和第二电极线62位于与衬底相平行的同一金属层中，以及，第一电极线61和第二电极线62的延伸方向一致，第三电极线63和第四电极线64沿与衬底相垂直的方向延伸。
从制得图21所示工艺结构的工艺方法讲，和上述的2T0C存储单元类似，可以采用一次工艺，同时制备沿与衬底相垂直方向堆叠的多个存储单元，这样，可以简化制备工艺流程，降低工艺繁琐性。
结合图21所示的2TnC存储单元工艺结构，和上述图7所示的2TnC存储单元电路结构，可以得知：图21中的第一电极线61为图7所示的写位线WBL，第二电极线62为图7所示的读位线RBL，第三电极线63为图7所示的源线SL，第四电极线64为图7所示的预充电线CL。
关于图21所示的第一晶体管T1的沟道层13，和第二晶体管T2的沟道层23的布设方式、第一电极线61和第二电极线62的延伸方向，可以参照上述2TnC存储单元。比如，见图21，第一晶体管T1的沟道层13，和第二晶体管T2的沟道层23相垂直布设，第一电极线61和第二电极线62的延伸方向，与沟道层23的延伸方向是一致的。
继续参阅图21，该2TnC存储单元的铁电电容C包括第一铁电电极81、铁电膜层82和第二铁电电极82，其中，铁电膜层82堆叠在第一铁电电极81和第二铁电电极82之间。
见图21，第一铁电电极81也位于第一晶体管T1和第二晶体管T2的第一极、第二极所在的金属层中。也就是说，图21的第一极11、第一极12、第二极22、沟道层13的至少部分、沟道层23的至少部分和第一铁电电极81均位于同一金属层内。
再参阅图21，第二晶体管T2的沟道层23的靠近第一晶体管T1的位置处形成有 凹腔231，第一晶体管T1的沟道层13的端部形成第一铁电电极81，第一铁电电极81的部分伸入至凹腔231内，第一铁电电极81通过铁电膜层82与沟道层23电隔离开。该第一铁电电极81不仅可以作为铁电电容的第一极，还可以作为第二晶体管的栅极，或者，也可以作为第一晶体管的电极。
依然参照图21，第二铁电电极83可以与第五电极线65电连接，比如与图7所示的字线WL电连接，第一铁电电极作为铁电电容的一个电极，通过与字线WL上的电压差完成存储信息的写入。
在此实施例中，预充电线CL和字线WL均沿与衬底相垂直的方向延伸。例如，在图21示例的2T2C存储单元中，两条字线WL和预充电线CL相平行的，沿着与衬底相垂直的方向布设。并且，字线WL和预充电线CL之间是电隔离开的，字线WL与字线WL之间也是电隔离开的。
图22是本申请实施例给出的另外一种2TnC存储单元的工艺结构图。在该实施例中，不仅示出了第一铁电电极81，还示出第二晶体管T2的栅极42，栅极42与第一铁电电极81接触电连接，栅极42的至少部分被嵌入沟道层23的凹腔231内。
在上述图21和图22所示的2TnC存储单元中，第一铁电电极81可以选择钨W、氮化钛TiN、多晶硅、钴Co、镍Ni、铜Cu中的至少一种制得，栅极42也可以选择钨W、氮化钛TiN、多晶硅、钴Co、镍Ni、铜Cu中的至少一种制得。当第一铁电电极81和栅极42采用相同的材料制得时，可以形成图21所示的第一铁电电极81和栅极层42为一体的结构，反之，当第一铁电电极81和栅极42采用不相同的材料制得时，可以形成图22所示的结构。
图23是本申请实施例给出的另外一种2TnC存储单元的工艺结构图。在此结构的存储单元中，和上述图21和图22相比，仅包括一个铁电电容C，其余结构类似。对比图23和图22，当2TnC存储单元包括多个铁电电容C时，这些多个铁电电容C间隔排布，并且排布方向与第一晶体管T1的沟道层13的延伸方向是一致的，多个铁电电容C包括的多个第二铁电电极83之间是绝缘的，比如，可以采用绝缘层将相邻两个第二铁电电极83电隔离开。
再结合图21至图22，电隔离第一铁电电极81和第二铁电电极83的铁电膜层82，可以和电隔离第一铁电电极81和沟道层23的栅介质层51，为一体结构，比如，可以选择ZrO 2(氧化锆)，HfO 2(二氧化铪)，Al掺杂HfO 2，Si掺杂HfO 2，Zr参杂HfO 2，La掺杂HfO 2，Y掺杂HfO 2等铁电材料或者基于该材料的进行其他元素掺杂的材料中的一种或者多种。
继续结合图21至图22，电隔离第一铁电电极81和第二铁电电极83的铁电膜层82，可以和电隔离沟道层13和第一电极线61的栅介质层51，为一体结构。
在一些可以选择的实施例中，为了简化制造工艺，如图23，可以将电隔离第一铁电电极81和第二铁电电极83的铁电膜层82、电隔离第二铁电电极83和沟道层23的栅介质层51、以及电隔离沟道层13和第一电极线61的栅介质层51，为一体结构。比如，可以选择ZrO 2(氧化锆)，HfO 2(二氧化铪)，Al掺杂HfO 2，Si掺杂HfO 2，Zr参杂HfO 2，La掺杂HfO 2，Y掺杂HfO 2等铁电材料或者基于该材料的进行其他元素掺杂的材料中的一种或者多种。
一并结合图21、图22和图23，均是在沟道层23上形成有凹腔231，并将第一铁电电极81的至少部分或者栅极42的至少部分嵌入至凹腔231内，这样一来，可以进一步的减小该存储单元的尺寸，提高该2TnC存储单元的集成密度。
图24是本申请实施例给出的又一种2TnC存储单元的工艺结构图。在该存储单元中，并未在沟道层23的侧面形成凹腔，即沟道层23的与第一铁电电极81相对的面为平面，第一铁电电极81通过铁电膜层82与沟道层23电隔离开。
对于图21至图24示例的2TnC存储单元，其余结构可以选择的材料可以参照上述2T0C存储单元中相对应结构的材料。
在一些可以实现的结构中，将图21至图24中的任一个存储单元在彼此相互垂直的X方向、Y方向和Z方向上排布，就可以得到三维存储阵列。
其中，图25简易的示例出采用图21所示2TnC存储单元时，在X-Y平面内形成的存储阵列。其中，第一电极线61和第二电极线62的延伸方向一致，比如，沿与衬底相平行的Y方向延伸，第三电极线63、第四电极线64和第五电极线65沿与衬底相垂直的方向延伸，比如，该第一电极线61为WBL，第二电极线62为RBL，第三电极线为CL，第四电极线为SL和第五电极线为WL。
除此之外，本申请实施例还给出了存储阵列的形成方法，图26示例性的给出了制备存储阵列的流程框图。
步骤S1：在衬底上形成多层半导体层和多层介质层，且多层半导体层和多层介质层沿着与衬底相垂直的方向交替堆叠。
比如，当需要制得5层存储单元时，那么，可以在衬底上堆叠5层半导体层和5层介质层，并且5层半导体层和5层介质层交替堆叠，即相邻两层半导体层之间被一层介质层隔离开。
这里的半导体层可以为Si(硅)、poly-Si(p-Si，多晶硅)、amorphous-Si(a-Si，非晶硅)、In-Ga-Zn-O(IGZO，铟镓锌氧化物)多元化合物、ZnO(氧化锌)、ITO(氧化铟锡)、TiO 2(二氧化钛)、MoS 2(二硫化钼)、WS 2(二硫化钨)等半导体材料中的一种或多种。
介质层可以选择SiO 2(二氧化硅)、Al 2O 3(氧化铝)、HfO 2(二氧化铪)、ZrO 2(氧化锆)、TiO 2(二氧化钛)、Y 2O 3(三氧化二钇)和Si 3N 4(氮化硅)等绝缘材料中的一种或多种。
步骤S2：对每一个半导体层进行图形化处理，以形成第一电极线、第二电极线、包含第一晶体管和第二晶体管的存储单元；第一晶体管和第二晶体管均包含第一极、第二极、栅极和沟道层，第一晶体管的第一极电连接第一电极线，第二晶体管的第一极电连接第二电极线，且第一电极线、第二电极线，以及第一晶体管和第二晶体管的每一个晶体管的第一极、第二极、沟道层的至少部分位于第一金属层中，第一金属层与介质层平行。
在执行步骤S2时，本申请实施例对第一电极线、第二电极线、第一晶体管、第二晶体管的制备顺序不做限定，比如，可以先制得第一晶体管和第一电极线，再制得第二晶体管和第二电极线。
其中，第一晶体管和第二晶体管均包含第一极、第二极、栅极和沟道层，第一晶 体管的第一极电连接第一电极线，第二晶体管的第一极电连接第二电极线。
此外，第一晶体管的栅极电连接第三电极线，第二晶体管的第二极电连接第四电极线。
且第一电极线、第二电极线，以及第一晶体管和第二晶体管的每一晶体管的第一极、第二极和沟道层，位于与衬底相平行的同一金属层中。也就是说，可以在同一半导体层上进行图案化处理，可以制得第一极、第二极、沟道层、第一电极线和第二电极线。
下面结合附图对上述步骤S1和步骤S2所涉及的具体工艺流程进行介绍。
图27a至图27l给出了制得本申请实施例一种存储阵列的工艺过程中每一步骤完成后的工艺结构。
如图27a，在衬底(图中未示出)上形成多层半导体层10和多层介质层20，且多层半导体层10和多层介质层20沿着与衬底相垂直的方向交替堆叠。上述介绍了半导体层和介质层可以选择的材料，在此不再叙述。
如图27b，沿着与衬底相平行的方向开设多个通孔301，比如，这些多个通孔301可以沿着与衬底平行的Y方向间隔排布。并且，每一个通孔301贯通多层半导体层10和多层介质层20。
如图27c，在每一个通孔301内填充绝缘材料，以形成绝缘层401。
图27c中的绝缘层401可以选择SiO 2(二氧化硅)、Al 2O 3(氧化铝)、HfO 2(二氧化铪)、ZrO 2(氧化锆)、TiO 2(二氧化钛)、Y 2O 3(三氧化二钇)和Si 3N 4(氮化硅)等绝缘材料中的一种或多种。
如图27d，在任一半导体层10上开设第一槽201，第一槽201包括沿Y方向延伸的第一部分201A，和位于相邻两个绝缘层401之间的第二部分201B。
在开设图27b所示的通孔301，和开设图27d所示的第一槽201时，可以采用刻蚀工艺。
在一些可以选择的工艺流程中，在开设第一槽201时，可以如图27d所示的，第一槽201的第二部分201B超出绝缘层401的远离所述第一部分的侧面，以在半导体层10内形成凹腔231。
此结构中形成的凹腔231可以形成上述图21所示的凹腔231，该凹腔231是用于将第一晶体管T1的沟道层13伸入，以减小该存储单元所占据的面积。
依照图27d，是在每一个半导体层10上开设第一槽201。示例的，可以采用刻蚀工艺同时在多个半导体层10上刻蚀第一槽201。即同时在多个半导体层上构图，同时形成多个堆叠的存储单元。
如图27e，在第一槽201的壁面上形成栅介质层51。
由于每一个半导体层10上均具有第一槽201，那么，可以给这些多个第一槽201的壁面同时形成栅介质层51。
如图27f，在第一槽201的第二部分201B内填充半导体材料，以形成第一晶体管T1的沟道层13；以及，在第一槽的第一部分内填充导电材料，比如，金属材料，以形成沿Y方向延伸的第一电极线61。
和上述图27d一样，可以在多个半导体层的每一个半导体层的第二部分内形成沟 道层13，以及，在每一个半导体层的第一部分内形成第一电极线61。即就是同时形成多个第一晶体管的沟道层13，同时形成多个第一电极线61。
如图27g，在图27f形成的第一晶体管T1的沟道层13的侧面开设通孔302，且使得通孔302沿着与衬底相垂直的方向贯通多层半导体层10和多层介质层20。
继续参阅图27g，由于本申请实施例制备环栅的第一晶体管T1，从而，可以在沟道层13的相对的两侧均开设通孔302。
在另外一些可以选择的工艺中，可以仅在沟道层13相对两侧中的一侧开设通孔，这样的话，形成的第一晶体管为单栅晶体管。
开设通孔302后，如图27h，再在通孔302内填充导电材料，比如，金属，以形成与第一晶体管的栅极电连接的第三电极线63。比如，当制得包含2T0C的存储单元时，第三电极线63为写字线WWL。再比如，当制得包含2TnC的存储单元时，第三电极线63为预充电线CL。
由图27a至图27h，可以看出，本申请示例性的给出了制得沿着Y方向布设的两个存储单元，其中，两个存储单元的第一晶体管T1可以被图27b形成的绝缘层电隔离开。
还有，由图27a至图27h，可以看出，可以利用一次工艺同时在多个堆叠的存储单元的第一晶体管。
如图27i，在每一个半导体层10上开设第二槽202，第二槽202包括沿Y方向延伸的第三部分202A，和位于相邻两个第一晶体管T1的沟道层13之间的第四部分202B。
如图27j，在第三部分202A和第四部分202B内均填充绝缘材料，以形成绝缘层402。
如图27k，对沿Y方向延伸的，且临接第二槽的第三部分的半导体层进行掺杂，以形成沿Y方向延伸的第二电极线62，以及，对临接第一晶体管的沟道层的半导体层进行掺杂，以形成与第二电极线62电连接的第二晶体管的第一极21。
在此中实现方式中，是通过对半导体层进行掺杂，以形成第二电极线和第二晶体管的第一极。在另外一些工艺流程中，也可以在图27j所示的每一个半导体层上开槽，通过在槽内填充金属材料，以形成第二电极线和第二晶体管的第一极。
如图27l，在位于第二槽的第四部分相对的两侧的半导体层上开设通孔303，以使通孔303沿着与衬底相垂直的方向贯通多层半导体层10和多层介质层20；
如图27m，在图27l开设的通孔303内填充导电材料，以形成第四电极线64。
由图27a至图27m所示的工艺流程得知：利用堆叠交替布设的半导体层和介质层(如图27a)→开孔、回填绝缘介质(如图27b和图27c)→刻蚀半导体材料、填充栅介质层、沟道层和第一电极线(如图27d、图27e和图27f)→开孔、回填金属，形成第三电极线(如图27g和图27h)→刻蚀半导体材料、形成第二电极线和第二晶体管的第一电极(如图27i、图27j和图27k)→开孔、回填金属，形成第四电极线(如图27l和图27m)。利用图27a至图27m所示的工艺流程，就可以制得多层堆叠的存储阵列。而不是制得一层存储阵列后，再制得另一层存储阵列。
若采用堆叠一层存储阵列后，再堆叠另一层存储阵列的方式制得存储器时，随着存储密度不断增加，堆叠层数也随之增加，进而对光刻对准精度要求也越来越高，如 果下一层存储阵列结构与上一层存储阵列结构对准精度较低时，可能会影响读写性能。然而，采用本申请实施例提供的存储阵列制备方法，对光刻对准精度要求较低，也不会给工艺提出较高的挑战，这样的话，不仅可以简化工艺制程，降低工艺难度，还会提升产品优良率，提升存储器的读写性能，另外，也会降低该存储器的制造成本。
在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (32)

  1. 一种存储阵列，其特征在于，包括：
    衬底；
    形成在所述衬底上的多个存储层，所述多个存储层沿着与所述衬底相垂直的方向堆叠；
    每一个所述存储层包括第一电极线和第二电极线，以及多个存储单元；
    每一个所述存储单元包括电连接的第一晶体管和第二晶体管，所述第一晶体管和所述第二晶体管均包括栅极、第一极和第二极，以及沟道层；所述第一晶体管的第一极与所述第一电极线电连接，所述第二晶体管的第一极与所述第二电极线连接；
    每一个所述存储层包括沿与所述衬底相垂直方向堆叠的第一金属层和第一介质层；
    所述第一电极线、所述第二电极线，以及所述第一晶体管和所述第二晶体管的每一个晶体管的所述第一极、所述第二极、所述沟道层的至少部分位于所述第一金属层中。
  2. 根据权利要求1所述的存储阵列，其特征在于，所述第一晶体管和所述第二晶体管的每一个晶体管的所述沟道层，一部分位于所述第一金属层中，另一部分延伸至所述第一介质层中。
  3. 根据权利要求1或2所述的存储阵列，其特征在于，所述存储阵列还包括第三电极线和第四电极线；
    所述第三电极线和所述第四电极线均沿与所述衬底相垂直的方向延伸；
    所述第三电极线电连接每相邻两层所述存储层中的所述第一晶体管的栅极；
    所述第四电极线电连接每相邻两层所述存储层中的所述第二晶体管的第二极。
  4. 根据权利要求3所述的存储阵列，其特征在于，所述第一晶体管的所述沟道层为第一沟道层，所述第二晶体管的所述沟道层为第二沟道层；
    所述第一沟道层与所述第二沟道层相垂直布设；
    所述第一电极线和所述第二电极线的延伸方向与所述第二沟道层的延伸方向一致。
  5. 根据权利要求4所述的存储阵列，其特征在于，所述第一沟道层的靠近所述第二沟道层的一端，通过形成在所述第一沟道层和所述第二沟道层界面处的栅介质层与所述第二沟道层电隔离开。
  6. 根据权利要求5所述的存储阵列，其特征在于，所述第二沟道层的靠近所述第一沟道层的位置处形成有凹腔，所述第一沟道层的一端设置在所述凹腔内，并通过形成在所述凹腔内壁上的所述栅介质层与所述第二沟道层电隔离开。
  7. 根据权利要求4所述的存储阵列，其特征在于，所述存储阵列还包括第五电极线，每一个所述存储单元还包括至少一个铁电电容；
    所述铁电电容包括第一铁电电极、铁电膜层和第二铁电电极，所述第一铁电电极与所述第一晶体管的所述第二极和所述第二晶体管的所述栅极分别电连接，所述第二铁电电极与所述第五电极线电连接；
    所述第一铁电电极位于所述第一金属层中；
    所述第五电极线沿与所述衬底相垂直的方向延伸。
  8. 根据权利要求7所述的存储阵列，其特征在于，所述第一铁电电极的延伸方向 与所述第一沟道层的延伸方向一致，且所述第一铁电电极形成在所述第一沟道层的靠近所述第二沟道层的一端，并通过栅介质层与所述第二沟道层电隔离开；
    所述第二铁电电极设置在所述第一铁电电极的侧面，并通过所述铁电膜层与所述第一铁电电极电隔离开。
  9. 根据权利要求8所述的存储阵列，其特征在于，所述第二沟道层的靠近所述第一铁电电极的位置处形成有凹腔，所述第一铁电电极的一端设置在所述凹腔内，并通过形成在所述凹腔内壁上的所述栅介质层与所述第二沟道层电隔离开。
  10. 根据权利要求7-9中任一项所述的存储阵列，其特征在于，每一个所述存储单元包括多个所述铁电电容；
    多个所述铁电电容沿着与所述第一沟道层延伸方向相平行的方向间隔排布。
  11. 根据权利要求4-10中任一项所述的存储阵列，其特征在于，所述第一沟道层的远离所述第二沟道层的一端，形成与所述第一沟道层的延伸方向相垂直的并与所述第一沟道层接触的所述第一电极线。
  12. 根据权利要求4-11中任一项所述的存储阵列，其特征在于，所述第一沟道层的侧面，形成与所述衬底相垂直的所述第三电极线，且所述第三电极线与所述第一沟道层之间被栅介质层电隔离开。
  13. 根据权利要求4-12中任一项所述的存储阵列，其特征在于，沿所述第二沟道层的延伸方向，所述第二沟道层的相对的两端中的其中一端形成所述第二晶体管的所述第一极。
  14. 根据权利要求13所述的存储阵列，其特征在于，所述第二电极线位于所述第二沟道层的远离所述第一沟道层的一侧；
    每一个所述存储单元还包括导电连接部，所述第二晶体管的所述第一极通过所述导电连接部与所述第二电极线电连接。
  15. 根据权利要求14所述的存储阵列，其特征在于，所述第二晶体管的所述第一极、所述第二电极线和所述导电连接部均在半导体层中通过掺杂工艺制得。
  16. 根据权利要求13-15中任一项所述的存储阵列，其特征在于，沿与所述衬底相垂直方向延伸的所述第四电极线，与所述第二沟道层的相对的两端中的另一端接触。
  17. 根据权利要求1-16中任一项所述的存储阵列，其特征在于，所述多个存储单元包括第一存储单元和第二存储单元；
    所述第一存储单元和所述第二存储单元沿与所述衬底相平行的方向排布；
    所述第一存储单元和所述第二存储单元的任一存储单元中，所述第一晶体管的第一极均与所述第一电极线电连接，所述第二晶体管的第一极均与所述第二电极线连接。
  18. 根据权利要求1-17中任一项所述的存储阵列，其特征在于，所述多个存储单元、所述第一电极线和所述第二电极线均采用后道工艺形成在所述衬底上。
  19. 根据权利要求1-6中任一项所述的存储阵列，其特征在于，所述存储阵列为DRAM存储阵列。
  20. 根据权利要求19所述的存储阵列，其特征在于，所述DRAM存储阵列还包括第三电极线和第四电极线；
    所述第三电极线电连接所述第一晶体管的栅极，所述第四电极线电连接所述第二 晶体管的第二极；
    其中，所述第一电极线为写位线，所述第二电极线为读位线，所述第三电极线为写字线，所述第四电极线为读字线。
  21. 根据权利要求1-6中任一项所述的存储阵列，其特征在于，所述存储阵列为铁电存储阵列。
  22. 根据权利要求21所述的存储阵列，其特征在于，所述铁电存储阵列还包括第三电极线和第四电极线；
    所述第三电极线电连接所述第一晶体管的栅极，所述第四电极线电连接所述第二晶体管的第二极；
    所述铁电存储阵列还包括第五电极线，每一个所述存储单元还包括至少一个铁电电容；
    所述铁电电容包括第一铁电电极、铁电膜层和第二铁电电极，所述第一铁电电极与所述第一晶体管的所述第二极和所述第二晶体管的所述栅极分别电连接，所述第二铁电电极与所述第五电极线电连接；
    其中，所述第一电极线为写位线，所述第二电极线为读位线，所述第三电极线为预充电线，所述第四电极线为源线，所述第五电极线为字线。
  23. 一种存储器，其特征在于，包括：
    如权利要求1-22中任一项所述的存储阵列；
    控制器，所述控制器与所述存储阵列电连接，所述控制器用于控制所述存储阵列的读写。
  24. 一种电子设备，其特征在于，包括：
    处理器；
    如权利要求23所述的存储器，所述处理器与所述存储器电连接，所述存储器用于存储所述处理器产生的数据。
  25. 一种存储阵列的形成方法，其特征在于，所述形成方法包括：
    在衬底上形成多层半导体层和多层介质层，且所述多层半导体层和所述多层介质层沿着与所述衬底相垂直的方向交替堆叠；
    对每一个所述半导体层进行图形化处理，以形成第一电极线、第二电极线、包含第一晶体管和第二晶体管的存储单元；
    其中，所述第一晶体管和所述第二晶体管均包含第一极、第二极、栅极和沟道层，所述第一晶体管的第一极电连接所述第一电极线，所述第二晶体管的第一极电连接所述第二电极线，且所述第一电极线、所述第二电极线，以及所述第一晶体管和所述第二晶体管的每一个晶体管的所述第一极、所述第二极、所述沟道层的至少部分位于第一金属层中，所述第一金属层与所述介质层平行。
  26. 根据权利要求25所述的存储阵列的形成方法，其特征在于，对每一个所述半导体层进行图形化处理，以形成第一电极线、第二电极线、包含第一晶体管和第二晶体管的存储单元之前，所述形成方法还包括：
    开设多个第一通孔，所述多个第一通孔沿第一方向间隔排布，且任一所述第一通孔沿着与所述衬底相垂直的方向贯通所述多层半导体层和所述多层介质层；
    在所述第一通孔内填充绝缘层。
  27. 根据权利要求26所述的存储阵列的形成方法，其特征在于，对每一个所述半导体层进行图形化处理，以形成第一电极线、第二电极线、包含第一晶体管和第二晶体管的存储单元，包括：
    在每一个所述半导体层上开设第一槽，所述第一槽包括沿所述第一方向延伸的第一部分，和位于相邻两个所述绝缘层之间的第二部分；
    在所述第一槽的壁面上形成栅介质层；
    在所述第二部分内填充半导体材料，以形成所述第一晶体管的沟道层；
    在所述第一部分内填充导电材料，以形成沿所述第一方向延伸的所述第一电极线。
  28. 根据权利要求27所述的存储阵列的形成方法，其特征在于，在每一个所述半导体层上开设第一槽，所述第一槽包括沿所述第一方向延伸的第一部分，和位于相邻两个所述绝缘层之间的第二部分，包括：
    所述第二部分超出所述绝缘层的远离所述第一部分的侧面，以在所述半导体层内形成凹腔，以使得所述第一晶体管的沟道层设置在所述凹腔内。
  29. 根据权利要求27或28所述的存储阵列的形成方法，其特征在于，对每一个所述半导体层进行图形化处理，以形成第一电极线、第二电极线、包含第一晶体管和第二晶体管的存储单元，还包括：
    在每一个所述半导体层上开设第二槽，所述第二槽包括沿所述第一方向延伸的第三部分，和位于相邻两个所述第一晶体管的沟道层之间的第四部分；
    在所述第三部分和所述第四部分内均填充绝缘层。
  30. 根据权利要求29所述的存储阵列的形成方法，其特征在于，在每一个所述半导体层上开设第二槽之后，所述形成方法还包括：
    对沿所述第一方向延伸的，且临接所述第二槽的所述第三部分的所述半导体层进行掺杂，以形成沿所述第一方向延伸的所述第二电极线，以及，对临接所述第一晶体管的所述沟道层的所述半导体层进行掺杂，以形成与所述第二电极线电连接的所述第二晶体管的第一极。
  31. 根据权利要求29或30所述的存储阵列的形成方法，其特征在于，所述形成方法还包括：
    在所述第一晶体管的沟道层的侧面开设第三通孔，以使所述第三通孔沿着与所述衬底相垂直的方向贯通所述多层半导体层和所述多层介质层；
    在所述第三通孔内填充导电材料，以形成与所述第一晶体管的栅极电连接的第三电极线。
  32. 根据权利要求29-31中任一项所述的存储阵列的形成方法，其特征在于，所述形成方法还包括：
    在所述第四部分相对的两侧的所述半导体层上开设第二通孔，以使第二通孔沿着与所述衬底相垂直的方向贯通所述多层半导体层和所述多层介质层；
    在所述第二通孔内填充导电材料，以形成与所述第二晶体管的第二极电连接的第四电极线。
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Publication number Priority date Publication date Assignee Title
US20020096702A1 (en) * 2000-09-14 2002-07-25 Tomoyuki Ishii Semiconductor memory device
CN102522407A (zh) * 2011-12-23 2012-06-27 清华大学 具有垂直晶体管的存储器阵列结构及其形成方法
CN114792735A (zh) * 2021-01-26 2022-07-26 华为技术有限公司 薄膜晶体管、存储器及制作方法、电子设备
CN114864582A (zh) * 2022-04-20 2022-08-05 南方科技大学 存储单元及其数据读写方法、制备方法及存储器

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020096702A1 (en) * 2000-09-14 2002-07-25 Tomoyuki Ishii Semiconductor memory device
CN102522407A (zh) * 2011-12-23 2012-06-27 清华大学 具有垂直晶体管的存储器阵列结构及其形成方法
CN114792735A (zh) * 2021-01-26 2022-07-26 华为技术有限公司 薄膜晶体管、存储器及制作方法、电子设备
CN114864582A (zh) * 2022-04-20 2022-08-05 南方科技大学 存储单元及其数据读写方法、制备方法及存储器

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