WO2023102785A1 - 存储器和存储器的制作方法 - Google Patents

存储器和存储器的制作方法 Download PDF

Info

Publication number
WO2023102785A1
WO2023102785A1 PCT/CN2021/136564 CN2021136564W WO2023102785A1 WO 2023102785 A1 WO2023102785 A1 WO 2023102785A1 CN 2021136564 W CN2021136564 W CN 2021136564W WO 2023102785 A1 WO2023102785 A1 WO 2023102785A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate
layer
metal layer
pole
metal
Prior art date
Application number
PCT/CN2021/136564
Other languages
English (en)
French (fr)
Inventor
殷士辉
景蔚亮
黄凯亮
冯君校
王正波
廖恒
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN202180037432.8A priority Critical patent/CN116583901A/zh
Priority to PCT/CN2021/136564 priority patent/WO2023102785A1/zh
Publication of WO2023102785A1 publication Critical patent/WO2023102785A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements

Definitions

  • the present application relates to the technical field of memory, and in particular to a memory and a manufacturing method of the memory.
  • the memory may include a write transistor (Write Transistor, WTR) and a read transistor (Read Transistor, RTR), the gate of the write transistor is connected to the write word line (Write Word Line, WWL), and the source of the write transistor is connected to the write word line.
  • Bit line (Write Bit Line, WBL)
  • the source of the read transistor is connected to the read bit line
  • the drain of the read transistor is connected to the read bit line
  • the drain of the write transistor is connected to the gate of the read transistor to form a storage node (Storage Node, SN).
  • Embodiments of the present application provide a memory and a manufacturing method of the memory, which can reduce the voltage coupling of the write word line and the read word line to the storage node.
  • An embodiment of the present application provides a memory on the one hand, including a write word line, a write bit line, a read word line, a read bit line, and a memory unit;
  • the memory unit includes write transistors and read transistors arranged in sequence in the first direction
  • the read transistor includes a first gate, a first pole and a second pole, wherein the first pole is a source, the second pole is a drain, or the first pole is a drain, and the second pole is a source;
  • the write transistor includes a second pole The gate, the third pole, and the fourth pole, wherein, the third pole is the source, the fourth pole is the drain, or the third pole is the drain, and the fourth pole is the source;
  • the second gate is connected to the write word line,
  • the fourth pole is connected to the write bit line, the second pole is connected to the read bit line, the first pole is connected to the read bit line, and the third pole is connected to the first gate to form a storage node;
  • the storage unit also includes a
  • the memory provided by the embodiment of the present application increases the total capacitance of the storage node by adding a decoupling capacitor to prolong the charge retention time. At the same time, since the newly added decoupling capacitor is larger than the gate-source and gate-drain capacitance, the write capacity can be greatly reduced.
  • the influence of the coupling of the byte line and the read word line on the storage node avoiding the influence of the voltage coupling on the normal operation of the memory; and, the memory provided by the embodiment of the present application arranges the write transistor and the read transistor along the first direction.
  • the first One direction may be a vertical direction, so that the integration level in the horizontal direction is not increased while the decoupling capacitor is introduced into the storage unit, the area of the device is not increased, and the memory density is not lost.
  • the storage unit further includes a coupling metal layer, the coupling metal layer is connected to a preset potential, and the decoupling capacitor includes a first capacitor plate and a second capacitor plate, wherein the first capacitor plate is In the coupling metal layer, the second capacitive plate is the first grid, or the second capacitive plate is the connection metal connecting the third electrode and the first grid.
  • the added coupling metal layer can be used as one of the plates of the decoupling capacitor, and the other plate of the decoupling capacitor can be the first gate of the read transistor, or other structures with the same potential as the first gate, such as connecting the third
  • the connection metal between the electrode and the first gate can be arranged in this way, and the original partial structure of the memory cell can be used to increase the decoupling capacitance, which has little impact on the volume of the device.
  • the read transistor includes a first channel extending along the first direction
  • the write transistor includes a second channel extending along the first direction
  • the writing transistors and reading transistors are arranged vertically, and the memory cells as a whole can have a columnar structure, which is beneficial to form a compact memory structure.
  • the first gate includes a first gate base layer and a first gate metal column, the first gate metal column is located in the first channel, and the first channel is provided with the first A semiconductor layer, and a first gate dielectric layer is arranged between the first gate metal column and the first semiconductor layer, the first gate base layer is connected to the side of the first gate metal column close to the write transistor, the first gate base layer Extending in a plane perpendicular to the first direction; both the second pole and the first pole are connected to the first semiconductor layer, both the second pole and the first pole extend in a plane perpendicular to the first direction, and the second pole is located at the first A first insulating layer is arranged between the first electrode and the first gate base layer, and between the second electrode and the first electrode.
  • This implementation mode provides a read transistor with a CAA (Channel All Around) structure
  • the first channel is a vertical columnar structure
  • the first gate metal column is located in the first channel
  • the first pole and the second pole are respectively connected to the first
  • the semiconductor layer is connected
  • the first pole, the second pole, and the first gate base layer all extend on the horizontal plane, and the overall structure of the read transistor is simple and easy to realize.
  • the second gate includes a second gate base layer and a second gate metal column, the second gate metal column is located in the second channel, and the second channel is provided with the first Two semiconductor layers, a second gate dielectric layer is arranged between the second gate metal column and the second semiconductor layer, the second gate base layer is connected to the side of the second gate metal column away from the read transistor, and the second gate base layer is on the Extending in a plane perpendicular to the first direction; both the third pole and the fourth pole are connected to the second semiconductor layer, the fourth pole is located between the third pole and the second gate base layer, and the third pole and the fourth pole are both on the Extending in a plane perpendicular to the first direction, a second insulating layer is arranged between the third pole and the fourth pole.
  • This embodiment provides a write transistor with a CAA (Channel All Around) structure, the second channel is a vertical columnar structure, the second gate metal column is located in the second channel, and the third pole and the fourth pole are respectively connected to the second The semiconductor layer is connected, and the third electrode, the fourth electrode, and the second gate base layer all extend on the horizontal plane, and the overall structure of the write transistor is simple and easy to realize.
  • CAA Channel All Around
  • the write transistor includes a second semiconductor layer, the second semiconductor layer extends along the first direction to form a second channel, the fourth electrode is connected to an end of the second semiconductor layer away from the read transistor, and the third The pole is connected to one end of the second semiconductor layer close to the read transistor, the second gate is located between the third pole and the fourth pole, and the third pole, the fourth pole, and the second gate are all on a plane perpendicular to the first direction extending inwardly, a second gate dielectric layer is arranged between the second gate and the second semiconductor layer, a second insulating layer is arranged between the second gate and the third electrode, and a second insulating layer is arranged between the second gate and the fourth electrode. There is a third layer of insulation.
  • This implementation mode provides a write transistor with a GAA (Gate All Around) structure
  • the second channel is a vertical columnar structure
  • the second semiconductor layer is located in the second channel
  • the third pole and the fourth pole are connected to the second semiconductor layer respectively.
  • the layers are connected
  • the second gate is arranged around the second channel
  • the third pole, the fourth pole, and the second gate all extend on the horizontal plane.
  • the overall structure of the write transistor is simple and easy to implement.
  • the coupling metal layer extends in a plane perpendicular to the first direction
  • the coupling metal layer is arranged on the side of the first gate base layer facing away from the write transistor
  • the coupling metal layer surrounds the first gate
  • the side of the coupling metal layer facing the first gate base layer, the side facing away from the first gate base layer, and the side facing the first gate metal pillars are all provided with capacitive dielectric layers.
  • This implementation mode provides a structure of the decoupling capacitor.
  • the coupling metal layer can be integrated in the read transistor and located under the first gate substrate layer.
  • the coupling metal layer and the first gate metal column are respectively used as the two capacitive electrodes of the decoupling capacitor.
  • the boards arranged in this way can form a compact storage unit structure without increasing the integration degree in the horizontal direction, and at the same time, have little influence on the height of the storage unit.
  • connection metal includes a connection metal layer and a connection metal post
  • the connection metal post extends along a first direction
  • the connection metal layer extends in a plane perpendicular to the first direction
  • the connection metal layer is connected to the third One side of the electrode facing the read transistor
  • the connecting metal post is connected between the connecting metal layer and the first gate
  • the coupling metal layer is arranged between the connecting metal layer and the first gate
  • the coupling metal layer surrounds the connecting metal post
  • a first isolation layer is provided between the coupling metal layer and the first gate
  • a second isolation layer is provided between the coupling metal layer and the connection metal layer
  • a capacitive dielectric layer is provided between the coupling metal layer and the connection metal column.
  • This implementation mode provides another structure of the decoupling capacitor.
  • the coupling metal layer can be arranged between the write transistor and the read transistor, and the coupling metal layer surrounds the connection metal column connecting the first gate and the third electrode.
  • the metal layer and the connecting metal pillar are respectively used as the two capacitive plates of the decoupling capacitor. This arrangement can form a compact memory cell structure without increasing the integration degree in the horizontal direction. At the same time, the structure of the decoupling capacitor is relatively simple and easy to process. accomplish.
  • the memory includes a plurality of storage units, the plurality of storage units are arranged in an array on a plane perpendicular to the first direction, and the write word line, the write bit line, the read byte line, the read bit The lines respectively extend on different planes perpendicular to the first direction.
  • a plurality of storage units are arranged in an array to form a memory.
  • a memory array structure of any size can be realized; write byte lines, write bit lines, read byte lines, The read bit lines are respectively connected to the second gate, the fourth pole, the second pole, and the first pole, and can be respectively arranged in a coplanar manner and distributed on different horizontal planes.
  • the coupling metal layers in the multiple storage units are connected as a whole, and the coupling metal layers are connected to a preset potential.
  • the coupling metal layers share a plane.
  • the fabrication of the coupling metal layers can be simplified; on the other hand, it is convenient to connect the coupling metal layers in each storage unit to a preset potential at the same time.
  • the write word lines extend along the second direction, a plurality of write word lines are arranged at intervals in the third direction, the plane where the second direction and the third direction are located is perpendicular to the first direction, and The second direction and the third direction are perpendicular to each other, the write bit lines extend along the third direction, a plurality of write bit lines are arranged at intervals in the second direction, and the second gates of the plurality of write transistors arranged at intervals in the second direction
  • the poles are connected to the same write word line, and the fourth poles of the plurality of write transistors arranged at intervals in the third direction are connected to the same write bit line;
  • the read word lines extend along the third direction and the multiple read word lines are Arranged at intervals in the second direction, the read bit lines extend along the second direction and a plurality of read bit lines are arranged at intervals in the third direction, the second poles of the plurality of read transistors arranged at intervals in the third direction are connected to the same read For the word line
  • the same write word line can control the opening of a plurality of write transistors arranged in the second direction, and the potential of a plurality of write bit lines arranged at intervals in the second direction can be
  • the data are transmitted to the first gates of the respective corresponding read transistors to realize batch writing of "0" and "1" and improve the read and write efficiency of the memory.
  • the preset potential is a ground terminal.
  • the preset potential can be a fixed potential, such as GND (ground terminal) or a fixed potential value, and the preset potential can also be a non-fixed potential, so that the preset potential can be adjusted to be low or high according to the needs of the circuit, so that Adjust the size of the decoupling capacitor. Setting the preset potential as the ground terminal is easy to implement.
  • the embodiments of the present application also provide a manufacturing method of a memory, the manufacturing method comprising:
  • the capacitive dielectric layer covers the periphery of the first gate and the upper surface of the second metal layer, and the coupling metal layer surrounds the first gate metal pillar;
  • the above manufacturing method can realize the manufacturing of the read transistor with CAA structure, and at the same time, can integrate the decoupling capacitor in the read transistor.
  • the manufacturing method adopts processes such as deposition and etching, and the process is less difficult.
  • a sacrificial layer is set to reserve a position for the coupling metal layer, so that the decoupling capacitor is integrated in the read transistor without affecting the structure of the read transistor, which is an ingenious idea.
  • the manufacturing method of the memory further includes:
  • the second gate includes a second gate base layer and a second gate metal column in the second channel.
  • the above fabrication method can realize the fabrication of the writing transistor with the CAA structure, and the writing transistor is fabricated by using processes such as deposition and etching, and the processing is simple and easy to implement.
  • the read transistor integrated with the decoupling capacitor continue to fabricate the write transistor provided in this embodiment, and a memory with a CAA structure of CAA+integrated with the decoupling capacitor can be obtained.
  • the manufacturing method of the memory further includes:
  • a fourth metal layer is deposited, and the fourth metal layer is etched to form a fourth pole.
  • the above-mentioned manufacturing method can realize the manufacturing of the write transistor with the GAA structure, and the write transistor is manufactured by using processes such as deposition and etching, and the processing is simple and easy to implement.
  • the read transistor integrated with the decoupling capacitor continue to fabricate the write transistor provided in this embodiment, and a memory with a CAA structure of GAA+integrated with the decoupling capacitor can be obtained.
  • a method for fabricating a memory includes:
  • the first gate includes a first gate metal pillar in the first trench and a first gate base layer above the first gate metal pillar;
  • connection groove is located above the first gate metal column
  • connection metal includes a connection metal post in the connection groove and a connection metal layer above the connection metal post.
  • the above manufacturing method can realize the fabrication of the read transistor and the decoupling capacitor of the CAA structure. After the read transistor is fabricated, continue to fabricate structures such as the coupling metal layer, so that the decoupling capacitor is formed above the read transistor. On the whole, the processing is simple and easy to implement. , the product yield is higher.
  • the manufacturing method of the memory further includes:
  • the second gate includes a second gate base layer and a second gate metal column in the second channel.
  • the above fabrication method can realize the fabrication of the writing transistor with the CAA structure, and the writing transistor is fabricated by using processes such as deposition and etching, and the processing is simple and easy to implement.
  • the completed read transistor and decoupling capacitor continue to fabricate the write transistor provided by this embodiment, and a memory with a structure of CAA+decoupling capacitor+CAA can be obtained.
  • the manufacturing method of the memory further includes:
  • a fifth metal layer is deposited, and the fifth metal layer is etched to form a fourth pole.
  • the above-mentioned manufacturing method can realize the manufacturing of the write transistor with the GAA structure, and the write transistor is manufactured by using processes such as deposition and etching, and the processing is simple and easy to implement.
  • the completed read transistor and decoupling capacitor continue to fabricate the write transistor provided by this embodiment, and a memory with a structure of GAA+decoupling capacitor+CAA can be obtained.
  • the memory and the manufacturing method of the memory provided in the embodiments of the present application increase the total capacitance of the storage node by increasing the decoupling capacitor to prolong the charge retention time.
  • the newly added decoupling capacitor is larger than the gate-source and gate-drain capacitance,
  • the influence of the coupling of the write word line and the read word line on the storage node can be greatly reduced, and the influence of the voltage coupling on the normal operation of the memory can be avoided.
  • the writing transistor and the reading transistor are arranged along the first direction. The area of the large device will not bring about the loss of memory density.
  • the combination of deposition, etching and other processes can realize the production of memories with different structures, the overall production process is less difficult, and the yield rate is high.
  • Fig. 1 is the circuit diagram of the memory that the related art provides
  • FIG. 2 is a potential change diagram of a storage node during the operation of the memory provided by the related art
  • FIG. 3 is a circuit diagram of a memory provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a storage unit provided by an embodiment of the present application.
  • FIG. 5 is another schematic structural diagram of a storage unit provided by an embodiment of the present application.
  • FIG. 6 is another schematic structural diagram of a storage unit provided by an embodiment of the present application.
  • FIG. 7 is another schematic structural diagram of a storage unit provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of an array structure of a memory provided by an embodiment of the present application.
  • FIG. 9 is a flow chart of a part of the manufacturing process of a memory cell provided by an embodiment of the present application.
  • 10a-10h are structural schematic diagrams of a part of the manufacturing process of a memory cell provided by an embodiment of the present application.
  • FIG. 11 is a flow chart of the preparation process of the write transistor provided by an embodiment of the present application.
  • FIG. 13 is a flow chart of another fabrication process of a write transistor provided by an embodiment of the present application.
  • FIGS. 14a-14e are schematic structural diagrams of another preparation process of a write transistor provided by an embodiment of the present application.
  • FIG. 15 is a partial flowchart of another manufacturing process of a memory cell provided by an embodiment of the present application.
  • 16a-16h are partial structural schematic diagrams of another manufacturing process of a memory cell provided by an embodiment of the present application.
  • Figure 17a is a simulation diagram of the capacitance value of the memory provided by the related art.
  • FIG. 17b is a simulation diagram of a capacitance value of a memory provided by an embodiment of the present application.
  • FIG. 18a is a schematic diagram of a coupling voltage of a storage node of a memory provided by the related art
  • FIG. 18b is a schematic diagram of a coupling voltage of a storage node of a memory provided by an embodiment of the present application.
  • Figure 19a is a schematic diagram of the charge retention time of the memory provided by the related art.
  • FIG. 19b is a schematic diagram of charge retention time of a memory provided by an embodiment of the present application.
  • Memory is a memory device used to save information in modern information technology.
  • the main function of memory is to store programs and various data, and to complete the access of programs or data automatically and at high speed during computer operation.
  • the gap between the processor and the memory is getting bigger and bigger.
  • the growth rate of the microprocessor far exceeds the growth rate of the memory, which eventually leads to the storage density and read and write speed of the memory not keeping up with the processor.
  • the calculation speed of the computer is high, so a "storage wall" appears, which ultimately affects the overall performance of the computer system.
  • SRAM Static Random-Access Memory
  • Embedded DRAM enhanced dynamic random access memory, eDRAM
  • the reading speed of eDRAM can be as low as nanoseconds, and its occupied area is only one third of SRAM memory, with the advantages of high-speed reading and writing and high-density integration.
  • FIG. 1 is a circuit diagram of a memory provided by the related art.
  • the related art provides a memory including a write word line 101 , a write bit line 102 , a read word line 103 , a read bit line 104 , a write transistor 110 and a read transistor 120 .
  • the read transistor 120 includes a first gate 121, a first pole 123 and a second pole 122, wherein the first pole 123 is a source, and the second pole 122 is a drain, or the first pole 123 is a drain, and the second pole 122 for the source.
  • the write transistor 110 includes a second gate 111, a third pole 113 and a fourth pole 112, wherein the third pole 113 is a source, the fourth pole 112 is a drain, or the third pole 113 is a drain, and the fourth pole 112 for the source.
  • the second gate 111 is connected to the write word line 101
  • the fourth pole 112 is connected to the write bit line 102
  • the second pole 122 is connected to the read word line 103
  • the first pole 123 is connected to the read bit line 104
  • the gate 121 is connected to form the storage node 105 .
  • the working principle of this memory is that in the “write” operation, the write transistor 110 is controlled by the write byte line 101, and the potential of the write bit line 102 is transmitted to the first gate 121 of the read transistor 120, so that the first The potential of the gate 121 is synchronized with the write bit line 102 to realize the writing of "0" and "1"; then, the write bit line 101 controls the write transistor 110 to turn off.
  • the "read” operation it is only necessary to judge the storage state according to the current level of the read transistor 120 .
  • FIG. 2 is a diagram of potential changes of storage nodes during the operation of the memory provided by the related art.
  • D1 is caused by the voltage coupling between the storage node 105 and the write word line 101
  • D2 is the voltage on the storage node 105 and the read word line 103. Therefore, it can be obtained that the storage node 105 and the write word line 101 and the read word line 103 will have obvious voltage coupling, which will cause the potential of the storage node 105 to increase or decrease, and the risk of misreading will increase.
  • the embodiment of the present application provides a memory that increases the total capacitance of the storage node by adding a decoupling capacitor to prolong the charge retention time.
  • the newly added decoupling capacitor is much larger than the Capacitance can greatly reduce the coupling effect of the write word line and the read word line on the storage node; and the memory provided by the embodiment of the present application arranges the write transistor and the read transistor vertically, which can not increase the level while introducing capacitance
  • the degree of integration in the direction does not increase the area of the device and does not cause a loss of memory density.
  • FIG. 3 is a circuit diagram of a memory provided by an embodiment of the present application.
  • an embodiment of the present application provides a memory, including a write byte line 101, a write bit line 102, a read byte line 103, a read bit line 104, a write transistor 110, a read transistor 120, and a decoupling capacitor 130. .
  • the read transistor 120 may include a first gate 121, a first pole 123 and a second pole 122, wherein the second pole 122 and the first pole 123 may be respectively the source and the drain of the read transistor 120, or the second pole 122 and the The first poles 123 may be the drain and the source of the read transistor 120, respectively.
  • the write transistor 110 may include a second gate 111, a third pole 113 and a fourth pole 112, the fourth pole 112 and the third pole 113 may be respectively the source and the drain of the write transistor 110, or the fourth pole 112 and The third pole 113 may be the drain and the source of the write transistor 110 respectively.
  • the second gate 111 can be connected to the write bit line 101
  • the fourth pole 112 can be connected to the write bit line 102
  • the second pole 122 can be connected to the read word line 103
  • the first pole 123 can be connected to the read bit line 104
  • the third pole 122 can be connected to the read bit line 104.
  • 113 and the first gate 121 may be connected to form the storage node 105 .
  • One end of the decoupling capacitor 130 can be connected to the storage node 105 , and the other end can be connected to a predetermined potential.
  • the preset potential can be a fixed potential, such as GND (ground terminal) or a fixed potential value, and the preset potential can also be a non-fixed potential, so that the preset potential can be adjusted to a low potential or High potential, so that the size of the decoupling capacitor 130 can be adjusted.
  • a decoupling capacitor 130 in parallel at the storage node 105, on the one hand, it can be used to increase the total capacitance of the storage node 105 to prolong the charge retention time; on the other hand, the capacitance value of the decoupling capacitor 130 is much larger than
  • the gate-source and gate-drain capacitance can greatly reduce the coupling effect of the write word line 101 and the read word line 103 on the storage node 105, and avoid voltage coupling from affecting the normal operation of the memory.
  • the writing transistor 110 and the reading transistor 120 can be thin film transistors (Thin film transistor, TFT), and the potential of the first gate 121 of the reading transistor 120 is determined by the charge amount of the storage node 105.
  • TFT thin film transistor
  • the traditional silicon transistor is much lower, and the leakage of the charge on the first gate 121 of the read transistor 120 through the write transistor 110 will be greatly reduced, so that the storage duration of the memory can be improved.
  • the write transistor 110 and the read transistor 120 can be arranged sequentially in the first direction, and the first direction can be defined as a vertical direction.
  • the decoupling capacitor 130 can be arranged between the write transistor 110 and the read transistor 120, so as not to Increasing the level of integration in the horizontal direction does not increase the area of the device and does not cause loss of memory density.
  • the read transistor 120 may include a first channel extending in a first direction, and the write transistor 110 may include a second channel extending in the first direction.
  • the vertical arrangement of the write transistor 110 and the read transistor 120 is beneficial to form a compact memory structure.
  • a write transistor 110 and a read transistor 120 arranged vertically may form a memory cell, and a memory cell may have a columnar structure as a whole.
  • the specific structure of the write transistor 110 and the read transistor 120 has various implementation manners, for example, it may be a GAA (Gate All Around) structure or a CAA (Channel All Around) structure.
  • the vertical direction in the figure below can be defined as the first direction
  • the horizontal plane in the figure below is a plane perpendicular to the first direction
  • FIG. 4 is a schematic structural diagram of a storage unit provided by an embodiment of the present application.
  • the read transistor 120 may be a CAA structure.
  • the read transistor 120 may include a first semiconductor layer 124, the first semiconductor layer 124 has a first channel (not marked in the figure), the first channel is the vertical channel of the read transistor 120, and the first channel may be a cuboid structure , cylindrical structure or other columnar structures.
  • the first gate 121 may include a first gate base layer 1211 and a first gate metal column 1212, the first gate metal column 1212 is located in the first trench, the first gate base layer 1211 is connected to the first gate metal column 1212 close to the write On one side of the transistor 110, the first gate base layer 1211 extends in a horizontal plane; a first gate dielectric layer 125 is arranged between the first gate 121 and the first semiconductor layer 124, and the first pole 123 and the second pole 122 are connected with each other.
  • the first semiconductor layer 124 is connected, the first pole 123 and the second pole 122 both extend in the horizontal plane, the second pole 122 is located between the first pole 123 and the first gate base layer 1211, the second pole 122 and the first pole 123 A first insulating layer 126 is disposed therebetween.
  • the writing transistor 110 may also be a CAA structure.
  • the write transistor 110 may include a second semiconductor layer 114, the second semiconductor layer 114 has a second channel (not marked in the figure), the second channel is the vertical channel of the write transistor 110, and the second channel may be a cuboid structure , cylindrical structure or other columnar structures.
  • the second gate 111 may include a second gate base layer 1111 and a second gate metal column 1112, the second gate metal column 1112 is located in the second channel, and the second gate base layer 1111 is connected to the On one side of the transistor 120, the second gate base layer 1111 extends in a horizontal plane.
  • a second gate dielectric layer 115 is disposed between the second gate 111 and the second semiconductor layer 114, the fourth pole 112 and the third pole 113 are both connected to the second semiconductor layer 114, and the fourth pole 112 and the third pole 113 are both connected to the second semiconductor layer 114. Extending in a horizontal plane, the fourth pole 112 is located between the third pole 113 and the second gate base layer 1111 , and a second insulating layer 116 is disposed between the fourth pole 112 and the third pole 113 .
  • one of the capacitive plates of the decoupling capacitor 130 can be the coupling metal layer 131
  • the other capacitive plate of the decoupling capacitor 130 can be the first gate 121
  • the coupling metal layer 131 can be Connect to preset potential
  • the coupling metal layer 131 can extend in the horizontal plane, the coupling metal layer 131 can be arranged on the side of the first gate base layer 1211 facing away from the write transistor 110, the coupling metal layer 131 can surround the first gate metal pillar 1212, and the coupling The side of the metal layer 131 facing the first gate base layer 1211 , the side facing away from the first gate base layer 1211 , and the side facing the first gate metal pillar 1212 are all provided with a capacitive dielectric layer 132 .
  • the coupling metal layer 131 and the first gate 121 constitute the decoupling capacitor 130, so that a compact memory cell structure can be formed without increasing the Integration.
  • FIG. 5 is another schematic structural diagram of a storage unit provided by an embodiment of the present application.
  • the write transistor 110 may be a GAA structure.
  • the write transistor 110 may include a second semiconductor layer 114, and the second semiconductor layer 114 extends along the first direction to form a second channel, and the second channel may be a cuboid structure, a cylinder structure or other columnar structures.
  • the fourth pole 112 may be connected to an end of the second semiconductor layer 114 away from the read transistor 120, the third pole 113 may be connected to an end of the second semiconductor layer 114 close to the read transistor 120, and the second gate 111 may be located at the fourth pole.
  • 112 and the third pole 113, the second gate 111 is arranged around the second semiconductor layer 114, the fourth pole 112, the third pole 113, and the second gate 111 can all extend in the horizontal plane, the second gate 111 and
  • a second gate dielectric layer 115 is arranged between the second semiconductor layer 114, a second insulating layer 117 is arranged between the second gate 111 and the third electrode 113, and a second insulating layer 117 is arranged between the second gate 111 and the fourth electrode 112.
  • the third insulating layer 116 is arranged between the second semiconductor layer 114 away from the read transistor 120
  • the third pole 113 may be connected to an end of the second semiconductor layer 114 close to the read transistor 120
  • the second gate 111 may be
  • the read transistor 120 may have a CAA structure, and its specific structure may refer to the description of the write transistor 110 in FIG. 4 , which will not be repeated here.
  • one of the capacitive plates of the decoupling capacitor 130 is the coupling metal layer 131, and the other capacitive plate of the decoupling capacitor 130 may be a plate connected to the third electrode 113 and the first gate 121. Connect metal 133 .
  • connection metal 133 may include a connection metal layer 1331 and a connection metal post 1332, the connection metal post 1332 extends along the first direction, the connection metal layer 1331 extends in the horizontal plane, and the connection metal layer 1331 is connected to the third electrode 113 facing the reading transistor 120. On one side, the connection metal pillar 1332 is connected between the connection metal layer 1331 and the first gate 121 .
  • the coupling metal layer 131 may be disposed between the connection metal layer 1331 and the first gate 121, the coupling metal layer 131 may surround the connection metal pillar 1332, and a first The isolation layer 135 , the second isolation layer 134 is disposed between the coupling metal layer 131 and the connecting metal layer 1331 , and the capacitive dielectric layer 132 is disposed between the coupling metal layer 131 and the connecting metal pillar 1332 .
  • the coupling metal layer 131 and the connection metal 133 form a decoupling capacitor 130, which can also form a compact memory cell structure, Does not increase the level of integration in the horizontal direction.
  • FIG. 6 is another schematic structural diagram of a storage unit provided by an embodiment of the present application.
  • both the write transistor 110 and the read transistor 120 can be configured as a CAA structure
  • the decoupling capacitor 130 can be composed of a coupling metal layer 131 and a connection metal layer 1331, wherein the write transistor
  • FIG. 7 is another schematic structural diagram of a storage unit provided by an embodiment of the present application.
  • the write transistor 110 can be configured as a GAA structure
  • the read transistor 120 can be configured as a CAA structure
  • the two capacitive plates of the decoupling capacitor 130 can be respectively made of a coupling metal layer 131 and the first gate 121, wherein the specific structure of the write transistor 110 and the read transistor 120 can refer to the description shown in FIG. 5, and the structure of the decoupling capacitor 130 can refer to the description shown in FIG.
  • one of the capacitive plates of the decoupling capacitor 130 is the coupling metal layer 131, and the other capacitive plate can be the first gate 121 or The connection metal 133, because the third pole 113, the first grid 121, and the connection metal 133 are connected to each other, the potentials of the various places are the same, so these four different implementation methods can be equivalent to the same circuit, that is, the circuit shown in Figure 3 circuit.
  • FIG. 8 is a schematic diagram of an array structure of a memory provided by an embodiment of the present application.
  • the memory may include a plurality of storage units, and the write transistor 110 and the read transistor 120 of each storage unit may be arranged along a first direction (Z direction), and a plurality of storage units are arranged on a plane perpendicular to the first direction. (XY plane) is arranged in an array, and the write word line 101 , the write bit line 102 , the read word line 103 , and the read bit line 104 respectively extend on different XY planes.
  • each storage unit may occupy an area of 4F 2 . It should be understood that by increasing the number of memory cells in the X direction or the Y direction, a larger memory array structure can be realized. It should be understood that by stacking memory cells in the Z direction, the size of the memory array can also be increased.
  • the write word lines 101 may extend along the second direction (Y direction), a plurality of write word lines 101 are arranged at intervals in the third direction (X direction), and the second direction and the second direction
  • the plane where the three directions are located is perpendicular to the first direction, and the second direction and the third direction are perpendicular to each other
  • the write bit lines 102 extend along the third direction and a plurality of write bit lines 102 are arranged at intervals in the second direction, and in the second
  • the second gates 111 of the plurality of write transistors 110 arranged at intervals in the direction are connected to the same write word line 101
  • the fourth electrodes 112 of the plurality of write transistors 110 arranged at intervals in the third direction are connected to the same write bit line 102.
  • the read bit lines 103 may extend along the third direction, the plurality of read bit lines 103 are arranged at intervals in the second direction, the read bit lines 104 may extend along the second direction, and the plurality of read bit lines 104 are spaced apart in the third direction Arrangement, the second electrodes 122 of the plurality of read transistors 120 arranged at intervals in the third direction are connected to the same read word line 103, and the first electrodes 123 of the plurality of read transistors 120 arranged at intervals in the second direction are connected to to the same read bit line 104.
  • the same write word line 101 can control the opening of a plurality of write transistors 110 arranged in the Y direction, and the multiple write bit lines 102 arranged at intervals in the Y direction can be
  • the potentials are transmitted to the first gates 121 of the respective corresponding read transistors 120 to implement batch writing of "0" and "1", improving the read and write efficiency of the memory.
  • the coupling metal layer 131 in a plurality of memory cells can be connected as a whole, and the coupling metal layer 131 can be connected to a predetermined potential.
  • the coupling metal layers 131 share a plane.
  • the fabrication of the coupling metal layer 131 can be simplified; on the other hand, it is convenient to connect the coupling metal layers 131 in each memory cell to a preset potential at the same time.
  • the materials of the first grid 121 and the second grid 111 can be metal materials or conductive materials, such as titanium nitride TiN, titanium Ti, gold Au, tungsten W, molybdenum Mo, indium tin oxide In-Ti-O (ITO), indium zinc oxide In-Zn-O (IZO), aluminum Al, copper Cu, ruthenium Ru, silver Ag, platinum Pt and other materials or any combination thereof.
  • metal materials or conductive materials such as titanium nitride TiN, titanium Ti, gold Au, tungsten W, molybdenum Mo, indium tin oxide In-Ti-O (ITO), indium zinc oxide In-Zn-O (IZO), aluminum Al, copper Cu, ruthenium Ru, silver Ag, platinum Pt and other materials or any combination thereof.
  • the materials of the first pole 123, the second pole 122, the third pole 113, and the fourth pole 112 can be metal materials or other conductive materials, such as titanium nitride TiN, titanium Ti, gold Au, tungsten W, molybdenum Mo, oxide Indium tin In-Ti-O (ITO), indium zinc oxide In-Zn-O (IZO), aluminum Al, copper Cu, ruthenium Ru, silver Ag, platinum Pt and other materials or any combination thereof.
  • the materials of each gate, source, drain, coupling metal layer 131 and connection metal 133 may be the same or different.
  • the materials of the first semiconductor layer 124 and the second semiconductor layer 114 can be semiconductor materials, such as silicon-based semiconductors such as silicon Si, polycrystalline silicon poly-Si, amorphous silicon amorphous-Si, or indium oxide In2O3, zinc oxide ZnO, calcium oxide Ga2O3 , indium tin oxide ITO, titanium dioxide TiO2 and other metal oxides, or indium gallium zinc oxide In-Ga-Zn-O (IGZO), indium gallium tin oxide In-Sn-Zn-O (ISZO) and other multi-component compounds, graphite Two-dimensional semiconductor materials such as alkene, molybdenum disulfide MoS2, black phosphorus, or any combination thereof.
  • silicon-based semiconductors such as silicon Si, polycrystalline silicon poly-Si, amorphous silicon amorphous-Si, or indium oxide In2O3, zinc oxide ZnO, calcium oxide Ga2O3 , indium tin oxide ITO, titanium dioxide TiO2 and other
  • first gate dielectric layer 125 and the second gate dielectric layer 115 can be insulating materials, such as silicon oxide SiOx, silicon nitride SiNx, aluminum oxide Al2O3, hafnium dioxide HfO2, zirconium dioxide ZrO2, titanium dioxide TiO2, yttrium oxide Y2O3 and other materials or their combined materials, laminated materials, and combined laminated materials.
  • insulating materials such as silicon oxide SiOx, silicon nitride SiNx, aluminum oxide Al2O3, hafnium dioxide HfO2, zirconium dioxide ZrO2, titanium dioxide TiO2, yttrium oxide Y2O3 and other materials or their combined materials, laminated materials, and combined laminated materials.
  • the materials of the insulating layer and the capacitor dielectric layer can be the same or different.
  • the insulating layers 116, 117, 126 and the isolation layers 134, 135 can be made of insulating materials, such as silicon oxide SiO2, silicon nitride Si3N4, aluminum oxide Al2O3, hafnium dioxide HfO2 and other materials.
  • the capacitor dielectric layer 132 can be an insulating material, such as silicon oxide SiOx, silicon nitride SiNx, aluminum oxide Al2O3, hafnium dioxide HfO2, zirconium dioxide ZrO2, titanium dioxide TiO2, yttrium oxide Y2O3, etc. or their combination materials, stacked materials, Combine laminated materials.
  • the fourth pole 112 and the third pole 113 respectively form ohmic contacts with the second semiconductor layer 114, and the second pole 122 and the first pole 123 respectively form ohmic contacts with the first semiconductor layer 124. Diffusion occurs in the contact area with the semiconductor layer to reduce the Fermi pinning effect of the contact.
  • An insulating layer of about 0.1nm-2nm can be introduced at the interface between the source and drain metal layer and the semiconductor layer to form a semiconductor layer-insulation layer-source Drain metal layer structure.
  • the material of the write word line 101 can be the same as that of the second gate 111
  • the material of the write bit line 102 can be the same as that of the fourth electrode 112
  • the material of the read word line 103 can be the same as that of the second electrode 122.
  • the materials are the same
  • the material of the read bit line 104 can be the same as that of the first pole 123 .
  • FIG. 9 is a flow chart of a part of the manufacturing process of a memory cell provided by an embodiment of the present application
  • FIGS. 10a-10h are schematic structural diagrams of a part of the manufacturing process of a memory cell provided by an embodiment of the present application. It should be noted that the manufacturing process flow shown in FIG. 9 and the partial structure of the memory cell prepared in FIG. 10a-FIG. 10h correspond to the lower half structure of the memory cell in FIG. 4 and FIG. The structure of the coupling capacitor 130.
  • two memory cells are taken as an example in the structural schematic diagram of the memory manufacturing process below, for example, two read transistors 120 are taken as an example in FIGS.
  • the manufacturing method of memory unit can comprise the following steps:
  • the first metal layer is deposited on the substrate (not shown in the figure), the first pole 123 can be formed by selectively etching the first metal layer, and the second pole 122 can be formed by selectively etching the second metal layer .
  • the first metal layer of the same layer is etched, a plurality of first poles 123 arranged in an array and separated from each other can be formed, and after the second metal layer of the same layer is etched, a plurality of electrodes 123 arranged in an array and mutually separated can be formed. Separated second poles 122 .
  • first channels 142 may be arranged in an array, and each first channel 142 is correspondingly arranged with each first pole 123 and each second pole 122 .
  • the first gate 121 includes a first gate metal column located in the first channel 142 1212 and the first gate base layer 1211 located above the first gate metal pillar 1212 may refer to the structure shown in FIG. 10d. It should be understood that two adjacent first gates 121 are separated by the first groove 143 .
  • dry selective etching can be used in S102 and S104
  • atomic layer deposition (ALD) process can be used in S103 and S107
  • wet etching can be used in S105 and S108.
  • FIG. 11 is a flow chart of a fabrication process of a write transistor provided by an embodiment of the present application
  • FIGS. 12a-12d are schematic structural diagrams of a fabrication process of a write transistor provided by an embodiment of the present application. It should be noted that the manufacturing process flow shown in FIG. 11 and the writing transistor prepared in FIG. 12a-FIG. 12d correspond to the structure of the writing transistor in FIG. 4 and FIG. 6 .
  • the fabrication process of the write transistor provided by an embodiment of the present application may include the following steps:
  • the second gate 111 includes a second gate base layer 1111 and a second gate metal pillar 1112 located in the second channel 144, refer to FIG. 12d structure shown. It should be understood that two adjacent second gates 111 are separated by the second groove 145 .
  • FIG. 13 is a flow chart of another manufacturing process of a write transistor provided by an embodiment of the present application
  • FIGS. 14a-14e are structural schematic diagrams of another manufacturing process of a write transistor provided by an embodiment of the present application. It should be noted that the manufacturing process flow shown in FIG. 13 and the writing transistor prepared in FIG. 14a-FIG. 14e correspond to the structure of the writing transistor in FIG. 5 and FIG. 7 .
  • the fabrication process of a write transistor provided by an embodiment of the present application may include the following steps:
  • FIG. 15 is a partial flowchart of another manufacturing process of a memory cell provided by an embodiment of the present application
  • FIGS. 16a-16h are partial structural schematic diagrams of another manufacturing process of a memory cell provided by an embodiment of the present application. It should be noted that the manufacturing process flow shown in FIG. 15 and the partial structure of the memory cell prepared in FIG. 16a-FIG. 16h correspond to the lower half structure of the memory cell in FIG. 5 and FIG. The structure of the coupling capacitor 130.
  • the manufacturing method of the memory cell may include the following steps:
  • the first gate 121 includes the first gate metal pillar 1212 located in the first trench 142 and the first gate metal pillar 1212 located above the first gate metal pillar 1212.
  • the gate base layer 1211 refer to the structure shown in FIG. 16d. It should be understood that two adjacent first gates 121 are separated by the first groove 143 .
  • connection groove 146 is located above the first gate metal pillar 1212 , and the structure shown in FIG. 16 f may be referred to.
  • connection metal 133 includes a connection metal column 1332 located in the connection groove 146 and a connection metal layer 1331 located above the second isolation layer 134, refer to FIG. The structure shown in 16h.
  • the memory shown in FIG. 4 can be obtained by continuing the manufacturing method shown in FIG. 11; on the basis of the manufacturing method shown in FIG. According to the manufacturing method shown, the memory shown in FIG. 7 can be obtained.
  • the memory shown in Figure 15 can be obtained on the basis of the production method shown in Figure 15, continue to carry out the production method shown in Figure 11, the memory shown in Figure 6 can be obtained; on the basis of the production method shown in Figure 15, continue to carry out the production method shown in Figure 13
  • the memory shown in FIG. 5 can be obtained.
  • the specific manufacturing steps of continuing to manufacture the write transistor based on the manufacturing method shown in FIG. 15 reference can be made to the foregoing, and details will not be repeated here.
  • Figure 17a is a simulation diagram of the capacitance value of the memory provided by the related art
  • Figure 17b is a simulation diagram of the capacitance value of the memory provided by an embodiment of the present application, wherein C1 represents the gate-drain capacitance, C2 represents the gate-source capacitance, and C3 represents the increased capacitance .
  • the memory provided by the related technology has a gate-source capacitance of 1.2e-16F, and a gate-drain capacitance of 5e-17F, while the memory provided by the embodiment of the present application has an increased capacitance of 2.5e-16F,
  • the increased capacitance Cgb is 2 to 5 times of the gate-source capacitance Cgs and the gate-drain capacitance Cgd.
  • Figure 18a is a schematic diagram of the coupling voltage of the storage node of the memory provided by the related art
  • Figure 18b is a schematic diagram of the coupling voltage of the storage node of the memory provided by an embodiment of the present application, wherein D1 represents the voltage of WWL, and D2 represents the voltage of SN.
  • the memory provided by the related technology when the voltage of WWL drops from 1.5V to -2V, the SN voltage drop caused by capacitive coupling is 992mV and 703mV respectively, while the memory provided by the embodiment of the present application, When the voltage of WWL drops from 1.5V to -2V, the SN voltage drop caused by capacitive coupling is 213mV and 158mV, respectively. Therefore, in the memory provided by the embodiment of the present application, the SN voltage drop caused by capacitive coupling is reduced to about 22% compared with the structure provided by the related art.
  • FIG. 19 a is a schematic diagram of a charge retention time of a memory provided in the related art
  • FIG. 19 b is a schematic diagram of a charge retention time of a memory provided by an embodiment of the present application.
  • the memory provided by the related art takes 0.7s for the voltage to drop from 1V to 0.8V, that is, the charge retention time is 0.7s
  • the memory provided by the embodiment of the present application takes the voltage to drop from 1V to 0.7s.
  • the time taken to reach 0.8V is 6.8s, that is, the charge retention time is 6.8s. Therefore, compared with the related art, the retention time of the memory provided by the embodiment of the present application can be increased nearly ten times.
  • the memory provided by the embodiment of the present application can increase the total capacitance of the storage node and prolong the charge retention time by increasing the decoupling capacitance.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Memories (AREA)

Abstract

本申请实施例提供一种存储器和存储器的制作方法，存储器包括写字节线、写比特线、读字节线、读比特线以及存储单元；存储单元包括在第一方向上依次排布的写晶体管和读晶体管，读晶体管包括第一栅极、第一极和第二极，写晶体管包括第二栅极、第三极和第四极，第二栅极连接写字节线，第四极连接写比特线，第二极连接读字节线，第一极连接读比特线，第三极和第一栅极连接形成存储节点；去耦合电容的一端连接至存储节点，另一端连接至预设电位。本申请实施例提供一种存储器和存储器的制作方法，可以减少写字节线、读字节线对存储节点的电压耦合。

Description

存储器和存储器的制作方法 技术领域
本申请涉及存储器技术领域，尤其涉及一种存储器和存储器的制作方法。
背景技术
随着互联网技术和云计算技术的发展，信息时代正向大数据时代飞速转变,使得存储系统的需求不断提升，日益增长的信息量使存储芯片在整个集成电路产业市场中占据非常重要的地位。
相关技术中，存储器可以包括写晶体管(Write Transistor，WTR)和读晶体管(Read Transistor，RTR)，写晶体管的栅极连接写字节线(Write Word Line，WWL)，写晶体管的源极连接写比特线(Write Bit Line，WBL)，读晶体管的源极连接读字节线，读晶体管的漏极连接读比特线，写晶体管的漏极和读晶体管的栅极连接形成存储节点(Storage Node，SN)。
由于晶体管本身的栅源、栅漏电容较小，存储器的保持时间受到限制，并且写字节线、读字节线与存储节点之间的电压耦合现象较为明显，影响存储器的正常工作。
发明内容
本申请实施例提供一种存储器和存储器的制作方法，可以减少写字节线、读字节线对存储节点的电压耦合。
本申请实施例一方面提供一种存储器，包括写字节线、写比特线、读字节线、读比特线以及存储单元；存储单元包括在第一方向上依次排布的写晶体管和读晶体管；读晶体管包括第一栅极、第一极和第二极，其中，第一极为源极，第二极为漏极，或者，第一极为漏极，第二极为源极；写晶体管包括第二栅极、第三极和第四极，其中，第三极为源极，第四极为漏极，或者第三极为漏极，第四极为源极；第二栅极连接写字节线，第四极连接写比特线，第二极连接读字节线，第一极连接读比特线，第三极和第一栅极连接形成存储节点；存储单元还包括去耦合电容，去耦合电容的一端连接至存储节点，另一端连接至预设电位。
本申请实施例提供的存储器，通过增加去耦合电容，来增加存储节点的总电容，以延长电荷保持时间，同时，由于新增的去耦合电容大于栅源、栅漏电容，可以大大减小写字节线和读字节线对存储节点的耦合影响，避免电压耦合影响存储器的正常运行；并且，本申请实施例提供的存储器将写晶体管和读晶体管沿第一方向布置，示例性的，第一方向可以为垂直方向，使得在为存储单元引入去耦合电容的同时不增大水平方向的集成度，不增大器件的面积，不会带来存储器密度的损失。
在一种可能的实施方式中，存储单元还包括耦合金属层，耦合金属层连接至预设电位， 去耦合电容包括第一电容极板和第二电容极板，其中，第一电容极板为耦合金属层，第二电容极板为第一栅极，或者第二电容极板为连接第三极和第一栅极的连接金属。
增加的耦合金属层可以作为去耦合电容的其中一个极板，去耦合电容的另一个极板可以为读晶体管的第一栅极，或者与第一栅极等电位的其它结构，例如连接第三极和第一栅极的连接金属，这样设置，可以利用存储单元原本的部分结构，来实现增加去耦合电容，对器件的体积影响较小。
在一种可能的实施方式中，读晶体管包括沿第一方向延伸的第一沟道，写晶体管包括沿第一方向延伸的第二沟道。
对于具有垂直沟道的写晶体管和读晶体管来说，将写晶体管和读晶体管垂直布置，存储器单元整体可以呈柱状结构，有利于形成紧凑的存储器结构。
在一种可能的实施方式中，第一栅极包括第一栅基底层和第一栅金属柱，第一栅金属柱位于第一沟道内，第一沟道的底面和侧壁上设置有第一半导体层，且第一栅金属柱和第一半导体层之间设置有第一栅介质层，第一栅基底层连接在第一栅金属柱的靠近写晶体管的一侧，第一栅基底层在垂直于第一方向的平面内延伸；第二极和第一极均与第一半导体层连接，第二极和第一极均在垂直于第一方向的平面内延伸，第二极位于第一极和第一栅基底层之间，第二极和第一极之间设置有第一绝缘层。
本实施方式提供了一种CAA(Channel All Around)结构的读晶体管，第一沟道呈垂直的柱状结构，第一栅金属柱位于第一沟道内，第一极和第二极分别与第一半导体层连接，第一极、第二极、第一栅基底层则均在水平面上延伸，读晶体管整体结构简单，容易实现。
在一种可能的实施方式中，第二栅极包括第二栅基底层和第二栅金属柱，第二栅金属柱位于第二沟道内，第二沟道的底面和侧壁上设置有第二半导体层，第二栅金属柱和第二半导体层之间设置有第二栅介质层，第二栅基底层连接在第二栅金属柱的远离读晶体管的一侧，第二栅基底层在垂直于第一方向的平面内延伸；第三极和第四极均与第二半导体层连接，第四极位于第三极和第二栅基底层之间，第三极和第四极均在垂直于第一方向的平面内延伸，第三极和第四极之间设置有第二绝缘层。
本实施方式提供了一种CAA(Channel All Around)结构的写晶体管，第二沟道呈垂直的柱状结构，第二栅金属柱位于第二沟道内，第三极和第四极分别与第二半导体层连接，第三极、第四极、第二栅基底层则均在水平面上延伸，写晶体管整体结构简单，容易实现。
在一种可能的实施方式中，写晶体管包括第二半导体层，第二半导体层沿第一方向延伸构成第二沟道，第四极连接在第二半导体层的远离读晶体管的一端，第三极连接在第二半导体层的靠近读晶体管的一端，第二栅极位于第三级和第四极之间，第三极、第四极、第二栅极均在垂直于第一方向的平面内延伸，第二栅极和第二半导体层之间设置有第二栅介质层，第二栅极和第三极之间设置有第二绝缘层，第二栅极和第四极之间设置有第三绝缘层。
本实施方式提供了一种GAA(Gate All Around)结构的写晶体管，第二沟道呈垂直的柱状结构，第二半导体层位于第二沟道内，第三极和第四极分别与第二半导体层连接，第二栅极围绕第二沟道设置，第三极、第四极、第二栅极则均在水平面上延伸，写晶体管整体结构简单，容易实现。
在一种可能的实施方式中，耦合金属层在垂直于第一方向的平面内延伸，耦合金属层 设置在第一栅基底层的背向写晶体管的一侧，耦合金属层环绕在第一栅金属柱的周围，耦合金属层的面向第一栅基底层的一侧、背向第一栅基底层的一侧、面向第一栅金属柱的一侧均设置有电容介质层。
本实施方式提供了去耦合电容的一种结构，耦合金属层可以集成在读晶体管内，位于第一栅基底层的下方，耦合金属层和第一栅金属柱分别作为去耦合电容的两个电容极板，这样设置，可以形成紧凑的存储单元结构，不增加水平方向的集成度，同时，对存储单元的高度的影响较小。
在一种可能的实施方式中，连接金属包括连接金属层和连接金属柱，连接金属柱沿第一方向延伸，连接金属层在垂直于第一方向的平面内延伸，连接金属层连接在第三极的面向读晶体管的一侧，连接金属柱连接在连接金属层和第一栅极之间，耦合金属层设置在连接金属层和第一栅极之间，耦合金属层环绕在连接金属柱的周围，耦合金属层和第一栅极之间设置有第一隔离层，耦合金属层和连接金属层之间设置有第二隔离层，耦合金属层和连接金属柱之间设置有电容介质层。
本实施方式提供了去耦合电容的另一种结构，耦合金属层可以设置在写晶体管和读晶体管之间，耦合金属层环绕在连接第一栅极和第三极的连接金属柱的周围，耦合金属层和连接金属柱分别作为去耦合电容的两个电容极板，这样设置，可以形成紧凑的存储单元结构，不增加水平方向的集成度，同时，去耦合电容的结构较为简单，工艺上容易实现。
在一种可能的实施方式中，存储器包括多个存储单元，多个存储单元在垂直于第一方向的平面上呈阵列排布，写字节线、写比特线、读字节线、读比特线分别在垂直于第一方向的不同平面上延伸。
多个存储单元呈阵列排布构成存储器，通过在垂直于第一方向的平面上增加存储单元的数量，可以实现任意规模的存储器阵列结构；写字节线、写比特线、读字节线、读比特线分别和第二栅极、第四极、第二极、第一极连接并可以各自对应呈共面设置，分布在不同的水平面上。
在一种可能的实施方式中，多个存储单元内的耦合金属层连接为一个整体，耦合金属层连接至预设电位。
耦合金属层共享一个平面，一方面可以使耦合金属层制作简单，另一方面，便于将各个存储单元内的耦合金属层同时连接至预设电位。
在一种可能的实施方式中，写字节线沿第二方向延伸，多条写字节线在第三方向上间隔排布，第二方向和第三方向所在的平面垂直于第一方向，且第二方向和第三方向互相垂直，写比特线沿第三方向延伸，多条写比特线在第二方向上间隔排布，在第二方向上间隔排布的多个写晶体管的第二栅极连接至同一写字节线，在上述第三方向上间隔排布的多个写晶体管的第四极连接至同一写比特线；读字节线沿第三方向延伸且多条读字节线在第二方向上间隔排布，读比特线沿第二方向延伸且多条读比特线在第三方向上间隔排布，在第三方向上间隔排布的多个读晶体管的第二极连接至同一读字节线，在第二方向上间隔排布的多个读晶体管的第一极连接至同一读比特线。
将多个存储单元阵列排布，则同一条写字节线可以控制在第二方向上排布的多个写晶体管开启，可以将在第二方向上间隔排布的多条写比特线的电位传递到各自对应的读晶体管的第一栅极上，以实现“0”和“1”的批量写入，提高存储器的读写效率。
在一种可能的实施方式中，预设电位为接地端。
预设电位可以为固定电位，例如GND(接地端)或者固定的某一电位值，预设电位也可以为非固定电位，以根据电路需要调节该预设电位处于低电位或者高电位，从而可以调节去耦合电容的大小。设置预设电位为接地端，容易实现。
本申请实施例另一方面还提供一种存储器的制作方法，该制作方法包括：
在衬底上沉积第一金属层，刻蚀第一金属层形成第一极；
依次沉积第一绝缘层和第二金属层，刻蚀第二金属层形成第二极；
沉积牺牲层，刻蚀牺牲层、第二金属层、第一绝缘层及部分厚度的第一金属层，形成垂直方向的第一沟道；
依次沉积第一半导体层、第一栅介质层和第一栅金属层；
刻蚀第一栅金属层、第一栅介质层和第一半导体层，形成第一栅极，第一栅极包括位于第一沟道内的第一栅金属柱和位于第一栅金属柱上方的第一栅基底层；
刻蚀去除牺牲层；
刻蚀去除位于第一栅基底层和第二金属层之间的第一半导体层和第一栅介质层；
依次沉积电容介质层和耦合金属层，电容介质层覆盖第一栅极的周围以及第二金属层的上表面，耦合金属层环绕第一栅金属柱；
刻蚀去除位于第一栅基底层侧面的电容介质层。
上述制作方法可以实现对CAA结构的读晶体管的制作，同时，可以将去耦合电容集成在读晶体管内，该制作方法采用沉积、刻蚀等工艺，工艺上难度较低。制作过程中，通过设置牺牲层，来为耦合金属层预留位置，从而在不影响到读晶体管的结构的同时，将去耦合电容集成在读晶体管内，思路巧妙。
在一种可能的实施方式中，存储器的制作方法还包括：
沉积第三金属层，刻蚀第三金属层形成第三极；
沉积第二绝缘层和第四金属层，刻蚀第四金属层形成第四极；
刻蚀第四金属层、第二绝缘层和部分厚度的第三金属层，形成垂直方向的第二沟道；
依次沉积第二半导体层、第二栅介质层和第二栅金属层；
刻蚀第二栅金属层，形成第二栅极，第二栅极包括第二栅基底层和位于第二沟道内的第二栅金属柱。
上述制作方法可以实现对CAA结构的写晶体管的制作，采用沉积、刻蚀等工艺来制作写晶体管，加工简单，容易实现。在已完成集成去耦合电容的读晶体管的基础上，继续制作本实施方式提供的写晶体管，可以得到CAA+集成去耦合电容的CAA结构的存储器。
在一种可能的实施方式中，存储器的制作方法还包括：
沉积第三金属层，刻蚀第三金属层形成第三极；
沉积第三绝缘层和第二栅金属层，刻蚀第二栅金属层形成第二栅极；
沉积第四绝缘层，刻蚀第四绝缘层、第二栅金属层和第三绝缘层，形成垂直方向的第二沟道；
沉积第二栅介质层，第二栅介质层覆盖第二沟道的侧壁；
沉积第二半导体层，第二半导体层填充在第二沟道内；
沉积第四金属层，刻蚀第四金属层形成第四极。
上述制作方法可以实现对GAA结构的写晶体管的制作，采用沉积、刻蚀等工艺来制作写晶体管，加工简单，容易实现。在已完成集成去耦合电容的读晶体管的基础上，继续制作本实施方式提供的写晶体管，可以得到GAA+集成去耦合电容的CAA结构的存储器。
本申请实施例又一方面还提供一种存储器的制作方法，该制作方法包括：
在衬底上沉积第一金属层，刻蚀第一金属层形成第一极；
依次沉积第一绝缘层和第二金属层，刻蚀第二金属层形成第二极；
刻蚀第二金属层、第一绝缘层及部分厚度的第一金属层，形成垂直方向的第一沟道；
依次沉积第一半导体层、第一栅介质层和第一栅金属层；
刻蚀第一栅金属层，形成第一栅极，第一栅极包括位于第一沟道内的第一栅金属柱和位于第一栅金属柱上方的第一栅基底层；
依次沉积第一隔离层、耦合金属层和第二隔离层；
刻蚀第二隔离层、耦合金属层和第一隔离层，形成连接槽，连接槽位于第一栅金属柱的上方；
沉积电容介质层，电容介质层覆盖连接槽的侧壁；
沉积第三金属层，刻蚀第三金属层形成连接金属，连接金属包括位于连接槽内的连接金属柱和位于连接金属柱上方的连接金属层。
上述制作方法可以实现对CAA结构的读晶体管和去耦合电容的制作，在读晶体管制作完成后，继续制作耦合金属层等结构，使去耦合电容形成在读晶体管的上方，整体上，加工简单，容易实现，产品良率更高。
在一种可能的实施方式中，存储器的制作方法还包括：
沉积第四金属层，刻蚀第四金属层形成第三极；
依次沉积第二绝缘层和第五金属层，刻蚀第五金属层形成第四极；
刻蚀第五金属层、第二绝缘层和部分厚度的第四金属层，形成垂直方向的第二沟道；
依次沉积第二半导体层、第二栅介质层和第二栅金属层；
刻蚀第二栅金属层，形成第二栅极，第二栅极包括第二栅基底层和位于第二沟道内的第二栅金属柱。
上述制作方法可以实现对CAA结构的写晶体管的制作，采用沉积、刻蚀等工艺来制作写晶体管，加工简单，容易实现。在已完成读晶体管和去耦合电容的基础上，继续制作本实施方式提供的写晶体管，可以得到CAA+去耦合电容+CAA结构的存储器。
在一种可能的实施方式中，存储器的制作方法还包括：
沉积第四金属层，刻蚀第四金属层形成第三极；
沉积第二绝缘层和第二栅金属层，刻蚀第二栅金属层形成第二栅极；
刻蚀第二栅金属层和第二绝缘层，形成垂直方向的第二沟道；
沉积第二栅介质层，第二栅介质层覆盖第二沟道的侧壁；
沉积第二半导体层，第二半导体层填充在第二沟道内；
沉积第五金属层，刻蚀第五金属层形成第四极。
上述制作方法可以实现对GAA结构的写晶体管的制作，采用沉积、刻蚀等工艺来制作写晶体管，加工简单，容易实现。在已完成读晶体管和去耦合电容的基础上，继续制作本实施方式提供的写晶体管，可以得到GAA+去耦合电容+CAA结构的存储器。
本申请实施例提供的存储器和存储器的制作方法，通过增加去耦合电容，来增加存储节点的总电容，以延长电荷保持时间，同时，由于新增的去耦合电容大于栅源、栅漏电容，可以大大减小写字节线和读字节线对存储节点的耦合影响，避免电压耦合影响存储器的正常运行。本申请实施例提供的存储器将写晶体管和读晶体管沿第一方向布置，第一方向例如可以为垂直方向，使得在为存储单元引入去耦合电容的同时不增大水平方向的集成度，不增大器件的面积，不会带来存储器密度的损失。并且，采用沉积、刻蚀等工艺的组合，可以实现不同结构的存储器的制作，整体制作工艺难度较低，良品率高。
附图说明
图1为相关技术提供的存储器的电路图；
图2为相关技术提供的存储器运行过程中存储节点的电位变化图；
图3为本申请一实施例提供的存储器的电路图；
图4为本申请一实施例提供的存储单元的结构示意图；
图5为本申请一实施例提供的存储单元的另一种结构示意图；
图6为本申请一实施例提供的存储单元的又一种结构示意图；
图7为本申请一实施例提供的存储单元的再一种结构示意图；
图8为本申请一实施例提供的存储器的阵列结构示意图；
图9为本申请一实施例提供的存储器单元的部分制备工艺流程图；
图10a-图10h为本申请一实施例提供的存储器单元的部分制备过程的结构示意图；
图11为本申请一实施例提供的写晶体管的制备工艺流程图；
图12a-图12d为本申请一实施例提供的写晶体管的制备过程的结构示意图；
图13为本申请一实施例提供的写晶体管的另一种制备工艺流程图；
图14a-图14e为本申请一实施例提供的另一种写晶体管的制备过程的结构示意图；
图15为本申请一实施例提供的存储器单元的另一种制备工艺的部分流程图；
图16a-图16h为本申请一实施例提供的存储器单元的另一种制备过程的部分结构示意图；
图17a为相关技术提供的存储器的电容值仿真图；
图17b为本申请一实施例提供的存储器的电容值仿真图；
图18a为相关技术提供的存储器的存储节点的耦合电压示意图；
图18b为本申请一实施例提供的存储器的存储节点的耦合电压示意图；
图19a为相关技术提供的存储器的电荷保持时间示意图；
图19b为本申请一实施例提供的存储器的电荷保持时间示意图。
具体实施方式
存储器(Memory)是现代信息技术中用于保存信息的记忆设备，存储器的主要功能是存储程序和各种数据，并能在计算机运行过程中高速、自动地完成程序或数据的存取。随着摩尔定律的发展，处理器和存储器之间的鸿沟越来越大，微处理器的增长速度远远超过了存储器的增长速度，最终导致存储器的存储密度及读写速度跟不上处理器的运算速度， 从而出现“存储墙”，最终影响计算机系统的整体性能。
传统的静态随机存储器(Static Random-Access Memory，SRAM)的面积大、功耗大，随着计算机技术以及片上系统的发展，存储器逐渐向着高密度、低功耗的方向发展，嵌入式动态随机存储器(enhanced dynamic random access memory，eDRAM)，eDRAM的读取速度可低至纳秒级，且其占用面积仅为SRAM存储器的三分之一，具有高速读写以及高密度集成的优点。
图1为相关技术提供的存储器的电路图。参考图1所示，相关技术提供一种存储器，包括写字节线101、写比特线102、读字节线103、读比特线104、写晶体管110和读晶体管120。读晶体管120包括第一栅极121、第一极123和第二极122，其中第一极123为源极，第二极122为漏极，或者第一极123为漏极，第二极122为源极。写晶体管110包括第二栅极111、第三极113和第四极112，其中第三极113为源极，第四极112为漏极，或者第三极113为漏极，第四极112为源极。第二栅极111连接写字节线101，第四极112连接写比特线102，第二极122连接读字节线103，第一极123连接读比特线104，第三极113和第一栅极121连接形成存储节点105。
该存储器的工作原理为，在“写”的操作中，通过写字节线101控制写晶体管110的开启，将写比特线102的电位传递到读晶体管120的第一栅极121，使得第一栅极121的电位与写比特线102同步以实现“0”和“1”的写入；然后，写字节线101控制写晶体管110关闭。在“读”的操作中，只需要根据读晶体管120的电流的高低来判断存储状态即可。
上述相关技术提供的存储器中，由于晶体管的栅源、栅漏电容较小，导致电荷保持时间有限；并且，在实际工作过程中，存储节点105与写字节线101、读字节线103和读比特线104之间都会存在较大的寄生电容，从而影响器件的正常运行。
图2为相关技术提供的存储器运行过程中存储节点的电位变化图。参考图2所示，存储节点105出现了两处电位降低D1和D2，其中D1为存储节点105与写字节线101出现电压耦合而导致，D2为存储节点105与读字节线103出现电压耦合而导致，从而可以得到，存储节点105与写字节线101、读字节线103会发生明显的电压耦合，导致存储节点105的电位抬高或者降低，误读风险增大。
基于上述问题，本申请实施例提供一种存储器，通过增加设置去耦合电容，来增加存储节点的总电容，以延长电荷保持时间，同时，由于新增的去耦合电容远大于栅源、栅漏电容，可以大大减小写字节线和读字节线对存储节点的耦合影响；并且，本申请实施例提供的存储器将写晶体管和读晶体管垂直布置，可以在引入电容的同时不增大水平方向的集成度，不增大器件的面积，不会带来存储器密度的损失。
以下，参考附图和具体的实施例，对本申请提供的存储器做具体的描述。
图3为本申请一实施例提供的存储器的电路图。参考图3所示，本申请实施例提供一种存储器，包括写字节线101、写比特线102、读字节线103、读比特线104、写晶体管110、读晶体管120和去耦合电容130。
读晶体管120可以包括第一栅极121、第一极123和第二极122，其中第二极122和第一极123可以分别为读晶体管120的源极和漏极，或者第二极122和第一极123可以分别为读晶体管120的漏极和源极。写晶体管110可以包括第二栅极111、第三极113和第四极112，第 四极112和第三极113可以分别为写晶体管110的源极和漏极，或者，第四极112和第三极113可以分别为写晶体管110的漏极和源极。
第二栅极111可以连接写字节线101，第四极112可以连接写比特线102，第二极122可以连接读字节线103，第一极123可以连接读比特线104，第三极113和第一栅极121可以连接形成存储节点105。去耦合电容130的一端可以连接至存储节点105，另一端可以连接至预设电位。
需要说明的是，预设电位可以为固定电位，例如GND(接地端)或者固定的某一电位值，预设电位也可以为非固定电位，以根据电路需要调节该预设电位处于低电位或者高电位，从而可以调节去耦合电容130的大小。
本申请实施例通过在存储节点105处并联一个去耦合电容130，一方面，可以用来增加存储节点105的总电容，以延长电荷保持时间；另一方面，去耦合电容130的电容值远大于栅源、栅漏电容，可以大大减小写字节线101和读字节线103对存储节点105的耦合影响，避免电压耦合影响存储器的正常运行。
本申请实施例中，写晶体管110和读晶体管120可以采用薄膜晶体管(Thin film transistor，TFT)，读晶体管120的第一栅极121的电位由存储节点105的电荷量决定，由于TFT的漏电比传统的硅晶体管低很多，读晶体管120的第一栅极121上的电荷通过写晶体管110的泄露将会大幅度降低，从而可以提高存储器的存储时长。
另外，写晶体管110和读晶体管120可以在第一方向上依次排布，第一方向可以定义为垂直方向，此时，去耦合电容130可以设置在写晶体管110和读晶体管120之间，从而不增大水平方向的集成度，不增大器件的面积，不会带来存储器密度的损失。
读晶体管120可以包括沿第一方向延伸的第一沟道，写晶体管110可以包括沿第一方向延伸的第二沟道。对于具有垂直沟道的写晶体管110和读晶体管120来说，将写晶体管110和读晶体管120垂直布置，有利于形成紧凑的存储器结构。
垂直布置的一个写晶体管110和一个读晶体管120可以构成一个存储器单元，对于一个存储器单元，其整体可以为柱状结构。写晶体管110和读晶体管120的具体结构具有多种实现方式，例如可以为GAA(Gate All Around)结构或者CAA(Channel All Around)结构。
为了便于描述，可以定义以下图中的垂直方向为第一方向，以下图中的水平面为垂直于第一方向的平面。
图4为本申请一实施例提供的存储单元的结构示意图。参考图4所示，在一种可能的实施方式中，读晶体管120可以为CAA结构。读晶体管120可以包括第一半导体层124，第一半导体层124具有第一沟道(图中未标记)，该第一沟道即读晶体管120的垂直沟道，第一沟道可以为长方体结构、圆柱体结构或者其它柱状结构。
第一栅极121可以包括第一栅基底层1211和第一栅金属柱1212，第一栅金属柱1212位于第一沟道内，第一栅基底层1211连接在第一栅金属柱1212的靠近写晶体管110的一侧，第一栅基底层1211在水平面内延伸；第一栅极121和第一半导体层124之间设置有第一栅介质层125，第一极123和第二极122均与第一半导体层124连接，第一极123和第二极122均在水平面内延伸，第二极122位于第一极123和第一栅基底层1211之间，第二极122和第一极123之间设置有第一绝缘层126。
在一种可能的实施方式中，写晶体管110也可以为CAA结构。写晶体管110可以包括第 二半导体层114，第二半导体层114具有第二沟道(图中未标记)，该第二沟道即写晶体管110的垂直沟道，第二沟道可以为长方体结构、圆柱体结构或者其它柱状结构。
第二栅极111可以包括第二栅基底层1111和第二栅金属柱1112，第二栅金属柱1112位于第二沟道内，第二栅基底层1111连接在第二栅金属柱1112的远离读晶体管120的一侧，第二栅基底层1111在水平面内延伸。第二栅极111和第二半导体层114之间设置有第二栅介质层115，第四极112和第三极113均和第二半导体层114连接，第四极112和第三极113均在水平面内延伸，第四极112位于第三极113和第二栅基底层1111之间，第四极112和第三极113之间设置有第二绝缘层116。
对于本申请实施例提供的存储单元，去耦合电容130的其中一个电容极板可以为耦合金属层131，去耦合电容130的另一个电容极板可以为第一栅极121，耦合金属层131可以连接至预设电位。
耦合金属层131可以在水平面内延伸，耦合金属层131可以设置在第一栅基底层1211的背向写晶体管110的一侧，耦合金属层131可以环绕在第一栅金属柱1212的周围，耦合金属层131的面向第一栅基底层1211的一侧、背向第一栅基底层1211的一侧、面向第一栅金属柱1212的一侧均设置有电容介质层132。
通过将耦合金属层131设置在读晶体管120的第一栅金属柱1212的周围，使耦合金属层131和第一栅极121构成去耦合电容130，可以形成紧凑的存储单元结构，不增加水平方向的集成度。
图5为本申请一实施例提供的存储单元的另一种结构示意图。参考图5所示，在另一种可能的实施方式中，写晶体管110可以为GAA结构。写晶体管110可以包括第二半导体层114，第二半导体层114沿第一方向延伸构成第二沟道，第二沟道可以为长方体结构、圆柱体结构或者其它柱状结构。
第四极112可以连接在第二半导体层114的远离读晶体管120的一端，第三极113可以连接在第二半导体层114的靠近读晶体管120的一端，第二栅极111可以位于第四极112和第三极113之间，第二栅极111环绕第二半导体层114设置，第四极112、第三极113、第二栅极111均可以在水平面内延伸，第二栅极111和第二半导体层114之间设置有第二栅介质层115，第二栅极111和第三极113之间设置有第二绝缘层117，第二栅极111和第四极112之间设置有第三绝缘层116。
图5提供的实施例中，读晶体管120可以为CAA结构，其具体结构可以参考图4中写晶体管110的描述，在此不再赘述。
对于本申请实施例提供的存储单元，去耦合电容130的其中一个电容极板为耦合金属层131，去耦合电容130的另一个电容极板可以为连接第三极113和第一栅极121的连接金属133。
连接金属133可以包括连接金属层1331和连接金属柱1332，连接金属柱1332沿第一方向延伸，连接金属层1331在水平面内延伸，连接金属层1331连接在第三极113的面向读晶体管120的一侧，连接金属柱1332连接在连接金属层1331和第一栅极121之间。
耦合金属层131可以设置在连接金属层1331和第一栅极121之间，耦合金属层131可以环绕在连接金属柱1332的周围，耦合金属层131和第一栅极121之间设置有第一隔离层135，耦合金属层131和连接金属层1331之间设置有第二隔离层134，耦合金属层131和连接金属 柱1332之间设置有电容介质层132。
通过将耦合金属层131设置在连接第三极113和第一栅极121的连接金属133的周围，使耦合金属层131和连接金属133构成去耦合电容130，同样可以形成紧凑的存储单元结构，不增加水平方向的集成度。
图6为本申请一实施例提供的存储单元的又一种结构示意图。参考图6所示，在另一种可能的实施方式中，写晶体管110和读晶体管120均可以设置为CAA结构，去耦合电容130可以由耦合金属层131和连接金属层1331构成，其中写晶体管110和读晶体管120的具体结构可以参照图4所示的描述，去耦合电容130的结构可以参照图5所示的描述，在此不再赘述。
图7为本申请一实施例提供的存储单元的再一种结构示意图。参考图7所示，在另一种可能的实施方式中，写晶体管110可以设置为GAA结构，读晶体管120可以设置为CAA结构，去耦合电容130的两个电容极板可以分别由耦合金属层131和第一栅极121构成，其中写晶体管110和读晶体管120的具体结构可以参照图5所示的描述，去耦合电容130的结构可以参照图4所示的描述，在此不再赘述。
图4-图7共示出了存储单元四种不同的实施方式，应理解，去耦合电容130的其中一个电容极板为耦合金属层131，另一个电容极板可以为第一栅极121或连接金属133，由于第三极113、第一栅极121、连接金属133互相连通，各处的电位一致，因此这四种不同的实施方式可以等效为同一个电路，即图3所示的电路。
图8为本申请一实施例提供的存储器的阵列结构示意图。参考图8所示，存储器可以包括多个存储单元，每个存储单元的写晶体管110和读晶体管120可以沿第一方向(Z方向)排布，多个存储单元在垂直于第一方向的平面(XY平面)上呈阵列排布，写字节线101、写比特线102、读字节线103、读比特线104分别在不同的XY平面上延伸。
示例性地，图8提供的存储器阵列结构，由9个存储单元在XY平面上紧密集成，形成3*3阵列，每个存储单元占用的面积可以为4F 2。应理解，通过在X方向或Y方向上增加存储单元的个数，可以实现更大规模的存储器阵列结构。应理解，通过在Z方向上堆叠存储单元，同样可以增大存储器阵列的规模。
在一种可能的实施方式中，写字节线101可以沿第二方向(Y方向)延伸，多条写字节线101在第三方向(X方向)上间隔排布，第二方向和第三方向所在的平面垂直于第一方向，且第二方向和第三方向互相垂直，写比特线102沿第三方向延伸且多条写比特线102在第二方向上间隔排布，在第二方向上间隔排布的多个写晶体管110的第二栅极111连接至同一写字节线101，在第三方向上间隔排布的多个写晶体管110的第四极112连接至同一写比特线102。
读字节线103可以沿第三方向延伸，多条读字节线103在第二方向上间隔排布，读比特线104可以沿第二方向延伸且多条读比特线104在第三方向上间隔排布，在第三方向上间隔排布的多个读晶体管120的第二极122连接至同一读字节线103，在第二方向上间隔排布的多个读晶体管120的第一极123连接至同一读比特线104。
将多个存储单元阵列排布，则同一条写字节线101可以控制在Y方向上排布的多个写晶体管110开启，可以将在Y方向上间隔排布的多条写比特线102的电位传递到各自对应的读晶体管120的第一栅极121上，以实现“0”和“1”的批量写入，提高存储器的读写效率。
此外，多个存储单元内的耦合金属层131可以连接为一个整体，且耦合金属层131可以连接至预设电位。耦合金属层131共享一个平面，一方面可以使耦合金属层131制作简单，另一方面，便于将各个存储单元内的耦合金属层131同时连接至预设电位。
上述本申请实施例中，对于写晶体管110和读晶体管120中各个结构的材料不做具体限制。其中，第一栅极121、第二栅极111的材料可以为金属材料或导电性材料，例如氮化钛TiN、钛Ti、金Au、钨W、钼Mo、氧化铟锡In-Ti-O(ITO)、氧化铟锌In-Zn-O(IZO)、铝Al、铜Cu、钌Ru、银Ag、铂Pt等材料或者它们的任意组合。
第一极123、第二极122、第三极113、第四极112的材料可以为金属材料或其他导电性材料，例如氮化钛TiN、钛Ti、金Au、钨W、钼Mo、氧化铟锡In-Ti-O(ITO)、氧化铟锌In-Zn-O(IZO)、铝Al、铜Cu、钌Ru、银Ag、铂Pt等材料或者它们的任意组合。各个栅极、源极、漏极、耦合金属层131、连接金属133的材料可以相同也可以不同。第一半导体层124和第二半导体层114的材料可以为半导体材料，例如硅Si、多晶硅poly-Si、非晶硅amorphous-Si等硅基半导体，或者氧化铟In2O3、氧化锌ZnO、氧化钙Ga2O3、氧化铟锡ITO、二氧化钛TiO2等金属氧化物，或者铟镓锌氧化物In-Ga-Zn-O(IGZO)、铟镓锡氧化物In-Sn-Zn-O(ISZO)等多元化合物，石墨烯、二硫化钼MoS2、黑磷等二维半导体材料或者它们的任意组合。
另外，第一栅介质层125和第二栅介质层115可以为绝缘材料，例如氧化硅SiOx、氮化硅SiNx、氧化铝Al2O3、二氧化铪HfO2、二氧化锆ZrO2、二氧化钛TiO2、氧化钇Y2O3等材料或者它们的组合材料、叠层材料、组合叠层材料。
绝缘层和电容介质层的材料可以相同也可以不同。绝缘层116、117、126以及隔离层134、135可以为绝缘材料，例如氧化硅SiO2、四氮化三硅Si3N4、氧化铝Al2O3、二氧化铪HfO2等材料。电容介质层132可以为绝缘材料，例如氧化硅SiOx、氮化硅SiNx、氧化铝Al2O3、二氧化铪HfO2、二氧化锆ZrO2、二氧化钛TiO2、氧化钇Y2O3等或者它们的组合材料、叠层材料、组合叠层材料。
应理解，第四极112、第三极113分别与第二半导体层114形成欧姆接触，第二极122、第一极123分别与第一半导体层124形成欧姆接触，为了避免源漏金属层在与半导体层接触区域发生扩散，降低接触的费米钉扎效应，可以在源漏金属层与半导体层接触的界面处引入一层约0.1nm-2nm的绝缘层，形成半导体层-绝缘层-源漏金属层结构。
另外，写字节线101的材料可以与第二栅极111的材料相同，写比特线102的材料可以与第四极112的材料相同，读字节线103的材料可以与第二极122的材料相同，读比特线104的材料可以与第一极123的材料相同。
以下，参考附图和具体的实施例，对本申请提供的存储器的制作方法做具体的描述。
图9为本申请一实施例提供的存储器单元的部分制备工艺流程图，图10a-图10h为本申请一实施例提供的存储器单元的部分制备过程的结构示意图。需要注意的是，图9所示的制作工艺流程以及图10a-图10h制备的为存储器单元的部分结构，对应图4和图7中的存储器单元的下半部分结构，即读晶体管120和去耦合电容130的结构。
为了便于附图理解，以下存储器制备过程的结构示意图中以两个存储器单元为例，例如图10a-图10h中以两个读晶体管120为例，实际上应理解存储器单元呈阵列排布。
参考图9所示，存储器单元的制作方法可以包括以下步骤：
S101、在衬底上沉积第一金属层，刻蚀第一金属层形成第一极123。
S102、沉积第一绝缘层126和第二金属层，刻蚀第二金属层形成第二极122。
其中，第一金属层沉积在衬底(图中未示出)上，通过选择性刻蚀第一金属层可以形成第一极123，通过选择性刻蚀第二金属层可以形成第二极122。应理解，同一层第一金属层刻蚀后可以形成多个呈阵列排布且互相分隔开的第一极123，同一层第二金属层刻蚀后可以形成多个呈阵列排布且互相分隔开的第二极122。
S103、沉积牺牲层141，得到图10a所示的结构，然后刻蚀牺牲层141、第二金属层(第二极122)、第一绝缘层126及部分厚度的第一金属层(第一极123)，形成垂直方向的第一沟道142，得到图10b所示的结构。应理解，第一沟道142可以呈阵列排布，每个第一沟道142和每个第一极123、第二极122对应设置。
S104、依次沉积第一半导体层124、第一栅介质层125和第一栅金属层1210，得到图10c所示的结构。
S105、刻蚀第一栅金属层1210、第一栅介质层125和第一半导体层124，形成第一栅极121，第一栅极121包括位于第一沟道142内的第一栅金属柱1212和位于第一栅金属柱1212上方的第一栅基底层1211，可参考图10d所示的结构。应理解，相邻两个第一栅极121被第一凹槽143分隔开。
S106、刻蚀去除牺牲层141，得到图10e所示的结构。
S107、刻蚀去除位于第一栅基底层1211和第二金属层(第二极122)之间的第一半导体层124和第一栅介质层125，得到图10f所示的结构。
S108、依次沉积电容介质层132和耦合金属层131，电容介质层132覆盖第一栅极121的周围以及第二金属层(第二极122)的上表面，耦合金属层131环绕第一栅金属柱1212，可参考图10g所示的结构。
S109、刻蚀去除位于第一栅基底层1211侧面的电容介质层132，得到图10h所示的结构。
其中，S102和S104中可以采用干法选择性刻蚀，S103和S107中可以采用原子层淀积ALD工艺，S105和S108中可以采用湿法刻蚀。
上述S01-S109完成了图4和图5所示的存储器中下半部分结构(读晶体管120及去耦合电容130)的制作，在此基础上，可以继续进行写晶体管110的制作。
图11为本申请一实施例提供的写晶体管的制备工艺流程图，图12a-图12d为本申请一实施例提供的写晶体管的制备过程的结构示意图。需要注意的是，图11所示的制作工艺流程以及图12a-图12d制备的写晶体管，对应图4和图6中的写晶体管的结构。
参考图11所示，本申请一实施例提供的写晶体管的制备工艺可以包括以下步骤：
S201、沉积第三金属层，刻蚀第三金属层形成第三极113；
S202、沉积第二绝缘层116和第四金属层，刻蚀第四金属层形成第四极112，得到图12a所示的结构。
S203、刻蚀第四金属层(第四极112)、第二绝缘层116和部分厚度的第三金属层(第三极113)，形成垂直方向的第二沟道144，得到图12b所示的结构。
S204、依次沉积第二半导体层114、第二栅介质层115和第二栅金属层1110，得到图12c所示的结构。
S205、刻蚀第二栅金属层1110，形成第二栅极111，第二栅极111包括第二栅基底层1111 和位于第二沟道144内的第二栅金属柱1112，可参考图12d所示的结构。应理解，相邻的两个第二栅极111被第二凹槽145分隔开。
图13为本申请一实施例提供的写晶体管的另一种制备工艺流程图，图14a-图14e为本申请一实施例提供的另一种写晶体管的制备过程的结构示意图。需要注意的是，图13所示的制作工艺流程以及图14a-图14e制备的写晶体管，对应图5和图7中的写晶体管的结构。
参考图13所示，本申请一实施例提供的写晶体管的制备工艺可以包括以下步骤：
S301、沉积第三金属层，刻蚀第三金属层形成第三极113；
S302、沉积第二绝缘层116和第二栅金属层，刻蚀第二栅金属层形成第二栅极111，得到图14a所示的结构。
S303、刻蚀第二栅金属层(第二栅极111)和第二绝缘层116，形成垂直方向的第二沟道144，得到图14b所示的结构。
S304、沉积第二栅介质层层115，第二栅介质层115覆盖第二沟道144的侧壁，得到图14c所示的结构。
S305、沉积第二半导体层114，第二半导体层114填充在第二沟道144内，得到图14d所示的结构。
S305、沉积第四金属层，刻蚀第四金属层形成第四极112，得到图14e所示的结构。
图15为本申请一实施例提供的存储器单元的另一种制备工艺的部分流程图，图16a-图16h为本申请一实施例提供的存储器单元的另一种制备过程的部分结构示意图。需要注意的是，图15所示的制作工艺流程以及图16a-图16h制备的为存储器单元的部分结构，对应图5和图6中的存储器单元的下半部分结构，即读晶体管120和去耦合电容130的结构。
参考图15所示，存储器单元的制作方法可以包括以下步骤：
S401、在衬底上沉积第一金属层并通过刻蚀形成第一极123；
S402、依次沉积第一绝缘层126和第二金属层，刻蚀第二金属层形成第二极122，得到图16a所示的结构。
S403、刻蚀第二金属层(第二极122)、第一绝缘层126及部分厚度的第一金属层(第一极123)，形成垂直方向的第一沟道142，得到图16b所示的结构。
S404、依次沉积第一半导体层124、第一栅介质层125和第一栅金属层1210，得到图16c所示的结构。
S405、刻蚀第一栅金属层1210，形成第一栅极121，第一栅极121包括位于第一沟道142内的第一栅金属柱1212和位于第一栅金属柱1212上方的第一栅基底层1211，可参考图16d所示的结构。应理解，相邻的两个第一栅极121被第一凹槽143分隔开。
S406、依次沉积第一隔离层135、耦合金属层131和第二隔离层134，得到图16e所示的结构。
S407、刻蚀第二隔离层135、耦合金属层131和第一隔离层134，形成连接槽146，连接槽146位于第一栅金属柱1212的上方，可参考图16f所示的结构。
S408、沉积电容介质层132，电容介质层132覆盖连接槽146的侧壁，可参考图16g所示的结构。
S409、沉积第三金属层，刻蚀第三金属层形成连接金属133，连接金属133包括位于连接槽内146的连接金属柱1332和位于第二隔离层134上方的连接金属层1331，可参考 图16h所示的结构。
应理解，在图9所示的制作方法的基础上，继续进行图11所示的制作方法，可以得到图4所示的存储器；在图9所示的制作方法的基础上，继续进行图13所示的制作方法，可以得到图7所示的存储器。在图15所示的制作方法的基础上，继续进行图11所示的制作方法，可以得到图6所示的存储器；在图15所示的制作方法的基础上，继续进行图13所示的制作方法，可以得到图5所示的存储器，对于在图15所示的制作方法的基础上，继续制作写晶体管的具体制作步骤，可参考前述，在此不再赘述。
图17a为相关技术提供的存储器的电容值仿真图，图17b为本申请一实施例提供的存储器的电容值仿真图，其中，C1代表栅漏电容，C2代表栅源电容，C3代表增加的电容。参考图17a和图17b所示，相关技术提供的存储器，栅源电容为1.2e-16F，栅漏电容为5e-17F，而本申请实施例提供的存储器，增加的电容为2.5e-16F，增加的电容Cgb是栅源电容Cgs及栅漏电容Cgd的2～5倍。
图18a为相关技术提供的存储器的存储节点的耦合电压示意图，图18b为本申请一实施例提供的存储器的存储节点的耦合电压示意图，其中，D1代表WWL的电压，D2代表SN电压。参考图18a和图18b所示，相关技术提供的存储器，在WWL的电压从1.5V降至-2V时，电容耦合导致的SN电压降低分别为992mV和703mV，而本申请实施例提供的存储器，在WWL的电压从1.5V降至-2V时，电容耦合导致的SN电压降低分别为213mV和158mV。因此，本申请实施例提供的存储器，电容耦合导致的SN电压降低与相关技术提供的结构相比减小至其22％左右。
图19a为相关技术提供的存储器的电荷保持时间示意图，图19b为本申请一实施例提供的存储器的电荷保持时间示意图。参考图19a和图19b所示，相关技术提供的存储器，电压从1V降至0.8V所用的时间为0.7s，即电荷保持时间为0.7s，而本申请实施例提供的存储器，电压从1V降至0.8V所用的时间为6.8s，即电荷保持时间为6.8s。因此，相比于相关技术，本申请实施例提供的存储器的保持时间可以增加近十倍。
综上所述，本申请实施例提供的存储器，通过增加去耦合电容，可以增加存储节点的总电容，延长电荷保持时间，同时，由于去耦合电容远大于栅源、栅漏电容，可以大大减小写字节线和读字节线对存储节点的耦合影响；并且，本申请实施例提供的存储器将写晶体管和读晶体管垂直布置，可以在引入电容的同时不增大水平方向的集成度，不增大器件的面积，不会带来存储器密度的损失。
最后应说明的是：以上各实施例仅用以说明本申请实施例的技术方案，而非对其限制；尽管参照前述各实施例对本申请实施例进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (18)

  1. 一种存储器，其特征在于，包括写字节线、写比特线、读字节线、读比特线以及存储单元；
    所述存储单元包括在第一方向上依次排布的写晶体管和读晶体管；
    所述读晶体管包括第一栅极、第一极和第二极，其中，所述第一极为源极，所述第二极为漏极，或者，所述第一极为漏极，所述第二极为源极；
    所述写晶体管包括第二栅极、第三极和第四极，其中，所述第三极为源极，所述第四极为漏极，或者所述第三极为漏极，所述第四极为源极；
    所述第二栅极连接所述写字节线，所述第四极连接所述写比特线，所述第二极连接所述读字节线，所述第一极连接所述读比特线，所述第三极和所述第一栅极连接形成存储节点；
    所述存储单元还包括去耦合电容，所述去耦合电容的一端连接至所述存储节点，另一端连接至预设电位。
  2. 根据权利要求1所述的存储器，其特征在于，所述存储单元还包括耦合金属层，所述耦合金属层连接至所述预设电位，所述去耦合电容包括第一电容极板和第二电容极板，其中，所述第一电容极板为所述耦合金属层，所述第二电容极板为所述第一栅极，或者所述第二电容极板为连接所述第三极和所述第一栅极的连接金属。
  3. 根据权利要求2所述的存储器，其特征在于，所述读晶体管包括沿所述第一方向延伸的第一沟道，所述写晶体管包括沿所述第一方向延伸的第二沟道。
  4. 根据权利要求3所述的存储器，其特征在于，所述第一栅极包括第一栅基底层和第一栅金属柱，所述第一栅金属柱位于所述第一沟道内，所述第一沟道的底面和侧壁上设置有第一半导体层，且所述第一栅金属柱和所述第一半导体层之间设置有第一栅介质层，所述第一栅基底层连接在所述第一栅金属柱的靠近所述写晶体管的一侧，所述第一栅基底层在垂直于所述第一方向的平面内延伸；
    所述第二极和所述第一极均与所述第一半导体层连接，所述第二极和所述第一极均在垂直于所述第一方向的平面内延伸，所述第二极位于所述第一极和所述第一栅基底层之间，所述第二极和所述第一极之间设置有第一绝缘层。
  5. 根据权利要求4所述的存储器，其特征在于，所述第二栅极包括第二栅基底层和第二栅金属柱，所述第二栅金属柱位于所述第二沟道内，所述第二沟道的底面和侧壁上设置有第二半导体层，所述第二栅金属柱和所述第二半导体层之间设置有第二栅介质层，所述第二栅基底层连接在所述第二栅金属柱的远离所述读晶体管的一侧，所述第二栅基底层在垂直于所述第一方向的平面内延伸；
    所述第三极和所述第四极均与所述第二半导体层连接，所述第四极位于所述第三极和所述第二栅基底层之间，所述第三极和所述第四极均在垂直于所述第一方向的平面内延伸，所述第三极和所述第四极之间设置有第二绝缘层。
  6. 根据权利要求4所述的存储器，其特征在于，所述写晶体管包括第二半导体层，所述第二半导体层沿第一方向延伸构成所述第二沟道，所述第四极连接在所述第二半导体层的远离所述读晶体管的一端，所述第三极连接在所述第二半导体层的靠近所述读晶体管的一 端，所述第二栅极位于所述第三极和所述第四极之间，所述第三极、所述第四极、所述第二栅极均在垂直于所述第一方向的平面内延伸，所述第二栅极和所述第二半导体层之间设置有第二栅介质层，所述第二栅极和所述第三极之间设置有第二绝缘层，所述第二栅极和所述第四极之间设置有第三绝缘层。
  7. 根据权利要求4-6任一项所述的存储器，其特征在于，所述耦合金属层在垂直于所述第一方向的平面内延伸，所述耦合金属层设置在所述第一栅基底层的背向所述写晶体管的一侧，所述耦合金属层环绕在所述第一栅金属柱的周围，所述耦合金属层的面向所述第一栅基底层的一侧、背向所述第一栅基底层的一侧、面向所述第一栅金属柱的一侧均设置有电容介质层。
  8. 根据权利要求4-6任一项所述的存储器，其特征在于，所述连接金属包括连接金属层和连接金属柱，所述连接金属柱沿所述第一方向延伸，所述连接金属层在垂直于所述第一方向的平面内延伸，所述连接金属层连接在所述第三极的面向所述读晶体管的一侧，所述连接金属柱连接在所述连接金属层和所述第一栅极之间，所述耦合金属层设置在所述连接金属层和所述第一栅极之间，所述耦合金属层环绕在所述连接金属柱的周围，所述耦合金属层和所述第一栅极之间设置有第一隔离层，所述耦合金属层和所述连接金属层之间设置有第二隔离层，所述耦合金属层和所述连接金属柱之间设置有电容介质层。
  9. 根据权利要求2-8任一项所述的存储器，其特征在于，所述存储器包括多个所述存储单元，多个所述存储单元在垂直于所述第一方向的平面上呈阵列排布，所述写字节线、所述写比特线、所述读字节线、所述读比特线分别在垂直于所述第一方向的不同平面上延伸。
  10. 根据权利要求9所述的存储器，其特征在于，多个所述存储单元内的所述耦合金属层连接为一个整体，所述耦合金属层连接至所述预设电位。
  11. 根据权利要求9所述的存储器，其特征在于，所述写字节线沿第二方向延伸，多条所述写字节线在第三方向上间隔排布，所述第二方向和所述第三方向所在的平面垂直于所述第一方向，且所述第二方向和所述第三方向互相垂直，所述写比特线沿所述第三方向延伸，多条所述写比特线在所述第二方向上间隔排布，在所述第二方向上间隔排布的多个所述写晶体管的所述第二栅极连接至同一所述写字节线，在上述第三方向上间隔排布的多个所述写晶体管的所述第四极连接至同一所述写比特线；
    所述读字节线沿所述第三方向延伸且多条所述读字节线在所述第二方向上间隔排布，所述读比特线沿所述第二方向延伸且多条所述读比特线在所述第三方向上间隔排布，在所述第三方向上间隔排布的多个所述读晶体管的所述第二极连接至同一所述读字节线，在所述第二方向上间隔排布的多个所述读晶体管的所述第一极连接至同一所述读比特线。
  12. 根据权利要求1-11任一项所述的存储器，其特征在于，所述预设电位为接地端。
  13. 一种存储器的制作方法，其特征在于，包括：
    在衬底上沉积第一金属层，刻蚀所述第一金属层形成第一极；
    依次沉积第一绝缘层和第二金属层，刻蚀所述第二金属层形成第二极；
    沉积牺牲层，刻蚀所述牺牲层、所述第二金属层、所述第一绝缘层及部分厚度的所述第一金属层，形成垂直方向的第一沟道；
    依次沉积第一半导体层、第一栅介质层和第一栅金属层；
    刻蚀所述第一栅金属层、所述第一栅介质层和所述第一半导体层，形成第一栅极，所 述第一栅极包括位于所述第一沟道内的第一栅金属柱和位于所述第一栅金属柱上方的第一栅基底层；
    刻蚀去除所述牺牲层；
    刻蚀去除位于所述第一栅基底层和所述第二金属层之间的所述第一半导体层和所述第一栅介质层；
    依次沉积电容介质层和耦合金属层，所述电容介质层覆盖所述第一栅极的周围以及所述第二金属层的上表面，所述耦合金属层环绕所述第一栅金属柱；
    刻蚀去除位于所述第一栅基底层侧面的所述电容介质层。
  14. 根据权利要求13所述的制作方法，其特征在于，还包括：
    沉积第三金属层，刻蚀所述第三金属层形成第三极；
    沉积第二绝缘层和第四金属层，刻蚀所述第四金属层形成第四极；
    刻蚀所述第四金属层、所述第二绝缘层和部分厚度的所述第三金属层，形成垂直方向的第二沟道；
    依次沉积第二半导体层、第二栅介质层和第二栅金属层；
    刻蚀所述第二栅金属层，形成第二栅极，所述第二栅极包括第二栅基底层和位于所述第二沟道内的第二栅金属柱。
  15. 根据权利要求13所述的制作方法，其特征在于，还包括：
    沉积第三金属层，刻蚀所述第三金属层形成第三极；
    沉积第三绝缘层和第二栅金属层，刻蚀所述第二栅金属层形成第二栅极；
    沉积第四绝缘层，刻蚀所述第四绝缘层、所述第二栅金属层和所述第三绝缘层，形成垂直方向的第二沟道；
    沉积第二栅介质层，所述第二栅介质层覆盖所述第二沟道的侧壁；
    沉积第二半导体层，所述第二半导体层填充在所述第二沟道内；
    沉积第四金属层，刻蚀所述第四金属层形成第四极。
  16. 一种存储器的制作方法，其特征在于，包括：
    在衬底上沉积第一金属层，刻蚀所述第一金属层形成第一极；
    依次沉积第一绝缘层和第二金属层，刻蚀所述第二金属层形成第二极；
    刻蚀所述第二金属层、所述第一绝缘层及部分厚度的所述第一金属层，形成垂直方向的第一沟道；
    依次沉积第一半导体层、第一栅介质层和第一栅金属层；
    刻蚀所述第一栅金属层，形成第一栅极，所述第一栅极包括位于所述第一沟道内的第一栅金属柱和位于所述第一栅金属柱上方的第一栅基底层；
    依次沉积第一隔离层、耦合金属层和第二隔离层；
    刻蚀所述第二隔离层、所述耦合金属层和所述第一隔离层，形成连接槽，所述连接槽位于所述第一栅金属柱的上方；
    沉积电容介质层，所述电容介质层覆盖所述连接槽的侧壁；
    沉积第三金属层，刻蚀所述第三金属层形成连接金属，所述连接金属包括位于所述连接槽内的连接金属柱和位于所述连接金属柱上方的连接金属层。
  17. 根据权利要求16所述的制作方法，其特征在于，还包括：
    沉积第四金属层，刻蚀所述第四金属层形成第三极；
    依次沉积第二绝缘层和第五金属层，刻蚀所述第五金属层形成第四极；
    刻蚀所述第五金属层、所述第二绝缘层和部分厚度的所述第四金属层，形成垂直方向的第二沟道；
    依次沉积第二半导体层、第二栅介质层和第二栅金属层；
    刻蚀所述第二栅金属层，形成第二栅极，所述第二栅极包括第二栅基底层和位于所述第二沟道内的第二栅金属柱。
  18. 根据权利要求16所述的制作方法，其特征在于，还包括：
    沉积第四金属层，刻蚀所述第四金属层形成第三极；
    沉积第二绝缘层和第二栅金属层，刻蚀所述第二栅金属层形成第二栅极；
    刻蚀所述第二栅金属层和所述第二绝缘层，形成垂直方向的第二沟道；
    沉积第二栅介质层，所述第二栅介质层覆盖所述第二沟道的侧壁；
    沉积第二半导体层，所述第二半导体层填充在所述第二沟道内；
    沉积第五金属层，刻蚀所述第五金属层形成第四极。
PCT/CN2021/136564 2021-12-08 2021-12-08 存储器和存储器的制作方法 WO2023102785A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202180037432.8A CN116583901A (zh) 2021-12-08 2021-12-08 存储器和存储器的制作方法
PCT/CN2021/136564 WO2023102785A1 (zh) 2021-12-08 2021-12-08 存储器和存储器的制作方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/136564 WO2023102785A1 (zh) 2021-12-08 2021-12-08 存储器和存储器的制作方法

Publications (1)

Publication Number Publication Date
WO2023102785A1 true WO2023102785A1 (zh) 2023-06-15

Family

ID=86729268

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/136564 WO2023102785A1 (zh) 2021-12-08 2021-12-08 存储器和存储器的制作方法

Country Status (2)

Country Link
CN (1) CN116583901A (zh)
WO (1) WO2023102785A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024103647A1 (zh) * 2022-11-15 2024-05-23 北京超弦存储器研究院 存储电路、存储单元、电子设备和数据读写方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001053164A (ja) * 1999-08-04 2001-02-23 Sony Corp 半導体記憶装置
CN110556377A (zh) * 2018-05-31 2019-12-10 英特尔公司 反铁电电容器存储器单元
CN111951848A (zh) * 2020-08-18 2020-11-17 上海交通大学 一种嵌入式动态随机存储器增益单元及其操作方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001053164A (ja) * 1999-08-04 2001-02-23 Sony Corp 半導体記憶装置
CN110556377A (zh) * 2018-05-31 2019-12-10 英特尔公司 反铁电电容器存储器单元
CN111951848A (zh) * 2020-08-18 2020-11-17 上海交通大学 一种嵌入式动态随机存储器增益单元及其操作方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024103647A1 (zh) * 2022-11-15 2024-05-23 北京超弦存储器研究院 存储电路、存储单元、电子设备和数据读写方法

Also Published As

Publication number Publication date
CN116583901A (zh) 2023-08-11

Similar Documents

Publication Publication Date Title
JP7150940B2 (ja) 半導体装置
WO2023184699A1 (zh) 半导体存储器件及其制造、读写方法、电子设备和存储电路
CN104576646B (zh) 一种集成电路芯片及其制造方法
WO2023184707A1 (zh) 存储器及其制作方法、电子设备
US11641732B2 (en) Self-aligned etch back for vertical three dimensional (3D) memory
US11532630B2 (en) Channel formation for vertical three dimensional (3D) memory
WO2023102785A1 (zh) 存储器和存储器的制作方法
WO2023272537A1 (zh) 存储器及其形成方法、电子设备
WO2024093178A1 (zh) 一种存储器、电子设备
WO2024066560A1 (zh) 一种存储阵列、存储器及电子设备
WO2023272536A1 (zh) 铁电存储器及其形成方法、电子设备
TWI828273B (zh) 記憶體元件及其製備方法
WO2024082403A1 (zh) 3d存储阵列及其制备方法、电子设备
US20240172450A1 (en) Ferroelectric memory and forming method thereof, and electronic device
WO2023197706A1 (zh) 一种场效应晶体管、存储器及电子设备
WO2024087380A1 (zh) 一种垂直环栅的晶体管、无电容存储器结构及其制备方法
JP7496861B2 (ja) 半導体装置
US11469230B2 (en) Vertically separated storage nodes and access devices for semiconductor devices
WO2024031438A1 (zh) 一种三维存储阵列、存储器及电子设备
WO2023221582A1 (zh) 存储阵列及存储阵列的制备方法
WO2024060021A1 (zh) 一种三维存储阵列、存储器及电子设备
WO2024113824A1 (zh) 一种存储阵列、存储器及电子设备
US11791260B2 (en) Contacts for twisted conductive lines within memory arrays
WO2024077910A1 (zh) 存储单元结构及其制备方法、读写电路及存储器
US20230081427A1 (en) Three-dimensional memory string array of thin-film ferroelectric transistors formed with an oxide semiconductor channel

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 202180037432.8

Country of ref document: CN