WO2024077910A1 - 存储单元结构及其制备方法、读写电路及存储器 - Google Patents

存储单元结构及其制备方法、读写电路及存储器 Download PDF

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Publication number
WO2024077910A1
WO2024077910A1 PCT/CN2023/088416 CN2023088416W WO2024077910A1 WO 2024077910 A1 WO2024077910 A1 WO 2024077910A1 CN 2023088416 W CN2023088416 W CN 2023088416W WO 2024077910 A1 WO2024077910 A1 WO 2024077910A1
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gate
layer
substrate
read
floating unit
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PCT/CN2023/088416
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English (en)
French (fr)
Inventor
唐怡
李渝
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长鑫存储技术有限公司
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Publication of WO2024077910A1 publication Critical patent/WO2024077910A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the technical field of integrated circuit design and manufacturing, and in particular to a storage unit structure and a preparation method thereof, a read-write circuit and a memory.
  • a storage cell is made of a single transistor and a single capacitor.
  • reading consumes the power of the capacitor, resulting in a reduced response speed. Even if reading is not performed, the charge may leak from the capacitor through the transistor, resulting in a reduced reliability of the semiconductor memory device. Therefore, the storage cell of a single transistor and a single capacitor needs to be refreshed regularly to maintain data, resulting in increased power consumption of the device.
  • the refresh circuit also occupies the volume of the storage cell, which hinders the miniaturization of the size of the dynamic random access memory.
  • a memory cell structure which includes a substrate, an isolation structure, a floating cell structure, a channel structure, a first gate structure and a second gate structure; the isolation structure is formed on the surface of the substrate; the floating cell structure is located on the surface of the isolation structure away from the substrate, extending along a first direction; the channel structure and the floating cell structure partially overlap and are insulated from each other, and the channel structure is configured as: including a first part located on the outer surface of the floating cell structure, and a second part and a third part located on opposite sides of the floating cell structure along a second direction, the second part and the third part are both electrically connected to the first part and are both located on the surface of the isolation structure away from the substrate, and the second direction intersects with the first direction; the first gate structure is located on the surface of the first part away from the substrate; the second gate structure is formed at one end of the floating cell structure along the first direction, and is insulated from the first gate structure.
  • the first part, the second part and the third part of the channel structure are an integrally formed structure prepared using the same process steps, and an insulating layer is provided between the first part of the channel structure and the floating unit structure.
  • the first gate structure includes a first gate dielectric layer and a first gate conductive layer; the first gate dielectric layer at least covers the outer surface of the channel structure; the first gate conductive layer is located on the surface of the first gate dielectric layer away from the substrate, and at least covers the surface of the first part of the floating unit structure away from the substrate.
  • the storage cell structure also includes a target protection structure, which covers the exposed outer surface of the floating cell structure and is configured as follows: the target protection structure includes a first oxide protection layer, a nitride protection layer and a second oxide protection layer, the first oxide protection layer is formed on the outer surface of the floating cell structure, the nitride protection layer is located on the surface of the first oxide protection layer away from the floating cell structure, and the second oxide protection layer is located on the surface of the nitride protection layer away from the floating cell structure, wherein the top surface of the second oxide protection layer is flush with the top surface of the first gate conductive layer.
  • the second gate structure includes a second gate conductive layer and a second gate dielectric layer; the second gate conductive layer and the first gate conductive layer are prepared in the same process step and are located at an end surface of the floating unit structure; the second gate dielectric layer is the portion of the second oxide protective layer located between the end surface and the second gate conductive layer.
  • the memory cell structure also includes a first gate electrode structure, a second gate electrode structure, a source electrode structure and a drain electrode structure; the first gate electrode structure is located on the top surface of the first gate conductive layer; the second gate electrode structure is located on the top surface of the second gate conductive layer; the source electrode structure is located on the top surface of the second part of the channel structure; and the drain electrode structure is located on the top surface of the third part of the channel structure.
  • the isolation structure includes a first oxide isolation layer, a nitride isolation layer and a second oxide isolation layer; the first oxide isolation layer is located on the surface of the substrate; the nitride isolation layer is located on the surface of the first oxide isolation layer away from the substrate; the second oxide isolation layer is located on the surface of the nitride isolation layer away from the substrate.
  • the material of the channel structure includes polysilicon, indium gallium zinc oxide, indium gallium arsenide, gallium nitride or a combination thereof; and the material of the floating unit structure includes doped polysilicon.
  • the present disclosure provides a read-write circuit, which includes a storage cell structure of any of the above embodiments, and is configured as follows: a first gate structure is electrically connected to a read word line; a second gate structure is electrically connected to a write word line; a second portion of the channel structure is electrically connected to a read bit line; a third portion of the channel structure is electrically connected to a write bit line; during a write state: the write word line is controlled to provide a first level signal to the second gate structure, so that the floating cell structure captures and stores electrons and is written to a first value; the write word line is controlled to provide a second level signal to the second gate structure, and the read word line is controlled to provide a third level signal to the first gate structure, so that the electrons stored in the floating cell structure are reset and are written to a second value, and the amplitude of the second level signal is smaller than the amplitude of the first level signal; during a read state: the read
  • a plurality of memory cell structures are arranged in multiple rows and columns, and are configured as follows: the memory cell structures located in the same row are all connected to the same read word line and the same write word line; the memory cell structures located in the same column are all connected to the same read bit line and the same write bit line; the memory cell structures in two adjacent rows are connected to different read word lines and different write word lines; and the memory cell structures in two adjacent columns are connected to different read bit lines and different write bit lines.
  • the first numerical value is “0” and the second numerical value is “1", thereby realizing the reading and writing functions of the read-write circuit for the numerical value "0" and the numerical value "1".
  • another aspect of the present disclosure provides a memory, the memory comprising the read/write circuit of any one of the above embodiments.
  • the read-write circuit includes the storage cell structure of any one of the above embodiments, the storage cell structure is configured as: the first gate structure is electrically connected to the read word line, the second gate structure is electrically connected to the write word line, the second part of the channel structure is electrically connected to the read bit line, and the third part of the channel structure is electrically connected to the write bit line;
  • the read-write control method includes: during the write state: controlling the write word line to provide a first level signal to the second gate structure, so that the floating cell structure captures and stores electrons and is written to the first value; or controlling the write word line to provide a second level signal to the second gate structure, and the read word line to provide a third level signal to the first gate structure, so that the electrons stored in the floating cell structure are reset and are written to the second value, and the amplitude of the second level signal is smaller than the amplitude of the first level signal; during the read state: controlling the
  • another aspect of the present disclosure provides a method for preparing a memory cell structure, the method for preparing a memory cell structure comprising: providing a substrate; forming an isolation structure on the surface of the substrate; forming a floating cell structure extending along a first direction on the surface of the isolation structure away from the substrate; forming a channel structure partially overlapping with the floating cell structure, the channel structure comprising a first part located on the outer surface of the floating cell structure, and a second part and a third part located on opposite sides of the floating cell structure along a second direction, the second part and the third part are both electrically connected to the first part and are both located on the surface of the isolation structure away from the substrate; the second direction intersects with the first direction; forming a first gate structure on the surface of the first part away from the substrate, and forming a second gate structure at one end of the floating cell structure along the first direction, the second gate structure and the first gate structure are insulated from each other.
  • the method for preparing a storage unit structure also includes: the outer surface of the floating unit structure is covered with an initial protection structure; forming a channel structure that partially overlaps with the floating unit structure includes: removing part of the initial protection structure to obtain a target protection structure with the floating unit structure exposed in the middle, and forming an insulating layer on the exposed outer surface of the floating unit structure; forming a channel structure covering the outer surface of the insulating layer, the channel structure including a first part covering the outer surface of the floating unit structure, and a second part and a third part located on opposite sides of the floating unit structure along the second direction.
  • the target protection structure includes a first oxide protection layer, a nitride protection layer and a second oxide protection layer, the first oxide protection layer is formed on the outer surface of the floating unit structure, the nitride protection layer is located on the surface of the first oxide protection layer away from the floating unit structure, and the second oxide protection layer is located on the surface of the nitride protection layer away from the floating unit structure; a first gate structure is formed on the surface of the first part away from the substrate, and a second gate structure is formed at one end of the floating unit structure along a first direction, including: forming a first gate dielectric layer covering the outer surface of the channel structure; while forming a first gate conductive layer on the surface of the first gate dielectric layer away from the substrate, a second gate conductive layer is formed on an end surface of the floating unit structure, the first gate conductive layer at least covers the surface of the first part of the floating unit structure away from the substrate; the top surface of the first gate conductive layer is flush with the top surface
  • the method for preparing a memory cell structure also includes: removing a portion of the first gate dielectric layer located on the top surface of the second part of the channel structure to obtain a first via hole exposing the top surface of the second part; removing a portion of the first gate dielectric layer located on the top surface of the third part of the channel structure to obtain a second via hole exposing the top surface of the third part; forming a source electrode structure that passes through the first via hole and is in contact with the top surface of the second part; and forming a drain electrode structure that passes through the second via hole and is in contact with the top surface of the third part.
  • the method for preparing a memory cell structure further includes: forming a first gate electrode structure on a top surface of the first gate conductive layer; and forming a second gate electrode structure on a top surface of the second gate conductive layer.
  • the method for preparing a memory cell structure also includes: forming an isolation structure on the surface of a substrate, including: forming a first oxide isolation layer on the surface of the substrate; forming a nitride isolation layer on the surface of the first oxide isolation layer away from the substrate; and forming a second oxide isolation layer on the surface of the nitride isolation layer away from the substrate.
  • the method for preparing a memory cell structure further includes: the material of the channel structure includes: polysilicon, indium gallium zinc oxide, indium gallium arsenide, gallium nitride or a combination thereof; the material of the floating cell structure includes doped polysilicon.
  • FIG1 is a partial three-dimensional structural diagram of a storage unit structure provided in one embodiment of the present disclosure.
  • FIG2 is a cross-sectional schematic diagram of the three-dimensional structure schematic diagram shown in FIG1 along the AA' direction;
  • FIG3 is a cross-sectional schematic diagram of the three-dimensional structure schematic diagram shown in FIG1 along the BB' direction;
  • FIG4 is a schematic diagram of a method for preparing a memory cell structure provided in an embodiment of the present disclosure
  • 5a to 5g are schematic diagrams of three-dimensional structures obtained in different steps of a method for preparing a memory cell structure in one embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a read/write circuit provided in an embodiment of the present disclosure.
  • first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components.
  • installed e.g., it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components.
  • the "deposition” process includes but is not limited to one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD).
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • the mutual insulation between the two described in the embodiments of the present disclosure includes but is not limited to one or more of the presence of insulating material, insulating atmosphere or gap between the two.
  • 3D DRAM three-dimensional dynamic random access memory
  • the traditional 3D DRAM storage cell consists of a single transistor and a single capacitor (1T1C structure).
  • the logical state is distinguished by whether the capacitor stores charge.
  • reading consumes the power of the capacitor, resulting in a decrease in response speed. Even if no reading is performed, the charge will leak out of the capacitor, resulting in reduced reliability. Therefore, the storage cell of a single transistor and a single capacitor needs to be refreshed regularly to maintain data, resulting in increased power consumption.
  • the refresh circuit will also occupy the volume of the storage cell, which will hinder the size reduction of dynamic random access memory.
  • the specific process of size reduction of traditional 1T1C 3D DRAM is less developable. For example, at small size nodes, the complexity of capacitor manufacturing process increases, the risk of charge leakage increases, and static power consumption increases.
  • the present disclosure aims to provide a memory cell structure and a preparation method thereof, a read/write circuit and a memory, which can at least reduce the charge leakage and power consumption of the memory cell and improve the response speed, storage density and reliability of the semiconductor memory device.
  • a memory cell structure which includes a substrate 10, an isolation structure 20, a floating cell structure 30, a channel structure 40, a first gate structure 510 and a second gate structure 520;
  • the isolation structure 20 is formed on the surface of the substrate 10;
  • the floating cell structure 30 is located on the surface of the isolation structure 20 away from the substrate 10, and extends along a first direction, for example, the first direction can be parallel to the OX direction;
  • the channel structure 40 partially overlaps with the floating cell structure 30 and is insulated from each other, and the channel structure 40 includes a first part 410, a second part 420 and a third part 430, the first part 410 of the channel structure is located on the outer surface of the floating cell structure 30, and the channel structure 40 includes a first part 410, a second part 420 and a third part 430.
  • the second part 420 and the third part 430 of the structure are located on opposite sides of the floating unit structure 30 along the second direction, and the second part 420 and the third part 430 of the channel structure are electrically connected to the first part 410 and are located on the surface of the isolation structure 20 away from the substrate 10;
  • the second direction can be parallel to the OY direction, and the second direction intersects with the first direction; for example, the angle between the first direction and the second direction can be 30 degrees, 45 degrees, 60 degrees, 75 degrees, 90 degrees, 135 degrees or 120 degrees, etc.
  • the first gate structure 510 is located on the surface of the first part 410 away from the substrate 10;
  • the second gate structure 520 is formed at one end of the floating unit structure 30 along the first direction, and is insulated from the first gate structure 510.
  • an insulating layer 310 is provided between the floating unit structure 30 and the channel structure 40. Electrons can form an F-N tunneling effect between the floating unit structure 30 and the channel structure 40.
  • the F-N tunneling effect (Fowler-Nordheim Tunneling) refers to the ability of microscopic particles to tunnel into a potential barrier region that is impossible to enter according to the laws of classical mechanics. It is a basic effect that reflects the wave nature of microscopic particles. According to the theory of quantum mechanics, electrons have wave properties.
  • the phenomenon of electron migration in semiconductors or insulators can be understood as electrons bound to an atom under an external electric field, which have a probability of tunneling through a potential barrier with higher energy than themselves to another atom.
  • the insulating layer 310 constitutes a potential barrier.
  • the electric field strength E of the insulating layer 310 can be set to a range of 10 megavolts per centimeter to 100 megavolts per centimeter, for example, E can be set to 10 megavolts per centimeter, 30 megavolts per centimeter, 50 megavolts per centimeter, 70 megavolts per centimeter, 90 megavolts per centimeter or 100 megavolts per centimeter, etc.; the thickness S of the insulating layer 310 can be set to a range of 1 nanometer to 10 nanometers, for example, S can be set to 1 nanometer, 2 nanometers, 4 nanometers, 6 nanometers, 8 nanometers or 10 nanometers, etc.; in some embodiments, the material of the insulating layer 310 includes poly
  • the first portion 410 , the second portion 420 , and the third portion 430 of the channel structure are an integrally formed structure prepared using the same process steps, thereby simplifying the process flow.
  • the first gate structure 510 includes a first gate dielectric layer 511 and a first gate conductive layer 512; the first gate dielectric layer 511 at least covers the outer surface of the channel structure 40; the first gate conductive layer 512 is located on the surface of the first gate dielectric layer 511 away from the substrate 10, and at least covers the surface of the first part 410 of the channel structure on the floating unit structure 30 away from the substrate 10; in some embodiments, the material of the first gate conductive layer 512 includes titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium nitride or a combination thereof; the material of the first gate dielectric layer 511 may include silicon oxide, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, strontium titanium oxide or a combination thereof.
  • the storage cell structure also includes a target protection structure 60, which covers the exposed outer surface of the floating cell structure 30 and is configured as follows: the target protection structure 60 includes a first oxide protection layer 610, a nitride protection layer 620 and a second oxide protection layer 630, the first oxide protection layer 610 is formed on the outer surface of the floating cell structure 30, the nitride protection layer 620 is located on the surface of the first oxide protection layer 310 away from the floating cell structure 30, and the second oxide protection layer 630 is located on the surface of the nitride protection layer 620 away from the floating cell structure 30, wherein the top surface of the second oxide protection layer 630 is adjacent to the first oxide protection layer 610.
  • the top surface of the gate conductive layer 512 is flush; in some embodiments, the nitride isolation layer 220 and the second oxide protection layer 630 are formed by a furnace tube low pressure chemical vapor deposition (LPCVD) process, the first oxide protection layer 610 is formed by a thermal oxidation process, or the first oxide protection layer 610 and the second oxide protection layer 630 are formed by a thermal oxidation process, and the nitride protection layer 620 is formed by a CVD deposition process, or the first oxide protection layer 610, the nitride protection layer 620 and the second oxide protection layer 630 can be formed in one stop in the same machine, for example, sequentially deposited by plasma enhanced chemical vapor deposition (PECVD).
  • PECVD plasma enhanced chemical vapor deposition
  • the material of the first oxide protection layer 610 includes silicon oxide
  • the material of the nitride protection layer 620 includes silicon nitride
  • the material of the second oxide protection layer 630 includes silicon oxide.
  • the target protection structure 60 is used to avoid charge leakage in the floating unit structure 30, improve the charge retention and reliability of the device, reduce the power consumption and defect density of the device, and extend the mean time between failures.
  • the second gate structure 520 includes a second gate conductive layer 522 and a second gate dielectric layer 521.
  • the second gate conductive layer 522 and the first gate conductive layer 512 are prepared in the same process step, and the second gate conductive layer 522 is located at one end surface of the floating body unit structure 30.
  • the second gate dielectric layer 521 is a portion of the second oxide protection layer 630 located between the end surface of the floating body unit structure 30 and the second gate conductive layer 522.
  • the material of the second gate conductive layer 522 includes titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium silicide or a combination thereof.
  • the material of the second gate dielectric layer 521 includes silicon oxide, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, strontium titanium oxide or a combination thereof.
  • the memory cell structure also includes a first gate electrode structure 513, a second gate electrode structure 523, a source electrode structure 710 and a drain electrode structure 720;
  • the first gate electrode structure 513 is located on the top surface of the first gate conductive layer 512;
  • the second gate electrode structure 523 is located on the top surface of the second gate conductive layer 522;
  • the source electrode structure 710 is located on the top surface of the second part 420 of the channel structure;
  • the drain electrode structure 720 is located on the top surface of the third part 430 of the channel structure, which is convenient for reading and writing control and/or performance testing of the memory cell structure through the first gate electrode structure 513, the second gate electrode structure 523, the source electrode structure 710 and the drain electrode structure 720, thereby improving the performance and reliability of the product.
  • the isolation structure 20 includes a first oxide isolation layer 210, a nitride isolation layer 220, and a second oxide isolation layer 230; the first oxide isolation layer 210 is located on the surface of the substrate 10; the nitride isolation layer 220 is located on the surface of the first oxide isolation layer 210 away from the substrate 10; and the second oxide isolation layer 230 is located on the surface of the nitride isolation layer 220 away from the substrate 10.
  • the nitride isolation layer 220 and the second oxide isolation layer 230 are formed by a furnace tube low pressure chemical vapor deposition (LPCVD) process, and the first oxide isolation layer 210 is formed by a thermal oxidation process, or the first oxide isolation layer 210 and the second oxide isolation layer 230 are formed by a thermal oxidation process, and the nitride isolation layer 220 is formed by a CVD deposition process, or the first oxide isolation layer 210, the nitride isolation layer 220, and the second oxide isolation layer 230 can be formed in one stop in the same machine, for example, sequentially deposited by plasma enhanced chemical vapor deposition (PECVD).
  • PECVD plasma enhanced chemical vapor deposition
  • the material of the first oxide isolation layer 210 includes silicon oxide
  • the material of the nitride isolation layer 220 includes silicon nitride
  • the material of the second oxide isolation layer 230 includes silicon oxide.
  • the isolation structure 20 is used to prevent charge leakage in the floating unit structure 30, improve the charge retention and reliability of the device, reduce the power consumption and defect density of the device, and extend the mean time between failures.
  • the material of the channel structure 40 includes polysilicon, indium gallium zinc oxide (IGZO), indium gallium arsenide (InGaAs), gallium nitride (GaN) or a combination thereof; the material of the floating unit structure 30 includes doped polysilicon.
  • IGZO indium gallium zinc oxide
  • InGaAs indium gallium arsenide
  • GaN gallium nitride
  • the material of the floating unit structure 30 includes doped polysilicon.
  • the present disclosure provides a method for preparing a memory cell structure, including:
  • Step S10 providing a substrate 10
  • Step S20 forming an isolation structure 20 on the surface of the substrate 10;
  • Step S30 forming a floating unit structure 30 extending along a first direction on a surface of the isolation structure 20 away from the substrate 10;
  • Step S40 forming a channel structure 40 partially overlapping with the floating body unit structure 30, the channel structure 40 comprising a first channel structure portion 410 located on the outer surface of the floating body unit structure 30, and a second channel structure portion 420 and a third channel structure portion 430 located on opposite sides of the floating body unit structure 30 along the second direction, the second channel structure portion 420 and the third channel structure portion 430 are both electrically connected to the first channel structure portion 410 and are both located on the surface of the isolation structure 20 away from the substrate 10; the second direction intersects with the first direction;
  • Step S50 forming a first gate structure 510 on a surface of the first channel structure portion 410 away from the substrate 10 , and forming a second gate structure 520 at one end of the floating body unit structure 30 along the first direction, wherein the second gate structure 520 is insulated from the first gate structure 510 .
  • step S10 please refer to FIG. 5a to provide a substrate 10; in step S20, please continue to refer to FIG. 5a to form an isolation structure 20 on the surface of the substrate 10; in step S30, please refer to FIG. 5b and 5c to form a floating unit structure 30 extending along a first direction on the surface of the isolation structure 20 away from the substrate 10, and the first direction may be parallel to the OX direction; for example, a deposition process is used to form a floating unit structure sacrificial layer 301 extending along the first direction on the surface of the isolation structure 20 away from the substrate 10, and then an etching process is used to remove part of the floating unit structure sacrificial layer 301 to form the floating unit structure 30; in step S40, please refer to FIG.
  • FIG. 4e and FIG. 5g to form a channel structure 40 partially overlapping with the floating unit structure 30, and the channel structure 40 includes a channel located in the floating unit structure 30 a first portion 410 on the outer surface, and a second portion 420 and a third portion 430 located on opposite sides of the floating unit structure 30 along the second direction, the second portion 420 and the third portion 430 are both electrically connected to the first portion 410 and are both located on the surface of the isolation structure 20 away from the substrate 10; the second direction can be parallel to the OY direction, and the second direction intersects with the first direction.
  • the angle between the first direction and the second direction can be 30 degrees, 45 degrees, 60 degrees, 75 degrees, 90 degrees, 135 degrees or 120 degrees, etc.; in step S50, please refer to Figure 1, a first gate structure 510 is formed on the surface of the first portion 410 away from the substrate 10, and a second gate structure 520 is formed at one end of the floating unit structure 30 along the first direction, and the second gate structure 520 and the first gate structure 510 are insulated from each other.
  • the method for preparing the memory cell structure further includes: forming an insulating layer 310 between the floating cell structure 30 and the channel structure 40.
  • an electric field is established in the insulating layer 310, and electrons can pass through the tunnel dielectric layer from the channel structure 40 into the floating cell structure 30 to form an F-N tunneling effect, thereby forming a tunneling current.
  • the material of the insulating layer 310 includes polysilicon oxide, and the insulating layer 310 can be formed by a deposition process. Since the tunneling effect occurs faster than the response speed of a traditional capacitor, there is no limit on the transit time, which can further improve the response speed of the semiconductor memory device.
  • the method for preparing a storage unit structure also includes: please refer to Figure 5d, the outer surface of the floating unit structure 30 is covered with an initial protection structure 601; forming a channel structure 40 that partially overlaps with the floating unit structure 30 includes: please refer to Figures 5d to 5e, removing part of the initial protection structure to obtain a target protection structure 60 with the floating unit structure 30 exposed in the middle; please refer to Figure 5f, forming an insulating layer 310 on the exposed outer surface of the floating unit structure 30; please refer to Figures 5e and 5g, forming a channel structure 40 covering the exposed outer surface of the floating unit structure 30, please refer to Figure 2, the channel structure 40 includes a first part 410 covering the outer surface of the floating unit structure 30, and a second part 420 and a third part 430 located on opposite sides of the floating unit structure 30 along the second direction.
  • the target protection structure 60 includes a first oxide protection layer 610, a nitride protection layer 620 and a second oxide protection layer 630.
  • the first oxide protection layer 610 is formed on the outer surface of the floating unit structure 30, the nitride protection layer 620 is located on the surface of the first oxide protection layer 310 away from the floating unit structure 30, and the second oxide protection layer 630 is located on the surface of the nitride protection layer 620 away from the floating unit structure 30; in some embodiments, the nitride isolation layer 620 and the second oxide protection layer 630 is formed by a furnace tube low pressure chemical vapor deposition (LPCVD) process, the first oxide protection layer 610 is formed by a thermal oxidation process, or the first oxide protection layer 610 and the second oxide protection layer 630 are formed by a thermal oxidation process, and the nitride protection layer 620 is formed by a CVD deposition process, or the first oxide protection layer 610, the nitrid
  • the material of the first oxide protection layer 610 includes silicon oxide
  • the material of the nitride protection layer 620 includes silicon nitride
  • the material of the second oxide protection layer 630 includes silicon oxide.
  • the target protection structure 60 is used to avoid charge leakage in the floating unit structure 30, improve the charge retention and reliability of the device, reduce the power consumption and defect density of the device, and extend the mean time between failures.
  • the method for preparing the memory cell structure further includes: forming a first gate structure 510 on a surface of the first portion 410 of the channel structure away from the substrate 10, and forming a second gate structure 520 at one end of the floating body cell structure 30 along the first direction, including: forming a first gate dielectric layer 511 covering the outer surface of the channel structure 40; forming a first gate conductive layer 512 on a surface of the first gate dielectric layer 511 away from the substrate 10, and forming a second gate conductive layer 520 on one end surface of the floating body cell structure 30; 22, the first gate conductive layer 512 at least covers the surface of the first portion 410 of the channel structure of the floating body unit structure 30 away from the substrate 10; the top surface of the first gate conductive layer 512 is flush with the top surface of the second oxide protection layer 630, the first gate dielectric layer 511 and the first gate conductive layer 512 constitute the first gate structure 510; the portion of the second oxide protection layer 630 between the end surface and the second
  • the material of the first gate conductive layer 512 includes titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium silicide or a combination thereof; the material of the first gate dielectric layer 511 may include silicon oxide, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, strontium titanium oxide or a combination thereof.
  • the method for preparing a memory cell structure further includes: removing a portion of the first gate dielectric layer 511 located on the top surface of the second portion 420 of the channel structure to obtain a first via hole (not shown in the figure) exposing the top surface of the second portion 420 of the channel structure; removing a portion of the first gate dielectric layer 511 located on the top surface of the third portion 430 of the channel structure to obtain a second via hole (not shown in the figure) exposing the top surface of the third portion 430 of the channel structure; forming a source electrode structure 710 that passes through the first via hole and is in contact with the top surface of the second portion 420 of the channel structure; forming a drain electrode structure 720 that passes through the second via hole and is in contact with the top surface of the third portion 430 of the channel structure, so as to facilitate read and write control and/or performance testing of the memory cell structure via the first gate electrode structure 513, the second gate electrode structure 523, the source electrode structure 710 and the drain
  • the method for preparing a memory cell structure also includes: forming a first gate electrode structure 513 on the top surface of the first gate conductive layer 512; forming a second gate electrode structure 523 on the top surface of the second gate conductive layer 522.
  • the isolation structure 20 is formed on the surface of the substrate 10, including: forming a first oxide isolation layer 210 on the surface of the substrate 10; forming a nitride isolation layer 220 on the surface of the first oxide isolation layer 210 away from the substrate 10; and forming a second oxide isolation layer 230 on the surface of the nitride isolation layer 220 away from the substrate 10.
  • the nitride isolation layer 220 and the second oxide isolation layer 230 are formed by a furnace tube low pressure chemical vapor deposition (LPCVD) process, and the first oxide isolation layer 210 is formed by a thermal oxidation process, or the first oxide isolation layer 210 and the second oxide isolation layer 230 are formed by a thermal oxidation process, and the nitride isolation layer 220 is formed by a CVD deposition process, or the first oxide isolation layer 210, the nitride isolation layer 220 and the second oxide isolation layer 230 can be formed in one stop in the same machine, for example, sequentially deposited by plasma enhanced chemical vapor deposition (PECVD).
  • PECVD plasma enhanced chemical vapor deposition
  • the material of the first oxide isolation layer 210 includes silicon oxide
  • the material of the nitride isolation layer 220 includes silicon nitride
  • the material of the second oxide isolation layer 230 includes silicon oxide.
  • the isolation structure 20 is used to prevent charge leakage in the floating unit structure 30, improve the charge retention and reliability of the device, reduce the power consumption and defect density of the device, and extend the mean time between failures.
  • the material of the channel structure 40 includes polysilicon, indium gallium zinc oxide, indium gallium arsenide, gallium nitride or a combination thereof; the material of the floating unit structure 30 includes doped polysilicon.
  • the stress and doping problems of traditional materials in the process stacking process are overcome, thereby reducing the difficulty of the multi-layer deposition process; as an example, the carrier mobility of IGZO is 20 to 30 times that of amorphous silicon. Using IGZO can improve the charge and discharge rate and response speed, and achieve a faster refresh rate.
  • the present disclosure provides a read-write circuit, which includes a memory cell structure of any of the above embodiments, and is configured as follows: a first gate structure 510 is electrically connected to a read word line RWL; a second gate structure 520 is electrically connected to a write word line WWL; a second portion 420 of the channel structure is electrically connected to a read bit line RBL; a third portion 430 of the channel structure is electrically connected to a write bit line WBL; during a write state: the write word line WWL is controlled to provide a first level signal to the second gate structure 520, so that the floating cell structure 30 captures and stores electrons, which are written into the first value; control the write word line WWL to provide a second level signal to the second gate structure 520, and the read word line RWL to provide a third level signal to the first gate structure 510, so that the electrons stored in the floating unit structure 30 are reset and written to the second value, and the amplitude of
  • the first gate structure 510 and the second gate structure 520 are electrically connected to the word line, and the channel structure 40 is electrically connected to the bit line.
  • the word line is controlled to provide a level signal to the first gate structure 510 and the second gate structure 520, the flow of electrons in the floating unit structure 30, and the drain current, thereby realizing the storage function and the read-write function of the storage unit. Since there are no traditional capacitors and refresh circuits in the read-write circuit, the increased power consumption caused by the frequent refresh of the refresh circuit is reduced, and the response speed and storage density of the semiconductor memory device can be improved while ensuring the storage capacity of the semiconductor memory device.
  • multiple memory cell structures are arranged in multiple rows and columns, and are configured as follows: the memory cell structures located in the same row are all connected to the same read word line RWL and the same write word line WWL; the memory cell structures located in the same column are all connected to the same read bit line RBL and the same write bit line WBL; the memory cell structures in two adjacent rows are connected to different read word lines RWL and different write word lines WWL; the memory cell structures in two adjacent columns are connected to different read bit lines RBL and different write bit lines WBL, so as to facilitate the implementation of read and write functions and/or performance testing in the read and write circuit via word lines and bit lines, thereby improving the performance and reliability of the product.
  • the first value is “0” and the second value is “1", thereby realizing the reading and writing functions of the read-write circuit for the value "0" and the value "1".
  • the present disclosure provides a memory, which includes the read/write circuit of any one of the above embodiments, and can at least reduce the charge leakage and power consumption of the memory, and improve the response speed, storage density and reliability of the memory.
  • the present disclosure provides a read-write circuit control method
  • the read-write circuit includes a memory cell structure of any one of the above embodiments, the memory cell structure is configured as follows: a first gate structure 510 is electrically connected to a read word line RWL, a second gate structure 520 is electrically connected to a write word line WWL, a second portion 420 of the channel structure is electrically connected to a read bit line RBL, and a third portion 430 of the channel structure is electrically connected to a write bit line WBL; the read-write circuit control method includes: during a write state: controlling the write word line WWL to provide a first level signal to the second gate structure 520, so that the floating cell structure 30 is captured Capture and store electrons, which are written to a first value; or control the write word line WWL to provide a second level signal to the second gate structure 520, and the read word line RWL to provide a third level signal to the first gate
  • the first value is “0" and the second value is “1".
  • the write word line WWL is controlled to provide a level signal to the first gate structure 510 and the second gate structure 520, causing the flow of electrons in the floating cell structure 30, thereby realizing the storage function and the write function of the memory cell;
  • the read word line RWL is controlled to provide a level signal to the first gate structure 510 and obtain the drain current, thereby realizing the read function of the memory cell; since there is no traditional capacitor and refresh circuit in the memory, the charge leakage caused by the capacitor is avoided, and the power consumption caused by the frequent refresh of the refresh circuit is reduced, which can improve the response speed and storage density of the semiconductor memory device while ensuring the storage capacity of the semiconductor memory device.

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Abstract

一种存储单元结构及其制备方法、读写电路及存储器，存储单元结构包括衬底（10）、隔离结构（20）、浮体单元结构（30）、沟道结构（40）、第一栅极结构（510）以及第二栅极结构（520）；浮体单元结构（30）位于隔离结构（20）远离衬底（10）的表面，沿第一方向延伸；沟道结构（40）与浮体单元结构（30）部分交叠，包括第一部分（410）、第二部分（420）及第三部分（430），第二部分（420）及第三部分（430）均与第一部分（410）电连接且均位于隔离结构（20）远离衬底（10）的表面；第一栅极结构（510）位于第一部分（410）远离衬底（10）的表面；第二栅极结构（520）形成于浮体单元结构（30）沿第一方向的一端，与第一栅极结构（510）相互绝缘。

Description

存储单元结构及其制备方法、读写电路及存储器
相关申请的交叉引用
本公开要求于2022年10月10日提交中国专利局、申请号为2022112348744、发明名称为“存储单元结构及其制备方法、读写电路及存储器”的中国专利申请的优先权，所述专利申请的全部内容通过引用结合在本公开中。
技术领域
本公开涉及集成电路设计及制造技术领域，特别是涉及一种存储单元结构及其制备方法、读写电路及存储器。
背景技术
随着集成电路制造工艺的不断发展，市场对半导体产品的性能及尺寸提出了更高的要求。对于半导体存储器件而言，如何在器件尺寸微缩的同时保证产品的功耗不增大、响应速度与存储密度不减小，是相关研发者不断追求的目标之一。
然而，传统的动态随机存取存储器中，存储单元由单个晶体管和单个电容器制成，对于这种结构的半导体存储器件而言，读取会消耗电容器的电量，导致响应速度降低。即使不进行读取，电荷也可能会通过晶体管从电容器中泄漏，导致半导体存储器件的可靠性降低。因此，单个晶体管和单个电容器的存储单元需要定期刷新以保持数据，导致器件的功耗增大。另外，刷新电路也会占据存储单元的体积，为动态随机存取存储器的尺寸微缩带来阻碍。
发明内容
根据本公开的各种实施例，一方面提供一种存储单元结构，存储单元结构包括衬底、隔离结构、浮体单元结构、沟道结构、第一栅极结构及第二栅极结构；隔离结构形成于衬底的表面；浮体单元结构位于隔离结构远离衬底的表面，沿第一方向延伸；沟道结构与浮体单元结构部分交叠且相互绝缘，沟道结构被配置为：包括位于浮体单元结构的外表面的第一部分，及位于浮体单元结构沿第二方向相对两侧的第二部分及第三部分，第二部分及第三部分均与第一部分电连接且均位于隔离结构远离衬底的表面，第二方向与第一方向相交；第一栅极结构位于第一部分远离衬底的表面；第二栅极结构形成于浮体单元结构沿第一方向的一端，与第一栅极结构相互绝缘。
根据本公开的一些实施例，沟道结构的第一部分、第二部分及第三部分为采用相同工艺步骤制备的一体成型结构，沟道结构的第一部分与浮体单元结构之间具有绝缘层。
根据本公开的一些实施例，第一栅极结构包括第一栅介质层及第一栅导电层；第一栅介质层至少覆盖沟道结构的外表面；第一栅导电层位于第一栅介质层远离衬底的表面，且至少覆盖浮体单元结构的第一部分的远离衬底的表面。
根据本公开的一些实施例，存储单元结构还包括目标保护结构，目标保护结构覆盖浮体单元结构的裸露外表面，被配置为：目标保护结构包括第一氧化物保护层、氮化物保护层及第二氧化物保护层，第一氧化物保护层形成于浮体单元结构的外表面，氮化物保护层位于第一氧化物保护层远离所述浮体单元结构的表面，第二氧化物保护层位于氮化物保护层远离所述浮体单元结构的表面，其中，第二氧化物保护层的顶面与第一栅导电层的顶面齐平。
根据本公开的一些实施例，第二栅极结构包括第二栅导电层及第二栅介质层；第二栅导电层与第一栅导电层在同一工艺步骤中制备而成，位于浮体单元结构的一端面；第二栅介质层为第二氧化物保护层位于端面与第二栅导电层之间的部分。
根据本公开的一些实施例，存储单元结构还包括第一栅电极结构、第二栅电极结构、源极电极结构及漏极电极结构；第一栅电极结构位于第一栅导电层的顶面；第二栅电极结构位于第二栅导电层的顶面；源极电极结构位于沟道结构的第二部分的顶面；漏极电极结构位于沟道结构的第三部分的顶面。
根据本公开的一些实施例，隔离结构包括第一氧化物隔离层、氮化物隔离层及第二氧化物隔离层；第一氧化物隔离层位于衬底的表面；氮化物隔离层位于第一氧化物隔离层远离衬底的表面；第二氧化物隔离层位于氮化物隔离层远离衬底的表面。
根据本公开的一些实施例，沟道结构的材料包括多晶硅、铟镓锌氧化物、砷化铟镓、氮化镓或其组合；浮体单元结构的材料包括掺杂多晶硅。
根据本公开的一些实施例，本公开另一方面提供一种读写电路，读写电路包括上述任一实施例的存储单元结构，被配置为：第一栅极结构与读字线电连接；第二栅极结构与写字线电连接；沟道结构的第二部分与读位线电连接；沟道结构的第三部分与写位线电连接；在写状态期间：控制写字线向第二栅极结构提供第一电平信号，使得浮体单元结构俘获并储存电子，被写入第一数值；控制写字线向第二栅极结构提供第二电平信号，及读字线向第一栅极结构提供第三电平信号，使得浮体单元结构存储的电子复位，被写入第二数值，第二电平信号的幅值小于第一电平信号的幅值；在读状态期间：控制读字线向第一栅极结构提供第三电平信号，根据获取的第一漏级电流判定读出第一数值，根据获取的第二漏级电流判定读出第二数值，第一漏级电流的幅值小于第二漏级电流的幅值。
根据本公开的一些实施例，多个存储单元结构呈多行多列排布，被配置为：位于同一行的存储单元结构均连接至相同的读字线及相同的写字线；位于同一列的存储单元结构均连接至相同的读位线及相同的写位线；相邻两行中的存储单元结构连接至不同的读字线及不同的写字线；相邻两列中的存储单元结构连接至不同的读位线及不同的写位线。
根据本公开的一些实施例，第一数值为“0”，第二数值为“1”，从而实现读写电路对于数值“0”与数值“1”的读写功能。
根据本公开的一些实施例，本公开又一方面提供一种存储器，存储器包括上述实施例任一项的读写电路。
根据本公开的一些实施例，本公开的又一方面提供一种读写电路控制方法，读写电路包括上述实施例任一项的存储单元结构，存储单元结构被配置为：第一栅极结构与读字线电连接，第二栅极结构与写字线电连接，沟道结构的第二部分与读位线电连接，沟道结构的第三部分与写位线电连接；读写控制方法包括：在写状态期间：控制写字线向第二栅极结构提供第一电平信号，使得浮体单元结构俘获并储存电子，被写入第一数值；或控制写字线向第二栅极结构提供第二电平信号，及读字线向第一栅极结构提供第三电平信号，使得浮体单元结构存储的电子复位，被写入第二数值，第二电平信号的幅值小于第一电平信号的幅值；在读状态期间：控制读字线向第一栅极结构提供第三电平信号，根据获取的第一漏级电流判定读出第一数值，根据获取的第二漏级电流判定读出第二数值，第一漏级电流的幅值小于第二漏级电流的幅值。
根据本公开的一些实施例，本公开的又一方面提供一种存储单元结构制备方法，存储单元结构制备方法包括：提供衬底；于衬底的表面形成隔离结构；于隔离结构远离衬底的表面形成沿第一方向延伸的浮体单元结构；形成与浮体单元结构部分交叠的沟道结构，沟道结构包括位于浮体单元结构的外表面的第一部分，及位于浮体单元结构沿第二方向相对两侧的第二部分及第三部分，第二部分及第三部分均与第一部分电连接且均位于隔离结构远离衬底的表面；第二方向与第一方向相交；于第一部分远离衬底的表面形成第一栅极结构，并于浮体单元结构沿第一方向的一端形成第二栅极结构，第二栅极结构与第一栅极结构相互绝缘。
根据本公开的一些实施例，存储单元结构制备方法还包括：浮体单元结构的外表面覆盖有初始保护结构；形成与浮体单元结构部分交叠的沟道结构包括：去除部分初始保护结构，得到中部暴露出浮体单元结构的目标保护结构，于所述浮体单元结构的裸露外表面形成绝缘层；形成覆盖绝缘层的外表面的沟道结构，沟道结构包括覆盖浮体单元结构的外表面的第一部分，及位于浮体单元结构沿第二方向相对两侧的第二部分及第三部分。
根据本公开的一些实施例，目标保护结构包括第一氧化物保护层、氮化物保护层及第二氧化物保护层，第一氧化物保护层形成于浮体单元结构的外表面，氮化物保护层位于第一氧化物保护层远离浮体单元结构的表面，第二氧化物保护层位于氮化物保护层远离浮体单元结构的表面；于第一部分远离衬底的表面形成第一栅极结构，并于浮体单元结构沿第一方向的一端形成第二栅极结构，包括：形成覆盖沟道结构的外表面的第一栅介质层；于第一栅介质层远离衬底的表面形成第一栅导电层的同时，于浮体单元结构的一端面形成第二栅导电层，第一栅导电层至少覆盖浮体单元结构的第一部分的远离衬底的表面；第一栅导电层的顶面与第二氧化物保护层的顶面齐平，第一栅介质层、第一栅导电层构成第一栅极结构；第二氧化物保护层位于端面与第二栅导电层之间的部分构成第二栅介质层，第二栅介质层、第二栅导电层构成第二栅极结构。
根据本公开的一些实施例，存储单元结构制备方法还包括：去除第一栅介质层位于沟道结构的第二部分的顶面的部分，得到暴露出第二部分的顶面的第一过孔；去除第一栅介质层位于沟道结构的第三部分的顶面的部分，得到暴露出第三部分的顶面的第二过孔；形成贯穿第一过孔并与第二部分的顶面接触连接的源极电极结构；形成贯穿第二过孔并与第三部分的顶面接触连接的漏极电极结构。
根据本公开的一些实施例，存储单元结构制备方法还包括：于第一栅导电层的顶面形成第一栅电极结构；于第二栅导电层的顶面形成第二栅电极结构。
根据本公开的一些实施例，存储单元结构制备方法还包括：于衬底的表面形成隔离结构，包括：于衬底的表面形成第一氧化物隔离层；于第一氧化物隔离层远离衬底的表面形成氮化物隔离层；于氮化物隔离层远离衬底的表面形成第二氧化物隔离层。
根据本公开的一些实施例，存储单元结构制备方法还包括：沟道结构的材料包括：多晶硅、铟镓锌氧化物、砷化铟镓、氮化镓或其组合；浮体单元结构的材料包括掺杂多晶硅。
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公开的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为本公开一实施例中提供的一种存储单元结构的部分立体结构示意图；
图2为图1所示立体结构示意图沿AA’方向的截面示意图；
图3为图1所示立体结构示意图沿BB’方向的截面示意图；
图4为本公开一实施例中提供的一种存储单元结构制备方法流程示意图；
图5a至图5g为本公开一实施例中存储单元结构制备方法中不同步骤所得立体结构示意图；
图6为本公开一实施例中提供的一种读写电路示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。在使用本文中描述的“包括”、“具有”、和“包含”的情况下，除非使用了明确的限定用语，例如“仅”、“由……组成”等，否则还可以添加另一部件。除非相反地提及，否则单数形式的术语可以包括复数形式，并不能理解为其数量为一个。
应当理解，尽管本文可以使用术语“第一”、“第二”等来描述各种元件，但是这些元件不应受这些术语的限制。这些术语仅用于将一元件和另一元件区分开。例如，在不脱离本公开的范围的情况下，第一元件可以被称为第二元件，并且类似地，第二元件可以被称为第一元件。
在本公开的描述中，除非另有明确规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是直接连接，亦可以是通过中间媒介间接连接，可以是两个部件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本公开的描述中，“沉积”工艺包括但不限于物理气相沉积(Physical Vapor Deposition，简称PVD)、化学气相沉积(Chemical Vapor Deposition，简称CVD)或原子层沉积(Atomic Layer Deposition，简称ALD)等中一种或多种。请注意，本公开实施例中所述的两者之间相互绝缘包括但不仅限于两者之间存在绝缘材料、绝缘气息或间隙等中一种或多种。
为了更好地适应器件尺寸按比例缩小的要求，半导体工艺逐渐从平面晶体管向具有更高功效的三维立体式的晶体管过渡，特别是三维动态随机存储器(3D Dynamic Random Access Memory，3D DRAM)技术的发展在半导体存储器件市场中占据重要位置。传统的3D DRAM存储单元由单个晶体管和单个电容器构成(1T1C结构)，通过电容器上是否存储电荷区分逻辑状态，对于这种结构的半导体存储器件而言，读取会消耗电容器的电量，导致响应速度降低。即使不进行读取，电荷也会从电容器中向外泄漏，导致可靠性降低。因此，单个晶体管和单个电容器的存储单元需要定期刷新以保持数据，导致功耗增大。另外，刷新电路也会占据存储单元的体积，为动态随机存取存储器的尺寸微缩带来阻碍。目前传统1T1C 3D DRAM的尺寸微缩的具体工艺可发展性较小，例如小尺寸节点下，电容制造工艺复杂性增大，电荷泄露风险上升，静态功耗上升等。
本公开旨在提供一种存储单元结构及其制备方法、读写电路及存储器，至少能够减轻存储单元的电荷泄露与功耗，提高半导体存储器件的响应速度、存储密度与可靠性。
请参考图1-图3，在一些实施例中，提供了一种存储单元结构，存储单元结构包括衬底10、隔离结构20、浮体单元结构30、沟道结构40、第一栅极结构510及第二栅极结构520；隔离结构20形成于衬底10的表面；浮体单元结构30位于隔离结构20远离衬底10的表面，沿第一方向延伸，例如第一方向可以与OX方向平行；沟道结构40与浮体单元结构30部分交叠且相互绝缘，沟道结构40包括第一部分410、第二部分420及第三部分430，沟道结构的第一部分410位于浮体单元结构30的外表面，沟道结构的第二部分420及第三部分430位于浮体单元结构30沿第二方向相对两侧，沟道结构的第二部分420及第三部分430均与其第一部分410电连接且均位于隔离结构20远离衬底10的表面；第二方向可以与OY方向平行，第二方向与第一方向相交；例如，第一方向与第二方向的夹角可以为30度、45度、60度、75度、90度、135度或120度等；第一栅极结构510位于第一部分410远离衬底10的表面；第二栅极结构520形成于浮体单元结构30沿第一方向的一端，与第一栅极结构510相互绝缘。
请继续参考图1-图2，在一些实施例中，通过在衬底10上依次设置隔离结构20、浮体单元结构30、沟道结构40、第一栅极结构510及第二栅极结构520，使得电荷可以存储在浮体单元结构30中，并且在浮体单元结构30与沟道结构40之间流动形成电流，从而实现存储单元的存储功能，同时避免电荷泄露，由于相对减小了单独的电容结构的体积并减少了外围电路的能耗，从而降低了半导体存储器件的功耗，能够在确保半导体存储器件的存储能力的前提下，减小存储单元的体积，提高半导体存储器件的响应速度与存储密度。
请继续参考图1-图2，在一些实施例中，浮体单元结构30与沟道结构40之间设置有绝缘层310，电子可以在浮体单元结构30与沟道结构40之间形成F-N隧穿效应，F-N隧穿效应(Fowler-Nordheim Tunneling)是指微观粒子能隧穿进入按经典力学规律不可能进入的势垒区，是反映微观粒子的波动性的一种基本效应；根据量子力学理论，电子具有波动性，可以把半导体或绝缘体中的电子迁移现象理解为在外电场下，束缚在一个原子中的电子，有几率可以隧穿比本身能量高的势垒，到另一个原子中；在一些实施例中，绝缘层310构成势垒，当在第二栅极结构520和衬底10之间施加一个电压时，在绝缘层310中会生成一个电场，由于空穴的有效质量和界面势垒均比电子要大，当绝缘层310中电场达到一定强度E，且绝缘层310达到一定厚度S时，电子可以从沟道结构40中穿过隧穿介质层进入到浮体单元结构30中形成F-N隧穿效应，从而形成隧穿电流；可以设置绝缘层310的电场强度E的范围包括每厘米10兆伏特至每厘米100兆伏特，例如可以设置E为每厘米10兆伏特、每厘米30兆伏特、每厘米50兆伏特、每厘米70兆伏特、每厘米90兆伏特或每厘米100兆伏特等；可以设置绝缘层310的厚度S的范围包括1纳米至10纳米，例如可以设置S为1纳米、2纳米、4纳米、6纳米、8纳米或10纳米等；在一些实施例中，绝缘层310的材料包括多晶硅氧化物，可以采取沉积工艺形成绝缘层310；由于隧道效应的发生速度较传统电容器的响应速度更快，没有渡越时间的限制，从而能够进一步提高半导体存储器件的响应速度。
请参考图2，在一些实施例中，沟道结构的第一部分410、第二部分420及第三部分430为采用相同工艺步骤制备的一体成型结构，从而简化工艺流程。
请参考图2，在一些实施例中，第一栅极结构510包括第一栅介质层511及第一栅导电层512；第一栅介质层511至少覆盖沟道结构40的外表面；第一栅导电层512位于第一栅介质层511远离衬底10的表面，且至少覆盖浮体单元结构30上的沟道结构第一部分410的远离衬底10的表面；在一些实施例中，第一栅导电层512的材料包括钛、钨、钽、钼、钴、铂、钛钨、氮化钨、氮化钛、氮硅化钛或其组合；第一栅介质层511的材料可以包括硅氧化物、氧化铝、氧化铪、氮氧化铪、氧化锆、氧化钽、氧化钛、锶钛氧化物或其组合。
请参考图3，在一些实施例中，存储单元结构还包括目标保护结构60，目标保护结构60覆盖浮体单元结构30的裸露外表面，被配置为：目标保护结构60包括第一氧化物保护层610、氮化物保护层620及第二氧化物保护层630，第一氧化物保护层610形成于浮体单元结构30的外表面，氮化物保护层620位于第一氧化物保护层310远离浮体单元结构30的表面，第二氧化物保护层630位于氮化物保护层620远离浮体单元结构30的表面，其中，第二氧化物保护层630的顶面与第一栅导电层512的顶面齐平；在一些实施例中，氮化物隔离层220及第二氧化物保护层630采用炉管低压化学气相沉积(LPCVD)工艺形成，第一氧化物保护层610采用热氧化工艺形成，或第一氧化物保护层610及第二氧化物保护层630采用热氧化工艺形成，氮化物保护层620采用CVD沉积工艺形成，再或，可以在同一台机台中一站式形成第一氧化物保护层610、氮化物保护层620及第二氧化物保护层630，例如采用等离子体增强化学的气相沉积法(PECVD)中进行依次沉积。在一些实施例中，第一氧化物保护层610的材料包括氧化硅，氮化物保护层620的材料包括氮化硅，及/或第二氧化物保护层630的材料包括氧化硅。目标保护结构60用于避免浮体单元结构30中的电荷泄露，提升器件的电荷保持性与可靠性，降低器件的功耗与缺陷密度，延长故障平均时间。
请参考图2-图3，在一些实施例中，第二栅极结构520包括第二栅导电层522及第二栅介质层521；第二栅导电层522与第一栅导电层512在同一工艺步骤中制备而成，第二栅导电层522位于浮体单元结构30的一端面；第二栅介质层521为第二氧化物保护层630位于浮体单元结构30的端面与第二栅导电层522之间的部分；在一些实施例中，第二栅导电层522的材料包括钛、钨、钽、钼、钴、铂、钛钨、氮化钨、氮化钛、氮硅化钛或其组合；第二栅介质层521的材料包括硅氧化物、氧化铝、氧化铪、氮氧化铪、氧化锆、氧化钽、氧化钛、锶钛氧化物或其组合。通过采用横向分布的双栅极结构，减小沟道结构的导通电阻，增强了通流能力和控制能力，减少漏电流的产生。
请参考图2-图3，在一些实施例中，存储单元结构还包括第一栅电极结构513、第二栅电极结构523、源极电极结构710及漏极电极结构720；第一栅电极结构513位于第一栅导电层512的顶面；第二栅电极结构523位于第二栅导电层522的顶面；源极电极结构710位于沟道结构的第二部分420的顶面；漏极电极结构720位于沟道结构的第三部分430的顶面，便于经由第一栅电极结构513、第二栅电极结构523、源极电极结构710及漏极电极结构720向存储单元结构进行读写控制及/或性能测试，提高产品的性能及可靠性。
请参考图2-图3，在一些实施例中，隔离结构20包括第一氧化物隔离层210、氮化物隔离层220及第二氧化物隔离层230；第一氧化物隔离层210位于衬底10的表面；氮化物隔离层220位于第一氧化物隔离层210远离衬底10的表面；第二氧化物隔离层230位于氮化物隔离层220远离衬底10的表面。在一些实施例中，氮化物隔离层220及第二氧化物隔离层230采用炉管低压化学气相沉积(LPCVD)工艺形成，第一氧化物隔离层210采用热氧化工艺形成，或第一氧化物隔离层210及第二氧化物隔离层230采用热氧化工艺形成，氮化物隔离层220采用CVD沉积工艺形成，再或，可以在同一台机台中一站式形成第一氧化物隔离层210、氮化物隔离层220及第二氧化物隔离层230，例如采用等离子体增强化学的气相沉积法(PECVD)中进行依次沉积。在一些实施例中，第一氧化物隔离层210的材料包括氧化硅，氮化物隔离层220的材料包括氮化硅及/或第二氧化物隔离层230的材料包括氧化硅。隔离结构20用于避免浮体单元结构30中的电荷泄露，提升器件的电荷保持性与可靠性，降低器件的功耗与缺陷密度，延长故障平均时间。
请参考图1-图3，在一些实施例中，沟道结构40的材料包括多晶硅、铟镓锌氧化物(IGZO)、砷化铟镓(InGaAs)、氮化镓(GaN)或其组合；浮体单元结构30的材料包括掺杂多晶硅。通过采用上述材料，克服传统的材料在工艺堆叠过程中的应力及掺杂问题，从而降低多层沉积工艺的难度；作为示例，IGZO的载流子迁移率是非晶硅的20倍至30倍，采用IGZO可以提高充放电速率与响应速度，实现更快的刷新频率。
请参考图1-图4，根据一些实施例，本公开提供一种存储单元结构制备方法，包括：
步骤S10：提供衬底10；
步骤S20：于衬底10的表面形成隔离结构20；
步骤S30：于隔离结构20远离衬底10的表面形成沿第一方向延伸的浮体单元结构30；
步骤S40：形成与浮体单元结构30部分交叠的沟道结构40，沟道结构40包括位于浮体单元结构30的外表面的沟道结构第一部分410，及位于浮体单元结构30沿第二方向相对两侧的沟道结构第二部分420及沟道结构第三部分430，沟道结构第二部分420及沟道结构第三部分430均与沟道结构第一部分410电连接且均位于隔离结构20远离衬底10的表面；第二方向与第一方向相交；
步骤S50：于沟道结构第一部分410远离衬底10的表面形成第一栅极结构510，并于浮体单元结构30沿第一方向的一端形成第二栅极结构520，第二栅极结构520与第一栅极结构510相互绝缘。
在步骤S10中，请参考图5a，提供衬底10；在步骤S20中，请继续参考图5a，于衬底10的表面形成隔离结构20；在步骤S30中，请参考图5b及5c，于隔离结构20远离衬底10的表面形成沿第一方向延伸的浮体单元结构30，第一方向可以与OX方向平行；例如，于隔离结构20远离衬底10的表面采用沉积工艺形成沿第一方向延伸的浮体单元结构牺牲层301，再采用刻蚀工艺去除部分浮体单元结构牺牲层301以形成浮体单元结构30；在步骤S40中，请参考图2、图4e及图5g，形成与浮体单元结构30部分交叠的沟道结构40，沟道结构40包括位于浮体单元结构30的外表面的第一部分410，及位于浮体单元结构30沿第二方向相对两侧的第二部分420及第三部分430，第二部分420及第三部分430均与第一部分410电连接且均位于隔离结构20远离衬底10的表面；第二方向可以与OY方向平行，第二方向与第一方向相交，例如，第一方向与第二方向的夹角可以为30度、45度、60度、75度、90度、135度或120度等；在步骤S50中，请参考图1，于第一部分410远离衬底10的表面形成第一栅极结构510，并于浮体单元结构30沿第一方向的一端形成第二栅极结构520，第二栅极结构520与第一栅极结构510相互绝缘。
请参考图1、图2、图5a至图5g，在一些实施例中，通过在衬底10上依次形成隔离结构20、浮体单元结构30、沟道结构40、第一栅极结构510及第二栅极结构520，使得电荷可以存储在浮体单元结构30中，并且在浮体单元结构30与沟道结构40之间流动形成电流，从而实现存储单元的存储功能，同时避免电荷泄露；由于相对减小了单独的电容结构的体积并减少了外围电路的能耗，本实施例降低了半导体存储器件的功耗，能够在确保半导体存储器件的存储能力的前提下，减小存储单元的体积，提高半导体存储器件的响应速度与存储密度。
请参考图1及图5f，在一些实施例中，存储单元结构制备方法还包括：于浮体单元结构30与沟道结构40之间形成绝缘层310，当在第二栅极结构520和衬底10之间施加一个电压时，在绝缘层310中会建立一个电场，电子可以从沟道结构40中穿过隧穿介质层进入到浮体单元结构30中形成F-N隧穿效应，从而形成隧穿电流。在一些实施例中，绝缘层310的材料包括多晶硅氧化物，可以采取沉积工艺形成绝缘层310。由于隧道效应的发生速度较传统电容器的响应速度更快，没有渡越时间的限制，从而能够进一步提高半导体存储器件的响应速度。
请参考图2、图5c-图5g，在一些实施例中，存储单元结构制备方法还包括：请参考图5d，浮体单元结构30的外表面覆盖有初始保护结构601；形成与浮体单元结构30部分交叠的沟道结构40包括：请参考图5d至图5e，去除部分初始保护结构，得到中部暴露出浮体单元结构30的目标保护结构60；请参考图5f，于浮体单元结构30的裸露外表面形成绝缘层310；请参考图5e及图5g，形成覆盖浮体单元结构30的裸露外表面的沟道结构40，请参考图2，沟道结构40包括覆盖浮体单元结构30的外表面的第一部分410，及位于浮体单元结构30沿第二方向相对两侧的第二部分420及第三部分430。
请参考图2及图3，在一些实施例中，目标保护结构60包括第一氧化物保护层610、氮化物保护层620及第二氧化物保护层630，第一氧化物保护层610形成于浮体单元结构30的外表面，氮化物保护层620位于第一氧化物保护层310远离浮体单元结构30的表面，第二氧化物保护层630位于氮化物保护层620远离浮体单元结构30的表面；在一些实施例中，氮化物隔离层620及第二氧化物保护层630采用炉管低压化学气相沉积(LPCVD)工艺形成，第一氧化物保护层610采用热氧化工艺形成，或第一氧化物保护层610及第二氧化物保护层630采用热氧化工艺形成，氮化物保护层620采用CVD沉积工艺形成，再或，可以在同一台机台中一站式形成第一氧化物保护层610、氮化物保护层620及第二氧化物保护层630，例如采用等离子体增强化学的气相沉积法(PECVD)中进行依次沉积。在一些实施例中，第一氧化物保护层610的材料包括氧化硅，氮化物保护层620的材料包括氮化硅及/或第二氧化物保护层630的材料包括氧化硅。目标保护结构60用于避免浮体单元结构30中的电荷泄露，提升器件的电荷保持性与可靠性，降低器件的功耗与缺陷密度，延长故障平均时间。
请继续参考图2及图3，在一些实施例中，存储单元结构制备方法还包括：于沟道结构的第一部分410远离衬底10的表面形成第一栅极结构510，并于浮体单元结构30沿第一方向的一端形成第二栅极结构520，包括：形成覆盖沟道结构40的外表面的第一栅介质层511；于第一栅介质层511远离衬底10的表面形成第一栅导电层512的同时，于浮体单元结构30的一端面形成第二栅导电层522，第一栅导电层512至少覆盖浮体单元结构30的沟道结构第一部分410的远离衬底10的表面；第一栅导电层512的顶面与第二氧化物保护层630的顶面齐平，第一栅介质层511、第一栅导电层512构成第一栅极结构510；第二氧化物保护层630位于端面与第二栅导电层522之间的部分构成第二栅介质层521，第二栅介质层521、第二栅导电层522构成第二栅极结构520。在一些实施例中，第一栅导电层512的材料包括钛、钨、钽、钼、钴、铂、钛钨、氮化钨、氮化钛、氮硅化钛或其组合；第一栅介质层511的材料可以包括硅氧化物、氧化铝、氧化铪、氮氧化铪、氧化锆、氧化钽、氧化钛、锶钛氧化物或其组合。通过采用横向分布的双栅极结构，减小沟道结构的导通电阻，增强了通流能力和控制能力，减少漏电流的产生。
请参考图2，在一些实施例中，存储单元结构制备方法还包括：去除第一栅介质层511位于沟道结构的第二部分420的顶面的部分，得到暴露出沟道结构的第二部分420的顶面的第一过孔(图中未示出)；去除第一栅介质层511位于沟道结构的第三部分430的顶面的部分，得到暴露出沟道结构的第三部分430的顶面的第二过孔(图中未示出)；形成贯穿第一过孔并与沟道结构的第二部分420的顶面接触连接的源极电极结构710；形成贯穿第二过孔并与沟道结构的第三部分430的顶面接触连接的漏极电极结构720，便于经由第一栅电极结构513、第二栅电极结构523、源极电极结构710及漏极电极结构720向存储单元结构进行读写控制及/或性能测试，提高产品的性能及可靠性。
请参考图3，在一些实施例中，存储单元结构制备方法还包括：于第一栅导电层512的顶面形成第一栅电极结构513；于第二栅导电层522的顶面形成第二栅电极结构523，通过采用横向分布的双栅电极结构，减小沟道结构的导通电阻，增强了通流能力和控制能力，减少漏电流的产生。
请参考图5c，在一些实施例中，于衬底10的表面形成隔离结构20，包括：于衬底10的表面形成第一氧化物隔离层210；于第一氧化物隔离层210远离衬底10的表面形成氮化物隔离层220；于氮化物隔离层220远离衬底10的表面形成第二氧化物隔离层230。在一些实施例中，氮化物隔离层220及第二氧化物隔离层230采用炉管低压化学气相沉积(LPCVD)工艺形成，第一氧化物隔离层210采用热氧化工艺形成，或第一氧化物隔离层210及第二氧化物隔离层230采用热氧化工艺形成，氮化物隔离层220采用CVD沉积工艺形成，再或，可以在同一台机台中一站式形成第一氧化物隔离层210、氮化物隔离层220及第二氧化物隔离层230，例如采用等离子体增强化学的气相沉积法(PECVD)中进行依次沉积。在一些实施例中，第一氧化物隔离层210的材料包括氧化硅，氮化物隔离层220的材料包括氮化硅及/或第二氧化物隔离层230的材料包括氧化硅。隔离结构20用于避免浮体单元结构30中的电荷泄露，提升器件的电荷保持性与可靠性，降低器件的功耗与缺陷密度，延长故障平均时间。
在一些实施例中，沟道结构40的材料包括多晶硅、铟镓锌氧化物、砷化铟镓、氮化镓或其组合；浮体单元结构30的材料包括掺杂多晶硅。通过采用上述材料，克服传统的材料在工艺堆叠过程中的应力及掺杂问题，从而降低多层沉积工艺的难度；作为示例，IGZO的载流子迁移率是非晶硅的20倍至30倍，采用IGZO可以提高充放电速率与响应速度，实现更快的刷新频率。
请参考图1、图3及图6，根据一些实施例，本公开提供一种读写电路，读写电路包括上述任一实施例的存储单元结构，被配置为：第一栅极结构510与读字线RWL电连接；第二栅极结构520与写字线WWL电连接；沟道结构的第二部分420与读位线RBL电连接；沟道结构的第三部分430与写位线WBL电连接；在写状态期间：控制写字线WWL向第二栅极结构520提供第一电平信号，使得浮体单元结构30俘获并储存电子，被写入第一数值；控制写字线WWL向第二栅极结构520提供第二电平信号，及读字线RWL向第一栅极结构510提供第三电平信号，使得浮体单元结构30存储的电子复位，被写入第二数值，第二电平信号的幅值小于第一电平信号的幅值；在读状态期间：控制读字线RWL向第一栅极结构510提供第三电平信号，根据获取的第一漏级电流Id1判定读出第一数值，根据获取的第二漏级电流判定读出第二数值，第一漏级电流的幅值小于第二漏级电流的幅值。
请继续参考图1、图3及图6，在一些实施例中，在写状态期间：第二栅电极结构523的电压VG2与第一电平信号G21的幅值关系包括：VG2＝G21>0，漏极电极结构710的电压VD的幅值等于漏极电源电压VDD的幅值，从而写入第一数值；第二栅电极结构513的电压VG3与第二电平信号G22的幅值关系包括：G22＝VG3<0，第一栅电极结构513的电压VG1与第三电平信号G1的幅值关系包括：VG1＝G1>0，从而写入第二数值，第二电平信号G22与第一电平信号G1的幅值关系包括：G22<G1；在读状态期间：第一栅电极结构513的电压VG1与第三电平信号G1的幅值关系包括：VG1＝G1；第一漏级电流Id1与第二漏级电流Id2的幅值关系包括：Id1<Id2。在一些实施例中，通过第一栅极结构510、第二栅极结构520与字线电连接，沟道结构40与位线电连接，控制字线向第一栅极结构510与第二栅极结构520提供电平信号、浮体单元结构30中电子流动、获取漏极电流，从而实现存储单元的存储功能与读写功能，由于读写电路中不存在传统电容器与刷新电路，从而降低刷新电路频繁刷新所导致的功耗增加，能够在确保半导体存储器件的存储能力的前提下，提高半导体存储器件的响应速度与存储密度。
请参考图6，在一些实施例中，多个存储单元结构呈多行多列排布，被配置为：位于同一行的存储单元结构均连接至相同的读字线RWL及相同的写字线WWL；位于同一列的存储单元结构均连接至相同的读位线RBL及相同的写位线WBL；相邻两行中的存储单元结构连接至不同的读字线RWL及不同的写字线WWL；相邻两列中的存储单元结构连接至不同的读位线RBL及不同的写位线WBL，便于经由字线及位线在读写电路中实现读写功能及/或性能测试，提高产品的性能及可靠性。
在一些实施例中，第一数值为“0”，第二数值为“1”，从而实现读写电路对于数值“0”及数值“1”的读写功能。
根据一些实施例，本公开提供一种存储器，存储器包括上述实施例任一项的读写电路，至少能够减轻存储器的电荷泄露与功耗，提高存储器的响应速度、存储密度与可靠性。
请参考图1、图3及图6，根据一些实施例，本公开提供一种读写电路控制方法，读写电路包括上述实施例任一项的存储单元结构，存储单元结构被配置为：第一栅极结构510与读字线RWL电连接，第二栅极结构520与写字线WWL电连接，沟道结构的第二部分420与读位线RBL电连接，沟道结构的第三部分430与写位线WBL电连接；读写电路控制方法包括：在写状态期间：控制写字线WWL向第二栅极结构520提供第一电平信号，使得浮体单元结构30俘获并储存电子，被写入第一数值；或控制写字线WWL向第二栅极结构520提供第二电平信号，及读字线RWL向第一栅极结构510提供第三电平信号，使得浮体单元结构30存储的电子复位，被写入第二数值，第二电平信号的幅值小于第一电平信号的幅值；在读状态期间：控制读字线RWL向第一栅极结构510提供第三电平信号，根据获取的第一漏级电流判定读出第一数值，根据获取的第二漏级电流判定读出第二数值，第一漏级电流的幅值小于第二漏级电流的幅值。
请继续参考图1、图3及图6，在一些实施例中，在写状态期间：第二栅电极结构523的电压VG2与第一电平信号G21的幅值关系包括：VG2＝G21>0，漏极电极结构710的电压VD的幅值等于漏极电源电压VDD的幅值，从而写入第一数值；第二栅电极结构513的电压VG3与第二电平信号G22的幅值关系包括：G22＝VG3<0，第一栅电极结构513的电压VG1与第三电平信号G1的幅值关系包括：VG1＝G1>0，从而写入第二数值，第二电平信号G22与第一电平信号G1的幅值关系包括：G22<G1；在读状态期间：第一栅电极结构513的电压VG1与第三电平信号G1的幅值关系包括：VG1＝G1；第一漏级电流Id1与第二漏级电流Id2的幅值关系包括：Id1<Id2。作为示例，第一数值为“0”，第二数值为“1”。在一些实施例中，通过控制写字线WWL向第一栅极结构510与第二栅极结构520提供电平信号，导致浮体单元结构30中电子流动，从而实现存储单元的存储功能与写入功能；通过控制读字线RWL向第一栅极结构510提供电平信号与获取漏极电流，从而实现存储单元的读取功能；由于存储器中不存在传统电容器与刷新电路，从而避免由电容器带来的电荷泄露，同时降低刷新电路频繁刷新所导致的功耗增加，能够在确保半导体存储器件的存储能力的前提下，提高半导体存储器件的响应速度与存储密度。
请注意，上述实施例仅出于说明性目的而不意味对本公开的限制。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上实施例仅表达了本公开的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对公开专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本公开构思的前提下，还可以做出若干变形和改进，这些都属于本公开的保护范围。因此，本公开专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种存储单元结构，包括：
    衬底(10)；
    隔离结构(20)，形成于所述衬底(10)的表面；
    浮体单元结构(30)，位于所述隔离结构(20)远离所述衬底(10)的表面，沿第一方向延伸；
    沟道结构(40)，与所述浮体单元结构(30)部分交叠且相互绝缘，包括位于所述浮体单元结构(30)的外表面的第一部分，及位于所述浮体单元结构(30)沿第二方向相对两侧的第二部分及第三部分，所述第二部分及所述第三部分均与所述第一部分电连接且均位于所述隔离结构(20)远离所述衬底(10)的表面；所述第二方向与所述第一方向相交；
    第一栅极结构(510)，位于所述第一部分远离所述衬底(10)的表面；
    第二栅极结构(520)，形成于所述浮体单元结构(30)沿所述第一方向的一端，与所述第一栅极结构(510)相互绝缘。
  2. 根据权利要求1所述的存储单元结构，其中，所述沟道结构(40)的所述第一部分、所述第二部分及所述第三部分为采用相同工艺步骤制备的一体成型结构；以及
    所述第一部分与所述浮体单元结构(30)之间具有绝缘层(310)。
  3. 根据权利要求1或2所述的存储单元结构，其中，所述第一栅极结构(510)包括：
    第一栅介质层(511)，至少覆盖所述沟道结构(40)的外表面；以及
    第一栅导电层(512)，位于所述第一栅介质层(511)远离所述衬底(10)的表面，且至少覆盖所述浮体单元结构(30)的第一部分的远离所述衬底(10)的表面。
  4. 根据权利要求1-3任一项所述的存储单元结构，其中，还包括：
    目标保护结构(60)，覆盖所述浮体单元结构(30)的裸露外表面；
    所述目标保护结构(60)包括：形成于所述浮体单元结构(30)的外表面的第一氧化物保护层(610)，位于所述第一氧化物保护层(610)远离所述浮体单元结构(30)的表面的氮化物保护层(620)，以及位于所述氮化物保护层(620)远离所述浮体单元结构(30)的表面的第二氧化物保护层(630)；
    其中，所述第一栅导电层(512)的顶面与所述第二氧化物保护层(630)的顶面齐平。
  5. 根据权利要求4所述的存储单元结构，其中，所述第二栅极结构(520)包括：
    第二栅导电层(522)，与所述第一栅导电层(512)在同一工艺步骤中制备而成，位于所述浮体单元结构(30)的一端面；
    第二栅介质层(521)，为所述第二氧化物保护层(630)位于所述端面与所述第二栅导电层(522)之间的部分。
  6. 根据权利要求5所述的存储单元结构，其中，还包括：
    第一栅电极结构(513)，位于所述第一栅导电层(512)的顶面；
    第二栅电极结构(523)，位于所述第二栅导电层(522)的顶面；
    源极电极结构(710)，位于所述沟道结构的第二部分(420)的顶面；以及
    漏极电极结构(720)，位于所述沟道结构的第三部分(430)的顶面。
  7. 根据权利要求1-6任一项所述的存储单元结构，其中，所述隔离结构(20)包括：
    第一氧化物隔离层(210)，位于所述衬底(10)的表面；
    氮化物隔离层(220)，位于所述第一氧化物隔离层(210)远离所述衬底(10)的表面；以及
    第二氧化物隔离层(230)，位于所述氮化物隔离层(220)远离所述衬底(10)的表面。
  8. 根据权利要求1-6任一项所述的存储单元结构，其中：
    所述沟道结构(40)的材料包括：多晶硅、铟镓锌氧化物、砷化铟镓、氮化镓或其组合；及/或
    所述浮体单元结构(30)的材料包括掺杂多晶硅。
  9. 一种读写电路，包括：
    权利要求1-8任一项所述的存储单元结构，被配置为：
    第一栅极结构(510)与读字线电连接；
    第二栅极结构(520)与写字线电连接；
    沟道结构的第二部分(420)与读位线电连接；
    沟道结构的第三部分(430)与写位线电连接；
    在写状态期间：
    控制所述写字线向所述第二栅极结构(520)提供第一电平信号，使得所述浮体单元结构(30)俘获并储存电子，被写入第一数值；
    控制所述写字线向所述第二栅极结构(520)提供第二电平信号，及所述读字线向所述第一栅极结构(510)提供第三电平信号，使得所述浮体单元结构(30)存储的电子复位，被写入第二数值，所述第二电平信号的幅值小于所述第一电平信号的幅值；
    在读状态期间：
    控制所述读字线向所述第一栅极结构(510)提供所述第三电平信号，根据获取的第一漏级电流判定读出所述第一数值，根据获取的第二漏级电流判定读出所述第二数值，所述第一漏级电流的幅值小于所述第二漏级电流的幅值。
  10. 根据权利要求9所述的读写电路，其中，多个所述存储单元结构呈多行多列排布；
    位于同一行的所述存储单元结构均连接至相同的读字线及相同的写字线；
    位于同一列的所述存储单元结构均连接至相同的读位线及相同的写位线；
    相邻两行中的所述存储单元结构连接至不同的读字线及不同的写字线；
    相邻两列中的所述存储单元结构连接至不同的读位线及不同的写位线。
  11. 根据权利要求9或10所述的读写电路，其中，所述第一数值为“0”，所述第二数值为“1”。
  12. 一种存储器，包括：
    权利要求9-11任一项所述的读写电路。
  13. 一种读写电路控制方法，所述读写电路包括权利要求1-8任一项所述的存储单元结构，所述存储单元结构被配置为：第一栅极结构(510)与读字线电连接，第二栅极结构(520)与写字线电连接，沟道结构的第二部分(420)与读位线电连接，沟道结构的第三部分(430)与写位线电连接；所述控制方法包括：
    在写状态期间：控制所述写字线向所述第二栅极结构(520)提供第一电平信号，使得所述浮体单元结构(30)俘获并储存电子，被写入第一数值；或控制所述写字线向所述第二栅极结构(520)提供第二电平信号，及所述读字线向所述第一栅极结构(510)提供第三电平信号，使得所述浮体单元结构(30)存储的电子复位，被写入第二数值，所述第二电平信号的幅值小于所述第一电平信号的幅值；
    在读状态期间：控制所述读字线向所述第一栅极结构(510)提供所述第三电平信号，根据获取的第一漏级电流判定读出所述第一数值，根据获取的第二漏级电流判定读出所述第二数值，所述第一漏级电流的幅值小于所述第二漏级电流的幅值。
  14. 一种存储单元结构制备方法，包括：
    提供衬底(10)；
    于所述衬底(10)的表面形成隔离结构(20)；
    于所述隔离结构(20)远离所述衬底(10)的表面形成沿第一方向延伸的浮体单元结构(30)；
    形成与所述浮体单元结构(30)部分交叠的沟道结构(40)，所述沟道结构(40)包括位于所述浮体单元结构(30)的外表面的第一部分，及位于所述浮体单元结构(30)沿第二方向相对两侧的第二部分及第三部分，所述第二部分及所述第三部分均与所述第一部分电连接且均位于所述隔离结构(20)远离所述衬底(10)的表面；所述第二方向与所述第一方向相交；
    于所述第一部分远离所述衬底(10)的表面形成第一栅极结构(510)，并于所述浮体单元结构(30)沿所述第一方向的一端形成第二栅极结构(520)，所述第二栅极结构(520)与所述第一栅极结构(510)相互绝缘。
  15. 根据权利要求14所述的存储单元结构制备方法，其中，所述浮体单元结构(30)的外表面覆盖有初始保护结构(601)；所述形成与所述浮体单元结构(30)部分交叠的沟道结构(40)，包括：
    去除部分所述初始保护结构(601)，得到中部暴露出所述浮体单元结构(30)的目标保护结构(60)；
    于所述浮体单元结构(30)的裸露外表面形成绝缘层(310)；
    形成覆盖所述绝缘层(310)的外表面的沟道结构(40)，所述沟道结构(40)包括覆盖所述浮体单元结构(30)的外表面的第一部分，及位于所述浮体单元结构(30)沿所述第二方向相对两侧的所述第二部分及所述第三部分。
  16. 根据权利要求15所述的存储单元结构制备方法，其中，所述目标保护结构(60)包括：形成于所述浮体单元结构(30)的外表面的第一氧化物保护层(610)，位于所述第一氧化物保护层(610)远离所述浮体单元结构(30)的表面的氮化物保护层(620)，以及位于所述氮化物保护层(620)远离所述浮体单元结构(30)的表面的第二氧化物保护层(630)；所述于所述第一部分远离所述衬底(10)的表面形成第一栅极结构(510)，并于所述浮体单元结构(30)沿所述第一方向的一端形成第二栅极结构(520)，包括：
    形成覆盖所述沟道结构(40)的外表面的第一栅介质层(511)；
    于所述第一栅介质层(511)远离所述衬底(10)的表面形成第一栅导电层(512)的同时，于所述浮体单元结构(30)的一端面形成第二栅导电层(522)，所述第一栅导电层(512)至少覆盖所述浮体单元结构(30)的第一部分的远离所述衬底(10)的表面；所述第一栅导电层(512)的顶面与所述第二氧化物保护层(630)的顶面齐平，所述第一栅介质层(511)、所述第一栅导电层(512)构成所述第一栅极结构(510)；所述第二氧化物保护层(630)位于所述端面与所述第二栅导电层(522)之间的部分构成第二栅介质层(521)，所述第二栅介质层(521)、所述第二栅导电层(522)构成所述第二栅极结构(520)。
  17. 根据权利要求16所述的存储单元结构制备方法，其中，还包括：
    去除所述第一栅介质层(511)位于所述沟道结构的第二部分(420)的顶面的部分，得到暴露出所述第二部分的顶面的第一过孔；
    去除所述第一栅介质层(511)位于所述沟道结构的第三部分(430)的顶面的部分，得到暴露出所述第三部分的顶面的第二过孔；
    形成贯穿所述第一过孔并与所述第二部分的顶面接触连接的源极电极结构(710)；
    形成贯穿所述第二过孔并与所述第三部分的顶面接触连接的漏极电极结构(720)。
  18. 根据权利要求16或17所述的存储单元结构制备方法，其中，还包括：
    于所述第一栅导电层(512)的顶面形成第一栅电极结构(513)；
    于所述第二栅导电层(522)的顶面形成第二栅电极结构(523)。
  19. 根据权利要求14-18任一项所述的存储单元结构制备方法，其中，所述于所述衬底(10)的表面形成隔离结构(20)，包括：
    于所述衬底(10)的表面形成第一氧化物隔离层(210)；
    于所述第一氧化物隔离层(210)远离所述衬底(10)的表面形成氮化物隔离层(220)；
    于所述氮化物隔离层(220)远离所述衬底(10)的表面形成第二氧化物隔离层(230)。
  20. 根据权利要求14-18任一项所述的存储单元结构制备方法，其中：
    所述沟道结构(40)的材料包括：多晶硅、铟镓锌氧化物、砷化铟镓、氮化镓或其组合：及/或
    所述浮体单元结构(30)的材料包括掺杂多晶硅。
PCT/CN2023/088416 2022-10-10 2023-04-14 存储单元结构及其制备方法、读写电路及存储器 WO2024077910A1 (zh)

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US20090173984A1 (en) * 2008-01-08 2009-07-09 Qimonda Ag Integrated circuit and method of manufacturing an integrated circuit
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