WO2022078004A1 - 半导体结构及其制作方法、存储器 - Google Patents

半导体结构及其制作方法、存储器 Download PDF

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WO2022078004A1
WO2022078004A1 PCT/CN2021/109353 CN2021109353W WO2022078004A1 WO 2022078004 A1 WO2022078004 A1 WO 2022078004A1 CN 2021109353 W CN2021109353 W CN 2021109353W WO 2022078004 A1 WO2022078004 A1 WO 2022078004A1
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Prior art keywords
bit line
layer
line contact
substrate
conductive layer
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PCT/CN2021/109353
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English (en)
French (fr)
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刘志拯
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长鑫存储技术有限公司
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Priority to US17/523,084 priority Critical patent/US20220122990A1/en
Publication of WO2022078004A1 publication Critical patent/WO2022078004A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Definitions

  • the embodiments of the present application relate to the technical field of semiconductors, and in particular, to a semiconductor structure, a method for fabricating the same, and a memory.
  • DRAM Dynamic Random Access Memory
  • DRAM is usually composed of many repeated memory cells, each memory cell usually includes a capacitor and a transistor, the gate of the transistor is connected to the word line (Word Line, WL), and the drain is connected to the bit line (Bit Line, abbreviated BL) , the source is connected to the capacitor.
  • the voltage signal on the word line can control the turning on or off of the transistor, and then read the data information stored in the capacitor through the bit line, or write the data information into the capacitor through the bit line for storage.
  • Embodiments of the present application provide a semiconductor structure, a method for fabricating the same, and a memory, which can reduce the contact resistance of the bit line contact structure.
  • an embodiment of the present application provides a semiconductor structure, and the semiconductor structure includes:
  • the substrate includes a plurality of active regions arranged in an array
  • the buried word line is located in the substrate, and each of the active regions intersects with two buried word lines;
  • the groove is located on the upper surface of the substrate, and the groove is located between two buried word lines in each of the active regions;
  • bit line contact layer filling the groove
  • the insulating layer is distributed between the two grooves, and the thickness of the upper surface of the insulating layer relative to the upper surface of the substrate is smaller than that of the upper surface of the bit line contact layer relative to the upper surface of the substrate the thickness of the upper surface of the substrate;
  • bit line conductive layer covers the bit line contact layer and the insulating layer.
  • an embodiment of the present application provides a method for fabricating a semiconductor structure, the fabrication method comprising:
  • a substrate is provided, the substrate includes buried word lines and a plurality of active regions arranged in an array, each of the active regions intersects with two buried word lines, and the upper surface of the substrate A groove is etched, and the groove is located between the two buried word lines in each of the active regions;
  • bit line contact layer depositing a bit line contact layer and an insulating layer, the bit line contact layer filling the groove, and the insulating layer is distributed between the two grooves;
  • bit line conductive layer is deposited, and the bit line conductive layer covers the bit line contact layer and the insulating layer.
  • embodiments of the present application provide a memory including the semiconductor structure provided in the first aspect.
  • the thickness of the bit line contact layer relative to the upper surface of the substrate in the first region is smaller than the thickness relative to the upper surface of the substrate in the second region, wherein the first region distributes Between the two grooves, the second region is distributed above each groove, so that when the bit line conductive layer covers the surface of the bit line contact layer, not only can it be in contact with the upper surface of the bit line contact structure, but also It can also be in contact with the sidewall of the bit line contact structure, thereby increasing the contact area between the bit line conductive layer and the bit line contact structure, thereby effectively reducing the contact resistance of the bit line contact structure and improving the performance of the memory.
  • FIG. 1 is a schematic process flow diagram of a method for fabricating a semiconductor device provided in an embodiment of the application
  • FIG. 2 is a schematic diagram of word line distribution of a semiconductor device provided in an embodiment of the application.
  • step S101 is performed in an embodiment of the present application
  • step S102 is performed in an embodiment of the present application
  • FIG. 5 is a schematic cross-sectional view of the semiconductor device shown in FIG. 2 in the AB direction when step S103 is performed in an embodiment of the present application;
  • FIG. 6 is a schematic cross-sectional view of the semiconductor device shown in FIG. 2 in the AB direction when step S104 is performed in the embodiment of the present application;
  • FIG. 7 is a schematic cross-sectional view of the semiconductor device shown in FIG. 2 along the AB direction during processing.
  • DRAM As a common semiconductor memory device, DRAM usually consists of many repeated memory cells. Wherein, each memory cell is mainly composed of a transistor and a capacitor controlled by the transistor, and the memory cells are arranged in an array form, and each memory cell is electrically connected to each other through word lines and bit lines.
  • each memory cell is mainly composed of a transistor and a capacitor controlled by the transistor, and the memory cells are arranged in an array form, and each memory cell is electrically connected to each other through word lines and bit lines.
  • the contact area between the formed bit line contact structure and the bit line conductive layer is also getting smaller and smaller, resulting in higher contact area of the bit line contact structure.
  • the resistance makes it difficult for the memory cell to perform normal data reading and writing, and affects the performance of the semiconductor device.
  • the embodiments of the present application provide a semiconductor structure applied to a semiconductor memory device.
  • the bit line contact structure can be effectively reduced high contact resistance, improving the performance of the memory.
  • the exemplary term "on” may also include “under” and other orientational relationships.
  • a layer, region, pattern or structure is referred to as being “on” a substrate, layer, region and/or pattern, it can be directly on another layer or substrate, and/or intervening layers may also be present.
  • a layer is referred to as being 'under' another layer, it can be directly under the other layer, and/or one or more intervening layers may also be present.
  • FIG. 1 is a schematic process flow diagram of a method for fabricating a semiconductor device provided in an embodiment of the present application.
  • the manufacturing method of the above-mentioned semiconductor device includes:
  • the substrate includes buried word lines and a plurality of active regions arranged in an array, each active region intersects with two buried word lines, and the upper surface of the substrate is etched A recess is etched between the two buried word lines in each active region.
  • FIG. 2 is a schematic diagram of word line distribution of a semiconductor device provided in an embodiment of the present application.
  • the substrate 10 includes a plurality of active regions 50 arranged in an array, and a plurality of buried word lines 20 and bit lines 80, wherein each active region 50 and two buried Type word lines 20 intersect.
  • the substrate 10 may use any material suitable for forming a semiconductor device, for example, a p-type silicon substrate, an n-type silicon substrate, a silicon germanium substrate, etc. may be used, which is not limited in this embodiment, and may be specifically determined according to actual situation to choose.
  • FIG. 3 is a schematic cross-sectional view of the semiconductor device shown in FIG. 2 in the AB direction when step S101 is performed in an embodiment of the present application.
  • the substrate 10 has several isolation structures 12 distributed at intervals, and the isolation structures 12 isolate several active regions 50 in the substrate 10 .
  • the numbers of the isolation structures 12 and the active regions 50 can be set according to actual needs. In other embodiments, the shape and arrangement of the active regions 50 can also be adjusted according to actual needs, for example, the active regions 50 can also be folded or wavy.
  • the isolation structures 12 may be shallow trench isolation structures (STI), and each isolation structure 12 includes an isolation trench formed in the substrate 10 and an isolation dielectric such as silicon oxide filled in the isolation trench.
  • STI shallow trench isolation structures
  • the buried word line 20 is formed in the substrate 10, extends along a surface parallel to the substrate 10, and intersects the active region 50 in the substrate 10, wherein the buried word line 20 intersects the active region 50
  • the part can be used as the source of the memory transistor.
  • the buried word line hole when forming the buried word line 20 , the buried word line hole may be formed first, and then the material of the gate electrode layer and the word line conductive layer may be filled therein.
  • a plurality of grooves 11 are etched on the substrate 10 , and the grooves 11 are respectively located between the two buried word lines 20 in each active region 50 . Therein, the grooves 11 extend in a direction parallel to the surface of the substrate 10 .
  • a dry etching process and/or a wet etching process may be used to etch the surface of the substrate 10 to form the grooves 11 .
  • the cross-sectional shape of the groove 11 may be any shape suitable for device performance, such as U-shape, rectangle, inverted trapezoid, etc.
  • the size of the opening of the groove 11 can be set according to actual needs.
  • the substrate 10 further includes a word line isolation layer 21 .
  • the word line isolation layer 21 can be used to isolate the buried word line 20 from other structures formed on the substrate subsequently.
  • the word line isolation layer 21 can be made of silicon nitride or silicon oxynitride. These two materials have relatively good insulating properties, and the silicon-nitrogen bond therein is favorable for selective etching.
  • the word line isolation layer 21 may be deposited by a chemical vapor deposition (Chemical Vapor Deposition, CVD) process.
  • CVD Chemical Vapor Deposition
  • the grooves above the buried word lines 20 are first filled, and then the entire upper surface of the semiconductor substrate 101 is covered to form a complete word line isolation layer 21 .
  • a chemical mechanical polishing (Chemical Mechanical Polishing, CMP) process may also be used to planarize the upper surface of the word line isolation layer 21 to obtain a flat film layer.
  • CMP Chemical Mechanical Polishing
  • the word line isolation layer 21 and/or the substrate 10 can be selectively etched between the two buried word lines 20 located in the same active region. etch to form grooves 11 .
  • a bit line contact layer is deposited on the substrate containing the above-mentioned grooves 11 , and the bit line contact layer fills the above-mentioned grooves 11 and is distributed above the grooves 11 .
  • the bit line contact layer has a certain thickness compared to the upper surface of the word line isolation layer 21 .
  • FIG. 4 is a schematic cross-sectional view of the semiconductor device shown in FIG. 2 in the AB direction when step S102 is performed in an embodiment of the present application.
  • the material used for the bit line contact layer 31 may include polysilicon (poly).
  • polysilicon poly
  • poly can be filled in the groove 11 and distributed over the groove 11 to form a bit line contact structure.
  • the thickness between the upper surface of the insulating layer 32 and the upper surface of the substrate 10 is smaller than the thickness between the upper surface of the bit line contact structure and the upper surface of the substrate 10 .
  • polysilicon has better electrical conductivity and better contact performance with the substrate 10 .
  • the insulating layer 32 may be formed of oxide.
  • the insulating layer 32 can be selectively etched, so that part of the sidewall of the bit line contact structure can be exposed.
  • FIG. 5 is a schematic cross-sectional view of the semiconductor device shown in FIG. 2 in the AB direction when step S103 is performed in an embodiment of the present application.
  • the insulating layer in the first region 33 is selectively etched, so that the thickness h of the upper surface of the insulating layer in the first region 33 relative to the upper surface of the substrate 10 is smaller than that in the second region 33 .
  • the area above each two grooves 11 is the first area 33 ; the area above each groove 11 is the second area 34 .
  • bit line contact layer 31 will form a raised bit line contact structure, and the raised bit line contact structure will expose part of the sidewall in the etched region.
  • the oxide filled on both sides of the bit line contact structure may be etched, so that the upper surface of the oxide is lower than the upper surface of the bit line contact structure, so that part of the sidewall of the bit line contact structure is exposed.
  • bit line conductive layer may be deposited on the surface of the etched bit line contact layer and the insulating layer.
  • the deposited bit line conductive layer can cover the upper surface of the insulating layer, the upper surface of the bit line contact structure and part of the sidewall of the bit line contact structure.
  • the material of the above-mentioned bit line conductive layer may include one or more of tungsten, titanium tungsten, and titanium nitride.
  • the above-mentioned bit line conductive layer may be deposited from a variety of materials simultaneously. Formed, various material components are uniformly distributed in the bit line conductive layer.
  • FIG. 6 is a schematic cross-sectional view of the semiconductor device shown in FIG. 2 in the AB direction when step S104 is performed in an embodiment of the present application.
  • the bit line conductive layer may include a metal barrier layer 40 and a metal conductive layer 60.
  • the metal barrier layer 40 may be deposited on the upper surface of the bit line contact layer first, so that the metal barrier layer 40 can cover the surface of the bit line contact layer 31 and the insulating layer 32 . Then, a metal conductive layer 60 is deposited on the surface of the metal barrier layer 40 , so that the metal conductive layer 60 covers the surface of the metal barrier layer 40 .
  • the material used for the metal barrier layer 40 includes titanium nitride TiN, and the material used for the metal conductive layer 60 includes tungsten W.
  • a physical vapor deposition (Physical Vapor Deposition, PVD) process may be used to deposit the above-mentioned metal conductive layer 60 and metal barrier layer 40 .
  • PVD Physical Vapor Deposition
  • the embodiment of the present application changes the surface structure of the bit line contact layer in the existing semiconductor device by selectively etching the insulating layer, so that the side wall of the bit line contact structure can also be in contact with the bit line conductive layer, Therefore, the contact area between the bit line conductive layer and the bit line contact structure can be effectively increased, thereby reducing the contact resistance of the bit line contact structure and improving the performance of the memory.
  • the bit line contact structure can be improved, the process flow is simple, and the practicability is high.
  • the ratio of the thickness h of the insulating layer 32 to the thickness L of the bit line contact structure is within a preset value range.
  • the above-mentioned value interval is (1/4, 1/2), that is, in the embodiment of the present application, the ratio of the thickness of the insulating layer 32 to the thickness of the bit line contact structure may be in the value interval (1/4, 1/2) within.
  • FIG. 7 is a schematic cross-sectional view of the semiconductor device shown in FIG. 2 along the AB direction during the processing.
  • the above-mentioned manufacturing method of the semiconductor device after depositing the bit line conductive layer, the above-mentioned manufacturing method of the semiconductor device further includes:
  • a dielectric layer 70 is deposited, wherein the dielectric layer 70 covers the surface of the bit line conductive layer.
  • the material that can be used for the dielectric layer 70 includes silicon nitride SiN.
  • the dielectric layer 70 can also be made of silicon dioxide or silicon oxynitride, or can also be made of various materials among silicon nitride, silicon dioxide and silicon oxynitride. Wherein, when the dielectric layer 70 includes multiple material components, it may be a stack composed of multiple single-component film layers.
  • the fabrication of the bit line can be performed. Since silicon nitride, silicon dioxide and silicon oxynitride all have good insulation and isolation, they can insulate and isolate bit lines.
  • the present application also provides a semiconductor device.
  • the above-mentioned semiconductor device includes: a substrate 10 , a Line 20, groove 11, bit line contact layer and bit line conductive layer. in:
  • the substrate 10 includes a plurality of active regions 50 arranged in an array.
  • the buried word lines 20 are located within the substrate 10 , and each active region 50 intersects two buried word lines 20 .
  • the grooves 11 are located on the upper surface of the substrate 10 , and the grooves 11 are located between the two buried word lines 20 in each active region 50 .
  • the substrate 10 may use any material suitable for forming a semiconductor device, for example, a p-type silicon substrate, an n-type silicon substrate, a silicon germanium substrate, etc. may be used, which is not limited in this embodiment, and may be specifically determined according to actual situation to choose.
  • the substrate 10 has an isolation structure 12 , and several active regions 50 are isolated in the substrate 10 by the isolation structure 12 .
  • the active regions 50 are arranged in an array in the substrate 10 .
  • the shape and arrangement of the active regions 50 can also be adjusted according to actual needs.
  • the active regions 50 can also be of a zigzag type or a wave type.
  • the isolation structures 12 may be shallow trench isolation structures (STI), and each isolation structure 12 includes an isolation trench formed in the substrate 10 and an isolation dielectric such as silicon oxide filled in the isolation trench.
  • STI shallow trench isolation structures
  • Buried word lines 20 are formed within substrate 10 and intersect active regions 50 within substrate 10 .
  • the buried word line hole can be formed first, and then the material of the gate electrode layer and the word line conductive layer is filled into the hole.
  • a word line isolation layer 21 is also included in the substrate 10 .
  • the word line isolation layer 21 can be used to isolate the buried word line 20 from other structures formed on the substrate subsequently.
  • the word line isolation layer 21 can be made of silicon nitride or silicon oxynitride. These two materials have relatively good insulating properties, and the silicon-nitrogen bond therein is favorable for selective etching.
  • the word line isolation layer 21 and/or the substrate 10 can be etched between the two buried word lines 20 located in the same active region. Grooves 11 are formed.
  • the bit line contact layer 31 may use polysilicon (poly). Among them, polysilicon (poly) is filled in the groove 11 and distributed over the groove 11 to form a bit line contact structure.
  • the above semiconductor structure further includes an insulating layer 32 , wherein the insulating layer 32 is filled between the two bit line contact structures 31 .
  • the thickness of the upper surface of the insulating layer 32 relative to the upper surface of the substrate 10 is smaller than the thickness of the upper surface of the bit line contact layer 31 relative to the upper surface of the substrate 10, that is, the upper surface of the insulating layer 32 is lower than the bit line contact upper surface of structure 31 .
  • the bit line conductive layer includes a metal barrier layer 40 and a metal conductive layer 60 .
  • the metal barrier layer 40 covers the surface of the bit line contact layer 31 and the insulating layer 32 , and the metal conductive layer 60 covers the surface of the metal barrier layer 40 .
  • the material used for the metal barrier layer 40 includes titanium nitride TiN, and the material used for the metal conductive layer 60 includes tungsten W.
  • the side wall of the bit line contact layer 31 can also be in contact with the bit line conductive layer, which effectively increases the bit line conductive layer.
  • the contact area with the bit line contact layer 31 can reduce the contact resistance of the bit line contact layer 31 and improve the performance of the memory.
  • the ratio of the thickness h of the insulating layer 32 to the thickness L of the bit line contact structure 31 is within a preset value range .
  • the above-mentioned value interval is (1/4, 1/2), that is, in the embodiment of the present application, the ratio of the thickness of the insulating layer 32 to the thickness of the bit line contact structure 31 is in the value interval (1/4, 1/2) within.
  • the above-mentioned semiconductor device further includes a dielectric layer 70, wherein the dielectric layer 70 covers the surface of the bit line conductive layer.
  • the material used for the dielectric layer 70 may include silicon nitride SiN. Wherein, when the dielectric layer 70 includes multiple material components, it may be a stack composed of multiple single-component film layers.
  • the semiconductor device provided by the embodiment of the present application changes the surface structure of the bit line contact layer in the existing semiconductor device, so that the side wall of the bit line contact structure 31 in the bit line contact layer can also be connected with the bit line.
  • the conductive layer is in contact, so that the contact area between the bit line conductive layer and the bit line contact structure 31 can be effectively increased, thereby reducing the contact resistance of the bit line contact structure 31 and improving the performance of the memory.
  • the bit line contact structure can be improved by selectively etching the bit line contact layer, the process flow is simple, and the practicability is high.

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Abstract

一种半导体结构及其制作方法、存储器，该半导体结构包括：衬底（10），该衬底（10）内包括呈阵列排布的多个有源区；埋入式字线（20），位于衬底（10）内，且各个有源区与两个埋入式字线（20）相交；凹槽，位于衬底（10）的上表面，且位于各个有源区内的两个埋入式字线（20）之间；位线接触层（31），填充上述凹槽；绝缘层（32），分布于两个凹槽之间，该绝缘层（32）的上表面相对于衬底（10）的上表面的厚度小于位线接触层（31）的上表面相对于衬底（10）的上表面的厚度；位线导电层（40、60），覆盖于位线接触层（31）与绝缘层（32）。

Description

半导体结构及其制作方法、存储器
本申请要求于2021年01月21日提交中国专利局、申请号为202110083678.0、申请名称为“半导体结构及其制作方法、存储器”的中国专利申请的优先权，上述两件中国专利申请的全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及半导体技术领域，尤其涉及一种半导体结构及其制作方法、存储器。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)作为一种半导体存储器件，目前已被广泛使用于各种电子设备中。
DRAM通常由许多重复的存储单元组成，每个存储单元通常包括电容器和晶体管，该晶体管的栅极与字线(Word Line，简称WL)相连，漏极与位线(Bit Line，简称BL)相连，源极与电容器相连。其中，字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
随着半导体制作工艺中集成度的不断增加，提升存储器的集成密度已成为一种趋势。然而，在存储器尺寸越来越小的情况下，相应的半导体制作过程中形成的位线接触结构的接触面积也越来越小，导致位线接触结构的接触电阻增大，影响存储器的性能。
发明内容
本申请实施例提供一种半导体结构及其制作方法、存储器，可以降低位线接触结构的接触电阻。
第一方面，本申请实施例提供一种半导体结构，该半导体结构包括：
衬底，所述衬底内包括呈阵列排布的多个有源区；
埋入式字线，所述埋入式字线位于所述衬底内，且各个所述有源区与两个埋入式字线相交；
凹槽，所述凹槽位于所述衬底的上表面，且所述凹槽位于各个所述有 源区内的两个埋入式字线之间；
位线接触层，所述位线接触层填充所述凹槽；
绝缘层，所述绝缘层分布于两个所述凹槽之间，所述绝缘层的上表面相对于所述衬底的上表面的厚度小于所述位线接触层的上表面相对于所述衬底的上表面的厚度；
位线导电层，所述位线导电层覆盖于所述位线接触层与所述绝缘层。
第二方面，本申请实施例提供一种半导体结构的制作方法，该制作方法包括：
提供衬底，所述衬底内包括埋入式字线与呈阵列排布的多个有源区，各个所述有源区与两个埋入式字线相交，所述衬底的上表面刻蚀有凹槽，所述凹槽位于各个所述有源区内的两个埋入式字线之间；
沉积位线接触层与绝缘层，所述位线接触层填充所述凹槽，所述绝缘层分布于两个所述凹槽之间；
选择性刻蚀所述绝缘层，使所述绝缘层的上表面相对于所述衬底的上表面的厚度小于所述位线接触层的上表面相对于所述衬底的上表面的厚度；
沉积位线导电层，所述位线导电层覆盖所述位线接触层与所述绝缘层。
第三方面，本申请实施例提供一种存储器，包括如第一方面提供的半导体结构。
本申请实施例所提供的半导体结构，位线接触层在第一区域内相对于衬底的上表面的厚度小于在第二区域内相对于衬底的上表面的厚度，其中，第一区域分布于两个凹槽之间，第二区域分布于各个凹槽的上方，由此可以使位线导电层在覆盖于位线接触层的表面时，不仅能够与位线接触结构的上表面接触，还能够与位线接触结构的侧壁接触，从而增大了位线导电层与位线接触结构的接触面积，进而能够有效减小位线接触结构的接触电阻，提升存储器的性能。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对本申请实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其 它的附图。
图1为本申请实施例中提供的一种半导体器件的制作方法的工艺流程示意图；
图2为本申请实施例中提供的一种半导体器件的字线分布示意图；
图3为本申请实施例中执行步骤S101时图2所示半导体器件在AB方向的切面示意图；
图4为本申请实施例中执行步骤S102时图2所示半导体器件在AB方向的切面示意图；
图5为本申请实施例中执行步骤S103时图2所示半导体器件在AB方向的切面示意图；
图6为为本申请实施例中执行步骤S104时图2所示半导体器件在AB方向的切面示意图；
图7为图2所示半导体器件在加工过程中沿AB方向的一种切面示意图。
元件标号说明：
10  衬底
11  凹槽
12  隔离结构
20  字线
21  字线隔离层
31  位线接触层
32  绝缘层
33  第一区域
34  第二区域
40  金属阻挡层
50  有源区
60  金属导电层
70  介质层
80  位线
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
DRAM作为常见的半导体存储器件，通常由许多重复的存储单元组成。其中，每个存储单元主要由一个晶体管与一个由晶体管所操控的电容器所构成，且存储单元会排列成阵列形式，每一个存储单元通过字线与位线彼此电性连接。随着电子产品日益朝向轻、薄、短、小发展，DRAM的设计也必须符合高集成度、高密度的要求朝小型化的趋势发展，为提高DRAM的积集度以加快组件的操作速度，以及符合消费者对于小型化电子装置的需求，近年来发展出具有埋入式字线的DRAM，以满足上述种种需求。
然而，随着DRAM的尺寸越来越小，现有的半导体制造方法中，形成的位线接触结构与位线导电层的接触面积也越来越小，导致位线接触结构产生较高的接触电阻，使存储单元难以进行正常的数据读写，影响半导体器件的性能。
为了解决上述技术问题，本申请实施例中提供了一种应用于半导体存储器件的半导体结构，通过增大位线导电层与位线接触结构之间的接触面积，能够有效减小位线接触结构的接触电阻，提升存储器的性能。
以下结合附图和具体实施例对本申请的半导体结构及其制作方法进一步详细说明。根据下面的说明，本申请的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。应该理解，在以下的描述中，可以基于附图进行关于在各层“上”和“下”的指代。但应当理解的是，空间相对术语旨在包含除了器件在图中所描述的方位之外的在使用或操作中的不同方位。例如，如果附图中的器件被倒置或者以其他不同方式定位(如旋转)，示例性术语“在……上”也可以包括“在……下”和其他方位关系。当层、区域、图案或结构被称作在衬底、层、区域和/或图案“上”时，它可以直接位于另一个层或衬底上，和/或还可以存在插入层。类似的，当层被称作在另一个层“下”时，它可以直接位于另一个层下，和/或还可以存在一个 或多个插入层。
参照图1，图1为本申请实施例中提供的一种半导体器件的制作方法的工艺流程示意图。在本申请实施例中，上述半导体器件的制作方法包括：
S101、提供衬底，该衬底内包括埋入式字线与呈阵列排布的多个有源区，各个有源区与两个埋入式字线相交，且该衬底的上表面刻蚀有凹槽，该凹槽位于各个有源区内的两个埋入式字线之间。
为了更好的理解本申请，参照图2，图2为本申请实施例中提供的一种半导体器件的字线分布示意图。在本申请实施例中，衬底10内包括呈阵列排布的多个有源区50，以及多个埋入式字线20与位线80，其中，各个有源区50与两个埋入式字线20相交。
可选的，衬底10可以采用任何适用于形成半导体器件的材料，例如可以采用p型硅衬底、n型硅衬底、硅锗衬底等，本实施例中不做限定，具体可以根据实际情况进行选择。
参照图3，图3为本申请实施例中执行步骤S101时图2所示半导体器件在AB方向的切面示意图。
在一种可行的实施方式中，衬底10中具有若干个间隔分布的隔离结构12，该隔离结构12在衬底10内隔离出若干个有源区50。其中，隔离结构12与有源区50的数量可以根据实际需要进行设定。在其它一些实施方式中，有源区50的形状与排列方式也可以根据实际需要进行调整，例如有源区50还可以是折线型或波浪型。
其中，隔离结构12可以是浅沟槽隔离结构(STI)，每个隔离结构12包括在衬底10中形成的隔离沟槽以及在该隔离沟槽中填充的隔离介质，例如氧化硅等。
埋入式字线20形成于衬底10内，沿平行于衬底10的表面延伸，并与衬底10内的有源区50相交，其中，埋入式字线20与有源区50相交的部分可以用作存储器的晶体管的源极。
本申请一种可行的实施方式中，在形成埋入式字线20时，可以先形成埋入式字线孔，再向其中填充栅极电极层与字线导电层的材料。
在本申请实施例中，衬底10上刻蚀有多个凹槽11，该凹槽11分别位于各个有源区50内的两个埋入式字线20之间。其中，凹槽11沿平行于衬 底10表面的方向延伸。
可选的，可以利用干法刻蚀工艺和/或湿法刻蚀工艺对衬底10的表面进行刻蚀，从而形成凹槽11。其中，凹槽11的截面形状可以为U形、矩形、倒梯形等适用于器件性能的任意形状。
需要说明的是，凹槽11的开口的尺寸可以根据实际需要进行设定。
在图3中，衬底10中还包括字线隔离层21。其中，字线隔离层21可以用于隔离埋入式字线20与后续在衬底上方形成的其它结构。在一示例性实施方式中，字线隔离层21可以采用氮化硅或氮氧化硅，这两种材料的绝缘性能比较好，且其中的硅-氮键有利于进行选择性刻蚀。
可选的，可以通过化学气相沉积(Chemical Vapor Deposition，CVD)工艺沉积字线隔离层21。在沉积过程中，首先填充埋入式字线20上方的凹槽，然后覆盖整个半导体衬底101的上表面，形成完整的字线隔离层21。
在一示例性实施例中，在沉积字线隔离层21后，还可以通过化学机械研磨(Chemical Mechanical Polishing，CMP)工艺对字线隔离层21的上表面进行平坦化处理，得到平整的膜层。
其中，在形成完整的字线隔离层21之后，即可在位于同一有源区内的两个埋入式字线20之间，对字线隔离层21和/或衬底10进行选择性刻蚀，形成凹槽11。
S102、沉积位线接触层与绝缘层，该位线接触层填充上述凹槽，绝缘层分布于两个凹槽之间。
本申请实施例中，在含有上述凹槽11的衬底上沉积位线接触层，该位线接触层填充上述凹槽11，并分布在凹槽11的上方。
其中，位线接触层相较于字线隔离层21的上表面具有一定的厚度。
参照图4，图4为本申请实施例中执行步骤S102时图2所示半导体器件在AB方向的切面示意图。
如图4所示，在本申请实施例中，位线接触层31采用的材料可以包括多晶硅(poly)。
在一种可行的实施方式中，可以将多晶硅(poly)填充于凹槽11内，且分布于凹槽11的上方，形成位线接触结构(bit line contact)。
两个位线接触结构31之间为绝缘层32，绝缘层32的上表面与衬底10 的上表面之间的厚度小于位线接触结构的上表面与衬底10的上表面之间的厚度。
其中，多晶硅的导电性能较好，且与衬底10的接触性能也较好。
其中，绝缘层32可以采用氧化物形成。
S103、选择性刻蚀绝缘层，使绝缘层的上表面相对于衬底的上表面的厚度小于位线接触层的上表面相对于衬底的上表面的厚度。
本申请实施例中，在沉积位线接触层31与绝缘层32之后，即可选择性刻蚀绝缘层32，使位线接触结构的部分侧壁能够暴露出来。
参照图5，图5为本申请实施例中执行步骤S103时图2所示半导体器件在AB方向的切面示意图。在本申请实施例中，对第一区域33内的绝缘层进行选择性刻蚀，使得在第一区域33内的绝缘层的上表面相对于衬底10的上表面的厚度h小于在第二区域34内的位线接触层的上表面相对于衬底10的上表面的厚度H。
其中，每两个凹槽11之间上方的区域为第一区域33；每个凹槽11上方的区域为第二区域34。
其中，在选择性刻蚀绝缘层32之后，位线接触层31会形成凸起的位线接触结构，该凸起的位线接触结构会在刻蚀区域露出部分侧壁。
示例性的，本实施例中可以对位线接触结构两侧填充的氧化物进行刻蚀，使氧化物的上表面低于位线接触结构的上表面，从而使位线接触结构的部分侧壁暴露出来。
S104、沉积位线导电层，该位线导电层覆盖上述位线接触层与绝缘层。
本申请实施例中，在选择性刻蚀绝缘层32之后，即可在刻蚀后的位线接触层与绝缘层的表面沉积位线导电层。
其中，沉积后的位线导电层能够覆盖于绝缘层的上表面、位线接触结构的上表面以及位线接触结构的部分侧壁。
可选的，上述位线导电层的材料可以包括钨、钨化钛、氮化钛中的一种或多种，当包括多种材料时，上述位线导电层可以由多种材料同时沉积而形成，各种材料成分在位线导电层中均匀分布。
参照图6，图6为本申请实施例中执行步骤S104时图2所示半导体器件在AB方向的切面示意图。在本申请实施例中，位线导电层可以包括金 属阻挡层40与金属导电层60。
其中，可以先在位线接触层的上表面沉积金属阻挡层40，使金属阻挡层40能够覆盖在位线接触层31与绝缘层32的表面。然后再在金属阻挡层40的表面沉积金属导电层60，使金属导电层60覆盖在金属阻挡层40的表面。
可选的，金属阻挡层40采用的材料包括氮化钛TiN，金属导电层60采用的材料包括钨W。
可选的，可应采用物理气相沉积(Physical Vapor Deposition，PVD)工艺来沉积上述金属导电层60与金属阻挡层40。
可以理解的是，本申请实施例通过选择性刻蚀绝缘层，改变了现有的半导体器件中位线接触层的表面结构，使得位线接触结构的侧壁也能够与位线导电层接触，从而能够有效增大位线导电层与位线接触结构的接触面积，进而减小位线接触结构的接触电阻，提升存储器的性能。
另一方面，本申请实施例通过选择性刻蚀绝缘层，即可实现位线接触结构的改善，工艺流程简单，实用性较高。
基于上述实施例所描述的内容，仍参照图6，在本申请一种可行的实施方式中，绝缘层32的厚度h与位线接触结构的厚度L之比处于预设的取值区间内。
可选的，上述取值区间为(1/4，1/2)，即本申请实施例中，绝缘层32的厚度与位线接触结构的厚度之比可以处于取值区间(1/4，1/2)内。
基于上述实施例所描述的内容，参照图7，图7为图2所示半导体器件在加工过程中沿AB方向的一种切面示意图。在本申请一种可行的实施方式中，在沉积位线导电层之后，上述半导体器件的制作方法还包括：
沉积介质层70，其中，介质层70覆盖于位线导电层的表面。
在一示例性实施例中，介质层70可以采用的材料包括氮化硅SiN。另外，介质层70也可以采用二氧化硅或氮氧化硅，或者，还可以采用氮化硅、二氧化硅以及氮氧化硅中的多种材料。其中，当介质层70包括多种材料成分时，可以是由多个单一成分膜层组成的叠层。
在本申请一种可行的实施方式中，在制备介质层70之后，便可以进行位线的制作。由于氮化硅、二氧化硅以及氮氧化硅都具有较好的绝缘性与 隔离性，因此可以对位线起到绝缘与隔离的作用。
基于上述实施例中所描述的半导体器件的制作方法，本申请中还提供了一种半导体器件，具体可以参照图7，本申请实施例中，上述半导体器件包括：衬底10、埋入式字线20、凹槽11、位线接触层以及位线导电层。其中：
衬底10内包括呈阵列排布的多个有源区50。埋入式字线20位于衬底10内，且各个有源区50与两个埋入式字线20相交。凹槽11位于衬底10的上表面，且凹槽11位于各个有源区50内的两个埋入式字线20之间。
示例性的，衬底10可以采用任何适用于形成半导体器件的材料，例如可以采用p型硅衬底、n型硅衬底、硅锗衬底等，本实施例中不做限定，具体可以根据实际情况进行选择。
衬底10中具有隔离结构12，由隔离结构12在衬底10内隔离出若干个有源区50。其中，有源区50在衬底10中以阵列形式排布。在其它实施例中，有源区50的形状与排列方式也可以根据实际需要进行调整，例如有源区50还可以是折线型或波浪型。
其中，隔离结构12可以是浅沟槽隔离结构(STI)，每个隔离结构12包括在衬底10中形成的隔离沟槽以及在该隔离沟槽中填充的隔离介质，例如氧化硅等。
埋入式字线20形成于衬底10内，并与衬底10内的有源区50相交。
在形成埋入式字线20时，可以先形成埋入式字线孔，再向其中填充上述栅极电极层与字线导电层的材料。
衬底10中还包括字线隔离层21。其中，字线隔离层21可以用于隔离埋入式字线20与后续在衬底上方形成的其它结构。在一示例性实施方式中，字线隔离层21可以采用氮化硅或氮氧化硅，这两种材料的绝缘性能比较好，且其中的硅-氮键有利于进行选择性刻蚀。
其中，在形成完整的字线隔离层21之后，即可在位于同一有源区内的两个埋入式字线20之间，对字线隔离层21和/或衬底10进行刻蚀，形成凹槽11。
位线接触层31可以采用多晶硅(poly)。其中，多晶硅(poly)填充于凹槽11内，且分布于凹槽11的上方，以形成位线接触结构(bit line  contact)。
上述半导体结构还包括绝缘层32，其中，绝缘层32填充于两个位线接触结构31之间。
其中，绝缘层32的上表面相对于衬底10的上表面的厚度小于位线接触层31的上表面相对于衬底10的上表面的厚度，即绝缘层32的上表面低于位线接触结构31的上表面。
其中，位线导电层包括金属阻挡层40与金属导电层60。
其中，金属阻挡层40覆盖于位线接触层31与绝缘层32的表面，金属导电层60覆盖于金属阻挡层40的表面。
可选的，金属阻挡层40采用的材料包括氮化钛TiN，金属导电层60采用的材料包括钨W。
可以理解的是，由于绝缘层32的上表面低于位线接触层31的上表面，使得位线接触层31的侧壁能够也能够与位线导电层接触，有效增大了位线导电层与位线接触层31的接触面积，从而可以减小位线接触层31的接触电阻，提升存储器的性能。
基于上述实施例中所描述的内容，在本申请一种可行的实施方式中，参照图6，绝缘层32的厚度h与位线接触结构31的厚度L之比处于预设的取值区间内。
可选的，上述取值区间为(1/4，1/2)，即本申请实施例中，绝缘层32的厚度与位线接触结构31的厚度之比处于取值区间(1/4，1/2)内。
在本申请一种可行的实施方式中，上述半导体器件还包括介质层70，其中，介质层70覆盖于位线导电层的表面。
在一示例性实施例中，介质层70采用的材料可以包括氮化硅SiN。其中，当介质层70包括多种材料成分时，可以是由多个单一成分膜层组成的叠层。
可以理解的是，本申请实施例提供的半导体器件，改变了现有的半导体器件中位线接触层的表面结构，使位线接触层中的位线接触结构31的侧壁也能够与位线导电层接触，从而能够有效增大位线导电层与位线接触结构31的接触面积，进而减小位线接触结构31的接触电阻，提升存储器的性能。另一方面，本申请实施例通过选择性刻蚀位线接触层，即可实现位 线接触结构的改善，工艺流程简单，实用性较高。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (20)

  1. 一种半导体结构，所述半导体结构包括：
    衬底，所述衬底内包括呈阵列排布的多个有源区；
    埋入式字线，所述埋入式字线位于所述衬底内，且各个所述有源区与两个埋入式字线相交；
    凹槽，所述凹槽位于所述衬底的上表面，且所述凹槽位于各个所述有源区内的两个埋入式字线之间；
    位线接触层，所述位线接触层填充所述凹槽；
    绝缘层，所述绝缘层分布于两个所述凹槽之间，所述绝缘层的上表面相对于所述衬底的上表面的厚度小于所述位线接触层的上表面相对于所述衬底的上表面的厚度；
    位线导电层，所述位线导电层覆盖于所述位线接触层与所述绝缘层。
  2. 根据权利要求1所述的半导体结构，其中，所述位线接触层采用的材料包括多晶硅；所述多晶硅填充于所述凹槽内，且分布于所述凹槽的上方，以形成位线接触结构。
  3. 根据权利要求2所述的半导体结构，其中，所述绝缘层采用氧化物，所述氧化物填充于两个所述位线接触结构之间，所述氧化物的上表面与所述衬底的上表面之间的厚度小于所述位线接触结构的上表面与所述衬底的上表面之间的厚度。
  4. 根据权利要求3所述的半导体结构，其中，所述位线导电层覆盖于所述氧化物的上表面、所述位线接触结构的上表面以及所述位线接触结构的部分侧壁。
  5. 根据权利要求3所述的半导体结构，其中，所述氧化物的厚度与所述位线接触结构的厚度之比处于预设的取值区间内。
  6. 根据权利要求5所述的半导体结构，其中，所述取值区间为(1/4，1/2)。
  7. 根据权利要求1所述的半导体结构，其中，所述位线导电层包括金属阻挡层与金属导电层，所述金属阻挡层覆盖于所述位线接触层与所述绝缘层的表面，所述金属导电层覆盖于所述金属阻挡层的表面。
  8. 根据权利要求7所述的半导体结构，其中，所述金属阻挡层采用的 材料包括氮化钛，所述金属导电层采用的材料包括钨。
  9. 根据权利要求1所述的半导体结构，其中，还包括：
    介质层，所述介质层覆盖于所述位线导电层的表面。
  10. 根据权利要求9所述的半导体结构，其中，所述介质层采用的材料包括氮化硅。
  11. 一种半导体结构的制作方法，所述制作方法包括：
    提供衬底，所述衬底内包括埋入式字线与呈阵列排布的多个有源区，各个所述有源区与两个埋入式字线相交，所述衬底的上表面刻蚀有凹槽，所述凹槽位于各个所述有源区内的两个埋入式字线之间；
    沉积位线接触层与绝缘层，所述位线接触层填充所述凹槽，所述绝缘层分布于两个所述凹槽之间；
    选择性刻蚀所述绝缘层，使所述绝缘层的上表面相对于所述衬底的上表面的厚度小于所述位线接触层的上表面相对于所述衬底的上表面的厚度；
    沉积位线导电层，所述位线导电层覆盖所述位线接触层与所述绝缘层。
  12. 根据权利要求11所述的制作方法，其中，所述位线接触层采用的材料包括多晶硅；所述多晶硅填充于所述凹槽内，且分布于所述凹槽的上方，以形成位线接触结构。
  13. 根据权利要求12所述的制作方法，其中，所述绝缘层为氧化物，所述氧化物填充于两个所述位线接触结构之间；
    所述选择性刻蚀所述绝缘层，包括：
    刻蚀所述氧化物，使得所述氧化物的上表面与所述衬底的上表面之间的厚度小于所述位线接触结构的上表面与所述衬底的上表面之间的厚度。
  14. 根据权利要求13所述的制作方法，其中，所述位线导电层覆盖于所述氧化物的上表面、所述位线接触结构的上表面以及所述位线接触结构的部分侧壁。
  15. 根据权利要求13所述的制作方法，其中，所述氧化物的厚度与所述位线接触结构的厚度之比处于预设的取值区间内。
  16. 根据权利要求15所述的制作方法，其中，所述取值区间为(1/4，1/2)。
  17. 根据权利要求11所述的制作方法，其中，所述位线导电层包括金 属阻挡层与金属导电层；
    所述沉积位线接触层，包括：
    在所述位线接触层与所述绝缘层的表面沉积所述金属阻挡层；
    在所述金属阻挡层的表面沉积所述金属导电层。
  18. 根据权利要求17所述的制作方法，其中，所述金属阻挡层采用的材料包括氮化钛，所述金属导电层采用的材料包括钨。
  19. 根据权利要求11所述的制作方法，其中，所述沉积位线导电层之后，还包括：
    沉积介质层，所述介质层覆盖于所述位线导电层的表面，所述介质层采用的材料包括氮化硅。
  20. 一种存储器，包括如权利要求1所述的半导体结构。
PCT/CN2021/109353 2020-10-15 2021-07-29 半导体结构及其制作方法、存储器 WO2022078004A1 (zh)

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