WO2023226446A1 - 一种互补场效应晶体管、其制备方法、存储器及电子设备 - Google Patents

一种互补场效应晶体管、其制备方法、存储器及电子设备 Download PDF

Info

Publication number
WO2023226446A1
WO2023226446A1 PCT/CN2023/070720 CN2023070720W WO2023226446A1 WO 2023226446 A1 WO2023226446 A1 WO 2023226446A1 CN 2023070720 W CN2023070720 W CN 2023070720W WO 2023226446 A1 WO2023226446 A1 WO 2023226446A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
layer
dielectric layer
gate oxide
fet
Prior art date
Application number
PCT/CN2023/070720
Other languages
English (en)
French (fr)
Inventor
孙莹
黄凯亮
王昭桂
景蔚亮
王正波
廖恒
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2023226446A1 publication Critical patent/WO2023226446A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present application relates to the field of semiconductor technology, and in particular to a complementary field effect transistor, its preparation method, memory and electronic equipment.
  • CMOS complementary metal oxide semiconductor
  • FET Field Effect Transistor
  • TFT thin film transistor
  • CMOS logic that only relies on NMOS integration will always have one transistor in a normally open state, resulting in large static power consumption.
  • people have proposed three-dimensional structure CMOS devices.
  • FIG. 1 is a schematic structural diagram of a three-dimensional CMOS device using Low Temperature Polycrystalline Oxide (LTPO) as a conductive channel proposed in the related art.
  • the common drain 01 connects the bottom P-type channel layer 02 and the top N-type channel layer 03, and the common gate 04 controls the working status of the NMOS device and the PMOS device.
  • the first source electrode 05 is connected to the bottom P-type channel layer 02 and is connected to a high level.
  • the second source electrode 06 is connected to the top N-type channel layer 03 and is connected to a low level.
  • the material of the P-type channel layer 02 is low temperature.
  • Polysilicon the material of N-type channel layer 03 is oxide.
  • the channel layer has a planar structure, and the horizontal projected area of the CMOS device is still large.
  • high-precision photolithography technology is required.
  • This application provides a complementary field effect transistor (CFET), its preparation method, memory and electronic equipment, which can reduce the horizontal projection area of CFET without increasing process difficulty.
  • CFET complementary field effect transistor
  • a CFET which includes a first FET and a second FET stacked on a substrate, wherein one of the first FET and the second FET is an N-type FET, and the other is One FET is a P-type FET.
  • the stacked first FET and the second FET mainly include a columnar gate electrode, a gate oxide dielectric layer, a first channel layer, a second channel layer, a first electrode, a second electrode and a third electrode.
  • the gate oxide dielectric layer covers at least one side wall of the gate electrode. For example, the gate oxide dielectric layer is located on one side wall of the gate electrode, or the gate oxide dielectric layer is arranged around the gate electrode.
  • the first electrode, the second electrode and the third electrode are sequentially spaced from bottom to top and are stacked on the outer wall of the gate oxide dielectric layer.
  • the three electrodes are isolated from the gate electrode by the gate oxide dielectric layer.
  • the first electrode and the second electrode are respectively the source and drain of the first FET
  • the third electrode and the second electrode are respectively the source and drain of the second FET. That is, the first FET and the second FET share a common drain. pole.
  • the first channel layer belongs to the first FET.
  • the first channel layer is located between the first electrode and the second electrode, and the first channel layer covers the upper surface of the first electrode, the lower surface of the second electrode and the first electrode.
  • the first channel layer is isolated from the gate electrode by the gate oxide dielectric layer.
  • the first channel layer may be an N-type channel layer or a P-type channel layer.
  • the second channel layer belongs to the second FET.
  • the second channel layer is located between the second electrode and the third electrode, and the second channel layer covers the upper surface of the second electrode, the lower surface of the third electrode and the second electrode.
  • the second channel layer is isolated from the gate electrode by the gate oxide dielectric layer. If the first channel layer is an N-type channel layer, the second channel layer is a P-type channel layer; if the first channel layer is a P-type channel layer, the second channel layer is an N-type channel layer layer.
  • the channel layers of the first FET and the second FET are all arranged around or partially surrounding the gate in the vertical direction. Therefore, compared with the planar FET, the present application has a vertical annular channel (Channel- The horizontal projected areas of the first FET and the second FET of the All-Around (CAA) structure are both relatively small. Moreover, by stacking the first FET and the second FET, the horizontal projection distance between the first FET and the second FET can be reduced to 0, thereby realizing a CFET with a smaller horizontal projection area.
  • CAA All-Around
  • the channel length of the two FETs in this CFET is determined by the distance between the source and drain, it can be achieved by controlling the thickness of the film layer during preparation without relying on high-precision photolithography technology. Therefore, the preparation process is simple and the cost is low.
  • the CFET provided in this application can, if process conditions permit, increase the effective channel length of the device by increasing the height of the channel layer in the vertical direction, thereby increasing the on-current of the device.
  • the materials of the first electrode, the second electrode and the third electrode may be the same or different.
  • the materials of the first electrode, the second electrode and the third electrode may be metal conductive materials or other conductive materials, such as TiN, Ti, Au, W, Mo, In-Ti-O (ITO), In- Zn-O (IZO), Al, Cu, Ru, Ag, Pt, etc. or any combination thereof.
  • the first electrode and the second electrode both form ohmic contact with the first channel layer
  • the second electrode and the third electrode both form ohmic contact with the second channel layer.
  • the material of the gate electrode in this application can be a metal material or other conductive material, such as TiN, Ti, Au, W, Mo, ITO, IZO, Al, Cu, Ru, Ag, Pt, etc. or any of them. combination.
  • the material of the gate oxide dielectric layer in this application can be an insulating material, such as SiO x , SiN x , Al 2 O 3 , HfO 2 , ZrO 2 , TiO 2 , Y 2 O 3 , etc. or their combination materials, Laminated materials, combined laminated materials.
  • an insulating material such as SiO x , SiN x , Al 2 O 3 , HfO 2 , ZrO 2 , TiO 2 , Y 2 O 3 , etc. or their combination materials, Laminated materials, combined laminated materials.
  • the material of the N-type channel layer can be silicon-based semiconductor materials such as Si, poly-Si (polycrystalline silicon), amorphous-Si (amorphous silicon), In 2 O 3 , ZnO, Ga 2 O 3.
  • Metal oxides such as ITO and TiO 2 , multi-component compounds such as In-Ga-Zn-O (IGZO) and In-Sn-Zn-O (ISZO), two-dimensional semiconductor materials such as graphene, MoS 2 and black phosphorus, or any combination of them.
  • the material of the P-type channel layer can be silicon-based semiconductors such as Si, poly-Si, amorphous-Si, etc., P-type oxide semiconductor materials such as ZnO 2 , CuO, and NiO x , or any combination thereof. .
  • a metal layer at the interface between the source/drain and the channel layer is added.
  • An insulating layer of about 0.1nm-2nm is introduced to form a structure of semiconductor material-insulating material-metal material.
  • the CFET may further include: a first insulating layer located between the first electrode and the first channel layer, and the thickness of the first insulating layer is 0.1 nm-2 nm. And/or, the CFET may further include a second insulating layer located between the second electrode and the first channel layer, and the thickness of the second insulating layer is 0.1 nm-2 nm. And/or, the CFET may further include a third insulating layer located between the second electrode and the second channel layer, and the thickness of the third insulating layer is 0.1 nm-2 nm. And/or, the CFET may further include a fourth insulating layer located between the third electrode and the second channel layer, and the thickness of the fourth insulating layer is 0.1 nm-2 nm.
  • the CFET may further include: a first back gate and a first isolation dielectric layer located between the first electrode and the second electrode; the first isolation dielectric layer is located between The first back gate and the first channel layer are isolated by a first isolation dielectric layer, thereby forming a first FET with a double gate structure.
  • the introduction of the first back gate will not cause a significant increase in process difficulty, and the applicability is strong.
  • the CFET may also include: a second back gate and a second isolation dielectric layer located between the second electrode and the third electrode; the second isolation dielectric layer is located between The second back gate and the second channel layer, that is, the second back gate and the second channel layer are isolated by a second isolation dielectric layer, thereby forming a second FET with a double gate structure.
  • the introduction of the second back gate will not cause a significant increase in process difficulty, and the applicability is strong.
  • the materials of the first isolation dielectric layer and the second isolation dielectric layer in this application can be insulating materials, such as SiO x , SiN x , Al 2 O 3 , HfO 2 , ZrO 2 , TiO 2 , Y 2 O 3 etc. or their combination materials, laminated materials, and combined laminated materials.
  • the materials of the first back gate and the second back gate in this application can be metal materials or other conductive materials, such as TiN, Ti, Au, W, Mo, ITO, IZO, Al, Cu, Ru , Ag, Pt, etc. or any combination thereof.
  • the gate oxide dielectric layer may include a first gate oxide dielectric layer and a second gate oxide dielectric layer located above the first gate oxide dielectric layer; the first gate oxide dielectric layer and the second gate oxide dielectric layer The interface is located in the area where the second electrode is located.
  • the CFET with two gate oxide dielectric layers can respectively adjust the threshold voltage of the N-type FET and the P-type FET to adjust the symmetry of the two FETs, thereby optimizing the device performance of the CFET and reducing power consumption.
  • first gate oxide dielectric layer and the second gate oxide dielectric layer can be prepared by regional doping or sub-regional deposition, which is not limited here.
  • the CFET provided by the embodiments of the present application can be used in the peripheral circuit of the DRAM through appropriate circuit connections, thereby reducing the memory circuit occupation area and improving the integration level.
  • the implementation method of CFET provided by the embodiments of the present application is compatible with traditional microelectronics processes, and can also be applied to BEOL processes to achieve heterogeneous integration or stacked integration.
  • embodiments of the present application also provide a memory, including a memory array and a control circuit for controlling the memory array.
  • the control circuit includes the CFET as described in the first aspect or various implementations of the first aspect. Since the problem-solving principle of this memory is similar to that of the aforementioned CFET, the implementation of this memory can be referred to the implementation of the aforementioned CFET, and repeated details will not be repeated.
  • embodiments of the present application further provide an electronic device, including a housing and a CFET disposed in the housing as described in the first aspect or various implementations of the first aspect. Since the problem-solving principle of this electronic device is similar to that of the aforementioned CFET, the implementation of this electronic device can refer to the implementation of the aforementioned CFET, and repeated details will not be repeated.
  • embodiments of the present application also provide a method for preparing a complementary field effect transistor.
  • the preparation method may include the following steps:
  • the stacked structure includes a first electrode, a first sacrificial layer, a second electrode, a second sacrificial layer and a third electrode that are stacked sequentially from bottom to top;
  • one of the first channel layer and the second channel layer is an N-type channel layer, and the other is a P-type channel layer.
  • the second channel layer after depositing the second channel layer, it may further include: depositing a layer between the first electrode and the second electrode to cover the first trench. a first isolation dielectric layer of the channel layer; forming a first back gate in the gap defined by the first isolation dielectric layer.
  • the preparation method provided by the embodiment of the present application after forming the first back gate, it further includes: depositing a second channel layer covering the second channel layer between the second electrode and the third electrode. a second isolation dielectric layer; forming a second back gate in the gap defined by the second isolation dielectric layer.
  • forming a gate oxide dielectric layer on the side wall of the groove may include: depositing a first gate oxide dielectric layer on the side wall of the groove; A protective layer is deposited in the groove where the first gate oxide dielectric layer is deposited, and the height of the protective layer is between the lower surface of the second electrode and the upper surface of the second electrode; remove the The first gate oxide dielectric layer above the protective layer; depositing a second gate oxide dielectric layer covering the groove sidewalls above the first gate oxide dielectric layer; and removing the protective layer.
  • the complementary field effect transistor may also include: etching the complementary field effect transistor, and etching the complementary field effect transistor into two independent complementary field effect transistors.
  • Figure 1 is a schematic structural diagram of a three-dimensional CMOS device proposed in the related art
  • Figure 2 is a schematic diagram of the three-dimensional structure of a CFET provided by an embodiment of the present application
  • Figure 3 is a schematic cross-sectional structural diagram of the complementary field effect transistor shown in Figure 2 along the direction AA';
  • Figure 4 is a schematic diagram of the three-dimensional structure of a CFET provided by an embodiment of the present application.
  • Figure 5 is a schematic cross-sectional structural diagram of the CFET shown in Figure 4 along the direction AA’;
  • Figure 6 is a schematic circuit structure diagram of a CFET provided by an embodiment of the present application.
  • Figure 7 is a schematic cross-sectional structural diagram of a CFET provided by another embodiment of the present application.
  • Figure 8 is a schematic diagram of the three-dimensional structure of a CFET provided by another embodiment of the present application.
  • Figure 9 is a schematic cross-sectional structural diagram of the CFET shown in Figure 8 along the direction AA';
  • Figure 10 is a schematic cross-sectional structural diagram of a CFET provided by another embodiment of the present application.
  • Figure 11 is a schematic diagram of another circuit structure of a CFET provided by an embodiment of the present application.
  • Figure 12 is a schematic diagram of the three-dimensional structure of a CFET provided by another embodiment of the present application.
  • Figure 13 is a schematic cross-sectional structural diagram of the CFET shown in Figure 12 along the direction AA';
  • Figure 14 is a schematic cross-sectional structural diagram of a CFET provided by another embodiment of the present application.
  • Figure 15 is a schematic cross-sectional structural diagram of a CFET provided by another embodiment of the present application.
  • Figure 16 is a schematic top structural view of a CFET provided by an embodiment of the present application.
  • Figure 17 is a schematic top structural view of a CFET provided by another embodiment of the present application.
  • Figure 18 is a schematic top view of a CFET provided by another embodiment of the present application.
  • Figure 19 is a schematic flow chart of a CFET preparation method provided by the embodiment of the present application.
  • Figures 20a to 20l are structural schematic diagrams of the preparation process of CFET in an embodiment of the present application.
  • 21a to 21e are structural schematic diagrams of the preparation process of the gate oxide dielectric layer in an embodiment of the present application.
  • Figure 22a and Figure 22b are schematic structural diagrams of the preparation process of CFET in another embodiment of the present application.
  • Figure 23 is a schematic structural diagram of the preparation process of CFET in another embodiment of the present application.
  • Figure 24 is a simulation electrical characterization diagram of CFET provided by an embodiment of the present application.
  • Figure 25 is a schematic structural diagram of a memory provided by an embodiment of the present application.
  • Figure 26 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • 10-complementary field effect transistor 100-substrate; 11-gate; 12-gate oxide dielectric layer; 13-first channel layer; 14-second channel layer; 15-first electrode; 16-second Electrode; 17-third electrode; 12a-first gate oxide dielectric layer; 12b-second gate oxide dielectric layer; 18-first insulating layer; 19-second insulating layer; 20-third insulating layer; 21-th Four insulating layers; 22-first back gate; 23-first isolation dielectric layer; 24-second back gate; 25-second isolation dielectric layer; 10a-first FET; 10b-second FET; 31- First sacrificial layer; 32-second sacrificial layer; 33-first protective layer; 34-second protective layer; V1-groove; V2-isolation groove; 1-memory; 101-storage array; 102-control circuit; 201-casing, 202-circuit board.
  • the CFET provided by the embodiments of this application can be applied to BEOL-based memories.
  • This memory can be used for data storage in electronic devices such as mobile phones, tablets, laptops, wearable devices, and vehicle-mounted devices.
  • the complementary field effect transistor and memory provided by this application can also be applied to other electronic devices, and are not limited here.
  • Figure 2 is a schematic three-dimensional structural diagram of a CFET provided by an embodiment of the present application
  • Figure 3 is a schematic cross-sectional structural diagram of the complementary field effect transistor shown in Figure 2 along the AA' direction
  • Figure 4 is a schematic diagram of the CFET of the present application
  • An embodiment provides a schematic diagram of the three-dimensional structure of CFET
  • FIG. 5 is a schematic cross-sectional structural diagram of the CFET shown in FIG. 4 along the direction AA'.
  • the CFET 10 includes a first FET 10 a and a second FET 10 b stacked on a substrate 100 along direction Z, wherein one of the first FET 10 a and the second FET 10 b is an N-type FET, and the other FET is a P-type FET.
  • the stacked first FET 10a and the second FET 10b mainly include a columnar gate electrode 11, a gate oxide dielectric layer 12, a first channel layer 13, a second channel layer 14, a first electrode 15, a second electrode 16 and a Three electrodes17.
  • the gate oxide dielectric layer 12 covers at least one sidewall of the gate electrode 11 .
  • the gate oxide dielectric layer 12 is located on one sidewall of the gate electrode 11 , or the gate oxide dielectric layer 12 is located on one sidewall of the gate electrode 11 .
  • 12 are arranged around the gate 11 .
  • the gate 11 taking the horizontal cross-section of the gate 11 (that is, the cross-section parallel to the direction of the substrate 100) as a rectangle, the gate 11 has four sidewalls, and the gate oxide dielectric layer 12 may only cover part of the sidewalls.
  • it can cover only 1 side wall, 2 side walls, or 3 side walls as shown in Figures 4 and 5, or it can also cover all side walls as shown in Figures 2 and 3 (that is, cover 4 side walls). wall).
  • the first electrode 15 , the second electrode 16 and the third electrode 17 are sequentially spaced from bottom to top and stacked on the outer wall of the gate oxide dielectric layer 12 .
  • the three electrodes are connected to the gate oxide dielectric layer 12 through the gate oxide dielectric layer 12 .
  • Gate 11 is isolated.
  • the first electrode 15 and the second electrode 16 are the source and drain of the first FET 10 a respectively
  • the third electrode 17 and the second electrode 16 are the source and drain of the second FET 10 b respectively, that is, the first FET 10 a and the second FET 10 b.
  • the two FET10b share the drain.
  • the first channel layer 13 belongs to the first FET 10a, the first channel layer 13 is located between the first electrode 15 and the second electrode 16, and the first channel layer 13 covers the first electrode 15 The upper surface of the second electrode 16 and the exposed outer side wall of the gate oxide dielectric layer 12 between the first electrode 15 and the second electrode 16.
  • the first channel layer 13 communicates with the gate electrode 11 through the gate oxide dielectric layer 12. isolation.
  • the first channel layer 13 may be an N-type channel layer or a P-type channel layer.
  • the second channel layer 14 belongs to the second FET 10b.
  • the second channel layer 14 is located between the second electrode 16 and the third electrode 17, and the second channel layer 14 covers the upper surface of the second electrode 16 and the third electrode 17.
  • the second channel layer 14 is isolated from the gate electrode 11 by the gate oxide dielectric layer 12 . If the first channel layer 13 is an N-type channel layer, the second channel layer 14 is a P-type channel layer. If the first channel layer 13 is a P-type channel layer, the second channel layer 14 is N-type channel layer.
  • the channel layers of the first FET 10 a and the second FET 10 b are all arranged around or partially surrounding the gate 11 in the vertical direction. Therefore, compared with the planar FET, the first FET 10 a in the present application has a CAA structure. Both the horizontal projected area of the second FET 10b and the second FET 10b are relatively small. Moreover, by stacking the first FET 10 a and the second FET 10 b, the horizontal projection distance between the first FET 10 a and the second FET 10 b can be reduced to 0, thereby realizing a CFET 10 with a smaller horizontal projection area.
  • the channel length of the two FETs in the CFET10 is determined by the distance between the source and the drain, it can be achieved by controlling the thickness of the film layer during preparation without relying on high-precision photolithography technology. Therefore, the preparation process is simple and the cost is low.
  • the CFET10 provided in this application can, if process conditions permit, increase the effective channel length of the device by increasing the height of the channel layer in the vertical direction, thereby increasing the on-current of the device.
  • the schematic circuit structure diagram of the CFET 10 in this application is shown in Figure 6 .
  • the common gate 11 of the first FET 10 a and the second FET 10 b When the received signal Vin is high level, the first FET10a is in the on state, and the second FET10b is in the off state. Therefore, the signal Vout output by the common drain of the first FET10a and the second FET10b (ie, the second electrode 16) is consistent with the first The signal VSS received by the source of the FET 10a (ie, the first electrode 15) is at the same potential.
  • Vout is low level.
  • the signal Vin received by the common gate 11 of the first FET10a and the second FET10b is low level, the first FET10a is in the off state, and the second FET10b is in the on state, so the common drain of the first FET10a and the second FET10b ( That is, the signal Vout output by the second electrode 16) and the signal VDD received by the source of the second FET 10b (ie, the third electrode 17) are at the same potential.
  • VDD is high level
  • Vout is high level.
  • the materials of the three electrodes may be the same or different.
  • the materials of the first electrode 15 , the second electrode 16 and the third electrode 17 can be metal conductive materials or other conductive materials, such as TiN, Ti, Au, W, Mo, In-Ti-O (ITO) , In-Zn-O (IZO), Al, Cu, Ru, Ag, Pt, etc. or any combination thereof.
  • the first electrode 15 and the second electrode 16 both form ohmic contact with the first channel layer 13
  • the second electrode 16 and the third electrode 17 both form ohmic contact with the second channel layer 14 .
  • the material of the gate 11 in this application can be a metal material or other conductive material, such as TiN, Ti, Au, W, Mo, ITO, IZO, Al, Cu, Ru, Ag, Pt, etc. or their random combination.
  • the material of the gate oxide dielectric layer 12 in this application can be an insulating material, such as SiO x , SiN x , Al 2 O 3 , HfO 2 , ZrO 2 , TiO 2 , Y 2 O 3 , etc., or a combination thereof. , laminated materials, combined laminated materials.
  • the material of the N-type channel layer can be silicon-based semiconductor materials such as Si, poly-Si (polycrystalline silicon), amorphous-Si (amorphous silicon), In 2 O 3 , ZnO, Ga 2 O 3.
  • Metal oxides such as ITO and TiO 2 , multi-component compounds such as In-Ga-Zn-O (IGZO) and In-Sn-Zn-O (ISZO), two-dimensional semiconductor materials such as graphene, MoS 2 and black phosphorus, or any combination of them.
  • the material of the P-type channel layer can be silicon-based semiconductors such as Si, poly-Si, amorphous-Si, etc., P-type oxide semiconductor materials such as ZnO 2 , CuO, and NiO x , or any combination thereof. .
  • a metal layer at the interface between the source/drain and the channel layer is added.
  • An insulating layer of about 0.1nm-2nm is introduced to form a structure of semiconductor material-insulating material-metal material.
  • FIG. 7 is a schematic cross-sectional structural diagram of a CFET provided by yet another embodiment of the present application.
  • the CFET 10 may also include: a first insulating layer 18 located between the first electrode 15 and the first channel layer 13, and the thickness of the first insulating layer 18 is 0.1 nm-2 nm. And/or, the CFET 10 may further include a second insulating layer 19 between the second electrode 16 and the first channel layer 13 , and the thickness of the second insulating layer 19 is 0.1 nm-2 nm.
  • the CFET 10 may further include a third insulating layer 20 between the second electrode 16 and the second channel layer 14 , and the thickness of the third insulating layer 20 is 0.1 nm-2 nm. And/or, the CFET 10 may further include a fourth insulating layer 21 located between the third electrode 17 and the second channel layer 14 , and the thickness of the fourth insulating layer 21 is 0.1 nm-2 nm.
  • FIG. 7 takes the CFET 10 including the first insulating layer 18, the second insulating layer 19, the third insulating layer 20 and the fourth insulating layer 21 as an example for illustration.
  • Figure 8 is a schematic three-dimensional structural diagram of a CFET provided by another embodiment of the present application.
  • Figure 9 is a schematic cross-sectional structural diagram of the CFET shown in Figure 8 along the direction AA';
  • Figure 10 is A schematic cross-sectional structural diagram of a CFET is provided in yet another embodiment of the present application.
  • the CFET 10 may also include: a first back gate 22 and a first isolation dielectric layer 23 located between the first electrode 15 and the second electrode 16; a first isolation dielectric layer 23 It is located between the first back gate 22 and the first channel layer 13 , that is, the first back gate 22 and the first channel layer 13 are isolated by the first isolation dielectric layer 23 , thereby forming the first FET 10 a with a double gate structure.
  • the introduction of the first back gate 22 will not significantly increase the process difficulty, and the applicability is strong.
  • the CFET 10 may also include: a second back gate 24 and a second isolation dielectric layer 25 located between the second electrode 16 and the third electrode 17;
  • the isolation dielectric layer 25 is located between the second back gate 24 and the second channel layer 14 , that is, the second back gate 24 and the second channel layer 14 are isolated by the second isolation dielectric layer 25 , thereby forming a double gate structure.
  • Second FET10b the introduction of the second back gate 24 will not significantly increase the process difficulty, and the applicability is strong.
  • both the first FET 10 a and the second FET 10 b include two gate electrodes 11 , that is, in the first FET 10 a , between the first electrode 15 and the second electrode 16 A first back gate 22 and a first isolation dielectric layer 23 are disposed therebetween.
  • a second back gate 24 and a second isolation dielectric layer 25 are disposed between the second electrode 16 and the third electrode 17 .
  • the materials of the first isolation dielectric layer 23 and the second isolation dielectric layer 25 in this application can be insulating materials, such as SiO x , SiN x , Al 2 O 3 , HfO 2 , ZrO 2 , TiO 2 , Y 2 O 3 , etc. or their combination materials, laminated materials, and combined laminated materials.
  • the materials of the first back gate 22 and the second back gate 24 in this application can be metal materials or other conductive materials, such as TiN, Ti, Au, W, Mo, ITO, IZO, Al, Cu , Ru, Ag, Pt, etc. or any combination thereof.
  • both the first FET 10 a and the second FET 10 b are FETs with a double-gate structure.
  • the circuit structure diagram of the CFET 10 in this application is shown in Figure 11 As shown, when the signal Vin received by the common gate 11 of the first FET10a and the second FET10b is high level, the first FET10a is in the on state, and the second FET10b is in the off state, so the common function of the first FET10a and the second FET10b The signal Vout output by the drain is at the same potential as the signal VSS received by the source of the first FET 10 a.
  • Vout is low level.
  • the signal Vin received by the common gate 11 of the first FET10a and the second FET10b is low level, the first FET10a is in the off state, and the second FET10b is in the on state, so the common drain output of the first FET10a and the second FET10b
  • the signal Vout has the same potential as the signal VDD received by the source of the second FET 10b. For example, if VDD is high level, then Vout is high level.
  • Figure 12 is a schematic three-dimensional structural diagram of a CFET provided by another embodiment of the present application.
  • Figure 13 is a schematic cross-sectional structural diagram of the CFET shown in Figure 12 along the direction AA';
  • Figure 14 is A schematic cross-sectional structural diagram of a CFET provided by yet another embodiment of the present application;
  • FIG. 15 is a schematic cross-sectional structural diagram of a CFET provided by yet another embodiment of the present application.
  • the gate oxide dielectric layer 12 may include a first gate oxide dielectric layer 12a and a second gate oxide dielectric layer 12b located above the first gate oxide dielectric layer 12a; the first gate oxide dielectric layer 12a and the second gate oxide dielectric layer 12a.
  • the interface of layer 12b is located in the area where second electrode 16 is located.
  • the CFET10 with two gate oxide dielectric layers can respectively adjust the threshold voltages of N-type FET and P-type FET to adjust the symmetry of the two FETs, thereby optimizing the device performance of CFET10 and reducing power consumption.
  • first gate oxide dielectric layer 12a and the second gate oxide dielectric layer 12b can be prepared by regional doping or sub-regional deposition, which is not limited here.
  • the present application does not limit the shape of the cross-section of the gate 11 in the direction parallel to the substrate 100. It can be a regular shape, such as a square, a circle as shown in Figure 16, or a hexagon as shown in Figure 17 etc., of course, it can also be an irregular shape, such as a semicircular shape as shown in Figure 18.
  • the gate oxide dielectric layer 12 may be provided around the gate electrode 11 , or, as shown in FIG. 18 , the gate oxide dielectric layer 12 may also be located on one side of the gate electrode 11 .
  • CFET CFET
  • the CFET provided in this application can be implemented in a variety of ways. The following examples are only some preferred implementation methods, used to illustrate the feasibility of CFET in this application, and do not limit the scope of the application. Implementing the CFET of the present application through other process methods or sequences is also within the protection scope of the present application.
  • Figure 19 is a schematic flow chart of a CFET preparation method provided by an embodiment of the present application.
  • the preparation method may include the following steps:
  • Step S101 as shown in FIG. 20a, a stacked layer structure is formed on the substrate 100, wherein the stacked layer structure includes a first electrode 15, a first sacrificial layer 31, a second electrode 16, a second sacrificial layer 32 and a Third electrode 17.
  • Step S102 Form a groove V1 penetrating the laminated structure.
  • multiple CFET10 will generally be formed on the substrate 100.
  • two CFET10 are used as an example.
  • the stacked structure is processed through an etching process.
  • the substrate 100 is etched until the substrate 100 is exposed, thereby forming two grooves V1 penetrating the stacked structure.
  • Step S103 Form a gate oxide dielectric layer 12 on the sidewall of the groove V1.
  • ALD and other technologies can be used to form the gate oxide dielectric layer 12 on the sidewalls of the groove V1 and the upper surface of the stacked structure.
  • the gate oxide dielectric layer 12 includes a first gate oxide dielectric layer 12a and a second gate oxide dielectric layer 12b
  • the first gate oxide dielectric layer 12a and the second gate oxide dielectric layer 12b may be formed in the following manner:
  • a first gate oxide dielectric layer 12a is deposited on the sidewall of the groove V1;
  • a first protective layer 33 is deposited in the groove V1 with the first gate oxide dielectric layer 12a deposited on the sidewall, and the height of the first protective layer 33 is located between the lower surface of the second electrode 16 and the second electrode 16. between the upper surfaces of electrodes 16;
  • a second gate oxide dielectric layer 12b covering the sidewalls of the groove V1 is deposited above the first gate oxide dielectric layer 12a;
  • the first protective layer 33 is removed.
  • Step S104 as shown in FIG. 20d, fill the groove V1 with the gate oxide dielectric layer 12 deposited on the sidewall with the gate electrode 11.
  • the gate oxide dielectric layer 12 and the gate electrode 11 on the upper surface of the stacked structure are removed by chemical mechanical polishing.
  • isolation trenches as shown in Figure 20f are etched between any adjacent CFETs 10 by dry etching.
  • Step S105 as shown in FIG. 20g, remove the first sacrificial layer 31.
  • the first sacrificial layer 31 can be selectively etched and removed through a wet etching method.
  • Step S106 deposit a third layer on the upper surface of the first electrode 15, the lower surface of the second electrode 16, and the outer side wall of the exposed gate oxide dielectric layer 12 between the first electrode 15 and the second electrode 16.
  • a channel layer 13 deposit a third layer on the upper surface of the first electrode 15, the lower surface of the second electrode 16, and the outer side wall of the exposed gate oxide dielectric layer 12 between the first electrode 15 and the second electrode 16.
  • the first channel layer 13 covering the entire surface layer can be formed through an ALD process, and then through a dry etching method, leaving only the upper surface of the first electrode 15, the lower surface of the second electrode 16, and The first channel layer 13 is exposed on the outer side wall of the gate oxide dielectric layer 12 between the first electrode 15 and the second electrode 16 .
  • a second protective layer 34 covering the first channel layer 13 is deposited to prevent subsequent material of the second channel layer 14 from being deposited on the surface of the first channel layer 13 .
  • Step S107 remove the second sacrificial layer 32.
  • the second sacrificial layer 32 can be selectively etched and removed through a wet etching method.
  • Step S108 deposit a third layer on the upper surface of the second electrode 16, the lower surface of the third electrode 17, and the outer side wall of the exposed gate oxide dielectric layer 12 between the second electrode 16 and the third electrode 17.
  • the second channel layer 14 covering the entire surface layer can be formed through an ALD process, and then through a dry etching method, leaving only the upper surface of the second electrode 16, the lower surface of the third electrode 17, and The second channel layer 14 on the outer side wall of the gate oxide dielectric layer 12 is exposed between the second electrode 16 and the third electrode 17, and then the second protective layer 34 is removed, thereby forming two CFETs as shown in FIG. 20l.
  • one of the first channel layer 13 and the second channel layer 14 is an N-type channel layer, and the other is a P-type channel layer.
  • the second channel layer 14 after depositing the second channel layer 14, it may also include: depositing a third layer covering the first channel layer 13 between the first electrode 15 and the second electrode 16.
  • An isolation dielectric layer 23; the first back gate 22 is formed in the gap defined by the first isolation dielectric layer 23.
  • the first back gate 22 after forming the first back gate 22 , it may also include: depositing a third layer covering the second channel layer 14 between the second electrode 16 and the third electrode 17 . Two isolation dielectric layers 25; a second back gate 24 is formed in the gap defined by the second isolation dielectric layer 25.
  • the CFET 10 when the CFET 10 also includes the first insulating layer 18 , the second insulating layer 19 , the third insulating layer 20 and the fourth insulating layer 21 , the first insulating layer 18 and the second insulating layer 19.
  • the first electrode 15, the first insulating layer 18, the first sacrificial layer 31, and the second insulating layer 19 are sequentially formed on the substrate 100.
  • the CFET 10 includes a first electrode 15 , a second electrode 16 , a third electrode 17 , a gate electrode 11 , a gate oxide dielectric layer 12 , a first channel layer 13 and a second channel layer 14 .
  • the channel layers of the first FET 10 a and the second FET 10 b are all arranged around or partially surrounding the gate 11 in the vertical direction. Therefore, compared with the planar FET, the CFET in the present application has a CAA structure.
  • the horizontal projected areas of both the first FET 10 a and the second FET 10 b are relatively small.
  • the horizontal projection distance between the first FET 10 a and the second FET 10 b can be reduced to 0, thereby realizing a CFET 10 with a smaller horizontal projection area.
  • the channel length of the two FETs in the CFET 10 is determined by the distance between the source and the drain, it can be achieved by controlling the thickness of the first sacrificial layer 31 and the second sacrificial layer 32 during preparation. It relies on high-precision photolithography technology, so the preparation process is simple and the cost is low.
  • FIG. 24 The electrical characterization diagram of the simulation of the CFET provided by the embodiment of this application is shown in Figure 24. It can be seen from Figure 24 that the CFET formed by vertically stacking N-type FET and P-type FET with CAA structure can achieve good performance. Voltage transfer characteristics. Moreover, this application can reduce the projection pitch of N-type FET and P-type FET to 0nm without requiring ultra-high-precision photolithography, thereby improving the integration of the device. At the same time, this application has the advantages of simple process, relatively low preparation cost, and compatibility with traditional microelectronics processes. It can be applied in BEOL processes to achieve heterogeneous integration or stacked integration.
  • the CFET provided by the embodiments of the present application can be used in the peripheral circuit of the DRAM through appropriate circuit connections, thereby reducing the memory circuit occupation area and improving the integration level.
  • the implementation method of CFET provided by the embodiments of the present application is compatible with traditional microelectronics processes, and can also be applied to BEOL processes to achieve heterogeneous integration or stacked integration.
  • An embodiment of the present application also provides a transmitter, including a circuit board and the power amplifier electrically connected to the circuit board. Since the problem-solving principle of this transmitter is similar to that of the foregoing power amplifier, the implementation of this transmitter can refer to the implementation of the foregoing power amplifier, and repeated details will not be repeated.
  • an embodiment of the present application also provides a memory 1, which includes a memory array 101 and a control circuit 102 connected to the memory array 101 for controlling the memory array 101.
  • the control circuit 102 includes any CFET provided in the above embodiments of the application. Since the problem-solving principle of the memory 1 is similar to that of the aforementioned CFET, the implementation of the memory 1 can refer to the implementation of the aforementioned CFET, and repeated details will not be described again.
  • an embodiment of the present application also provides an electronic device, which includes a housing 201 and any CFET provided in the above embodiments of the present application disposed in the housing 201 .
  • a circuit board 202 is provided in the casing, and the CFET can be disposed in the circuit board 202. Since the principle of solving problems of this electronic device is similar to that of the aforementioned CFET, the electronic device has For implementation, please refer to the aforementioned implementation of CFET, and the repeated points will not be repeated.

Abstract

一种互补场效应晶体管、其制备方法、存储器及电子设备。其中，该互补场效应晶体管中包括第一FET和第二FET，第一FET和第二FET中一个FET为N型FET，另一个FET为P型FET。由于第一FET和第二FET的沟道层均沿垂直方向环绕或部分环绕栅极设置，因此相比平面型的FET，本申请中第一FET和第二FET的水平投影面积均比较小。并且，将第一FET和第二FET堆叠设置，可以使得第一FET和第二FET的水平投影间距缩小至0，从而实现一种水平投影面积较小的CFET。并且，由于该CFET中两个FET的沟道长度均由源极和漏极之间的距离决定，在制备时，可以通过控制膜层的厚度来实现，不需要依赖高精度的光刻技术，因此制备工艺简单，成本低。

Description

一种互补场效应晶体管、其制备方法、存储器及电子设备
相关申请的交叉引用
本申请要求在2022年05月25日提交中国专利局、申请号为202210579793.1、申请名称为“一种互补场效应晶体管、其制备方法、存储器及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种互补场效应晶体管、其制备方法、存储器及电子设备。
背景技术
随着动态随机存取存储器(Dynamic Random Access Memory，DRAM)存储密度的不断增加，对存储器外围电路的集成度要求也越来越高，传统的DRAM使用前道(Front End Of Line，FEOL)工艺互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)场效应晶体管(Field Effect Transistor，FET)作为存储单元的外围电路，给前道带来了较大的集成面积消耗及成本压力，因此，在后道(Back End Of Line，BEOL)工艺中实现CMOS器件集成不仅可以节约前道电路的占用面积，还可以实现三维集成及片上集成，成为目前发展的潜在趋势。目前，基于低温氧化物半导体的薄膜晶体管(Thin Film Transistor，TFT)技术已经可以实现稳定且性能优异的NMOS器件，但由于低温氧化物半导体的固有导电机制，使其难以实现高性能且稳定的PMOS器件，而仅靠NMOS集成的CMOS逻辑，会总有一个晶体管处于常开状态，从而导致较大的静态功耗。与此同时，为进一步减小外围电路的占用面积，缩小PMOS器件和NMOS器件的间距，人们提出了三维结构的CMOS器件。
参见图1，图1为相关技术中提出的一种以低温多晶硅氧化物(Low Temperature Polycrystalline Oxide，LTPO)为导电沟道的三维CMOS器件的结构示意图。其中，公共漏极01连接底部P型沟道层02和顶部N型沟道层03，公共栅极04控制NMOS器件和PMOS器件的工作状态。第一源极05与底部P型沟道层02相连接入高电平，第二源极06与顶部N型沟道层03相连接入低电平，P型沟道层02的材料为低温多晶硅，N型沟道层03的材料为氧化物。
但是，上述基于LTPO的CMOS器件中，沟道层为平面结构，CMOS器件的水平投影面积仍然较大，要想进一步缩小器件水平投影面积需要高精度的光刻技术。
发明内容
本申请提供一种互补场效应晶体管(Complementary Field Effect Transistor，CFET)、其制备方法、存储器及电子设备，可以在不增加工艺难度的基础上降低CFET的水平投影面积。
第一方面，本申请实施例提供的一种CFET，该CFET包括堆叠设置在衬底上的第一 FET和第二FET，其中，第一FET和第二FET中一个FET为N型FET，另一个FET为P型FET。该堆叠设置的第一FET和第二FET主要包括柱状的栅极、栅氧介质层、第一沟道层、第二沟道层、第一电极、第二电极和第三电极。栅氧介质层至少覆盖栅极的一侧侧壁，例如栅氧介质层位于栅极的一侧侧壁，或者栅氧介质层环绕栅极设置。第一电极、第二电极和第三电极由下向上依次间隔且层叠设置于栅氧介质层外侧壁，三个电极均通过栅氧介质层与栅极隔离。其中，第一电极和第二电极分别为第一FET的源极和漏极，第三电极和第二电极分别为第二FET的源极和漏极，即第一FET和第二FET共用漏极。第一沟道层属于第一FET，第一沟道层位于第一电极和第二电极之间，且第一沟道层覆盖第一电极的上表面、第二电极的下表面以及第一电极和第二电极之间裸露的栅氧介质层的外侧壁，第一沟道层通过栅氧介质层与栅极隔离。而第一沟道层可以N型沟道层，也可以为P型沟道层。第二沟道层属于第二FET，第二沟道层位于第二电极和第三电极之间，且第二沟道层覆盖第二电极的上表面、第三电极的下表面以及第二电极和第三电极之间裸露的栅氧介质层的外侧壁，第二沟道层通过栅氧介质层与栅极隔离。如果第一沟道层为N型沟道层，第二沟道层则为P型沟道层，如果第一沟道层为P型沟道层，第二沟道层则为N型沟道层。
本申请实施例提供的CFET，第一FET和第二FET的沟道层均沿垂直方向环绕或部分环绕栅极设置，因此相比平面型的FET，本申请中具有垂直环形沟道(Channel-All-Around，CAA)结构的第一FET和第二FET的水平投影面积均比较小。并且，将第一FET和第二FET堆叠设置，可以使得第一FET和第二FET的水平投影间距缩小至0，从而实现一种水平投影面积较小的CFET。并且，由于该CFET中两个FET的沟道长度均由源极和漏极之间的距离决定，在制备时，可以通过控制膜层的厚度来实现，不需要依赖高精度的光刻技术，因此制备工艺简单，成本低。
本申请提供的CFET，在工艺条件允许的情况下，可以通过增加沟道层在垂直方向的高度来增大器件的有效沟道长度，从而提高器件的开电流。
本申请对第一电极、第二电极以及第三电极的材料不作限定，三个电极的材料可以相同，也可以不相同。示例性的，第一电极、第二电极以及第三电极的材料可以为金属导电材料或其它导电性材料，如TiN、Ti、Au、W、Mo、In-Ti-O(ITO)、In-Zn-O(IZO)、Al、Cu、Ru、Ag、Pt等或者它们的任意组合。第一电极和第二电极均与第一沟道层形成欧姆接触，第二电极和第三电极均与第二沟道层形成欧姆接触。
示例性的，本申请中栅极的材料可以为金属材料或其它导电性材料，如TiN、Ti、Au、W、Mo、ITO、IZO、Al、Cu、Ru、Ag、Pt等或者它们的任意组合。
示例性的，本申请中栅氧介质层的材料可以为绝缘材料，如SiO x、SiN x、Al 2O 3、HfO 2、ZrO 2、TiO 2、Y 2O 3等或者它们的组合材料、叠层材料、组合叠层材料。
示例性的，在本申请中N型沟道层的材料可以为Si、poly-Si(多晶硅)、amorphous-Si(非晶硅)等硅基半导体材料，In 2O 3、ZnO、Ga 2O 3、ITO、TiO 2等金属氧化物，In-Ga-Zn-O(IGZO)、In-Sn-Zn-O(ISZO)等多元化合物，石墨烯、MoS 2、黑磷等二维半导体材料或者它们的任意组合。
示例性的，在本申请中P型沟道层的材料可以为Si、poly-Si、amorphous-Si等硅基半导体，ZnO 2、CuO以及NiO x等P型氧化物半导体材料或它们的任意组合。
进一步地，为了避免源极\漏极的金属在与沟道层接触的界面处发生扩散，以降低接触面的费米钉扎效应，可以在源极\漏极与沟道层接触的界面处引入一层约0.1nm-2nm绝缘 层，从而形成半导体材料-绝缘材料-金属材料的结构。
示例性的，该CFET中还可以包括：位于第一电极与第一沟道层之间第一绝缘层，且第一绝缘层的厚度为0.1nm-2nm。和/或，该CFET中还可以包括位于第二电极与第一沟道层之间第二绝缘层，且第二绝缘层的厚度为0.1nm-2nm。和/或，该CFET中还可以包括位于第二电极与第二沟道层之间第三绝缘层，且第三绝缘层的厚度为0.1nm-2nm。和/或，该CFET中还可以包括位于第三电极与第二沟道层之间第四绝缘层，且第四绝缘层的厚度为0.1nm-2nm。
示例性的，为了提升第一FET的栅控能力，该CFET中还可以包括：位于第一电极与第二电极之间的第一背栅极和第一隔离介质层；第一隔离介质层位于第一背栅极与第一沟道层之间，即第一背栅极和第一沟道层通过第一隔离介质层隔离，从而形成双栅结构的第一FET。并且，第一背栅极的引入并不会导致工艺难度的大幅度增加，可适用性较强。
同理的，为了提升第二FET的栅控能力，该CFET中还可以包括：位于第二电极与第三电极之间的第二背栅极和第二隔离介质层；第二隔离介质层位于第二背栅极与第二沟道层之间，即第二背栅极和第二沟道层通过第二隔离介质层隔离，从而形成双栅结构的第二FET。并且，第二背栅极的引入并不会导致工艺难度的大幅度增加，可适用性较强。
示例性的，本申请中第一隔离介质层和第二隔离介质层的材料可以为绝缘材料，如SiO x、SiN x、Al 2O 3、HfO 2、ZrO 2、TiO 2、Y 2O 3等或者它们的组合材料、叠层材料、组合叠层材料。
示例性的，本申请中第一背栅极和第二背栅极的材料可以为金属材料或其它导电性材料，如TiN、Ti、Au、W、Mo、ITO、IZO、Al、Cu、Ru、Ag、Pt等或者它们的任意组合。
示例性的，该CFET中，栅氧介质层可以包括第一栅氧介质层和位于第一栅氧介质层上方的第二栅氧介质层；第一栅氧介质层与第二栅氧介质层的交界面位于第二电极所在的区域。该具有两种栅氧介质层的CFET，可以分别调控N型FET和P型FET的阈值电压，以调节两种FET的对称性，从而优化CFET的器件性能，降低功耗。
其中，第一栅氧介质层和第二栅氧介质层可以通过区域掺杂或者分区域沉积方法制备，在此不作限定。
在具体实施时，本申请实施例提供的CFET，可通过合适的电路连接应用于DRAM的外围电路中，从而可以缩小存储器的电路占用面积，提高集成度。此外，本申请实施例提供的CFET的实现方式与传统的微电子工艺相兼容，还可应用于BEOL工艺，实现异质集成或堆叠集成。
第二方面，本申请实施例还提供了一种存储器，包括存储阵列和控制该存储阵列的控制电路，该控制电路中包括如第一方面或第一方面的各种实施方式所述的CFET。由于该存储器解决问题的原理与前述一种CFET相似，因此该存储器的实施可以参见前述CFET的实施，重复之处不再赘述。
上述第二方面可以达到的技术效果可以参照上述第一方面中任一可能设计可以达到的技术效果说明，这里不再重复赘述。
第三方面，本申请实施例还提供了一种电子设备，包括壳体和设置在壳体内的如第一方面或第一方面的各种实施方式所述的CFET。由于该电子设备解决问题的原理与前述一种CFET相似，因此该电子设备的实施可以参见前述CFET的实施，重复之处不再赘述。
上述第三方面可以达到的技术效果可以参照上述第一方面中任一可能设计可以达到 的技术效果说明，这里不再重复赘述。
第四方面，本申请实施例还提供了一种互补场效应晶体管的制备方法，该制备方法可以包括以下步骤：
在衬底上形成叠层结构，其中所述叠层结构包括由下向上依次层叠设置的第一电极、第一牺牲层、第二电极、第二牺牲层和第三电极；
形成贯穿所述叠层结构的凹槽；
在所述凹槽的侧壁形成栅氧介质层；
在侧壁沉积形成有所述栅氧介质层的凹槽内填充栅极；
去除所述第一牺牲层；
在所述第一电极的上表面、所述第二电极的下表面以及所述第一电极和所述第二电极之间裸露的所述栅氧介质层的外侧壁沉积第一沟道层；
去除所述第二牺牲层；
在所述第二电极的上表面、所述第三电极的下表面以及所述第二电极和所述第三电极之间裸露的所述栅氧介质层的外侧壁沉积第二沟道层；
其中，所述第一沟道层和所述第二沟道层中之一为N型沟道层，另一为P型沟道层。
可选的，在本申请实施例提供的制备方法中，在沉积所述第二沟道层之后还可以包括：在所述第一电极与所述第二电极之间沉积覆盖所述第一沟道层的第一隔离介质层；在所述第一隔离介质层所限定的间隙中形成第一背栅极。
进一步的，在本申请实施例提供的制备方法中，在形成所述第一背栅极之后还包括：在所述第二电极与所述第三电极之间沉积覆盖所述第二沟道层的第二隔离介质层；在所述第二隔离介质层所限定的间隙中形成第二背栅极。
可选的，在本申请实施例提供的制备方法中，在所述凹槽的侧壁形成栅氧介质层可以包括：在所述凹槽的侧壁沉积第一栅氧介质层；在侧壁沉积有所述第一栅氧介质层的凹槽内沉积保护层，且所述保护层的高度位于所述第二电极的下表面与所述第二电极的上表面之间；去除位于所述保护层上方的所述第一栅氧介质层；在所述第一栅氧介质层上方沉积覆盖所述凹槽侧壁的第二栅氧介质层；去除所述保护层。
进一步的，在形成所述互补场效应晶体管之后，还可以包括：对所述互补场效应晶体管进行刻蚀，将所述互补场效应晶体管刻蚀成两个独立的互补场效应晶体管。
附图说明
图1为相关技术中提出的一种三维CMOS器件的结构示意图；
图2为本申请一种实施例提供的CFET的三维结构示意图；
图3为图2所示的互补场效应晶体管沿AA’方向的剖面结构示意图；
图4为本申请一种实施例提供的CFET的三维结构示意图；
图5为图4所示的CFET沿AA’方向的剖面结构示意图；
图6为本申请实施例提供的CFET的一种电路结构示意图；
图7为本申请又一种实施例提供的CFET的剖面结构示意图；
图8为本申请又一种实施例提供的CFET的三维结构示意图；
图9为图8所示的CFET沿AA’方向的剖面结构示意图；
图10为本申请又一种实施例提供的CFET的剖面结构示意图；
图11为本申请实施例提供的CFET的另一种电路结构示意图；
图12为本申请又一种实施例提供的CFET的三维结构示意图；
图13为图12所示的CFET沿AA’方向的剖面结构示意图；
图14为本申请又一种实施例提供的CFET的剖面结构示意图；
图15为本申请又一种实施例提供的CFET的剖面结构示意图；
图16为本申请一种实施例提供的CFET的俯视结构示意图；
图17为本申请另一种实施例提供的CFET的俯视结构示意图；
图18为本申请又一种实施例提供的CFET的俯视结构示意图；
图19为本申请实施例提供的一种CFET的制备方法的流程示意图；
图20a至图20l为本申请一种实施例中CFET的制备过程的结构示意图；
图21a至图21e为本申请一种实施例中栅氧介质层的制备过程的结构示意图；
图22a和图22b本申请另一种实施例中CFET的制备过程的结构示意图；
图23为本申请又一种实施例中CFET的制备过程的结构示意图；
图24为本申请一种实施例提供的CFET的模拟仿真电学表征图；
图25为本申请实施例提供的一种存储器的结构示意图；
图26为本申请实施例提供的一种电子设备的结构示意图。
附图标记说明：
10-互补场效应晶体管；100-衬底；11-栅极；12-栅氧介质层；13-第一沟道层；14-第二沟道层；15-第一电极；16-第二电极；17-第三电极；12a-第一栅氧介质层；12b-第二栅氧介质层；18-第一绝缘层；19-第二绝缘层；20-第三绝缘层；21-第四绝缘层；22-第一背栅极；23-第一隔离介质层；24-第二背栅极；25-第二隔离介质层；10a-第一FET；10b-第二FET；31-第一牺牲层；32-第二牺牲层；33-第一保护层；34-第二保护层；V1-凹槽；V2-隔离槽；1-存储器；101-存储阵列；102-控制电路；201-壳体，202-电路板。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
应注意的是，在本说明书中，相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。
在本申请的描述中，需要说明的是，术语“中”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。本申请中所描述的表达位置与方向的词，均是以附图为例进行的说明，但根据需要也可以做出改变，所做改变均包含在本发明保护范围内。本申请的附图仅用于示意相对位置关系不代表真实比例。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。
为了方便理解本申请实施例提供的技术方法，下面首先介绍一下其应用场景。本申请实施例提供的CFET可以应用于基于BEOL的存储器中。该存储器可用于手机、平板电脑、笔记本电脑、可穿戴设备、车载设备等电子设备中的数据存储。当然，本申请提供的互补场效应晶体管和存储器也可以应用于其他电子设备中，在此不作限定。
下面结合附图来说明本申请技术方案中的CFET、其制备方法、存储器及电子设备。
参见图2至图5，图2为本申请一种实施例提供的CFET的三维结构示意图；图3为图2所示的互补场效应晶体管沿AA’方向的剖面结构示意图；图4为本申请一种实施例提供的CFET的三维结构示意图；图5为图4所示的CFET沿AA’方向的剖面结构示意图。该CFET10包括沿方向Z堆叠设置在衬底100上的第一FET10a和第二FET10b，其中，第一FET10a和第二FET10b中一个FET为N型FET，另一个FET为P型FET。该堆叠设置的第一FET10a和第二FET10b主要包括柱状的栅极11、栅氧介质层12、第一沟道层13、第二沟道层14、第一电极15、第二电极16和第三电极17。
继续参见图2至图5，在本申请中，栅氧介质层12至少覆盖栅极11的一侧侧壁，例如栅氧介质层12位于栅极11的一侧侧壁，或者栅氧介质层12环绕栅极11设置。示例性的，以栅极11的水平截面(即平行于衬底100方向的截面)为矩形为例，栅极11具有4个侧壁，栅氧介质层12可以是仅覆盖其中部分侧壁，例如可以仅覆盖1个侧壁、2个侧壁或者或如图4和图5所示的3个侧壁，还可以覆盖如图2和图3所示的所有侧壁(即覆盖4个侧壁)。
继续参见图2至图5，第一电极15、第二电极16和第三电极17由下向上依次间隔且层叠设置于栅氧介质层12外侧壁，三个电极均通过栅氧介质层12与栅极11隔离。其中，第一电极15和第二电极16分别为第一FET10a的源极和漏极，第三电极17和第二电极16分别为第二FET10b的源极和漏极，即第一FET10a和第二FET10b共用漏极。
继续参见图2至图5，第一沟道层13属于第一FET10a，第一沟道层13位于第一电极15和第二电极16之间，且第一沟道层13覆盖第一电极15的上表面、第二电极16的下表面以及第一电极15和第二电极16之间裸露的栅氧介质层12的外侧壁，第一沟道层13通过栅氧介质层12与栅极11隔离。而第一沟道层13可以N型沟道层，也可以为P型沟道层。第二沟道层14属于第二FET10b，第二沟道层14位于第二电极16和第三电极17之间，且第二沟道层14覆盖第二电极16的上表面、第三电极17的下表面以及第二电极16和第三电极17之间裸露的栅氧介质层12的外侧壁，第二沟道层14通过栅氧介质层12与栅极11隔离。如果第一沟道层13为N型沟道层，第二沟道层14则为P型沟道层，如果第一沟道层13为P型沟道层，第二沟道层14则为N型沟道层。
本申请实施例提供的CFET10，第一FET10a和第二FET10b的沟道层均沿垂直方向环绕或部分环绕栅极11设置，因此相比平面型的FET，本申请中具有CAA结构的第一FET10a和第二FET10b的水平投影面积均比较小。并且，将第一FET10a和第二FET10b堆叠设置，可以使得第一FET10a和第二FET10b的水平投影间距缩小至0，从而实现一种水平投影面积较小的CFET10。并且，由于该CFET10中两个FET的沟道长度均由源极和漏极之间的距离决定，在制备时，可以通过控制膜层的厚度来实现，不需要依赖高精度的光刻技术，因此制备工艺简单，成本低。
本申请提供的CFET10，在工艺条件允许的情况下，可以通过增加沟道层在垂直方向的高度来增大器件的有效沟道长度，从而提高器件的开电流。
示例性的，以第一FET10a为N型FET，第二FET10b为P型FET为例，本申请中CFET10的电路结构示意图如图6所示，当第一FET10a和第二FET10b的共用栅极11接收的信号Vin为高电平时，第一FET10a处于开启状态，而第二FET10b处于关闭状态，因此第一FET10a和第二FET10b的共用漏极(即第二电极16)输出的信号Vout与第一FET10a 的源极(即第一电极15)接收的信号VSS等电位，例如VSS为低电平，则Vout为低电平。当第一FET10a和第二FET10b的共用栅极11接收的信号Vin为低电平时，第一FET10a处于关闭状态，而第二FET10b处于开启状态，因此第一FET10a和第二FET10b的共用漏极(即第二电极16)输出的信号Vout与第二FET10b的源极(即第三电极17)接收的信号VDD等电位，例如VDD为高电平，则Vout为高电平。
本申请对第一电极15、第二电极16以及第三电极17的材料不作限定，三个电极的材料可以相同，也可以不相同。示例性的，第一电极15、第二电极16以及第三电极17的材料可以为金属导电材料或其它导电性材料，如TiN、Ti、Au、W、Mo、In-Ti-O(ITO)、In-Zn-O(IZO)、Al、Cu、Ru、Ag、Pt等或者它们的任意组合。第一电极15和第二电极16均与第一沟道层13形成欧姆接触，第二电极16和第三电极17均与第二沟道层14形成欧姆接触。
示例性的，本申请中栅极11的材料可以为金属材料或其它导电性材料，如TiN、Ti、Au、W、Mo、ITO、IZO、Al、Cu、Ru、Ag、Pt等或者它们的任意组合。
示例性的，本申请中栅氧介质层12的材料可以为绝缘材料，如SiO x、SiN x、Al 2O 3、HfO 2、ZrO 2、TiO 2、Y 2O 3等或者它们的组合材料、叠层材料、组合叠层材料。
示例性的，在本申请中N型沟道层的材料可以为Si、poly-Si(多晶硅)、amorphous-Si(非晶硅)等硅基半导体材料，In 2O 3、ZnO、Ga 2O 3、ITO、TiO 2等金属氧化物，In-Ga-Zn-O(IGZO)、In-Sn-Zn-O(ISZO)等多元化合物，石墨烯、MoS 2、黑磷等二维半导体材料或者它们的任意组合。
示例性的，在本申请中P型沟道层的材料可以为Si、poly-Si、amorphous-Si等硅基半导体，ZnO 2、CuO以及NiO x等P型氧化物半导体材料或它们的任意组合。
进一步地，为了避免源极\漏极的金属在与沟道层接触的界面处发生扩散，以降低接触面的费米钉扎效应，可以在源极\漏极与沟道层接触的界面处引入一层约0.1nm-2nm绝缘层，从而形成半导体材料-绝缘材料-金属材料的结构。
示例性的，参见图7，图7为本申请又一种实施例提供的CFET的剖面结构示意图。该CFET10中还可以包括：位于第一电极15与第一沟道层13之间第一绝缘层18，且第一绝缘层18的厚度为0.1nm-2nm。和/或，该CFET10中还可以包括位于第二电极16与第一沟道层13之间第二绝缘层19，且第二绝缘层19的厚度为0.1nm-2nm。和/或，该CFET10中还可以包括位于第二电极16与第二沟道层14之间第三绝缘层20，且第三绝缘层20的厚度为0.1nm-2nm。和/或，该CFET10中还可以包括位于第三电极17与第二沟道层14之间第四绝缘层21，且第四绝缘层21的厚度为0.1nm-2nm。其中，图7中以CFET10中包括第一绝缘层18、第二绝缘层19、第三绝缘层20和第四绝缘层21为例进行示意。
示例性的，参见图8至图10，图8为本申请又一种实施例提供的CFET的三维结构示意图，图9为图8所示的CFET沿AA’方向的剖面结构示意图；图10为本申请又一种实施例提供的CFET的剖面结构示意图。为了提升第一FET10a的栅控能力，该CFET10中还可以包括：位于第一电极15与第二电极16之间的第一背栅极22和第一隔离介质层23；第一隔离介质层23位于第一背栅极22与第一沟道层13之间，即第一背栅极22和第一沟道层13通过第一隔离介质层23隔离，从而形成双栅结构的第一FET10a。并且，第一背栅极22的引入并不会导致工艺难度的大幅度增加，可适用性较强。同理的，为了提升第二FET10b的栅控能力，该CFET10中还可以包括：位于第二电极16与第三电极17之间的第 二背栅极24和第二隔离介质层25；第二隔离介质层25位于第二背栅极24与第二沟道层14之间，即第二背栅极24和第二沟道层14通过第二隔离介质层25隔离，从而形成双栅结构的第二FET10b。并且，第二背栅极24的引入并不会导致工艺难度的大幅度增加，可适用性较强。
示例性的，如图8至图10所示，该CFET10中，第一FET10a和第二FET10b中均包括两个栅极11，即在第一FET10a中，第一电极15与第二电极16之间设置有第一背栅极22和第一隔离介质层23，在第二FET10b中，第二电极16与第三电极17之间设置有第二背栅极24和第二隔离介质层25。
示例性的，本申请中第一隔离介质层23和第二隔离介质层25的材料可以为绝缘材料，如SiO x、SiN x、Al 2O 3、HfO 2、ZrO 2、TiO 2、Y 2O 3等或者它们的组合材料、叠层材料、组合叠层材料。
示例性的，本申请中第一背栅极22和第二背栅极24的材料可以为金属材料或其它导电性材料，如TiN、Ti、Au、W、Mo、ITO、IZO、Al、Cu、Ru、Ag、Pt等或者它们的任意组合。
示例性的，以第一FET10a为N型FET，第二FET10b为P型FET为例，第一FET10a和第二FET10b均为具有双栅结构的FET，本申请中CFET10的电路结构示意图如图11所示，当第一FET10a和第二FET10b的共用栅极11接收的信号Vin为高电平时，第一FET10a处于开启状态，而第二FET10b处于关闭状态，因此第一FET10a和第二FET10b的共用漏极输出的信号Vout与第一FET10a的源极接收的信号VSS等电位，例如VSS为低电平，则Vout为低电平。当第一FET10a和第二FET10b的共用栅极11接收的信号Vin为低电平时，第一FET10a处于关闭状态，而第二FET10b处于开启状态，因此第一FET10a和第二FET10b的共用漏极输出的信号Vout与第二FET10b的源极接收的信号VDD等电位，例如VDD为高电平，则Vout为高电平。
示例性的，参见图12至图15，图12为本申请又一种实施例提供的CFET的三维结构示意图，图13为图12所示的CFET沿AA’方向的剖面结构示意图；图14为本申请又一种实施例提供的CFET的剖面结构示意图；图15为本申请又一种实施例提供的CFET的剖面结构示意图。该CFET10中，栅氧介质层12可以包括第一栅氧介质层12a和位于第一栅氧介质层12a上方的第二栅氧介质层12b；第一栅氧介质层12a与第二栅氧介质层12b的交界面位于第二电极16所在的区域。该具有两种栅氧介质层的CFET10，可以分别调控N型FET和P型FET的阈值电压，以调节两种FET的对称性，从而优化CFET10的器件性能，降低功耗。
其中，第一栅氧介质层12a和第二栅氧介质层12b可以通过区域掺杂或者分区域沉积方法制备，在此不作限定。
需要说明的是，本申请对栅极11在平行于衬底100方向的截面的形状不作限定，可以是规则的形状，例如正方形、图16所示的圆形、图17所示的六边形等，当然也可以是不规则的形状，例如图18所示的类半圆形。示例性的，如图16和图17所示，栅氧介质层12可以环绕栅极11设置，或者，如图18所示，栅氧介质层12也可以位于栅极11的一侧。
为方便理解本申请实施例提供的CFET，下面结合制备方法对本申请实施例提供的上述CFET进行进一步的说明。
需要注意的是，本申请提供的CFET可以通过多种方式实现。下面实施例仅仅是一些 优选实现方法，用于阐述本申请CFET的可行性，不对申请的范围进行限制。通过其它工艺方法或顺序实现本申请的CFET的，亦在本申请的保护范围之内。
参见图19，图19为本申请实施例提供的一种CFET的制备方法的流程示意图。该制备方法可以包括以下步骤：
步骤S101、如图20a所示，在衬底100上形成叠层结构，其中叠层结构包括依次层叠设置的第一电极15、第一牺牲层31、第二电极16、第二牺牲层32和第三电极17。
步骤S102、形成贯穿叠层结构的凹槽V1。
在具体实施时，在制备CFET10时，一般会在衬底100上形成多个CFET10，示例性的，以两个CFET10为例进行示意，如图20b所示，通过刻蚀工艺对叠层结构进行刻蚀直至露出衬底100，从而形成贯穿叠层结构的两个凹槽V1。
步骤S103、在凹槽V1的侧壁形成栅氧介质层12。
示例性的，如图20c所示，可以采用ALD等技术在凹槽V1的侧壁以及叠层结构的上表面形成栅氧介质层12。
可选地，当栅氧介质层12包括第一栅氧介质层12a和第二栅氧介质层12b时，可以通过以下方式形成第一栅氧介质层12a和第二栅氧介质层12b：
如图21a所示，在凹槽V1的侧壁沉积第一栅氧介质层12a；
如图21b所示，在侧壁沉积形成有第一栅氧介质层12a的凹槽V1内沉积第一保护层33，且第一保护层33的高度位于第二电极16的下表面与第二电极16的上表面之间；
如图21c所示，去除位于第一保护层33上方的第一栅氧介质层12a；
如图21d所示，在第一栅氧介质层12a上方沉积覆盖凹槽V1侧壁的第二栅氧介质层12b；
如图21e所示，去除第一保护层33。
步骤S104、如图20d所示，在侧壁沉积形成有栅氧介质层12的凹槽V1内填充栅极11。
如图20e所示，通过化学机械磨平方法去除叠层结构的上表面的栅氧介质层12和栅极11。
进一步地，当在衬底100上同时形成多个CFET10时，为了隔离不同的CFET10，在任意相邻的CFET10之间通过干法刻蚀方法刻蚀出如图20f所示的隔离槽。
步骤S105、如图20g所示，去除第一牺牲层31。
示例性的，可以通过湿法刻蚀方法选择性腐蚀去除第一牺牲层31。
步骤S106、如图20h所示，在第一电极15的上表面、第二电极16的下表面、以及第一电极15和第二电极16之间裸露的栅氧介质层12的外侧壁沉积第一沟道层13。
示例性的，可以通过ALD工艺形成覆盖整个表面层的第一沟道层13，然后通过干法刻蚀方法，只留下位于第一电极15的上表面、第二电极16的下表面、以及第一电极15和第二电极16之间裸露的栅氧介质层12的外侧壁的第一沟道层13。
在具体实施时，如图20i所示，沉积覆盖第一沟道层13的第二保护层34，以避免后续第二沟道层14的材料沉积在第一沟道层13的表面。
步骤S107、如图20j所示，去除第二牺牲层32。
示例性的，可以通过湿法刻蚀方法选择性腐蚀去除第二牺牲层32。
步骤S108、如图20k所示，在第二电极16的上表面、第三电极17的下表面、以及第 二电极16和第三电极17之间裸露的栅氧介质层12的外侧壁沉积第二沟道层14。
示例性的，可以通过ALD工艺形成覆盖整个表面层的第二沟道层14，然后通过干法刻蚀方法，只留下位于第二电极16的上表面、第三电极17的下表面、以及第二电极16和第三电极17之间裸露的栅氧介质层12的外侧壁的第二沟道层14，然后去除第二保护层34，从而形成如图20l所示的两个CFET。
示例性的，在本申请，第一沟道层13和第二沟道层14中之一为N型沟道层，另一为P型沟道层。
示例性的，在本申请中，如图22a所示，在沉积第二沟道层14之后还可以包括：在第一电极15与第二电极16之间沉积覆盖第一沟道层13的第一隔离介质层23；在第一隔离介质层23所限定的间隙中形成第一背栅极22。
示例性的，在本申请中，如图22b所示，在形成第一背栅极22之后还可以包括：在第二电极16与第三电极17之间沉积覆盖第二沟道层14的第二隔离介质层25；在第二隔离介质层25所限定的间隙中形成第二背栅极24。
可选地的，在本申请中，当CFET10中还包括第一绝缘层18、第二绝缘层19、第三绝缘层20和第四绝缘层21时，第一绝缘层18、第二绝缘层19、第三绝缘层20和第四绝缘层21可以在形成叠层结构时，在衬底100上依次形成第一电极15、第一绝缘层18、第一牺牲层31、第二绝缘层19、第二电极16、第三绝缘层20、第二牺牲层32、第四绝缘层21和第三电极17。
在本申请，对于上述任意结构的CFET10，还可以通过简单的光刻、刻蚀技术形成两个CFET10。示例性的，以CFET10中包括第一电极15、第二电极16、第三电极17、栅极11、栅氧介质层12、第一沟道层13和第二沟道层14为例进行示意，参见图23，以图23中的CFET10为例；在形成该CFET10之后，对该CFET10进行刻蚀，例如沿图中BB’方向进行刻蚀，去除CFET10中各膜层的部分区域，将各膜层均分割成两部分，从而将CFET10分割成两个独立的CFET10(1)和CFET10(2)，即将图23中的一个CFET10分割成图23中的两个CFET：CFET10(1)和CFET10(2)，原CFET10中各膜层的两部分分别属于该两个独立的CFET10(1)和CFET10(2)。从而可以在不增加工艺难度的条件下，通过简单的光刻、刻蚀技术就可在相同的投影面积下，实现双倍的集成度。
综上，本申请实施例提供的CFET10，第一FET10a和第二FET10b的沟道层均沿垂直方向环绕或部分环绕栅极11设置，因此相比平面型的FET，本申请中具有CAA结构的第一FET10a和第二FET10b的水平投影面积均比较小。并且，将第一FET10a和第二FET10b堆叠设置，可以使得第一FET10a和第二FET10b的水平投影间距缩小至0，从而实现一种水平投影面积较小的CFET10。并且，由于该CFET10中两个FET的沟道长度均由源极和漏极之间的距离决定，在制备时，可以通过控制第一牺牲层31和第二牺牲层32的厚度来实现，不需要依赖高精度的光刻技术，因此制备工艺简单，成本低。
本申请实施例提供的CFET，模拟仿真的电学表征图如图24所示，由图24可以看出，本申请通过垂直堆叠具有CAA结构的N型FET和P型FET形成的CFET可以实现良好的电压转移特性。并且，本申请可在不需要超高精度光刻的条件下，将N型FET和P型FET的投影间距缩小至0nm，从而可以提高器件的集成度。同时本申请具有工艺简单，制备成本相对较低，与传统的微电子工艺相兼容等优势，可应用于BEOL工艺中，实现异质集成或堆叠集成。
在具体实施时，本申请实施例提供的CFET，可通过合适的电路连接应用于DRAM的外围电路中，从而可以缩小存储器的电路占用面积，提高集成度。此外，本申请实施例提供的CFET的实现方式与传统的微电子工艺相兼容，还可应用于BEOL工艺，实现异质集成或堆叠集成。
本申请实施例还提供了一种发射机，包括电路板和与所述电路板电连接的所述功率放大器。由于该发射机解决问题的原理与前述一种功率放大器相似，因此该发射机的实施可以参见前述功率放大器的实施，重复之处不再赘述。
相应地，参见图25，本申请实施例还提供了一种存储器1，该存储器1中包括存储阵列101和与该存储阵列101连接的用于控制该存储阵列101的控制电路102，该控制电路102中包括本申请上述实施例提供的任一种CFET。由于该存储器1解决问题的原理与前述一种CFET相似，因此该存储器1的实施可以参见前述CFET的实施，重复之处不再赘述。
相应地，参见图26，本申请实施例还提供了一种电子设备，该电子设备包括壳体201和设置在该壳体201内的本申请上述实施例提供的任一种CFET。示例性，以该电子设备为手机为例，壳体内设置有电路板202，该CFET可以设置在电路板202中，由于该电子设备解决问题的原理与前述一种CFET相似，因此该电子设备的实施可以参见前述CFET的实施，重复之处不再赘述。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (13)

  1. 一种互补场效应晶体管，其特征在于，包括：
    柱状的栅极；
    至少覆盖所述栅极一侧侧壁的栅氧介质层；
    位于所述栅氧介质层外侧壁、且由下向上依次间隔层叠设置的第一电极、第二电极和第三电极；
    位于所述第一电极和所述第二电极之间的第一沟道层，且所述第一沟道层覆盖所述第一电极的上表面、所述第二电极的下表面以及所述第一电极和所述第二电极之间裸露的所述栅氧介质层的外侧壁；
    位于所述第二电极和所述第三电极之间的第二沟道层，所述第二沟道层覆盖所述第二电极的上表面、所述第三电极的下表面以及所述第二电极和所述第三电极之间裸露的所述栅氧介质层的外侧壁；
    其中，所述第一沟道层和所述第二沟道层中之一为N型沟道层，另一为P型沟道层。
  2. 如权利要求1所述的互补场效应晶体管，其特征在于，所述互补场效应晶体管还包括：
    位于所述第一电极与所述第二电极之间的第一背栅极和第一隔离介质层，且所述第一隔离介质层位于所述第一背栅极与所述第一沟道层之间。
  3. 如权利要求1或2所述的互补场效应晶体管，其特征在于，所述互补场效应晶体管还包括：
    位于所述第二电极与所述第三电极之间的第二背栅极和第二隔离介质层，且所述第二隔离介质层位于所述第二背栅极与所述第二沟道层之间。
  4. 如权利要求1-3任一项所述的互补场效应晶体管，其特征在于，所述栅氧介质层包括第一栅氧介质层和位于所述第一栅氧介质层上方的第二栅氧介质层；
    所述第一栅氧介质层与所述第二栅氧介质层的交界面位于所述第二电极所在的区域。
  5. 如权利要求1-4任一项所述的互补场效应晶体管，其特征在于，所述互补场效应晶体管还包括：
    位于所述第一电极与所述第一沟道层之间第一绝缘层，且所述第一绝缘层的厚度为0.1nm-2nm；
    和/或，位于所述第二电极与所述第一沟道层之间第二绝缘层，且所述第二绝缘层的厚度为0.1nm-2nm；
    和/或，位于所述第二电极与所述第二沟道层之间第三绝缘层，且所述第三绝缘层的厚度为0.1nm-2nm；
    和/或，位于所述第三电极与所述第二沟道层之间第四绝缘层，且所述第四绝缘层的厚度为0.1nm-2nm。
  6. 如权利要求1-5任一项所述的互补场效应晶体管，其特征在于，所述栅氧介质层环绕所述栅极设置。
  7. 一种存储器，其特征在于，包括存储阵列和控制所述存储阵列的控制电路，所述控制电路中包括如权利要求1-6任一项所述的互补场效应晶体管。
  8. 一种电子设备，其特征在于，包括壳体和设置在所述壳体内的如权利要求1-6任一项所述的互补场效应晶体管。
  9. 一种互补场效应晶体管的制备方法，其特征在于，包括：
    在衬底上形成叠层结构，其中所述叠层结构包括由下向上依次层叠设置的第一电极、第一牺牲层、第二电极、第二牺牲层和第三电极；
    形成贯穿所述叠层结构的凹槽；
    在所述凹槽的侧壁形成栅氧介质层；
    在侧壁沉积形成有所述栅氧介质层的凹槽内填充栅极；
    去除所述第一牺牲层；
    在所述第一电极的上表面、所述第二电极的下表面以及所述第一电极和所述第二电极之间裸露的所述栅氧介质层的外侧壁沉积第一沟道层；
    去除所述第二牺牲层；
    在所述第二电极的上表面、所述第三电极的下表面以及所述第二电极和所述第三电极之间裸露的所述栅氧介质层的外侧壁沉积第二沟道层；
    其中，所述第一沟道层和所述第二沟道层中之一为N型沟道层，另一为P型沟道层。
  10. 如权利要求9所述的制备方法，其特征在于，在沉积所述第二沟道层之后还包括：
    在所述第一电极与所述第二电极之间沉积覆盖所述第一沟道层的第一隔离介质层；
    在所述第一隔离介质层所限定的间隙中形成第一背栅极。
  11. 如权利要求10所述的制备方法，其特征在于，在形成所述第一背栅极之后还包括：
    在所述第二电极与所述第三电极之间沉积覆盖所述第二沟道层的第二隔离介质层；
    在所述第二隔离介质层所限定的间隙中形成第二背栅极。
  12. 如权利要求9-11任一项所述的制备方法，其特征在于，在所述凹槽的侧壁形成栅氧介质层，包括：
    在所述凹槽的侧壁沉积第一栅氧介质层；
    在侧壁沉积有所述第一栅氧介质层的凹槽内沉积保护层，且所述保护层的高度位于所述第二电极的下表面与所述第二电极的上表面之间；
    去除位于所述保护层上方的所述第一栅氧介质层；
    在所述第一栅氧介质层上方沉积覆盖所述凹槽侧壁的第二栅氧介质层；
    去除所述保护层。
  13. 如权利要求9-12任一项所述的制备方法，其特征在于，在形成所述互补场效应晶体管之后，还包括：对所述互补场效应晶体管进行刻蚀，将所述互补场效应晶体管刻蚀成两个独立的互补场效应晶体管。
PCT/CN2023/070720 2022-05-25 2023-01-05 一种互补场效应晶体管、其制备方法、存储器及电子设备 WO2023226446A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210579793.1A CN117199073A (zh) 2022-05-25 2022-05-25 一种互补场效应晶体管、其制备方法、存储器及电子设备
CN202210579793.1 2022-05-25

Publications (1)

Publication Number Publication Date
WO2023226446A1 true WO2023226446A1 (zh) 2023-11-30

Family

ID=88918329

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/070720 WO2023226446A1 (zh) 2022-05-25 2023-01-05 一种互补场效应晶体管、其制备方法、存储器及电子设备

Country Status (2)

Country Link
CN (1) CN117199073A (zh)
WO (1) WO2023226446A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5140388A (en) * 1991-03-22 1992-08-18 Hewlett-Packard Company Vertical metal-oxide semiconductor devices
US20140070327A1 (en) * 2012-09-11 2014-03-13 Texas Instruments Incorporated Replacement Metal Gate Process for CMOS Integrated Circuits
US20180212054A1 (en) * 2017-01-23 2018-07-26 International Business Machines Corporation Vertical transistor with enhanced drive current
CN111755512A (zh) * 2019-03-27 2020-10-09 芯恩（青岛）集成电路有限公司 一种半导体器件及其制备方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5140388A (en) * 1991-03-22 1992-08-18 Hewlett-Packard Company Vertical metal-oxide semiconductor devices
US20140070327A1 (en) * 2012-09-11 2014-03-13 Texas Instruments Incorporated Replacement Metal Gate Process for CMOS Integrated Circuits
US20180212054A1 (en) * 2017-01-23 2018-07-26 International Business Machines Corporation Vertical transistor with enhanced drive current
CN111755512A (zh) * 2019-03-27 2020-10-09 芯恩（青岛）集成电路有限公司 一种半导体器件及其制备方法

Also Published As

Publication number Publication date
CN117199073A (zh) 2023-12-08

Similar Documents

Publication Publication Date Title
JP6955060B2 (ja) トランジスタ
WO2023097743A1 (zh) 半导体存储单元结构、半导体存储器及其制备方法、应用
US11721735B2 (en) Thin film transistors having U-shaped features
US20180226416A1 (en) Structure featuring ferroelectric capacitance in interconnect level for steep sub-threshold complementary metal oxide semiconductor transistors
US20140291755A1 (en) Semiconductor device and semiconductor module
CN104160507A (zh) 在三栅极（finfet）工艺上集成多个栅极电介质晶体管的方法
CN104377197A (zh) 半导体器件及其制造方法
TWI546966B (zh) 形成於相同塊狀基板上的隔離及塊狀半導體裝置
JP2009038201A (ja) 半導体装置および半導体装置の製造方法
US20200220024A1 (en) Charge trap layer in back-gated thin-film transistors
US10304736B2 (en) Self-aligned contact
WO2023284123A1 (zh) 半导体结构及其制造方法
CN111900168A (zh) 存储单元、存储器件及电子设备
CN116322041B (zh) 存储器及其制造方法、电子设备
CN105655334A (zh) 在三栅极（finfet）工艺上集成多个栅极电介质晶体管的方法
US9991266B2 (en) Semiconductor memory device and semiconductor memory array comprising the same
WO2019132939A1 (en) Shielded capacitors and embedded memory employing shielded capacitors
US20240057312A1 (en) Array structure, semiconductor structure, and method for manufacturing semiconductor structure
US11296229B2 (en) Vertical thin film transistors having self-aligned contacts
US11411119B2 (en) Double gated thin film transistors
WO2023226446A1 (zh) 一种互补场效应晶体管、其制备方法、存储器及电子设备
CN116133407B (zh) 一种半导体器件结构及其制造方法、dram和电子设备
CN116234305B (zh) 一种半导体器件结构及其制造方法、dram和电子设备
JPWO2012077178A1 (ja) 半導体装置
WO2023197769A1 (zh) 一种cmos反相器、存储芯片、存储器及电子装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23810523

Country of ref document: EP

Kind code of ref document: A1