WO2023206677A1 - Goa电路及显示面板 - Google Patents

Goa电路及显示面板 Download PDF

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Publication number
WO2023206677A1
WO2023206677A1 PCT/CN2022/094910 CN2022094910W WO2023206677A1 WO 2023206677 A1 WO2023206677 A1 WO 2023206677A1 CN 2022094910 W CN2022094910 W CN 2022094910W WO 2023206677 A1 WO2023206677 A1 WO 2023206677A1
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WO
WIPO (PCT)
Prior art keywords
transistor
pull
signal
level
node
Prior art date
Application number
PCT/CN2022/094910
Other languages
English (en)
French (fr)
Inventor
任蕫壎
杨慧
Original Assignee
惠州华星光电显示有限公司
Tcl华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 惠州华星光电显示有限公司, Tcl华星光电技术有限公司 filed Critical 惠州华星光电显示有限公司
Priority to US17/780,981 priority Critical patent/US20240161677A1/en
Publication of WO2023206677A1 publication Critical patent/WO2023206677A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • This application relates to the field of display technology, and specifically to a GOA circuit and a display panel.
  • Gate Driver On Array (GOA) technology integrates gate drive circuits on the array substrate of the display panel to achieve a progressive scanning driving method.
  • This driving technology can eliminate the need for gate drivers, has the advantages of reducing production costs and achieving narrow bezel designs for panels, and is used by a variety of displays.
  • the GOA circuit usually includes a pull-down maintenance module.
  • the pull-down maintenance module is always in working state during the pull-down period, which affects its working life and in turn affects the working stability of the GOA circuit.
  • This application provides a GOA circuit and a display panel to solve the technical problem in the existing GOA circuit that the pull-down maintenance module of the GOA unit is always in a working state and the working life is reduced, thereby affecting the working stability of the GOA circuit.
  • the Nth level GOA unit includes: a pull-up control module, a pull-up output module, a pull-down module and a pull-down maintenance module;
  • the pull-up control module is connected to a control signal and a pull-up signal, and is connected to a pull-up node, for outputting the pull-up signal to the pull-up signal under the control of the control signal and the pull-up signal.
  • the pull-up output module is connected to the clock signal and is connected to the pull-up node, the Nth level scanning signal output end and the Nth level transmission signal output end, and is used to adjust the potential sum of the pull-up node Under the control of the clock signal, the Nth level scanning signal and the Nth level transmission signal are output;
  • the pull-down module is connected to the N+m-th level transmission signal and the reference low-level signal, and is connected to the pull-up node and the N-th level scanning signal output terminal, for use in the N+m-th level
  • the potential of the pull-up node and the Nth stage scan signal output terminal is pulled down under the control of the stage transmission signal and the reference low-level signal
  • the pull-down maintenance module is connected to the low-frequency clock signal, the clock signal and the reference low-level signal, and is connected to the pull-up node and the N-th level scan signal output terminal for controlling the low-frequency clock signal.
  • the potential of the N-th level scanning signal output terminal and the pull-up node is maintained under the control of the signal, the clock signal and the reference low-level signal.
  • the pull-up control module includes a first transistor
  • the gate of the first transistor is connected to the control signal or the pull-up signal, the source of the first transistor is connected to the pull-up signal, and the drain of the first transistor is connected to the pull-up signal. Pull node.
  • the pull-up output module includes a second transistor, a third transistor and a bootstrap capacitor
  • the gate of the second transistor, the gate of the third transistor and one end of the bootstrap capacitor are all connected to the pull-up node, and the source of the second transistor and the source of the third transistor are connected to the pull-up node. Both terminals are connected to the clock signal, the drain of the second transistor is connected to the Nth stage signal output terminal, the drain of the third transistor and the other end of the bootstrap capacitor are both connected to The Nth level scanning signal output terminal.
  • the pull-down module includes a fourth transistor and a fifth transistor
  • the gate electrode of the fourth transistor and the gate electrode of the fifth transistor are both connected to the N+mth level scanning signal, and the source electrode of the fourth transistor and the source electrode of the fifth transistor are both connected to The reference low level signal, the drain of the fourth transistor is connected to the pull-up node, and the drain of the fifth transistor is connected to the Nth level scan signal output terminal.
  • the pull-down sustain module includes a first pull-down sustain unit and a second pull-down sustain unit
  • the low-frequency clock signal includes a first low-frequency clock signal and a second low-frequency clock signal
  • the first pull-down maintaining unit is connected to the first low-frequency clock signal and the reference low-level signal, and is connected to the pull-up node and the Nth level scan signal output terminal for maintaining the The potential of the Nth level scan signal output terminal;
  • the second pull-down holding unit is connected to the second low-frequency clock signal, the reference low-level signal and the clock signal, and is connected to the pull-up node and the The Nth level scanning signal output terminal is used to maintain the potential of the pull-up node and the Nth level scanning signal output terminal.
  • the first low-frequency clock signal and the second low-frequency clock signal remain in opposite phases.
  • the first low-frequency clock signal and the second low-frequency clock signal remain in the same phase.
  • the first pull-down holding unit includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor;
  • the gate electrode of the sixth transistor, the source electrode of the sixth transistor, and the source electrode of the seventh transistor are all connected to the first low-frequency clock signal, and the drain electrode of the sixth transistor, the seventh transistor
  • the gate electrode of the transistor and the drain electrode of the eighth transistor are connected together, and the drain electrode of the seventh transistor, the drain electrode of the ninth transistor and the gate electrode of the tenth transistor are connected to the first pull-down node.
  • the gate electrode of the eighth transistor and the gate electrode of the ninth transistor are both connected to the pull-up node, the source electrode of the eighth transistor, the source electrode of the ninth transistor and the tenth transistor
  • the sources of the tenth transistor are all connected to the reference low level signal, and the drain of the tenth transistor is connected to the Nth level scanning signal output terminal.
  • the first pull-down holding unit further includes a seventeenth transistor, the gate of the seventeenth transistor is connected to the first pull-down node, and the gate of the seventeenth transistor is connected to the first pull-down node.
  • the source of the seventeenth transistor is connected to the reference low level signal, and the drain of the seventeenth transistor is connected to the pull-up node or the Nth stage signal output terminal.
  • the second pull-down holding unit further includes an eighteenth transistor, the gate of the eighteenth transistor is connected to the second pull-down node, and the gate of the eighteenth transistor
  • the source electrode is connected to the reference low-level signal
  • the drain electrode of the eighteenth transistor is connected to the pull-up node or the N-th stage transmission signal output end.
  • the second pull-down holding unit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor. ;
  • the gate of the eleventh transistor, the source of the eleventh transistor, and the source of the twelfth transistor are all connected to the second low-frequency clock signal.
  • the drain of the eleventh transistor, The gate of the twelfth transistor and the drain of the thirteenth transistor are connected together, and the drain of the twelfth transistor, the drain of the fourteenth transistor and the drain of the fifteenth transistor are connected together.
  • the gate is connected to the second pull-down node, the gates of the thirteenth transistor and the fourteenth transistor are both connected to the pull-up node, and the source of the thirteenth transistor and the gate of the fourteenth transistor are connected to the pull-up node.
  • the sources of the fourteenth transistor and the source of the fifteenth transistor are both connected to the reference low level signal, and the drain of the fifteenth transistor is connected to the source of the sixteenth transistor.
  • the gate of the sixteenth transistor is connected to the clock signal, and the drain of the sixteenth transistor is connected to the Nth level scanning signal output terminal.
  • the first pull-down holding unit further includes a seventeenth transistor, the gate of the seventeenth transistor is connected to the first pull-down node, and the gate of the seventeenth transistor is connected to the first pull-down node.
  • the source of the seventeenth transistor is connected to the reference low level signal, and the drain of the seventeenth transistor is connected to the pull-up node or the Nth stage signal output terminal.
  • the second pull-down holding unit further includes an eighteenth transistor, the gate of the eighteenth transistor is connected to the second pull-down node, and the eighteenth transistor The source of the transistor is connected to the reference low-level signal, and the drain of the eighteenth transistor is connected to the pull-up node or the Nth stage signal output terminal.
  • control signal is the N-mth level transmission signal or the N-mth level scanning signal
  • pull-up signal is the N-mth level transmission signal, the N-mth level transmission signal, the N-mth level transmission signal, or the N-mth level scanning signal.
  • Level scanning signal or high-level DC signal; N and m are both integers greater than 0, and N>m.
  • the pull-down sustain module includes a first pull-down sustain unit
  • the low-frequency clock signal includes a first low-frequency clock signal
  • the first pull-down sustain unit is connected to the The first low-frequency clock signal and the reference low-level signal are connected to the pull-up node and the N-th level scanning signal output terminal, and are used to maintain the potential of the N-th level scanning signal output terminal.
  • the pull-down sustain module includes a second pull-down sustain unit
  • the low-frequency clock signal includes a second low-frequency clock signal
  • the second pull-down sustain unit is connected to the second pull-down sustain unit.
  • the low-frequency clock signal, the reference low-level signal and the clock signal are connected to the pull-up node and the N-th level scan signal output terminal, and are used to maintain the pull-up node and the N-th level Scan the potential at the signal output.
  • the display panel includes a display area and a non-display area connected to the display area.
  • the display panel includes a GOA circuit, and the GOA circuit is located in the non-display area.
  • the GOA The circuit outputs multiple scanning signals to the display area.
  • the display panel includes a multi-level GOA unit.
  • the Nth level GOA unit includes: a pull-up control module, a pull-up output module, a pull-down module and a pull-down maintenance module;
  • the pull-up control module is connected to a control signal and a pull-up signal, and is connected to a pull-up node, for outputting the pull-up signal to the pull-up signal under the control of the control signal and the pull-up signal. node;
  • the pull-up output module is connected to the clock signal and is connected to the pull-up node, the N-th level scanning signal output end and the N-th level transmission signal output end, and is used to adjust the potential of the pull-up node and the Under the control of the clock signal, the Nth level scanning signal and the Nth level transmission signal are output;
  • the pull-down module is connected to the N+m-th level transmission signal and the reference low-level signal, and is connected to the pull-up node and the N-th level scanning signal output terminal, for use in the N+m-th level
  • the potential of the pull-up node and the Nth stage scan signal output terminal is pulled down under the control of the stage transmission signal and the reference low-level signal
  • the pull-down maintenance module is connected to the low-frequency clock signal, the clock signal and the reference low-level signal, and is connected to the pull-up node and the N-th level scan signal output terminal for controlling the low-frequency clock signal.
  • the potential of the N-th level scanning signal output terminal and the pull-up node is maintained under the control of the signal, the clock signal and the reference low-level signal.
  • the pull-down sustain module includes a first pull-down sustain unit and a second pull-down sustain unit
  • the low-frequency clock signal includes a first low-frequency clock signal and a second low-frequency clock signal
  • the first pull-down holding unit includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor;
  • the gate electrode of the sixth transistor, the source electrode of the sixth transistor, and the source electrode of the seventh transistor are all connected to the first low-frequency clock signal, and the drain electrode of the sixth transistor, the seventh transistor
  • the gate electrode of the transistor and the drain electrode of the eighth transistor are connected together, and the drain electrode of the seventh transistor, the drain electrode of the ninth transistor and the gate electrode of the tenth transistor are connected to the first pull-down node.
  • the gate electrode of the eighth transistor and the gate electrode of the ninth transistor are both connected to the pull-up node, the source electrode of the eighth transistor, the source electrode of the ninth transistor and the tenth transistor
  • the sources of the tenth transistor are all connected to the reference low-level signal, and the drain of the tenth transistor is connected to the Nth level scanning signal output terminal;
  • the second pull-down holding unit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor and a sixteenth transistor;
  • the gate of the eleventh transistor, the source of the eleventh transistor, and the source of the twelfth transistor are all connected to the second low-frequency clock signal.
  • the drain of the eleventh transistor, The gate of the twelfth transistor and the drain of the thirteenth transistor are connected together, and the drain of the twelfth transistor, the drain of the fourteenth transistor and the drain of the fifteenth transistor are connected together.
  • the gate is connected to the second pull-down node, the gates of the thirteenth transistor and the fourteenth transistor are both connected to the pull-up node, and the source of the thirteenth transistor and the gate of the fourteenth transistor are connected to the pull-up node.
  • the sources of the fourteenth transistor and the source of the fifteenth transistor are both connected to the reference low level signal, and the drain of the fifteenth transistor is connected to the source of the sixteenth transistor.
  • the gate of the sixteenth transistor is connected to the clock signal, and the drain of the sixteenth transistor is connected to the Nth level scanning signal output terminal.
  • the first low-frequency clock signal and the second low-frequency clock signal remain in phase or in phase.
  • control signal is the N-mth level transmission signal or the N-mth level scanning signal
  • pull-up signal is the N-mth level transmission signal, the N-mth level transmission signal, the N-mth level transmission signal, or the N-mth level scanning signal.
  • Level scanning signal or high-level DC signal; N and m are both integers greater than 0, and N>m.
  • the GOA circuit includes a multi-level GOA unit.
  • the Nth level GOA unit includes a pull-up control module, a pull-up output module, a pull-down module and a pull-down maintenance module.
  • the structure is simple. Among them, the pull-down maintenance module is connected to the clock signal and can pull down the potential of the pull-up node under the control of the clock signal. Since the clock signal is always in a state of switching between high level and low level, the working time of the pull-down maintenance module can be reduced, the working life of the pull-down maintenance module can be extended, and the working stability of the GOA circuit can be improved.
  • Figure 1 is a first structural schematic diagram of the Nth level GOA unit provided by this application.
  • Figure 2 is a first circuit schematic diagram of the Nth level GOA unit shown in Figure 1;
  • Figure 3 is a signal timing diagram of the Nth level GOA unit provided by this application.
  • Figure 4 is a second circuit schematic diagram of the Nth level GOA unit shown in Figure 1;
  • Figure 5 is a second structural schematic diagram of the Nth level GOA unit provided by this application.
  • Figure 6 is a circuit schematic diagram of the Nth level GOA unit shown in Figure 5;
  • Figure 7 is a schematic structural diagram of a display panel provided by this application.
  • This application provides a GOA circuit and a display panel, which are described in detail below. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments of the present application.
  • Figure 1 is a first structural schematic diagram of the Nth level GOA unit provided by this application.
  • the GOA circuit includes a multi-stage GOA unit 100 .
  • the Nth level GOA unit 100 includes a pull-up control module 101 , a pull-up output module 102 , a pull-down module 103 and a pull-down maintenance module 104 .
  • the pull-up control module 101 accesses the control signal EM and the pull-up signal EN, and is connected to the pull-up node Q(N).
  • the pull-up control module 101 is used to output the pull-up signal EN to the pull-up node Q(N) under the control of the control signal EM and the pull-up signal EN.
  • control signal EM may be the N-m-th stage transmission signal ST(N-m) or the N-m-th stage scanning signal G(N-m).
  • the pull-up signal EN can be an N-m-th level transmission signal ST(N-m), an N-m-th level scanning signal G(N-m), or other high-level DC signals. Thereby improving the signal connection flexibility in the GOA circuit.
  • the pull-up control module 101 can only access the N-m-th stage transmission signal ST(N-m).
  • the pull-up control module 101 may also only access the N-mth level scanning signal G(N-m).
  • the pull-up control module 101 can also access the N-mth level transmission signal ST(N-m) and the N-mth level scanning signal G(N-m) at the same time.
  • the pull-up control module 101 can also access other control signals with the same timing sequence as the N-mth level transmission signal ST(N-m) or the N-mth level scanning signal G(N-m), which is not limited in the embodiment of the present application.
  • a start signal can be set to replace the N-m-th stage transmission signal ST(N-m) and the N-m-th stage scanning signal G(N-m), which will not be described here.
  • the N+m-th stage transmission signal ST(N+m) and the N+m-th stage scanning signal G(N+m) do not exist.
  • a start signal or another signal can also be set to replace the N+m-th stage transmission signal ST(N+m) and the N+m-th stage scanning signal G(N+m).
  • virtual GOA units can also be set in the GOA circuit. It should be noted that, except for the above differences, the circuit structures and signal connections of the first m-level GOA units 100 and the last m-level GOA units 100 are the same as those of other levels of GOA units 100, and will not be described again here.
  • the pull-up output module 102 receives the clock signal CLK and is connected to the pull-up node Q(N), the N-th stage scanning signal output terminal A and the N-th stage transmission signal output terminal B.
  • the pull-up output module 102 is used to output the N-th level scanning signal G(N) and the N-th level transmission signal ST(N) under the control of the potential of the pull-up node Q(N) and the clock signal CLK.
  • the pull-down module 103 is connected to the N+m-th stage transmission signal ST(N+m) and the reference low-level signal VSS, and is connected to the pull-up node Q(N) and the N-th stage scanning signal output terminal A.
  • the pull-down module 103 is used to pull down the potential of the pull-up node Q(N) and the N-th stage scan signal output terminal A under the control of the N+m-th stage transmission signal ST(N+m) and the reference low-level signal VSS.
  • the pull-down sustain module 104 receives the low-frequency clock signal LC, the clock signal CLK and the reference low-level signal VSS, and is connected to the pull-up node Q(N) and the N-th level scan signal output terminal A.
  • the pull-down maintenance module 104 is used to maintain the potential of the N-th level scan signal output terminal A and the pull-up node Q(N) under the control of the low-frequency clock signal LC, the clock signal CLK and the reference low-level signal VSS.
  • the pull-down maintenance module 104 is connected to the clock signal CLK and can pull down the potential of the pull-up node Q(N) under the control of the clock signal CLK. Since the clock signal CLK is always switching between high level and low level, the working time of the pull-down sustaining module 104 can be reduced and the working life of the pull-down sustaining module 104 can be extended, thus improving the working stability of the GOA circuit.
  • the N-th level GOA unit 100 provided by the embodiment of the present application has a simple structure, which can reduce the size of the GOA circuit and achieve a narrow frame of the display panel.
  • the pull-up control module 101 includes a first transistor T1.
  • the gate of the first transistor T1 is connected to the control signal EM.
  • the source of the first transistor T1 is connected to the pull-up signal EN.
  • the drain of the first transistor T1 is connected to the pull-up node Q(N).
  • the gate and the source of the first transistor T1 may be respectively connected to one of the control signal EM and the pull-up signal EN.
  • the gate and source of the first transistor T1 may also be connected to the same one of the control signal EM and the pull-up signal EN at the same time.
  • the control signal EM and the pull-up signal EN please refer to the above content and will not be repeated here.
  • the gate of the first transistor T1 is connected to the N-3 level scanning signal ST(N-3), and the source of the first transistor T1 is connected to the N-3 level scanning signal G( N-3) is explained as an example, but it cannot be understood as limiting the present application.
  • the pull-up output module 102 includes a second transistor T2, a third transistor T3, and a bootstrap capacitor Cbt.
  • the gate of the second transistor T2, the gate of the third transistor T3 and one end of the bootstrap capacitor Cbt are all connected to the pull-up node Q(N).
  • the source of the second transistor T2 and the source of the third transistor T3 are both connected to the clock signal CLK.
  • the drain of the second transistor T2 is connected to the N-th stage signal output terminal B.
  • the drain of the third transistor T3 and the other end of the bootstrap capacitor Cbt are both connected to the Nth level scanning signal output terminal A.
  • the pull-down module 103 includes a fourth transistor T4 and a fifth transistor T5.
  • the gate electrode of the fourth transistor T4 and the gate electrode of the fifth transistor T5 are both connected to the N+3-th level scanning signal G(N+3).
  • the source of the fourth transistor T4 and the source of the fifth transistor T5 are both connected to the reference low level signal VSS.
  • the drain of the fourth transistor T4 is connected to the pull-up node Q(N).
  • the drain of the fifth transistor T5 is connected to the N-th level scanning signal output terminal A.
  • the pull-down maintenance module 104 includes a first pull-down maintenance unit 1041 and a second pull-down maintenance unit 1042.
  • the low-frequency clock signal LC includes a first low-frequency clock signal LC1 and a second low-frequency clock signal LC2.
  • the first pull-down holding unit 1041 is connected to the first low-frequency clock signal LC1 and the reference low-level signal VSS, and is connected to the pull-up node Q(N) and the N-th level scanning signal output terminal A.
  • the first pull-down maintaining unit 1041 is used to maintain the potential of the Nth level scanning signal output terminal A.
  • the second pull-down holding unit 1042 receives the second low-frequency clock signal LC2, the reference low-level signal VSS and the clock signal CLK, and is connected to the pull-up node Q(N) and the N-th level scanning signal output terminal A.
  • the second pull-down maintaining unit 1042 is used to maintain the potential of the pull-up node Q(N) and the N-th level scanning signal output terminal A.
  • the first low-frequency clock signal LC1 and the second low-frequency clock signal LC2 remain in inversion.
  • the first low-frequency clock signal LC1 is high level
  • the second low-frequency clock signal LC2 is low level.
  • the first low-frequency clock signal LC1 is low level
  • the second low-frequency clock signal LC2 is high level.
  • the first pull-down maintaining unit 1041 and the second pull-down maintaining unit 1042 can work alternately, thereby extending the lifespan of the first pull-down maintaining unit 1041 and the second pull-down maintaining unit 1042 .
  • the first low-frequency clock signal LC1 and the second low-frequency clock signal LC2 can also be kept in the same phase, so that the first pull-down sustaining unit 1041 and the second pull-down sustaining unit 1042 work at the same time.
  • the pull-down maintenance module 104 may only include the first pull-down maintenance unit 1041. In other embodiments of the present application, the pull-down maintenance module 104 may only include the second pull-down maintenance unit 1042. This further simplifies the structure of the GOA unit 100 and reduces the size of the GOA circuit.
  • the first pull-down holding unit 1041 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10.
  • the gate of the sixth transistor T6, the source of the sixth transistor T6, and the source of the seventh transistor T7 are all connected to the first low-frequency clock signal LC1.
  • the drain of the sixth transistor T6, the gate of the seventh transistor T7, and the drain of the eighth transistor T8 are connected together.
  • the drain of the seventh transistor T7, the drain of the ninth transistor T9, and the gate of the tenth transistor T10 are connected to the first pull-down node P(N).
  • the gate electrode of the eighth transistor T8 and the gate electrode of the ninth transistor T9 are both connected to the pull-up node Q(N).
  • the source of the eighth transistor T8, the source of the ninth transistor T9, and the source of the tenth transistor T10 are all connected to the reference low level signal VSS.
  • the drain of the tenth transistor T10 is connected to the N-th level scanning signal output terminal A.
  • the second pull-down holding unit 1042 includes an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, and a sixteenth transistor T16. .
  • the gate of the eleventh transistor T11, the source of the eleventh transistor T11, and the source of the twelfth transistor T12 are all connected to the second low-frequency clock signal LC2.
  • the drain of the eleventh transistor T11, the gate of the twelfth transistor T12, and the drain of the thirteenth transistor T13 are connected together.
  • the drain of the twelfth transistor T12 , the drain of the fourteenth transistor T14 and the gate of the fifteenth transistor T15 are connected to the second pull-down node K(N).
  • the gate electrode of the thirteenth transistor T13 and the gate electrode of the fourteenth transistor T14 are both connected to the pull-up node Q(N).
  • the source of the thirteenth transistor T13, the source of the fourteenth transistor T14, and the source of the fifteenth transistor T15 are all connected to the reference low level signal VSS.
  • the drain of the fifteenth transistor T15 and the source of the sixteenth transistor T16 are connected together.
  • the gate of the sixteenth transistor T16 is connected to the clock signal CLK.
  • the drain of the sixteenth transistor T16 is connected to the Nth stage scanning signal output terminal A.
  • Tri-gate architecture rotates all sub-pixel units 90 degrees.
  • the number of scan lines is tripled and the number of data lines is reduced to 1/3 of the original number.
  • the number of driver chips can be reduced and production costs can be reduced.
  • the wiring space occupied by the GOA circuit structure becomes larger, which is not conducive to narrowing the bezel of the display panel.
  • the N-th level GOA unit 100 only includes 16T1C (16 transistors and 1 bootstrap capacitor), with a simple structure and a small number of transistors. Therefore, the size of the GOA circuit is effectively reduced, which facilitates the realization of a narrow frame of the display panel.
  • the transistors used in all embodiments of the present application can be thin film transistors, field effect transistors, or other devices with the same characteristics. Since the source and drain of the transistor used here are symmetrical, their source and drain The poles are interchangeable. In the embodiment of the present application, in order to distinguish the two electrodes of the transistor except the gate electrode, one electrode is called the source electrode and the other electrode is called the drain electrode. According to the form in the attached figure, the middle terminal of the switching transistor is the gate, the signal input terminal is the source, and the signal output terminal is the drain. In addition, the transistors used in the embodiments of the present application may include P-type transistors and/or N-type transistors.
  • the P-type transistor is turned on when the gate is at a low level and is turned off when the gate is at a high level.
  • the N-type transistor is when the gate is at a high level. It is turned on when the gate is high and turned off when the gate is low.
  • transistors in the following embodiments of the present application are all described using N-type transistors as examples, but this should not be understood as limiting the present application.
  • Figure 3 is a signal timing diagram of the Nth level GOA unit provided by this application.
  • the working sequence of the N-th level GOA unit 100 includes a pull-up phase t1, a signal output phase t2, a pull-down phase t3, and a pull-down sustaining phase t4.
  • the N-3 stage transmission signal ST(N-3) is high level.
  • the first transistor T1 is turned on under the control of the N-3th stage transmission signal ST(N-3).
  • the N-3rd level scan signal G(N-3) is transmitted to the pull-up node Q(N) through the first transistor T1. Since the N-3th level scanning signal G(N-3) is high level, the potential of the pull-up node Q(N) is pulled high.
  • the second transistor T2 and the third transistor T3 are turned on. At this time, since the clock signal CLK is at low level, the Nth stage transmission signal ST(N) and the Nth stage scanning signal G(N) are both at low level.
  • the eighth transistor T8 and the ninth transistor T9 are turned on.
  • the reference low level signal VSS is transmitted to the gate of the seventh transistor T7 and the first pull-down node P(N).
  • the seventh transistor T7 is in a closed state.
  • the potential of the first pull-down node P(N) is pulled down.
  • the tenth transistor T10 is turned off.
  • the thirteenth transistor T13 and the fourteenth transistor T14 are turned on.
  • the reference low level signal VSS is transmitted to the gate of the twelfth transistor T12 and the second pull-down node K(N).
  • the twelfth transistor T12 is in a closed state.
  • the potential of the second pull-down node K(N) is pulled down.
  • the fifteenth transistor T15 is turned off.
  • the clock signal CLK transitions to high level.
  • the potential of the pull-up node Q(N) is further pulled up under the action of the bootstrap capacitor Cbt and the clock signal CLK.
  • the second transistor T2 and the third transistor T3 are fully turned on, the clock signal CLK is output through the second transistor T2 and the third transistor T3 respectively, and the loss is small. Therefore, the Nth stage transmission signal ST(N) and the Nth stage scanning signal G(N) are both high level.
  • the first pull-down maintaining unit 1041 and the second pull-down maintaining unit 1042 basically maintain the state during the pull-up stage t1.
  • the difference is that the sixteenth transistor T16 is turned on under the control of the clock signal CLK.
  • the potential of the pull-up node Q(N) is transmitted to the Nth level scan signal output terminal A, which can enhance the output of the Nth level scan signal G(N) and improve the charging capacity of the corresponding scan line.
  • the N+3-th level scanning signal G(N+3) is high level, and the fourth transistor T4 and the fifth transistor T5 are turned on.
  • the potential of the pull-up node Q(N) and the potential of the N-th level scanning signal G(N) are both pulled down to the reference low-level signal VSS, thereby realizing the reset of the N-th level scanning signal G(N).
  • the eighth transistor T8 and the ninth transistor T9 are turned off.
  • the first low-frequency clock signal LC1 remains at a high level, and both the sixth transistor T6 and the seventh transistor T7 are turned on.
  • the potential of the first pull-down node P(N) is pulled high.
  • the tenth transistor T10 is turned on to further pull down the N-th level scanning signal G(N).
  • the eleventh transistor T11 and the twelfth transistor T12 are turned off.
  • the second low-frequency clock signal LC2 remains at a low level.
  • the potential of the second pull-down node K(N) remains low.
  • the first low-frequency clock signal LC1 transitions to low level
  • the second low-frequency clock signal LC2 transitions to high level.
  • the potential of the first pull-down node P(N) is pulled down, and the potential of the second pull-down node K(N) is pulled up.
  • the fifteenth transistor T15 is turned on to further maintain the low potential of the Nth level scanning signal G(N).
  • the clock signal CLK is always in a state of switching between high level and low level. Therefore, the sixteenth transistor T16 is in an alternately turned on state to indirectly maintain the potential of the pull-up node Q(N). Therefore, the operating time of the sixteenth transistor T16 can be reduced and the bias voltage can be reduced, thereby increasing the life of the sixteenth transistor T16.
  • the embodiment of the present application can extend the second pull-down sustain by increasing the life of the sixteenth transistor T16 The operating life of the unit 1042.
  • FIG. 4 is a second circuit schematic diagram of the N-th level GOA unit shown in FIG. 1 .
  • the first pull-down holding unit 1041 also includes a seventeenth transistor T17.
  • the gate of the seventeenth transistor T17 is connected to the first pull-down node P(N).
  • the source of the seventeenth transistor T17 is connected to the reference low level signal VSS.
  • the drain of the seventeenth transistor T17 is connected to the pull-up node Q(N).
  • the second pull-down holding unit 1042 further includes an eighteenth transistor T18.
  • the gate of the eighteenth transistor T18 is connected to the second pull-down node K(N).
  • the source of the eighteenth transistor T18 is connected to the reference low level signal VSS.
  • the drain of the eighteenth transistor T18 is connected to the pull-up node Q(N).
  • Figure 5 is a second structural schematic diagram of the Nth level GOA unit provided by this application.
  • the difference from the N-th level GOA unit 100 shown in FIG. 1 is that in the embodiment of the present application, the pull-down maintenance module 104 is also connected to the N-th level transmission signal output terminal B.
  • the pull-down holding module 104 is also used to pull down the potential of the N-th stage transmission signal output terminal B under the action of the low-frequency clock signal LC.
  • FIG. 6 is a schematic circuit diagram of the N-th level GOA unit shown in FIG. 5.
  • the gate of the seventeenth transistor T17 is connected to the first pull-down node P(N).
  • the source of the seventeenth transistor T17 is connected to the reference low level signal VSS.
  • the drain of the seventeenth transistor T17 is connected to the N-th stage signal output terminal B.
  • the second pull-down holding unit 1042 further includes an eighteenth transistor T18.
  • the gate of the eighteenth transistor T18 is connected to the second pull-down node K(N).
  • the source of the eighteenth transistor T18 is connected to the reference low level signal VSS.
  • the drain of the eighteenth transistor T18 is connected to the Nth stage signal output terminal B.
  • the N-th level transmission signal output terminal B will be in a floating state for a long time. It will fluctuate greatly in high-temperature simulations, which is a big hidden danger.
  • a seventeenth transistor T17 and/or an eighteenth transistor T18 is added to the pull-down sustaining module 104 to continuously pull down the N-th stage transmission signal output terminal B, so that the N-th stage transmission signal ST(N) depends on Increased sex.
  • one of the seventeenth transistor T17 and the eighteenth transistor T18 can also be used to pull down the potential of the pull-up node Q(N), and the other one can be used to pull down the Nth stage signal output terminal.
  • the potential of B is not limited in this application.
  • this application also provides a display panel, which includes the GOA circuit described in any of the above embodiments.
  • FIG. 7 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the display panel 1000 includes a display area AA and a non-display area NA connected to the display area AA.
  • the GOA circuit 200 is integrated and arranged in the non-display area NA.
  • the structure and principle of the GOA circuit 200 are similar to those of the above-mentioned GOA circuit, and will not be described again here.
  • the display panel 1000 provided by the present application is introduced by taking the single-sided driving mode in which the GOA circuit 200 is disposed on the side of the display area AA as an example, but this should not be understood as a limitation of the present application.
  • double-sided driving or other driving methods may also be used according to the actual needs of the display panel 1000, which is not specifically limited in this application.
  • the GOA unit includes a pull-up control module, a pull-up output module, a pull-down module and a pull-down maintenance module, and has a simple structure.
  • the pull-down maintenance module is connected to the clock signal and can pull down the potential of the pull-up node under the control of the clock signal. Since the clock signal is always switching between high level and low level, the working time of the pull-down sustain module can be reduced, the working life of the pull-down sustain module can be extended, and the working stability of the GOA circuit 200 can be improved.
  • the embodiments of the present application can reduce the number of transistors in the GOA unit, thereby reducing the size of the GOA circuit 200 and achieving a narrow frame of the display panel 1000, making the display panel 1000 suitable for Based on Tri-gate architecture.

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Abstract

一种GOA电路及显示面板。GOA电路包括多级级传的GOA单元（100），第N级GOA单元（100）包括上拉控制模块（101）、上拉输出模块（102）、下拉模块（103）以及下拉维持模块（104）。下拉维持模块（104）接入时钟信号（CLK），可以在时钟信号（CLK）的控制下下拉上拉节点（Q(N)）的电位，由此减少下拉维持模块（104）的工作时长，延长下拉维持模块（104）的工作寿命，进而提高GOA电路的工作稳定性。

Description

GOA电路及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种GOA电路及显示面板。
 背景技术
阵列基板栅极驱动(Gate Driver On Array, GOA)技术是将栅极驱动电路集成在显示面板的阵列基板上，以实现逐行扫描的驱动方式。该驱动技术可以省掉栅极驱动器，具有降低生产成本和实现面板窄边框设计的优点，为多种显示器所使用。GOA电路通常包括下拉维持模块，下拉维持模块在下拉期间一直处于工作状态，影响其工作寿命，进而影响GOA电路的工作稳定性。
 技术问题
本申请提供一种GOA电路及显示面板，以解决现有GOA电路中，GOA单元的下拉维持模块一直处于工作状态，工作寿命减少，进而影响GOA电路工作稳定性的技术问题。
 技术解决方案
本申请提供一种GOA电路，其包括多级级传的GOA单元，第N级GOA单元包括：上拉控制模块、上拉输出模块、下拉模块以及下拉维持模块；
所述上拉控制模块接入控制信号和上拉信号，并连接于上拉节点，用于在所述控制信号和所述上拉信号的控制下将所述上拉信号输出至所述上拉节点；所述上拉输出模块接入时钟信号，并连接于所述上拉节点、第N级扫描信号输出端以及第N级级传信号输出端，用于在所述上拉节点的电位和所述时钟信号的控制下输出第N级扫描信号和第N级级传信号；
所述下拉模块接入第N+m级级传信号和参考低电平信号，并连接于所述上拉节点和所述第N级扫描信号输出端，用于在所述第N+m级级传信号和所述参考低电平信号的控制下下拉所述上拉节点和所述第N级扫描信号输出端的电位；
所述下拉维持模块接入低频时钟信号、所述时钟信号以及所述参考低电平信号，并连接于所述上拉节点和所述第N级扫描信号输出端，用于在所述低频时钟信号、所述时钟信号以及所述参考低电平信号的控制下维持所述第N级扫描信号输出端和所述上拉节点的电位。
可选的，在本申请的一些实施例中，所述上拉控制模块包括第一晶体管；
所述第一晶体管的栅极接入所述控制信号或所述上拉信号，所述第一晶体管的源极接入所述上拉信号，所述第一晶体管的漏极连接于所述上拉节点。
可选的，在本申请的一些实施例中，所述上拉输出模块包括第二晶体管、第三晶体管以及自举电容；
所述第二晶体管的栅极、所述第三晶体管的栅极以及所述自举电容的一端均连接于所述上拉节点，所述第二晶体管的源极和所述第三晶体管的源极均接入所述时钟信号，所述第二晶体管的漏极连接于所述第N级级传信号输出端，所述第三晶体管的漏极和所述自举电容的另一端均连接于所述第N级扫描信号输出端。
可选的，在本申请的一些实施例中，所述下拉模块包括第四晶体管和第五晶体管；
所述第四晶体管的栅极和所述第五晶体管的栅极均接入所述第N+m级扫描信号，所述第四晶体管的源极和所述第五晶体管的源极均接入所述参考低电平信号，所述第四晶体管的漏极连接于所述上拉节点，所述第五晶体管的漏极连接于所述第N级扫描信号输出端。
可选的，在本申请的一些实施例中，所述下拉维持模块包括第一下拉维持单元和第二下拉维持单元，所述低频时钟信号包括第一低频时钟信号和第二低频时钟信号；
所述第一下拉维持单元接入所述第一低频时钟信号和所述参考低电平信号，并连接于所述上拉节点和所述第N级扫描信号输出端，用于维持所述第N级扫描信号输出端的电位；所述第二下拉维持单元接入所述第二低频时钟信号、所述参考低电平信号以及所述时钟信号，并连接于所述上拉节点和所述第N级扫描信号输出端，用于维持所述上拉节点和所述第N级扫描信号输出端的电位。
可选的，在本申请的一些实施例中，所述第一低频时钟信号所述和第二低频时钟信号保持反相。
可选的，在本申请的一些实施例中，所述第一低频时钟信号所述和第二低频时钟信号保持同相。
可选的，在本申请的一些实施例中，所述第一下拉维持单元包括第六晶体管、第七晶体管、第八晶体管、第九晶体管以及第十晶体管；
所述第六晶体管的栅极、所述第六晶体管的源极以及所述第七晶体管的源极均接入所述第一低频时钟信号，所述第六晶体管的漏极、所述第七晶体管的栅极以及所述第八晶体管的漏极连接在一起，所述第七晶体管的漏极、所述第九晶体管的漏极以及所述第十晶体管的栅极连接于第一下拉节点，所述第八晶体管的栅极和所述第九晶体管的栅极均连接于所述上拉节点，所述第八晶体管的源极、所述第九晶体管的源极以及所述第十晶体管的源极均接入所述参考低电平信号，所述第十晶体管的漏极连接于所述第N级扫描信号输出端。
可选的，在本申请的一些实施例中，所述第一下拉维持单元还包括第十七晶体管，所述第十七晶体管的栅极连接于所述第一下拉节点，所述第十七晶体管的源极接入所述参考低电平信号，所述第十七晶体管的漏极连接于所述上拉节点或所述第N级级传信号输出端。
可选的，在本申请的一些实施例中，所述第二下拉维持单元还包括第十八晶体管，所述第十八晶体管的栅极连接于第二下拉节点，所述第十八晶体管的源极接入所述参考低电平信号，所述第十八晶体管的漏极连接于所述上拉节点或所述第N级级传信号输出端。
可选的，在本申请的一些实施例中，所述第二下拉维持单元包括第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管以及第十六晶体管；
所述第十一晶体管的栅极、所述第十一晶体管的源极以及所述第十二晶体管的源极均接入所述第二低频时钟信号，所述第十一晶体管的漏极、所述第十二晶体管的栅极以及所述第十三晶体管的漏极连接在一起，所述第十二晶体管的漏极、所述第十四晶体管的漏极以及所述第十五晶体管的栅极连接于第二下拉节点，所述第十三晶体管的栅极和所述第十四晶体管的栅极均连接于所述上拉节点，所述第十三晶体管的源极、所述第十四晶体管的源极以及所述第十五晶体管的源极均接入所述参考低电平信号，所述第十五晶体管的漏极与所述第十六晶体管的源极连接在一起，所述第十六晶体管的栅极接入所述时钟信号，所述第十六晶体管的漏极连接于所述第N级扫描信号输出端。
可选的，在本申请的一些实施例中，所述第一下拉维持单元还包括第十七晶体管，所述第十七晶体管的栅极连接于所述第一下拉节点，所述第十七晶体管的源极接入所述参考低电平信号，所述第十七晶体管的漏极连接于所述上拉节点或所述第N级级传信号输出端。
可选的，在本申请的一些实施例中，所述第二下拉维持单元还包括第十八晶体管，所述第十八晶体管的栅极连接于所述第二下拉节点，所述第十八晶体管的源极接入所述参考低电平信号，所述第十八晶体管的漏极连接于所述上拉节点或所述第N级级传信号输出端。
可选的，在本申请的一些实施例中，所述控制信号为第N-m级级传信号或第N-m级扫描信号，所述上拉信号为所述第N-m级级传信号、所述第N-m级扫描信号或高电平直流信号；N和m均为大于0的整数，且N>m。
可选的，在本申请的一些实施例中，所述下拉维持模块包括第一下拉维持单元，所述低频时钟信号包括第一低频时钟信号，所述第一下拉维持单元接入所述第一低频时钟信号和所述参考低电平信号，并连接于所述上拉节点和所述第N级扫描信号输出端，用于维持所述第N级扫描信号输出端的电位。
可选的，在本申请的一些实施例中，所述下拉维持模块包括第二下拉维持单元，所述低频时钟信号包括第二低频时钟信号，所述第二下拉维持单元接入所述第二低频时钟信号、所述参考低电平信号以及所述时钟信号，并连接于所述上拉节点和所述第N级扫描信号输出端，用于维持所述上拉节点和所述第N级扫描信号输出端的电位。
本申请还提供一种显示面板，所述显示面板包括显示区以及与所述显示区连接的非显示区，所述显示面板包括GOA电路，所述GOA电路位于所述非显示区，所述GOA电路输出多个扫描信号至所述显示区，所述显示面板包括多级级传的GOA单元，第N级GOA单元包括：上拉控制模块、上拉输出模块、下拉模块以及下拉维持模块；
所述上拉控制模块接入控制信号和上拉信号，并连接于上拉节点，用于在所述控制信号和所述上拉信号的控制下将所述上拉信号输出至所述上拉节点；
所述上拉输出模块接入时钟信号，并连接于所述上拉节点、第N级扫描信号输出端以及第N级级传信号输出端，用于在所述上拉节点的电位和所述时钟信号的控制下输出第N级扫描信号和第N级级传信号；
所述下拉模块接入第N+m级级传信号和参考低电平信号，并连接于所述上拉节点和所述第N级扫描信号输出端，用于在所述第N+m级级传信号和所述参考低电平信号的控制下下拉所述上拉节点和所述第N级扫描信号输出端的电位；
所述下拉维持模块接入低频时钟信号、所述时钟信号以及所述参考低电平信号，并连接于所述上拉节点和所述第N级扫描信号输出端，用于在所述低频时钟信号、所述时钟信号以及所述参考低电平信号的控制下维持所述第N级扫描信号输出端和所述上拉节点的电位。
可选的，在本申请的一些实施例中，所述下拉维持模块包括第一下拉维持单元和第二下拉维持单元，所述低频时钟信号包括第一低频时钟信号和第二低频时钟信号；
所述第一下拉维持单元包括第六晶体管、第七晶体管、第八晶体管、第九晶体管以及第十晶体管；
所述第六晶体管的栅极、所述第六晶体管的源极以及所述第七晶体管的源极均接入所述第一低频时钟信号，所述第六晶体管的漏极、所述第七晶体管的栅极以及所述第八晶体管的漏极连接在一起，所述第七晶体管的漏极、所述第九晶体管的漏极以及所述第十晶体管的栅极连接于第一下拉节点，所述第八晶体管的栅极和所述第九晶体管的栅极均连接于所述上拉节点，所述第八晶体管的源极、所述第九晶体管的源极以及所述第十晶体管的源极均接入所述参考低电平信号，所述第十晶体管的漏极连接于所述第N级扫描信号输出端；
所述第二下拉维持单元包括第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管以及第十六晶体管；
所述第十一晶体管的栅极、所述第十一晶体管的源极以及所述第十二晶体管的源极均接入所述第二低频时钟信号，所述第十一晶体管的漏极、所述第十二晶体管的栅极以及所述第十三晶体管的漏极连接在一起，所述第十二晶体管的漏极、所述第十四晶体管的漏极以及所述第十五晶体管的栅极连接于第二下拉节点，所述第十三晶体管的栅极和所述第十四晶体管的栅极均连接于所述上拉节点，所述第十三晶体管的源极、所述第十四晶体管的源极以及所述第十五晶体管的源极均接入所述参考低电平信号，所述第十五晶体管的漏极与所述第十六晶体管的源极连接在一起，所述第十六晶体管的栅极接入所述时钟信号，所述第十六晶体管的漏极连接于所述第N级扫描信号输出端。
可选的，在本申请的一些实施例中，所述第一低频时钟信号所述和第二低频时钟信号保持反相或保持同相。
可选的，在本申请的一些实施例中，所述控制信号为第N-m级级传信号或第N-m级扫描信号，所述上拉信号为所述第N-m级级传信号、所述第N-m级扫描信号或高电平直流信号；N和m均为大于0的整数，且N>m。
 有益效果
本申请提供一种GOA电路及显示面板。GOA电路包括多级级传的GOA单元，第N级GOA单元包括上拉控制模块、上拉输出模块、下拉模块以及下拉维持模块，结构简单。其中，下拉维持模块接入时钟信号，可以在时钟信号的控制下下拉上拉节点的电位。由于时钟信号一直处于在高电平和低电平之间转换的状态，由此可以减少下拉维持模块的工作时长，延长下拉维持模块的工作寿命，进而提高GOA电路的工作稳定性。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请提供的第N级GOA单元的第一结构示意图；
图2是图1所示的第N级GOA单元的第一电路示意图；
图3是本申请提供的第N级GOA单元的信号时序图；
图4是图1所示的第N级GOA单元的第二电路示意图；
图5是本申请提供的第N级GOA单元的第二结构示意图；
图6是图5所示的第N级GOA单元的电路示意图；
图7是本申请提供的显示面板的一种结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
此外，本申请的说明书和权利要求书中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。
本申请提供一种GOA电路及显示面板，以下进行详细说明。需要说明的是，以下实施例的描述顺序不作为对本申请实施例优选顺序的限定。
请参阅图1，图1是本申请提供的第N级GOA单元的第一结构示意图。在本申请实施例中，GOA电路包括多级级传的GOA单元100。第N级GOA单元100包括上拉控制模块101、上拉输出模块102、下拉模块103以及下拉维持模块104。
其中，上拉控制模块101接入控制信号EM和上拉信号EN，并连接于上拉节点Q(N)。上拉控制模块101用于在控制信号EM和上拉信号EN的控制下将上拉信号EN输出至上拉节点Q(N)。
需要说明的是，控制信号EM可以为第N-m级级传信号ST(N-m)或第N-m级扫描信号G(N-m)。上拉信号EN可以为第N-m级级传信号ST(N-m)、第N-m级扫描信号G(N-m)或其它高电平直流信号。从而提高GOA电路中的信号连接灵活性。
也即，上拉控制模块101可以仅接入第N-m级级传信号ST(N-m)。上拉控制模块101也可以仅接入第N-m级扫描信号G(N-m)。上拉控制模块101也可以同时接入第N-m级级传信号ST(N-m)和第N-m级扫描信号G(N-m)。
当然，上拉控制模块101还可以接入其它与第N-m级级传信号ST(N-m)或第N-m级扫描信号G(N-m)时序相同的控制信号，本申请实施例对此不作限定。
此外，在GOA电路中，对于前m级GOA单元100而言，第N-m级级传信号ST(N-m)以及第N-m级扫描信号G(N-m)均不存在。因此，在前m级GOA单元100中，可设置起始信号替代第N-m级级传信号ST(N-m)以及第N-m级扫描信号G(N-m)，在此不再描述。同理，对于后m级GOA单元100而言，第N+m级级传信号ST(N+m)以及第N+m级扫描信号G(N+m)不存在。因此，在后m级GOA单元100中，也可设置起始信号或另一信号替代第N+m级级传信号ST(N+m)以及第N+m级扫描信号G(N+m)。或者，还可以在GOA电路中设置虚拟GOA单元。需要说明的是，除上述区别之外，前m级GOA单元100和后m级GOA单元100与其他级GOA单元100的电路结构以及信号连接均相同，在此不再赘述。
其中，上拉输出模块102接入时钟信号CLK，并连接于上拉节点Q(N)、第N级扫描信号输出端A以及第N级级传信号输出端B。上拉输出模块102用于在上拉节点Q(N)的电位和时钟信号CLK的控制下输出第N级扫描信号G(N)和第N级级传信号ST(N)。
其中，下拉模块103接入第N+m级级传信号ST(N+m)和参考低电平信号VSS，并连接于上拉节点Q(N)和第N级扫描信号输出端A。下拉模块103用于在第N+m级级传信号ST(N+m)和参考低电平信号VSS的控制下下拉上拉节点Q(N)和第N级扫描信号输出端A的电位。
下拉维持模块104接入低频时钟信号LC、时钟信号CLK以及参考低电平信号VSS，并连接于上拉节点Q(N)和第N级扫描信号输出端A。下拉维持模块104用于在低频时钟信号LC、时钟信号CLK以及参考低电平信号VSS的控制下维持第N级扫描信号输出端A和上拉节点Q(N)的电位。
本申请实施例提供的第N级GOA单元100中，下拉维持模块104接入时钟信号CLK，可以在时钟信号CLK的控制下下拉上拉节点Q(N)的电位。由于时钟信号CLK一直处于在高电平和低电平之间转换的状态，由此可以减少下拉维持模块104的工作时长，延长下拉维持模块104的工作寿命，从而提高GOA电路的工作稳定性。此外，相较于相关技术中GOA电路结构，本申请实施例提供的第N级GOA单元100的结构简单，可以减小GOA电路的尺寸，实现显示面板的窄边框化。
请同时参阅图1和图2。图2是图1所示的第N级GOA单元的第一电路示意图。需要说明的是，本申请以下实施例均以m=3为例进行说明，但不能理解为对本申请的限定。
在本申请一些实施例中，上拉控制模块101包括第一晶体管T1。第一晶体管T1的栅极接入控制信号EM。第一晶体管T1的源极接入上拉信号EN。第一晶体管T1的漏极连接于上拉节点Q(N)。
其中，第一晶体管T1的栅极和源极可以分别接入控制信号EM和上拉信号EN的一者。第一晶体管T1的栅极和源极也可以同时接入控制信号EM和上拉信号EN中的同一者。控制信号EM和上拉信号EN具体可参阅上述内容，在此不再赘述。
本申请以下实施例均以第一晶体管T1的栅极接入第N-3级级传信号ST(N-3)，以及第一晶体管T1的源极接入第N-3级扫描信号G(N-3)为例进行说明，但不能理解为对本申请的限定。
在本申请一些实施例中，上拉输出模块102包括第二晶体管T2、第三晶体管T3以及自举电容Cbt。
其中，第二晶体管T2的栅极、第三晶体管T3的栅极以及自举电容Cbt的一端均连接于上拉节点Q(N)。第二晶体管T2的源极和第三晶体管T3的源极均接入时钟信号CLK。第二晶体管T2的漏极连接于第N级级传信号输出端B。第三晶体管T3的漏极和自举电容Cbt的另一端均连接于第N级扫描信号输出端A。
在本申请一些实施例中，下拉模块103包括第四晶体管T4和第五晶体管T5。
其中，第四晶体管T4的栅极和第五晶体管T5的栅极均接入第N+3级扫描信号G(N+3)。第四晶体管T4的源极和第五晶体管T5的源极均接入参考低电平信号VSS。第四晶体管T4的漏极连接于上拉节点Q(N)。第五晶体管T5的漏极连接于第N级扫描信号输出端A。
在本申请一些实施例中，下拉维持模块104包括第一下拉维持单元1041和第二下拉维持单元1042。低频时钟信号LC包括第一低频时钟信号LC1和第二低频时钟信号LC2。
其中，第一下拉维持单元1041接入第一低频时钟信号LC1和参考低电平信号VSS，并连接于上拉节点Q(N)和第N级扫描信号输出端A。第一下拉维持单元1041用于维持第N级扫描信号输出端A的电位。第二下拉维持单元1042接入第二低频时钟信号LC2、参考低电平信号VSS以及时钟信号CLK，并连接于上拉节点Q(N)和第N级扫描信号输出端A。第二下拉维持单元1042用于维持上拉节点Q(N)和第N级扫描信号输出端A的电位。
其中，第一低频时钟信号LC1和第二低频时钟信号LC2保持反相。当第一低频时钟信号LC1为高电平时，第二低频时钟信号LC2为低电平。当第一低频时钟信号LC1为低电平时，第二低频时钟信号LC2为高电平。如此，可使第一下拉维持单元1041和第二下拉维持单元1042交替工作，延长第一下拉维持单元1041和第二下拉维持单元1042的寿命。当然，为了提高下拉的稳定性，也可以使第一低频时钟信号LC1和第二低频时钟信号LC2保持同相，使得第一下拉维持单元1041和第二下拉维持单元1042同时工作。
当然，在本申请一些实施例中，下拉维持模块104可以仅包括第一下拉维持单元1041。在本申请另一些实施例中，下拉维持模块104可以仅包括第二下拉维持单元1042。从而进一步简化GOA单元100的结构，减小GOA电路的尺寸。
在本申请一些实施例中，第一下拉维持单元1041包括第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9以及第十晶体管T10。
其中，第六晶体管T6的栅极、第六晶体管T6的源极以及第七晶体管T7的源极均接入第一低频时钟信号LC1。第六晶体管T6的漏极、第七晶体管T7的栅极以及第八晶体管T8的漏极连接在一起。第七晶体管T7的漏极、第九晶体管T9的漏极以及第十晶体管T10的栅极连接于第一下拉节点P(N)。第八晶体管T8的栅极和第九晶体管T9的栅极均连接于上拉节点Q(N)。第八晶体管T8的源极、第九晶体管T9的源极以及第十晶体管T10的源极均接入参考低电平信号VSS。第十晶体管T10的漏极连接于第N级扫描信号输出端A。
在本申请一些实施例中，第二下拉维持单元1042包括第十一晶体管T11、第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第十五晶体管T15以及第十六晶体管T16。
其中，第十一晶体管T11的栅极、第十一晶体管T11的源极以及第十二晶体管T12的源极均接入第二低频时钟信号LC2。第十一晶体管T11的漏极、第十二晶体管T12的栅极以及第十三晶体管T13的漏极连接在一起。第十二晶体管T12的漏极、第十四晶体管T14的漏极以及第十五晶体管T15的栅极连接于第二下拉节点K(N)。第十三晶体管T13的栅极和第十四晶体管T14的栅极均连接于上拉节点Q(N)。第十三晶体管T13的源极、第十四晶体管T14的源极以及第十五晶体管T15的源极均接入参考低电平信号VSS。第十五晶体管T15的漏极与第十六晶体管T16的源极连接在一起。第十六晶体管T16的栅极接入时钟信号CLK。第十六晶体管T16的漏极连接于第N级扫描信号输出端A。
可以理解的是，为降低生产成本，相关技术中的显示面板会采用Tri-gate架构。相较于传统像素架构，Tri-gate架构把所有的子像素单元旋转90度设置。比如，当子像素单元以RGB的结构排列时，扫描线的数目增加为三倍，数据线数目减少为原本的1/3。如此，可以减少驱动芯片的数量，降低生产成本。但是，随着GOA单元的数量增加，GOA电路结构占用的布线空间变大，不利于实现显示面板窄边框化。
在本申请实施例中，第N级GOA单元100仅包括16T1C（16个晶体管和1个自举电容），结构简单，晶体管的数量较少。因此，有效地减小了GOA电路的尺寸，便于实现显示面板的窄边框。
需要说明的是，本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定开关晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。此外本申请实施例所采用的晶体管可以包括P型晶体管和/或N型晶体管两种，其中，P型晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型晶体管为在栅极为高电平时导通，在栅极为低电平时截止。
此外，本申请以下实施例中的晶体管均以N型晶体管为例进行说明，但不能理解为对本申请的限制。
请同时参阅图2和图3，图3是本申请提供的第N级GOA单元的信号时序图。在本申请实施例中，第N级GOA单元100的工作时序包括上拉阶段t1、信号输出阶段t2、下拉阶段t3以及下拉维持阶段t4。
在上拉阶段t1，第N-3级级传信号ST(N-3)为高电平。第一晶体管T1在第N-3级级传信号ST(N-3)的控制下打开。第N-3级扫描信号G(N-3)通过第一晶体管T1传输至上拉节点Q(N)。由于第N-3级扫描信号G(N-3)为高电平，上拉节点Q(N)的电位被拉高。第二晶体管T2和第三晶体管T3打开。此时，由于时钟信号CLK为低电平，第N级级传信号ST(N)和第N级扫描信号G(N)均为低电平。
与此同时，在第一下拉维持单元1041中，由于第N-3级扫描信号G(N-3)为高电平，第八晶体管T8和第九晶体管T9打开。参考低电平信号VSS传输至第七晶体管T7的栅极和第一下拉节点P(N)。第七晶体管T7处于关闭状态。第一下拉节点P(N)的电位被拉低。第十晶体管T10关闭。
在第二下拉维持单元1042中，由于第N-3级扫描信号G(N-3)为高电平，第十三晶体管T13和第十四晶体管T14打开。参考低电平信号VSS传输至第十二晶体管T12的栅极和第二下拉节点K(N)。第十二晶体管T12处于关闭状态。第二下拉节点K(N)的电位被拉低。第十五晶体管T15关闭。
在信号输出阶段t2，时钟信号CLK转变为高电平。上拉节点Q(N)的电位在自举电容Cbt和时钟信号CLK的作用下，被进一步拉高。第二晶体管T2和第三晶体管T3充分打开，时钟信号CLK分别通过第二晶体管T2和第三晶体管T3输出，损耗较小。由此，第N级级传信号ST(N)和第N级扫描信号G(N)均为高电平。
此时，第一下拉维持单元1041和第二下拉维持单元1042基本保持在上拉阶段t1时的状态。不同之处在于，第十六晶体管T16在时钟信号CLK的控制下打开。上拉节点Q(N)的电位传输至第N级扫描信号输出端A，可以增强第N级扫描信号G(N)的输出，提高相应扫描线的充电能力。
在下拉阶段t3，第N+3级扫描信号G(N+3)为高电平，第四晶体管T4和第五晶体管T5打开。上拉节点Q(N)的电位和第N级扫描信号G(N)的电位均被下拉至参考低电平信号VSS，实现第N级扫描信号G(N)的重置。
此时，由于上拉节点Q(N)的电位被拉低，第八晶体管T8和第九晶体管T9关闭。第一低频时钟信号LC1保持为高电平，第六晶体管T6和第七晶体管T7均打开。第一下拉节点P(N)的电位被拉高。第十晶体管T10打开，进一步下拉第N级扫描信号G(N)。同理，第十一晶体管T11和第十二晶体管T12关闭。但由于第二低频时钟信号LC2保持为低电平。第二下拉节点K(N)的电位保持为低电平。
在下拉维持阶段t4，第一低频时钟信号LC1转变为低电平，第二低频时钟信号LC2转变为高电平。第一下拉节点P(N)的电位被拉低，第二下拉节点K(N)的电位被拉高。第十五晶体管T15打开，进一步维持第N级扫描信号G(N)的低电位。
在此阶段，时钟信号CLK一直处于在高电平和低电平之间转换的状态。因此第十六晶体管T16处于交替打开的状态，以间接性维持上拉节点Q(N)的电位。由此，可以减少第十六晶体管T16的工作时长，减少偏压，从而提高第十六晶体管T16的寿命。此外，相较于现有GOA单元通过在下拉维持模块中设置通过下拉节点控制的晶体管维持上拉节点的低电位，本申请实施例可以通过提高第十六晶体管T16的寿命，延长第二下拉维持单元1042的工作寿命。
请参阅图4，图4是图1所示的第N级GOA单元的第二电路示意图。与图1所示的第N级GOA单元100的不同之处在于，在本申请实施例中，第一下拉维持单元1041还包括第十七晶体管T17。第十七晶体管T17的栅极连接于第一下拉节点P(N)。第十七晶体管T17的源极接入参考低电平信号VSS。第十七晶体管T17的漏极连接于上拉节点Q(N)。
结合图3以及上述分析可知，在下拉阶段t3，第十七晶体管T17在第一下拉节点P(N)的控制下打开。参考低电平信号VSS通过第十七晶体管T17传输至上拉节点Q(N)，进一步拉低上拉节点Q(N)的电位，避免错误输出扫描信号。
进一步的，在本申请一些实施例中，第二下拉维持单元1042还包括第十八晶体管T18。第十八晶体管T18的栅极连接于第二下拉节点K(N)。第十八晶体管T18的源极接入参考低电平信号VSS。第十八晶体管T18的漏极连接于上拉节点Q(N)。
结合图3以及上述分析可知，在下拉维持阶段t4，第十八晶体管T18在第二下拉节点K(N)的控制下打开。参考低电平信号VSS通过第十八晶体管T18传输至上拉节点Q(N)，进一步拉低上拉节点Q(N)的电位，避免错误输出扫描信号。
请参阅图5。图5是本申请提供的第N级GOA单元的第二结构示意图。与图1所示的第N级GOA单元100的不同之处在于，在本申请实施例中，下拉维持模块104还连接于第N级级传信号输出端B。下拉维持模块104还用于在低频时钟信号LC的作用下下拉第N级级传信号输出端B的电位。
具体的，请参阅图6。图6是图5所示的第N级GOA单元的电路示意图，在本申请实施例中，第十七晶体管T17的栅极连接于第一下拉节点P(N)。第十七晶体管T17的源极接入参考低电平信号VSS。第十七晶体管T17的漏极连接于第N级级传信号输出端B。
结合图3以及上述分析可知，在下拉阶段t3，第十七晶体管T17在第一下拉节点P(N)的控制下打开。参考低电平信号VSS可通过第十七晶体管T17传输至第N级级传信号输出端B，拉低第N级级传信号输出端B的电位。
进一步的，在本申请一些实施例中，第二下拉维持单元1042还包括第十八晶体管T18。第十八晶体管T18的栅极连接于第二下拉节点K(N)。第十八晶体管T18的源极接入参考低电平信号VSS。第十八晶体管T18的漏极连接于第N级级传信号输出端B。
结合图3以及上述分析可知，在下拉维持阶段t4，第十八晶体管T18在第二下拉节点K(N)的控制下打开。参考低电平信号VSS可通过第十八晶体管T18传输至第N级级传信号输出端B，拉低第N级级传信号输出端B的电位。
可以理解的是，若没有下拉第N级级传信号输出端B的电位，第N级级传信号输出端B长期处于floating（悬空）状态，高温模拟中波动很大，是一个很大的隐患。本申请实施例在下拉维持模块104中增设第十七晶体管T17和/或第十八晶体管T18对第N级级传信号输出端B进行持续下拉，第N级级传信号ST(N)的信赖性增加。
当然，在本申请实施例中，也可以通过第十七晶体管T17和第十八晶体管T18中的一者下拉上拉节点Q(N)的电位，另一者下拉第N级级传信号输出端B的电位，本申请对此不作限定。
相应的，本申请还提供一种显示面板，其包括上述任一实施例所述的GOA电路。具体的，请参阅图7，图7为本申请实施例提供的显示面板的一种结构示意图。如图7所示，显示面板1000包括显示区域AA以及与显示区AA连接的非显示区NA。GOA电路200集成设置在非显示区NA。其中，该GOA电路200与上述的GOA电路的结构与原理类似，这里不再赘述。需要说明的是，本申请提供的显示面板1000以GOA电路200设置在显示区域AA一侧的单侧驱动方式为例进行介绍，但不能理解为对本申请的限制。在一些实施例中，也可根据显示面板1000的实际需求采用双侧驱动或其他驱动方式，本申请对此不作具体限定。
在本申请实施例提供的显示面板中，GOA单元包括上拉控制模块、上拉输出模块、下拉模块以及下拉维持模块，结构简单。其中，下拉维持模块接入时钟信号，可以在时钟信号的控制下下拉上拉节点的电位。由于时钟信号一直处于在高电平和低电平之间转换的状态，由此可以减少下拉维持模块的工作时长，延长下拉维持模块的工作寿命，进而提高GOA电路200的工作稳定性。此外，相较于相关技术中的GOA电路结构，本申请实施例可以减少GOA单元中的晶体管的数量，进而减小GOA电路200的尺寸，实现显示面板1000的窄边框化，使得显示面板1000适用于Tri-gate架构。
以上对本申请实施例所提供的GOA电路和显示面板进行了详细介绍。本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想，并非因此限制本申请的专利范围。凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (20)

  1. 一种GOA电路，其包括多级级传的GOA单元，第N级GOA单元包括：上拉控制模块、上拉输出模块、下拉模块以及下拉维持模块；
    所述上拉控制模块接入控制信号和上拉信号，并连接于上拉节点，用于在所述控制信号和所述上拉信号的控制下将所述上拉信号输出至所述上拉节点；
    所述上拉输出模块接入时钟信号，并连接于所述上拉节点、第N级扫描信号输出端以及第N级级传信号输出端，用于在所述上拉节点的电位和所述时钟信号的控制下输出第N级扫描信号和第N级级传信号；
    所述下拉模块接入第N+m级级传信号和参考低电平信号，并连接于所述上拉节点和所述第N级扫描信号输出端，用于在所述第N+m级级传信号和所述参考低电平信号的控制下下拉所述上拉节点和所述第N级扫描信号输出端的电位；
    所述下拉维持模块接入低频时钟信号、所述时钟信号以及所述参考低电平信号，并连接于所述上拉节点和所述第N级扫描信号输出端，用于在所述低频时钟信号、所述时钟信号以及所述参考低电平信号的控制下维持所述第N级扫描信号输出端和所述上拉节点的电位。
  2. 根据权利要求1所述的GOA电路，其中，所述上拉控制模块包括第一晶体管；
    所述第一晶体管的栅极接入所述控制信号或所述上拉信号，所述第一晶体管的源极接入所述上拉信号，所述第一晶体管的漏极连接于所述上拉节点。
  3. 根据权利要求1所述的GOA电路，其中，所述上拉输出模块包括第二晶体管、第三晶体管以及自举电容；
    所述第二晶体管的栅极、所述第三晶体管的栅极以及所述自举电容的一端均连接于所述上拉节点，所述第二晶体管的源极和所述第三晶体管的源极均接入所述时钟信号，所述第二晶体管的漏极连接于所述第N级级传信号输出端，所述第三晶体管的漏极和所述自举电容的另一端均连接于所述第N级扫描信号输出端。
  4. 根据权利要求1所述的GOA电路，其中，所述下拉模块包括第四晶体管和第五晶体管；
    所述第四晶体管的栅极和所述第五晶体管的栅极均接入所述第N+m级扫描信号，所述第四晶体管的源极和所述第五晶体管的源极均接入所述参考低电平信号，所述第四晶体管的漏极连接于所述上拉节点，所述第五晶体管的漏极连接于所述第N级扫描信号输出端。
  5. 根据权利要求1所述的GOA电路，其中，所述下拉维持模块包括第一下拉维持单元和第二下拉维持单元，所述低频时钟信号包括第一低频时钟信号和第二低频时钟信号；
    所述第一下拉维持单元接入所述第一低频时钟信号和所述参考低电平信号，并连接于所述上拉节点和所述第N级扫描信号输出端，用于维持所述第N级扫描信号输出端的电位；所述第二下拉维持单元接入所述第二低频时钟信号、所述参考低电平信号以及所述时钟信号，并连接于所述上拉节点和所述第N级扫描信号输出端，用于维持所述上拉节点和所述第N级扫描信号输出端的电位。
  6. 根据权利要求5所述的GOA电路，其中，所述第一低频时钟信号所述和第二低频时钟信号保持反相。
  7. 根据权利要求5所述的GOA电路，其中，所述第一低频时钟信号所述和第二低频时钟信号保持同相。
  8. 根据权利要求5所述的GOA电路，其中，所述第一下拉维持单元包括第六晶体管、第七晶体管、第八晶体管、第九晶体管以及第十晶体管；
    所述第六晶体管的栅极、所述第六晶体管的源极以及所述第七晶体管的源极均接入所述第一低频时钟信号，所述第六晶体管的漏极、所述第七晶体管的栅极以及所述第八晶体管的漏极连接在一起，所述第七晶体管的漏极、所述第九晶体管的漏极以及所述第十晶体管的栅极连接于第一下拉节点，所述第八晶体管的栅极和所述第九晶体管的栅极均连接于所述上拉节点，所述第八晶体管的源极、所述第九晶体管的源极以及所述第十晶体管的源极均接入所述参考低电平信号，所述第十晶体管的漏极连接于所述第N级扫描信号输出端。
  9. 根据权利要求8所述的GOA电路，其中，所述第一下拉维持单元还包括第十七晶体管，所述第十七晶体管的栅极连接于所述第一下拉节点，所述第十七晶体管的源极接入所述参考低电平信号，所述第十七晶体管的漏极连接于所述上拉节点或所述第N级级传信号输出端。
  10. 根据权利要求8所述的GOA电路，其中，所述第二下拉维持单元还包括第十八晶体管，所述第十八晶体管的栅极连接于第二下拉节点，所述第十八晶体管的源极接入所述参考低电平信号，所述第十八晶体管的漏极连接于所述上拉节点或所述第N级级传信号输出端。
  11. 根据权利要求8所述的GOA电路，其中，所述第二下拉维持单元包括第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管以及第十六晶体管；
    所述第十一晶体管的栅极、所述第十一晶体管的源极以及所述第十二晶体管的源极均接入所述第二低频时钟信号，所述第十一晶体管的漏极、所述第十二晶体管的栅极以及所述第十三晶体管的漏极连接在一起，所述第十二晶体管的漏极、所述第十四晶体管的漏极以及所述第十五晶体管的栅极连接于第二下拉节点，所述第十三晶体管的栅极和所述第十四晶体管的栅极均连接于所述上拉节点，所述第十三晶体管的源极、所述第十四晶体管的源极以及所述第十五晶体管的源极均接入所述参考低电平信号，所述第十五晶体管的漏极与所述第十六晶体管的源极连接在一起，所述第十六晶体管的栅极接入所述时钟信号，所述第十六晶体管的漏极连接于所述第N级扫描信号输出端。
  12. 根据权利要求11所述的GOA电路，其中，所述第一下拉维持单元还包括第十七晶体管，所述第十七晶体管的栅极连接于所述第一下拉节点，所述第十七晶体管的源极接入所述参考低电平信号，所述第十七晶体管的漏极连接于所述上拉节点或所述第N级级传信号输出端。
  13. 根据权利要求11所述的GOA电路，其中，所述第二下拉维持单元还包括第十八晶体管，所述第十八晶体管的栅极连接于所述第二下拉节点，所述第十八晶体管的源极接入所述参考低电平信号，所述第十八晶体管的漏极连接于所述上拉节点或所述第N级级传信号输出端。
  14. 根据权利要求1所述的GOA电路，其中，所述控制信号为第N-m级级传信号或第N-m级扫描信号，所述上拉信号为所述第N-m级级传信号、所述第N-m级扫描信号或高电平直流信号；N和m均为大于0的整数，且N>m。
  15. 根据权利要求1所述的GOA电路，其中，所述下拉维持模块包括第一下拉维持单元，所述低频时钟信号包括第一低频时钟信号，所述第一下拉维持单元接入所述第一低频时钟信号和所述参考低电平信号，并连接于所述上拉节点和所述第N级扫描信号输出端，用于维持所述第N级扫描信号输出端的电位。
  16. 根据权利要求1所述的GOA电路，其中，所述下拉维持模块包括第二下拉维持单元，所述低频时钟信号包括第二低频时钟信号，所述第二下拉维持单元接入所述第二低频时钟信号、所述参考低电平信号以及所述时钟信号，并连接于所述上拉节点和所述第N级扫描信号输出端，用于维持所述上拉节点和所述第N级扫描信号输出端的电位。
  17. 一种显示面板，其中，所述显示面板包括显示区以及与所述显示区连接的非显示区，所述显示面板包括GOA电路，所述GOA电路位于所述非显示区，所述GOA电路输出多个扫描信号至所述显示区，所述显示面板包括多级级传的GOA单元，第N级GOA单元包括：上拉控制模块、上拉输出模块、下拉模块以及下拉维持模块；
    所述上拉控制模块接入控制信号和上拉信号，并连接于上拉节点，用于在所述控制信号和所述上拉信号的控制下将所述上拉信号输出至所述上拉节点；
    所述上拉输出模块接入时钟信号，并连接于所述上拉节点、第N级扫描信号输出端以及第N级级传信号输出端，用于在所述上拉节点的电位和所述时钟信号的控制下输出第N级扫描信号和第N级级传信号；
    所述下拉模块接入第N+m级级传信号和参考低电平信号，并连接于所述上拉节点和所述第N级扫描信号输出端，用于在所述第N+m级级传信号和所述参考低电平信号的控制下下拉所述上拉节点和所述第N级扫描信号输出端的电位；
    所述下拉维持模块接入低频时钟信号、所述时钟信号以及所述参考低电平信号，并连接于所述上拉节点和所述第N级扫描信号输出端，用于在所述低频时钟信号、所述时钟信号以及所述参考低电平信号的控制下维持所述第N级扫描信号输出端和所述上拉节点的电位。
  18. 根据权利要求17所述的显示面板，其中，所述下拉维持模块包括第一下拉维持单元和第二下拉维持单元，所述低频时钟信号包括第一低频时钟信号和第二低频时钟信号；
    所述第一下拉维持单元包括第六晶体管、第七晶体管、第八晶体管、第九晶体管以及第十晶体管；
    所述第六晶体管的栅极、所述第六晶体管的源极以及所述第七晶体管的源极均接入所述第一低频时钟信号，所述第六晶体管的漏极、所述第七晶体管的栅极以及所述第八晶体管的漏极连接在一起，所述第七晶体管的漏极、所述第九晶体管的漏极以及所述第十晶体管的栅极连接于第一下拉节点，所述第八晶体管的栅极和所述第九晶体管的栅极均连接于所述上拉节点，所述第八晶体管的源极、所述第九晶体管的源极以及所述第十晶体管的源极均接入所述参考低电平信号，所述第十晶体管的漏极连接于所述第N级扫描信号输出端；
    所述第二下拉维持单元包括第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管以及第十六晶体管；
    所述第十一晶体管的栅极、所述第十一晶体管的源极以及所述第十二晶体管的源极均接入所述第二低频时钟信号，所述第十一晶体管的漏极、所述第十二晶体管的栅极以及所述第十三晶体管的漏极连接在一起，所述第十二晶体管的漏极、所述第十四晶体管的漏极以及所述第十五晶体管的栅极连接于第二下拉节点，所述第十三晶体管的栅极和所述第十四晶体管的栅极均连接于所述上拉节点，所述第十三晶体管的源极、所述第十四晶体管的源极以及所述第十五晶体管的源极均接入所述参考低电平信号，所述第十五晶体管的漏极与所述第十六晶体管的源极连接在一起，所述第十六晶体管的栅极接入所述时钟信号，所述第十六晶体管的漏极连接于所述第N级扫描信号输出端。
  19. 根据权利要求18所述的显示面板，其中，所述第一低频时钟信号所述和第二低频时钟信号保持反相或保持同相。
  20. 根据权利要求17所述的显示面板，其中，所述控制信号为第N-m级级传信号或第N-m级扫描信号，所述上拉信号为所述第N-m级级传信号、所述第N-m级扫描信号或高电平直流信号；N和m均为大于0的整数，且N>m。
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Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130010714A (ko) * 2011-07-19 2013-01-29 엘지디스플레이 주식회사 쉬프트 레지스터
CN103400601A (zh) * 2013-05-28 2013-11-20 友达光电股份有限公司 移位寄存器电路
CN103680451A (zh) * 2013-12-18 2014-03-26 深圳市华星光电技术有限公司 用于液晶显示的goa电路及显示装置
CN104157260A (zh) * 2014-09-10 2014-11-19 深圳市华星光电技术有限公司 基于igzo制程的栅极驱动电路
CN104167191A (zh) * 2014-07-04 2014-11-26 深圳市华星光电技术有限公司 用于平板显示的互补型goa电路
CN105139815A (zh) * 2015-09-18 2015-12-09 友达光电股份有限公司 一种下传控制电路及其goa电路
CN106205528A (zh) * 2016-07-19 2016-12-07 深圳市华星光电技术有限公司 一种goa电路及液晶显示面板
CN106328084A (zh) * 2016-10-18 2017-01-11 深圳市华星光电技术有限公司 Goa驱动电路及液晶显示装置
CN106448595A (zh) * 2016-10-24 2017-02-22 南京华东电子信息科技股份有限公司 一种高可靠性的栅极驱动电路
CN106448594A (zh) * 2016-10-24 2017-02-22 南京华东电子信息科技股份有限公司 一种高可靠性的栅极驱动电路
CN106652936A (zh) * 2016-12-09 2017-05-10 深圳市华星光电技术有限公司 Goa电路及显示装置
CN107799087A (zh) * 2017-11-24 2018-03-13 深圳市华星光电技术有限公司 一种goa电路及显示装置
CN109192156A (zh) * 2018-09-25 2019-01-11 南京中电熊猫平板显示科技有限公司 一种栅极驱动电路和显示装置
CN110010055A (zh) * 2019-05-07 2019-07-12 深圳市华星光电半导体显示技术有限公司 驱动电路

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106297715B (zh) * 2016-09-30 2019-02-26 深圳市华星光电技术有限公司 一种三阶驱动的goa电路及液晶显示器
CN106448588B (zh) * 2016-10-09 2018-12-28 深圳市华星光电技术有限公司 Goa驱动电路及液晶显示装置
CN106571123B (zh) * 2016-10-18 2018-05-29 深圳市华星光电技术有限公司 Goa驱动电路及液晶显示装置
CN106448606A (zh) * 2016-11-23 2017-02-22 深圳市华星光电技术有限公司 一种goa驱动电路
CN107331360B (zh) * 2017-08-14 2019-12-24 深圳市华星光电半导体显示技术有限公司 Goa电路及液晶显示装置
CN107393473B (zh) * 2017-08-25 2018-11-23 深圳市华星光电半导体显示技术有限公司 Goa电路
CN107369426B (zh) * 2017-09-04 2019-12-03 深圳市华星光电半导体显示技术有限公司 防止时钟信号丢失的goa电路
CN107705761B (zh) * 2017-09-27 2019-07-23 深圳市华星光电技术有限公司 一种goa电路及液晶显示器
CN107492362B (zh) * 2017-09-27 2020-01-14 深圳市华星光电技术有限公司 一种栅极驱动电路及液晶显示器
CN107919100B (zh) * 2018-01-04 2020-10-13 深圳市华星光电技术有限公司 一种栅极驱动电路及液晶显示器
CN109215557A (zh) * 2018-10-18 2019-01-15 深圳市华星光电技术有限公司 Goa驱动电路及显示面板
CN109448624B (zh) * 2018-12-03 2020-10-13 深圳市华星光电半导体显示技术有限公司 Goa电路及显示面板
CN109345998B (zh) * 2018-12-20 2021-09-03 Tcl华星光电技术有限公司 Goa电路及显示面板
CN109509459B (zh) * 2019-01-25 2020-09-01 深圳市华星光电技术有限公司 Goa电路及显示装置
CN111145680B (zh) * 2020-02-24 2021-07-27 苏州华星光电技术有限公司 驱动电路及显示面板
CN111477156A (zh) * 2020-05-13 2020-07-31 深圳市华星光电半导体显示技术有限公司 Goa电路及显示面板
CN111754925A (zh) * 2020-07-13 2020-10-09 武汉华星光电技术有限公司 Goa电路以及显示面板
CN113593460A (zh) * 2021-07-19 2021-11-02 Tcl华星光电技术有限公司 Goa电路
CN113658539B (zh) * 2021-08-23 2023-10-31 深圳市华星光电半导体显示技术有限公司 Goa电路

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130010714A (ko) * 2011-07-19 2013-01-29 엘지디스플레이 주식회사 쉬프트 레지스터
CN103400601A (zh) * 2013-05-28 2013-11-20 友达光电股份有限公司 移位寄存器电路
CN103680451A (zh) * 2013-12-18 2014-03-26 深圳市华星光电技术有限公司 用于液晶显示的goa电路及显示装置
CN104167191A (zh) * 2014-07-04 2014-11-26 深圳市华星光电技术有限公司 用于平板显示的互补型goa电路
CN104157260A (zh) * 2014-09-10 2014-11-19 深圳市华星光电技术有限公司 基于igzo制程的栅极驱动电路
CN105139815A (zh) * 2015-09-18 2015-12-09 友达光电股份有限公司 一种下传控制电路及其goa电路
CN106205528A (zh) * 2016-07-19 2016-12-07 深圳市华星光电技术有限公司 一种goa电路及液晶显示面板
CN106328084A (zh) * 2016-10-18 2017-01-11 深圳市华星光电技术有限公司 Goa驱动电路及液晶显示装置
CN106448595A (zh) * 2016-10-24 2017-02-22 南京华东电子信息科技股份有限公司 一种高可靠性的栅极驱动电路
CN106448594A (zh) * 2016-10-24 2017-02-22 南京华东电子信息科技股份有限公司 一种高可靠性的栅极驱动电路
CN106652936A (zh) * 2016-12-09 2017-05-10 深圳市华星光电技术有限公司 Goa电路及显示装置
CN107799087A (zh) * 2017-11-24 2018-03-13 深圳市华星光电技术有限公司 一种goa电路及显示装置
CN109192156A (zh) * 2018-09-25 2019-01-11 南京中电熊猫平板显示科技有限公司 一种栅极驱动电路和显示装置
CN110010055A (zh) * 2019-05-07 2019-07-12 深圳市华星光电半导体显示技术有限公司 驱动电路

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