WO2022241821A1 - 一种栅极驱动电路及显示面板 - Google Patents

一种栅极驱动电路及显示面板 Download PDF

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Publication number
WO2022241821A1
WO2022241821A1 PCT/CN2021/097130 CN2021097130W WO2022241821A1 WO 2022241821 A1 WO2022241821 A1 WO 2022241821A1 CN 2021097130 W CN2021097130 W CN 2021097130W WO 2022241821 A1 WO2022241821 A1 WO 2022241821A1
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WIPO (PCT)
Prior art keywords
clock signal
transistor
level
node
terminal
Prior art date
Application number
PCT/CN2021/097130
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English (en)
French (fr)
Inventor
管延庆
田超
曹海明
Original Assignee
武汉华星光电技术有限公司
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Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to EP21809903.4A priority Critical patent/EP4343746A1/en
Priority to JP2021541539A priority patent/JP7399172B2/ja
Priority to KR1020217034718A priority patent/KR102542852B1/ko
Priority to US17/419,876 priority patent/US11996062B2/en
Publication of WO2022241821A1 publication Critical patent/WO2022241821A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present application relates to the field of display technology, in particular to a gate drive circuit and a display panel.
  • Liquid crystal display devices have been widely used in various electronic products as display components of electronic equipment, and GOA (Gate Driver On Array, GOA) circuit is an important part of the liquid crystal display device. That is to use the existing thin-film transistor liquid crystal display array (Array) process to fabricate the gate (Gate) row scanning drive signal circuit on the Array substrate to realize a technology that drives the gate progressively.
  • Array thin-film transistor liquid crystal display array
  • Gate Gate
  • TFT Thin Film Transistor
  • NMOS N-type metal oxide semiconductor
  • PMOS P-type metal oxide semiconductor
  • CMOS Complementary Metal Oxide Semiconductor
  • gate driving circuits are divided into NMOS circuits, PMOS circuits and CMOS circuits.
  • NMOS circuits can save processes, which is of great benefit to improving yield and reducing costs. Therefore, the development of stable NMOS circuits has a realistic industrial demand.
  • NMOS TFT carriers are electrons with high mobility, and the device is easier to damage than PMOS (carriers are holes).
  • the inventors of the present application found that, in order to ensure normal display, when the circuit is pulled down and held, the TFT gate level is in a high potential state for a long time, so that the bias voltage of the TFT is too large and damages the device.
  • the performance on the panel is that the high temperature reliability of the product is insufficient, and it is prone to failure of the gate drive circuit, split screen, abnormal picture and so on.
  • the present application provides a gate drive circuit and a display panel, which can prevent the transistor from being in a biased state for a long time, thereby enhancing circuit stability and avoiding failure of the gate drive circuit.
  • the present application provides a gate drive circuit, including a multi-stage cascaded gate drive unit, wherein each level of the gate drive unit includes:
  • the pull-up control module is electrically connected to the first node, and the pull-up control module is used to control the potential of the first node;
  • a pull-up module is electrically connected to the first node and the scan signal output end of the current stage, and the pull-up module is used to pull up the current level under the control of the potential of the first node.
  • a pull-down module the pull-down module is electrically connected to the scan signal output terminal of the current stage, and the pull-down module is used to pull down the potential of the scan signal output terminal of the current stage;
  • a pull-down control module is electrically connected to the second node, the first node, the first clock signal terminal and the scan signal output terminal of the current stage, and the pull-down control module is used to Under the control of the signal input from the clock signal terminal, the potential of the second node is intermittently pulled down to maintain the potential of the first node and the potential of the scanning signal output terminal of the current stage.
  • the pull-up control module includes a first transistor and a bootstrap capacitor, the gate of the first transistor is electrically connected to the second clock signal terminal, and the first One of the source or the drain of the transistor is electrically connected to the output terminal of the upper scan signal, and the other of the source or the drain of the first transistor is electrically connected to the first node; the self One end of the bootstrap capacitor is electrically connected to the first node, and the other end of the bootstrap capacitor is electrically connected to the scan signal output end of the current stage.
  • the pull-up module includes a second transistor, the gate of the second transistor is electrically connected to the first node, and the source of the second transistor or One of the drains is electrically connected to the third clock signal terminal, and the other of the source or the drain of the second transistor is electrically connected to the scanning signal output terminal of the current stage.
  • the pull-down module includes a third transistor, the gate of the third transistor is electrically connected to the second clock signal terminal, and the source or drain of the third transistor One of the poles is connected to a constant-voltage low-level signal, and the other of the source or the drain of the third transistor is electrically connected to the scan signal output terminal of the current stage.
  • the pull-down control module includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;
  • the gate of the fourth transistor is electrically connected to the first clock signal terminal, one of the source or the drain of the fourth transistor is connected to a constant-voltage low-level signal, and the source of the fourth transistor The other of the electrode or the drain is electrically connected to the second node;
  • the gate of the fifth transistor is electrically connected to the second node, one of the source or the drain of the fifth transistor is connected to the constant-voltage low-level signal, and the source of the fifth transistor The other of the electrode or the drain is electrically connected to the first node;
  • the gate of the sixth transistor is electrically connected to the first node, one of the source or the drain of the sixth transistor is connected to the constant-voltage low-level signal, and the source of the sixth transistor The other of the electrode or the drain is electrically connected to the second node;
  • One of the gate and the source or the drain of the seventh transistor is electrically connected to the fourth clock signal terminal, and the other of the source or the drain of the seventh transistor is electrically connected to the first Two nodes;
  • the gate of the eighth transistor is electrically connected to the second node, one of the source or the drain of the eighth transistor is connected to the constant-voltage low-level signal, and the source of the eighth transistor The other of the electrode or the drain is electrically connected to the scan signal output end of the current stage.
  • a reset module is also included, the reset module is connected to a reset signal and a constant voltage low-level signal, and is electrically connected to the first node and the second node , for resetting the potentials of the first node and the second node.
  • the reset module includes a ninth transistor and a tenth transistor
  • the gate of the ninth transistor is connected to the reset signal, one of the source or drain of the ninth transistor is connected to the constant voltage low-level signal, and the source or drain of the ninth transistor is The other of the poles is electrically connected to the second node;
  • the gate of the tenth transistor is connected to the reset signal, one of the source or drain of the tenth transistor is connected to the constant voltage low-level signal, and the source or drain of the tenth transistor is The other of the poles is electrically connected to the first node.
  • the full-switch control module accesses the full-switch control signal, the constant voltage low-level signal, and is electrically connected to the scan Signal output terminal: the full-switch control module is used to simultaneously control the potential of the scan signal output terminal of each gate driving unit based on the full-switch control signal and the constant-voltage low-level signal.
  • the full-switch control module includes an eleventh transistor, the gate of the eleventh transistor is connected to the full-switch control signal, and the gate of the eleventh transistor One of the source or the drain is connected to the constant-voltage low-level signal, and the other of the source or the drain of the eleventh transistor is electrically connected to the scan signal output terminal of the current stage.
  • the gate drive circuit accesses the first clock signal, the second clock signal, the third clock signal, the fourth clock signal, the fifth clock signal, and the sixth clock signal , the seventh clock signal and the eighth clock signal;
  • the gate drive circuit includes a plurality of odd-numbered gate drive units arranged in cascade and a plurality of even-numbered gate drive units arranged in cascade; wherein,
  • the plurality of odd-level gate drive units arranged in cascade access the first clock signal, the third clock signal, the fifth clock signal, and the seventh clock signal;
  • the plurality of even-numbered gate driving units arranged in cascade access the second clock signal, the fourth clock signal, the sixth clock signal, and the eighth clock signal.
  • the gate driving unit at each stage is also electrically connected to the second clock signal terminal, the third clock signal terminal and the fourth clock signal terminal;
  • the first clock signal terminal of the 1+8k-stage gate drive unit is connected to the third clock signal, and the 1+8k-stage gate
  • the second clock signal terminal of the drive unit is connected to the fifth clock signal
  • the third clock signal terminal of the 1+8k-level gate drive unit is connected to the first clock signal
  • the fourth clock signal terminal of the gate drive unit is connected to the seventh clock signal;
  • the first clock signal terminal of the 3+8k level gate driving unit is connected to the fifth clock signal, and the second clock signal terminal of the 3+8k level gate driving unit is connected to the seventh clock signal,
  • the third clock signal terminal of the 3+8k level gate drive unit is connected to the third clock signal, and the fourth clock signal terminal of the 3+8k level gate drive unit is connected to the first clock signal Signal;
  • the first clock signal terminal of the 5+8k-level gate driving unit is connected to the seventh clock signal
  • the second clock signal terminal of the 5+8k-level gate driving unit is connected to the first clock signal
  • the third clock signal terminal of the 5+8k-level gate drive unit is connected to the fifth clock signal
  • the fourth clock signal terminal of the 5+8k-level gate drive unit is connected to the third clock signal Signal
  • the first clock signal terminal of the 7+8k-level gate driving unit is connected to the first clock signal
  • the second clock signal terminal of the 7+8k-level gate driving unit is connected to the third clock signal
  • the third clock signal terminal of the 7+8k-level gate drive unit is connected to the seventh clock signal
  • the fourth clock signal terminal of the 7+8k-level gate drive unit is connected to the fifth clock signal Signal
  • the first clock signal terminal of the 2+8k level gate driving unit is connected to the fourth clock signal, and the 2+8k level gate
  • the second clock signal terminal of the drive unit is connected to the sixth clock signal
  • the third clock signal terminal of the 2+8k-level gate drive unit is connected to the second clock signal
  • the 2+8k-level gate drive unit is connected to the second clock signal.
  • the fourth clock signal terminal of the gate drive unit is connected to the eighth clock signal;
  • the first clock signal terminal of the 4+8k-level gate drive unit is connected to the sixth clock signal, and the second clock signal terminal of the 4+8k-level gate drive unit is connected to the eighth clock signal,
  • the third clock signal terminal of the 4+8k-level gate driving unit is connected to the fourth clock signal, and the fourth clock signal terminal of the 4+8k-level gate driving unit is connected to the second clock signal Signal;
  • the first clock signal terminal of the 6+8k-level gate driving unit is connected to the eighth clock signal
  • the second clock signal terminal of the 6+8k-level gate driving unit is connected to the second clock signal
  • the third clock signal terminal of the 6+8k-level gate drive unit is connected to the sixth clock signal
  • the fourth clock signal terminal of the 6+8k-level gate drive unit is connected to the fourth clock signal Signal
  • the first clock signal terminal of the 8+8k-level gate driving unit is connected to the second clock signal, and the second clock signal terminal of the 8+8k-level gate driving unit is connected to the fourth clock signal,
  • the third clock signal terminal of the 8+8k-level gate driving unit is connected to the eighth clock signal, and the fourth clock signal terminal of the 8+8k-level gate driving unit is connected to the sixth clock signal Signal; where k is an integer greater than or equal to zero.
  • the gate drive circuit is connected to the first clock signal, the second clock signal, the third clock signal and the fourth clock signal.
  • the gate driving unit at each stage is also electrically connected to the second clock signal terminal, the third clock signal terminal and the fourth clock signal terminal;
  • the first clock signal terminal of the 1+4k-level gate drive unit is connected to the first and second clock signals
  • the second clock signal terminal of the 1+4k-level gate drive unit is connected to the fourth and third clock signals signal
  • the third clock signal terminal of the 1+4k level gate drive unit is connected to the second clock signal
  • the fourth clock signal terminal of the 1+4k level gate drive unit is connected to the The third and fourth clock signals
  • the first clock signal terminal of the 2+4k level gate drive unit is connected to the second three clock signal, and the second clock signal terminal of the 2+4k level gate drive unit is connected to the first four clock signal signal, the third clock signal terminal of the 2+4k level gate drive unit is connected to the third and second clock signals, and the fourth clock signal terminal of the 2+4k level gate drive unit is connected to the a fourth first clock signal;
  • the first clock signal terminal of the 3+4k level gate driving unit is connected to the third four clock signal
  • the second clock signal terminal of the 3+4k level gate driving unit is connected to the second clock signal signal
  • the third clock signal terminal of the 3+4k level gate drive unit is connected to the fourth third clock signal
  • the fourth clock signal terminal of the 3+4k level gate drive unit is connected to the First and second clock signals
  • the first clock signal terminal of the 4+4k-level gate drive unit is connected to the fourth first clock signal
  • the second clock signal terminal of the 4+4k-level gate drive unit is connected to the third and second clock signals signal
  • the third clock signal terminal of the 4+4k level gate drive unit is connected to the first four clock signals
  • the fourth clock signal terminal of the 4+4k level gate drive unit is connected to the The second and third clock signals; wherein, k is an integer greater than or equal to zero.
  • the driving sequence of the gate driving circuit includes:
  • the scanning signal output terminal of the current stage outputs the scanning signal of the current stage
  • the potential of the first node and the potential of the output terminal of the scanning signal of the current stage are maintained, and the potential of the second node is pulled down intermittently.
  • the sustain phase includes a first sustain phase and a second sustain phase
  • the gate drive circuit is also connected to a fourth clock signal terminal
  • the fourth clock signal terminal is connected to a high-level signal for pulling up the potential of the second node
  • the first clock signal terminal is connected to a high-level signal for pulling down the potential of the second node, so as to intermittently pull down the potential of the second node.
  • a multi-level cascaded gate driving unit is included, wherein each level of the gate driving unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;
  • the gate of the first transistor is electrically connected to the second clock signal terminal, and one of the source or the drain of the first transistor is electrically connected to the output terminal of the previous scan signal.
  • the other of the source or the drain is electrically connected to the first node;
  • the gate of the second transistor is electrically connected to the first node, one of the source or the drain of the second transistor is electrically connected to the third clock signal terminal, and the source of the second transistor or the other of the drains is electrically connected to the scan signal output terminal of the current stage;
  • the gate of the third transistor is electrically connected to the second clock signal terminal, one of the source or the drain of the third transistor is connected to a constant-voltage low-level signal, and the source of the third transistor
  • the other of the electrode or the drain is electrically connected to the output terminal of the scan signal of the current stage;
  • the gate of the fourth transistor is electrically connected to the first clock signal terminal, one of the source or the drain of the fourth transistor is connected to the constant voltage low-level signal, and the fourth transistor The other of the source or the drain is electrically connected to the second node;
  • the gate of the fifth transistor is electrically connected to the second node, one of the source or the drain of the fifth transistor is connected to the constant-voltage low-level signal, and the source of the fifth transistor The other of the electrode or the drain is electrically connected to the first node;
  • the gate of the sixth transistor is electrically connected to the first node, one of the source or the drain of the sixth transistor is connected to the constant-voltage low-level signal, and the source of the sixth transistor The other of the electrode or the drain is electrically connected to the second node;
  • One of the gate and the source or the drain of the seventh transistor is electrically connected to the fourth clock signal terminal, and the other of the source or the drain of the seventh transistor is electrically connected to the first Two nodes;
  • the gate of the eighth transistor is electrically connected to the second node, one of the source or the drain of the eighth transistor is connected to the constant-voltage low-level signal, and the source of the eighth transistor The other of the electrode or the drain is electrically connected to the scan signal output end of the current stage.
  • the gate drive circuit further includes a ninth transistor and a tenth transistor
  • the gate of the ninth transistor is connected to a reset signal, one of the source or drain of the ninth transistor is connected to the constant voltage low-level signal, and the source or drain of the ninth transistor is The other one is electrically connected to the second node;
  • the gate of the tenth transistor is connected to the reset signal, one of the source or drain of the tenth transistor is connected to the constant voltage low-level signal, and the source or drain of the tenth transistor is The other of the poles is electrically connected to the first node.
  • the driving sequence of the gate driving circuit includes:
  • the scanning signal output terminal of the current stage outputs the scanning signal of the current stage
  • the potential of the first node and the potential of the output terminal of the scanning signal of the current stage are maintained, and the potential of the second node is pulled down intermittently.
  • the maintenance phase includes a first maintenance phase and a second maintenance phase
  • the fourth clock signal terminal is connected to a high-level signal for pulling up the potential of the second node
  • the first clock signal terminal is connected to a high-level signal for pulling down the potential of the second node, so as to intermittently pull down the potential of the second node.
  • the present application also provides a display panel, including the above-mentioned gate driving circuit.
  • the gate drive circuit provided by the present application intermittently pulls up and pulls down the potential of the second node through the pull-down control module, so that the potential of the second node is intermittently at a high potential, effectively reducing the time that the second node is at a high potential , so that the thin film transistor electrically connected to the second node can have sufficient recovery time after receiving the forward bias voltage.
  • This solution effectively improves the bias voltage of the thin film transistor in the pull-down control module, makes the circuit more stable, and improves the reliability of the circuit.
  • the display panel provided by the present application reduces the number of thin film transistors in the gate driving unit, can reduce the frame width of the display panel, and is easier to realize a narrow frame display panel.
  • FIG. 1 is a first circuit schematic diagram of a gate drive unit in the gate drive circuit provided by the present application
  • FIG. 2 is a second schematic circuit diagram of a gate drive unit in the gate drive circuit provided by the present application.
  • FIG. 3 is a schematic diagram of the first structure of the gate drive circuit provided by the present application.
  • FIG. 4 is a second structural schematic diagram of the gate drive circuit provided by the present application.
  • FIG. 5 is a schematic circuit diagram of a third-level gate drive unit corresponding to the gate drive circuit provided by the present application.
  • FIG. 6 is a timing diagram of a third-level gate drive unit corresponding to the gate drive circuit provided by the present application.
  • FIG. 7 is a schematic structural diagram of a display panel provided by the present application.
  • the transistors used in all embodiments of the present application can be thin film transistors or field effect transistors or other devices with the same characteristics, because one of the source or drain of the transistors used here, and the other of the source or drain is symmetrical , so one of its source or drain and the other of source or drain are interchangeable.
  • one of the poles is called the source or the drain
  • the other pole is called the other of the source or the drain.
  • the middle terminal of the switch transistor is the gate
  • the signal input terminal is one of the source or the drain
  • the output terminal is the other of the source or the drain.
  • the transistors used in the embodiments of the present application may include P-type transistors and/or N-type transistors, wherein the P-type transistors are turned on when the gate is at a low level, and are turned off when the gate is at a high level, and the N-type transistors are turned on when the gate is at a high level. It turns on when the gate is high and turns off when the gate is low.
  • the present application provides a gate driving circuit and a display panel. Each will be described in detail below. It should be noted that the description sequence of the following embodiments is not intended to limit the preferred sequence of the embodiments.
  • the present application provides a gate drive circuit, including gate drive units arranged in multi-stage cascade.
  • the nth level gate driving unit is used to output the nth level scanning driving signal to charge the corresponding nth scanning line in the display area, so as to realize the normal display of the display panel.
  • FIG. 1 is a first circuit schematic diagram of a gate driving unit in the gate driving circuit provided by the present application.
  • each level of gate driving unit 100 includes a pull-up control module 101 , a pull-up module 102 , a pull-down module 103 and a pull-down control module 104 .
  • the pull-up control module 101 is electrically connected to the first node Q.
  • the pull-up control module 101 is used to control the potential of the first node Q.
  • the pull-up module 102 is electrically connected to the first node Q and the scan signal output terminal Gn of the current stage.
  • the pull-up module 102 is configured to pull up the potential of the scanning signal output terminal Gn of the current stage under the control of the potential of the first node Q.
  • the pull-down module 103 is electrically connected to the scanning signal output terminal Gn of the current stage.
  • the pull-down module 103 is used for pulling down the potential of the scan signal output terminal Gn of the current stage.
  • the pull-down control module 104 is electrically connected to the second node P, the first node Q, the first clock signal terminal CKa, and the scan signal output terminal Gn of the current stage.
  • the pull-down control module 104 is used to intermittently pull down the potential of the second node P under the control of the signal input from the first clock signal terminal CKa, to maintain the potential of the first node Q and the potential of the scanning signal output terminal Gn of the current stage.
  • the pull-down control module 104 in the gate driving unit 100 provided in the present application can intermittently pull down the potential of the second node P under the control of the signal input from the first clock signal terminal CKa. Therefore, the duration of the high potential of the second node P is reduced, and the bias voltage received by the thin film transistor in the pull-down control module 104 is weakened. Further, the stability of the gate driving circuit is improved.
  • the pull-up control module 101 includes a first transistor T1 and a bootstrap capacitor C.
  • the gate of the first transistor T1 is electrically connected to the second clock signal terminal CKb.
  • One of the source and the drain of the first transistor T1 is electrically connected to the upper scan signal output terminal Gn-2.
  • the other of the source or the drain of the first transistor T1 is electrically connected to the first node Q.
  • One end of the bootstrap capacitor C is electrically connected to the first node Q.
  • the other end of the bootstrap capacitor C is electrically connected to the scan signal output end Gn of the current stage.
  • a start signal is connected to the scan signal output terminal Gn-2 of the upper level to trigger the gate drive unit.
  • the GOA unit 100 outputs scan drive Signal.
  • the pull-up module 102 includes a second transistor T2.
  • the gate of the second transistor T2 is electrically connected to the first node Q.
  • One of the source or the drain of the second transistor T2 is electrically connected to the third clock signal terminal CKc.
  • the other of the source or the drain of the second transistor T2 is electrically connected to the scanning signal output terminal Gn of the current stage.
  • the pull-down module 103 includes a third transistor T3.
  • the gate of the third transistor T3 is electrically connected to the second clock signal terminal CKb.
  • One of the source or the drain of the third transistor T3 is connected to the constant-voltage low-level signal VGL.
  • the other of the source or the drain of the third transistor T3 is electrically connected to the scanning signal output terminal Gn of the current stage.
  • the pull-down control module 104 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8.
  • the gate of the fourth transistor T4 is electrically connected to the first clock signal terminal CKa.
  • One of the source or the drain of the fourth transistor T4 is connected to the constant-voltage low-level signal VGL.
  • the other of the source or the drain of the fourth transistor T4 is electrically connected to the second node P.
  • the gate of the fifth transistor T5 is electrically connected to the second node P.
  • One of the source or the drain of the fifth transistor T5 is connected to the constant-voltage low-level signal VGL.
  • the other of the source or the drain of the fifth transistor T5 is electrically connected to the first node Q.
  • the gate of the sixth transistor T6 is electrically connected to the first node Q.
  • One of the source or the drain of the sixth transistor T6 is connected to the constant-voltage low-level signal VGL.
  • the other of the source or the drain of the sixth transistor T6 is electrically connected to the second node P.
  • the gate and one of the source or the drain of the seventh transistor T7 are electrically connected to the fourth clock signal terminal CKd.
  • the other of the source or the drain of the seventh transistor T7 is electrically connected to the second node P.
  • the gate of the eighth transistor T8 is electrically connected to the second node P.
  • One of the source or the drain of the eighth transistor T8 is connected to the constant-voltage low-level signal VGL.
  • the other of the source or the drain of the eighth transistor T8 is electrically connected to the scanning signal output terminal Gn of the current stage.
  • the gate drive unit 100 controls the potential of the second node P by adding the first clock signal terminal CKa in the pull-down control module 104, thereby reducing the duration of the high potential of the second node P, and further The bias voltage received by the fifth transistor T5 and the eighth transistor T8 during operation is weakened, thereby improving the stability of the circuit.
  • FIG. 2 is a second schematic circuit diagram of a gate driving unit in the gate driving circuit provided by the present application.
  • the gate driving unit 100 shown in FIG. 2 further includes a reset module 105, which is connected to the reset signal RE and the constant voltage low-level signal VGL, and is electrically connected to the first node Q and the second node P for to reset the potentials of the first node Q and the second node P.
  • a reset module 105 which is connected to the reset signal RE and the constant voltage low-level signal VGL, and is electrically connected to the first node Q and the second node P for to reset the potentials of the first node Q and the second node P.
  • the reset module 105 includes a ninth transistor T9 and a tenth transistor T10.
  • the gate of the ninth transistor T9 is connected to the reset signal RE.
  • One of the source or the drain of the ninth transistor T9 is connected to the constant-voltage low-level signal VGL.
  • the other of the source or the drain of the ninth transistor T9 is electrically connected to the second node P.
  • the gate of the tenth transistor T10 is connected to the reset signal RE.
  • One of the source or the drain of the tenth transistor T10 is connected to the constant-voltage low-level signal VGL.
  • the other of the source or the drain of the tenth transistor T10 is electrically connected to the first node Q.
  • the gate driving unit 100 shown in FIG. 2 further includes a full switch control module 106 .
  • the full-switch control module 106 is connected to the full-switch control signal GAS and the constant-voltage low-level signal VGL, and is electrically connected to the scanning signal output terminal Gn of the current stage.
  • the full-switch control module 106 is used for simultaneously controlling the potential of the scan signal output terminal of each gate driving unit 100 based on the full-switch control signal GAS and the constant-voltage low-level signal VGL.
  • the full switch control module 106 includes an eleventh transistor T11.
  • the gate of the eleventh transistor T11 is connected to the full switch control signal GAS.
  • One of the source or the drain of the eleventh transistor T11 is connected to the constant-voltage low-level signal VGL.
  • the source or the drain of the eleventh transistor T11 is electrically connected to the scanning signal output terminal Gn of the current stage.
  • the gate driving circuit provided in the present application may adopt double-sided driving or single-sided driving, which is not limited in the present application.
  • FIG. 3 is a schematic diagram of the first structure of the gate driving circuit provided in the present application.
  • the gate drive circuit receives the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, the fourth clock signal CK4, the fifth clock signal CK5, the sixth clock signal CK6, the seventh clock signal CK7 and the eighth clock signal Clock signal CK8.
  • the gate driving circuit includes a plurality of odd-numbered gate driving units arranged in cascade and a plurality of even-numbered gate driving units arranged in cascade.
  • a plurality of odd-level gate driving units arranged in cascade are connected to the first clock signal CK1 , the third clock signal CK3 , the fifth clock signal CK5 and the seventh clock signal CK7 .
  • a plurality of even-numbered gate driving units arranged in cascade are connected to the second clock signal CK2 , the fourth clock signal CK4 , the sixth clock signal CK6 and the eighth clock signal CK8 .
  • each stage of the gate driving unit 100 is electrically connected to the first clock signal terminal CKa, the second clock signal terminal CKb, the third clock signal terminal CKc and the fourth clock signal terminal CKd.
  • the first clock signal terminal CKa of the 1+8k-th stage gate drive units is connected to the third clock signal CK3.
  • the second clock signal terminal CKb of the 1+8k stage gate driving unit is connected to the fifth clock signal CK5.
  • the third clock signal terminal CKc of the 1+8k stage gate driving unit is connected to the first clock signal CK1.
  • the fourth clock signal terminal CKd of the 1+8k stage gate driving unit is connected to the seventh clock signal CK7.
  • the first clock signal terminal CKa of the gate driving unit of the 3+8k stage is connected to the fifth clock signal CK5.
  • the second clock signal terminal CKb of the 3+8k stage gate driving unit is connected to the seventh clock signal CK7.
  • the third clock signal terminal CKc of the 3+8k stage gate driving unit is connected to the third clock signal CK3.
  • the fourth clock signal terminal CKd of the 3+8k stage gate driving unit is connected to the first clock signal CK1.
  • the first clock signal terminal CKa of the 5th+8kth stage gate driving unit is connected to the seventh clock signal CK7.
  • the second clock signal terminal CKb of the 5th+8k stage gate driving unit is connected to the first clock signal CK1.
  • the third clock signal terminal CKc of the gate driving unit of the 5+8k stage is connected to the fifth clock signal CK5.
  • the fourth clock signal terminal CKd of the 5+8k stage gate driving unit is connected to the third clock signal CK3.
  • the first clock signal terminal CKa of the 7th+8kth stage gate driving unit is connected to the first clock signal CK1.
  • the second clock signal terminal CKb of the 7th+8k-level gate driving unit is connected to the third clock signal CK3.
  • the third clock signal terminal CKc of the 7+8k-level gate driving unit is connected to the seventh clock signal CK7.
  • the fifth clock signal CK5 is connected to the fourth clock signal terminal CKd of the 7th+8k-level gate driving unit.
  • the first clock signal terminal CKa of the 2+8kth level gate driving units is connected to the fourth clock signal CK4 .
  • the second clock signal terminal CKb of the 2+8k stage gate driving unit is connected to the sixth clock signal CK6.
  • the third clock signal terminal CKc of the 2+8k stage gate driving unit is connected to the second clock signal CK2.
  • the fourth clock signal terminal CKd of the 2+8k stage gate driving unit is connected to the eighth clock signal CK8.
  • the sixth clock signal CK6 is connected to the first clock signal terminal CKa of the 4+8kth stage gate driving unit.
  • the second clock signal terminal CKb of the 4+8k stage gate driving unit is connected to the eighth clock signal CK8.
  • the third clock signal terminal CKc of the gate driving unit of the 4+8k stage is connected to the fourth clock signal CK4.
  • the fourth clock signal terminal CKd of the gate driving unit of the 4+8k stage is connected to the second clock signal CK2.
  • the first clock signal terminal CKa of the 6+8kth stage gate driving unit is connected to the eighth clock signal CK8 .
  • the second clock signal terminal CKb of the gate driving unit of the 6+8k stage is connected to the second clock signal CK2.
  • the sixth clock signal CK6 is connected to the third clock signal terminal CKc of the 6+8k stage gate driving unit.
  • the fourth clock signal terminal CKd of the gate driving unit of the 6+8k stage is connected to the fourth clock signal CK4.
  • the first clock signal terminal CKa of the gate driving unit of the 8+8k stage is connected to the second clock signal CK2.
  • the second clock signal terminal CKb of the 8+8k stage gate driving unit is connected to the fourth clock signal CK4.
  • the third clock signal terminal CKc of the gate driving unit of the 8+8k stage is connected to the eighth clock signal CK8.
  • the fourth clock signal terminal CKd of the gate driving unit of the 8+8k stage is connected to the sixth clock signal CK6.
  • k is an integer greater than or equal to zero.
  • FIG. 4 is a schematic diagram of the second structure of the gate driving circuit provided by the present application.
  • a plurality of cascaded gate driving circuits are connected to the first clock signal CK1 , the second clock signal CK2 , the third clock signal CK3 and the fourth clock signal CK4 .
  • each stage of the gate driving unit 100 is electrically connected to the first clock signal terminal CKa, the second clock signal terminal CKb, the third clock signal terminal CKc and the fourth clock signal terminal CKd.
  • the first clock signal terminal CKa of the 1+4kth stage gate driving unit is connected to the second clock signal CK2.
  • the second clock signal terminal CKb of the 1+4k stage gate driving unit is connected to the third clock signal CK3.
  • the third clock signal terminal CKc of the gate driving unit of the 1+4k stage is connected to the first clock signal CK1.
  • the fourth clock signal terminal CKd of the 1+4k stage gate driving unit is connected to the fourth clock signal CK4.
  • the first clock signal terminal CKa of the 2+4k-level gate driving unit is connected to the third clock signal CK3.
  • the second clock signal terminal CKb of the 2+4k stage gate driving unit is connected to the fourth clock signal CK4.
  • the third clock signal terminal CKc of the 2+4k stage gate driving unit is connected to the second clock signal CK2.
  • the fourth clock signal terminal CKd of the 2+4k stage gate driving unit is connected to the first clock signal CK1.
  • the first clock signal terminal CKa of the 3+4k-level gate driving unit is connected to the fourth clock signal CK4.
  • the second clock signal terminal CKb of the 3+4k stage gate driving unit is connected to the first clock signal CK1.
  • the third clock signal terminal CKc of the 3+4k stage gate driving unit is connected to the third clock signal CK3.
  • the fourth clock signal terminal CKd of the 3+4k stage gate driving unit is connected to the second clock signal CK2.
  • the first clock signal terminal CKa of the 4+4kth level gate driving unit is connected to the first clock signal CK1.
  • the second clock signal terminal CKb of the 4+4k stage gate driving unit is connected to the second clock signal CK2.
  • the third clock signal terminal CKc of the gate driving unit of the 4+4k stage is connected to the fourth clock signal CK4.
  • the fourth clock signal terminal CKd of the 4+4k stage gate driving unit is connected to the third clock signal CK3.
  • k is an integer greater than or equal to zero.
  • the driving sequence of the gate driving circuit provided in the present application includes a charging phase, an output phase, a pull-down phase and a maintenance phase.
  • the charging phase the first node is charged.
  • the output stage the scanning signal output terminal of the current stage outputs the scanning signal of the current stage.
  • the pull-down stage the potential of the first node and the potential of the output end of the scanning signal of the current stage are pulled down.
  • the maintenance phase the potential of the first node and the potential of the output terminal of the scanning signal of the current stage are maintained, and the potential of the second node is intermittently pulled down.
  • the maintenance phase includes a first maintenance phase and a second maintenance phase.
  • the fourth clock signal terminal is connected to a high-level signal for pulling up the potential of the second node.
  • the first clock signal terminal is connected with a high-level signal for pulling down the potential of the second node, so as to intermittently pull down the potential of the second node.
  • FIG. 5 is a schematic circuit diagram of a third-level gate driving unit corresponding to the gate driving circuit provided in the present application.
  • FIG. 6 is a timing diagram of a third-level gate drive unit corresponding to the gate drive circuit provided in the present application.
  • the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, the fourth clock signal CK4, the fifth clock signal CK5, the sixth clock signal CK6, the seventh clock signal CK7 and the eighth clock signal CK8 are A clock signal with the same period and a phase difference.
  • the first clock signal terminal CKa is connected to the fifth clock signal CK5.
  • the second clock signal terminal CKb is connected to the seventh clock signal CK7.
  • the third clock signal terminal CKc is connected to the third clock signal CK3.
  • the fourth clock signal terminal CKd is connected to the first clock signal CK1.
  • the output terminal of the upper-level scan signal is connected to the first-level scan signal G1 , and both the first-level scan signal G1 and the seventh clock signal CK7 are at high potential.
  • the first transistor T1 is turned on, and the first-level scan signal G1 is output to the first node Q through the first transistor T1 and charged to the bootstrap capacitor C, so that the potential of the first node Q is high.
  • the second transistor T2 is turned on.
  • the third clock signal CK3 is at a low potential, so that the potential at the third-level scan signal output terminal G3 is at a low potential.
  • the first-level scan signal G1 turns on the sixth transistor T6, and the constant-voltage low-level signal VGL is output to the second node P through the sixth transistor T6 to pull down the potential of the second node P.
  • the first clock signal CK1 is also at a high level.
  • the first clock signal CK1 or the seventh transistor T7 needs to be adjusted so that the current flowing through the seventh transistor T7 is small and the seventh transistor T7 cannot be turned on, thereby ensuring the operation of the circuit.
  • the potential of the first node Q is still at a high potential at this time.
  • the third clock signal CK3 is at a high potential.
  • the high potential of the first node Q turns on the second transistor T2, and the third clock signal CK3 is output to the third-level scanning signal output terminal G3 through the second transistor T2.
  • the potential of the third-level scan signal output terminal G3 is a high potential.
  • the potential of the first node Q is further pulled up, thereby further ensuring that the second transistor T2 is turned on.
  • the first-level scan signal G1 is at a low potential
  • the seventh clock signal CK7 is at a high potential.
  • the third transistor T3 is turned on, and the constant-voltage low-level signal VGL is output to the first node Q and the third-level scanning signal output terminal G3 through the third transistor T3.
  • the constant-voltage low-level signal VGL pulls down the potential of the first node Q.
  • the potential of the third-level scanning signal output terminal G3 is pulled down to the potential of the constant-voltage low-level signal VGL.
  • the first clock signal CK1 is at a high potential, and the seventh transistor T7 is turned on.
  • the first clock signal CK1 is output to the second node P through the seventh transistor T7 to pull up the potential of the second node P.
  • the fifth transistor T5 and the eighth transistor T8 are turned on.
  • the constant-voltage low-level signal is output to the first node Q.
  • the first node Q and the third-level scanning signal output terminal G3 maintain a low potential.
  • the maintenance period t4 includes a first maintenance period t41 and a second maintenance period t42.
  • the first clock signal CK1 is at a high level, and the seventh transistor T7 is turned on.
  • the first clock signal CK1 is output to the second node P through the seventh transistor T7 to pull up the potential of the second node P.
  • the fifth clock signal CK5 is at a high potential, and the fourth transistor T4 is turned on.
  • the constant-voltage low-level signal VGL is output to the second node P through the fourth transistor T4 to pull down the potential of the second node P.
  • the potential of the second node P is pulled down through the second maintenance period t42, so that the potential of the second node P is intermittently high. Therefore, the time when the fifth transistor T5 and the eighth transistor T8 are subjected to the high potential is reduced, the bias voltage of the fifth transistor T5 and the eighth transistor T8 is weakened, and the stability of the circuit is enhanced.
  • the duration of the first sustaining phase t41 and the second sustaining phase t42 can both be set to be half of the sustaining phase t4. Therefore, under the condition of ensuring the normal operation of the circuit, the bias voltage of the fifth transistor T5 and the eighth transistor T8 is weakened.
  • the first maintenance period t41 and the second maintenance period t42 may also be set at other time ratios, which is not limited in this application.
  • the pull-down control module 104 intermittently pulls up and pulls down the potential of the second node P, so that the potential of the second node P is intermittently high.
  • the high potential time of the second node P is greatly reduced, so that the fifth transistor T5 and the eighth transistor T8 can have sufficient recovery time after being forward biased.
  • the bias voltage of the thin film transistor in the pull-down control module 104 is effectively weakened, making the circuit more stable and improving the reliability of the circuit.
  • the present application provides a display panel, including the above-mentioned gate driving circuit.
  • FIG. 7 is a schematic structural diagram of a display panel provided by the present application.
  • the display panel 1000 includes a display area 10 and a gate driving circuit 20 integrated on the edge of the display area 10 .
  • the structure and principle of the gate driving circuit 20 are similar to those of the above-mentioned gate driving circuit, which will not be repeated here.
  • the display panel 1000 provided in this application adopts a gate driving circuit.
  • the gate drive circuit provided by the present application intermittently pulls up and pulls down the potential of the second node through the pull-down control module, so that the potential of the second node is intermittently at a high potential, effectively reducing the time that the second node is at a high potential .
  • the thin film transistor electrically connected to the second node can have sufficient recovery time after receiving the forward bias voltage, thereby making the circuit more stable and improving the reliability of the circuit.
  • the display panel 1000 provided by the present application reduces the number of thin film transistors in the gate driving unit, which can reduce the frame width of the display panel 1000 , making it easier to realize a narrow frame display panel.

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Abstract

一种栅极驱动电路及显示面板，栅极驱动电路通过下拉控制模块（104）对第二节点（P）的电位进行间歇性上拉和下拉，使得第二节点（P）的电位间歇性为高电位。有效减小了第二节点（P）的高电位时间，使得与第二节点（P）电性连接的薄膜晶体管在受到正向偏压后，能够有足够的恢复时间，从而使得电路更加稳定，提升电路的信赖能力。

Description

一种栅极驱动电路及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种栅极驱动电路及显示面板。
 背景技术
液晶显示装置作为电子设备的显示部件已经广泛的应用于各种电子产品中，而GOA（Gate Driver On Array, GOA）电路是液晶显示装置中的一个重要组成部分。也就是利用现有薄膜晶体管液晶显示器阵列（Array）制程将栅极（Gate）行扫描驱动信号电路制作在Array基板上，实现对Gate逐行扫描的驱动方式的一项技术。
根据面板内采用的薄膜晶体管（Thin Film Transistor, TFT）类型，可以分为N型金属氧化物半导体（Negative channel-Metal-Oxide-Semiconductor, NMOS）型，P型金属氧化物半导体（Positive channel-Metal-Oxide-Semiconductor, PMOS）型，以及皆有NMOS和PMOS TFT的互补金属氧化物半导体（Complementary Metal Oxide Semiconductor, CMOS）。类似的，栅极驱动电路分为NMOS电路、PMOS电路以及CMOS电路。相比于CMOS电路，由于NMOS电路可节省工序，对于提高良率以及降低成本都大有裨益，所以开发稳定的NMOS电路具有现实的产业需求。NMOS TFT载流子为电子，迁移率较高，器件相对于PMOS（载流子为空穴）更容易损伤。
在对现有技术的研究和实践过程中，本申请的发明人发现，为保证显示正常，电路下拉保持时，TFT栅极准位长时间处于高电位状态，使得TFT的偏压过大从而破坏器件。表现在面板上就是产品的高温信赖性不足，容易出现栅极驱动电路失效，出现分屏、画面异常等现象。
 技术问题
本申请提供一种栅极驱动电路及显示面板，可以避免晶体管长时间处于偏压状态，从而增强电路稳定性，避免栅极驱动电路失效。
 技术解决方案
本申请提供一种栅极驱动电路，包括多级级联设置的栅极驱动单元，其中，每一级所述栅极驱动单元均包括：
上拉控制模块，所述上拉控制模块电性连接于第一节点，所述上拉控制模块用于控制所述第一节点的电位；
上拉模块，所述上拉模块电性连接于所述第一节点以及本级扫描信号输出端，所述上拉模块用于在所述第一节点的电位的控制下，拉高所述本级扫描信号输出端的电位；
下拉模块，所述下拉模块电性连接于所述本级扫描信号输出端，所述下拉模块用于拉低所述本级扫描信号输出端的电位；以及
下拉控制模块，所述下拉控制模块电性连接于第二节点、所述第一节点、第一时钟信号端以及所述本级扫描信号输出端，所述下拉控制模块用于在所述第一时钟信号端输入的信号的控制下，间歇性拉低所述第二节点的电位，维持所述第一节点的电位以及所述本级扫描信号输出端的电位。
可选的，在本申请的一些实施例中，所述上拉控制模块包括第一晶体管以及自举电容，所述第一晶体管的栅极电性连接于第二时钟信号端，所述第一晶体管的源极或漏极中的一个电性连接于上一级扫描信号输出端，所述第一晶体管的源极或漏极中的另一个电性连接于所述第一节点；所述自举电容的一端电性连接于所述第一节点，所述自举电容的另一端电性连接于所述本级扫描信号输出端。
可选的，在本申请的一些实施例中，所述上拉模块包括第二晶体管，所述第二晶体管的栅极电性连接于所述第一节点，所述第二晶体管的源极或漏极中的一个电性连接于第三时钟信号端，所述第二晶体管的源极或漏极中的另一个电性连接于所述本级扫描信号输出端。
可选的，在本申请的一些实施例中，所述下拉模块包括第三晶体管，所述第三晶体管的栅极电性连接于第二时钟信号端，所述第三晶体管的源极或漏极中的一个接入恒压低电平信号，所述第三晶体管的源极或漏极中的另一个电性连接于所述本级扫描信号输出端。
可选的，在本申请的一些实施例中，所述下拉控制模块包括第四晶体管、第五晶体管、第六晶体管、第七晶体管以及第八晶体管；
所述第四晶体管的栅极电性连接于所述第一时钟信号端，所述第四晶体管的源极或漏极中的一个接入恒压低电平信号，所述第四晶体管的源极或漏极中的另一个电性连接于所述第二节点；
所述第五晶体管的栅极电性连接于所述第二节点，所述第五晶体管的源极或漏极中的一个接入所述恒压低电平信号，所述第五晶体管的源极或漏极中的另一个电性连接于所述第一节点；
所述第六晶体管的栅极电性连接于所述第一节点，所述第六晶体管的源极或漏极中的一个接入所述恒压低电平信号，所述第六晶体管的源极或漏极中的另一个电性连接于所述第二节点；
所述第七晶体管的栅极和源极或漏极中的一个均电性连接于第四时钟信号端，所述第七晶体管的源极或漏极中的另一个电性连接于所述第二节点；
所述第八晶体管的栅极电性连接于所述第二节点，所述第八晶体管的源极或漏极中的一个接入所述恒压低电平信号，所述第八晶体管的源极或漏极中的另一个电性连接于所述本级扫描信号输出端。
可选的，在本申请的一些实施例中，还包括复位模块，所述复位模块接入复位信号以及恒压低电平信号，并电性连接于所述第一节点以及所述第二节点，用于复位所述第一节点以及所述第二节点的电位。
可选的，在本申请的一些实施例中，所述复位模块包括第九晶体管和第十晶体管；
所述第九晶体管的栅极接入所述复位信号，所述第九晶体管的源极或漏极中的一个接入所述恒压低电平信号，所述第九晶体管的源极或漏极中的另一个电性连接于所述第二节点；
所述第十晶体管的栅极接入所述复位信号，所述第十晶体管的源极或漏极中的一个接入所述恒压低电平信号，所述第十晶体管的源极或漏极中的另一个电性连接于所述第一节点。
可选的，在本申请的一些实施例中，还包括全开关控制模块，所述全开关控制模块接入全开关控制信号、恒压低电平信号，并电性连接于所述本级扫描信号输出端；所述全开关控制模块用于基于所述全开关控制信号以及所述恒压低电平信号同时控制每一所述栅极驱动单元的扫描信号输出端的电位。
可选的，在本申请的一些实施例中，所述全开关控制模块包括第十一晶体管，所述第十一晶体管的栅极接入所述全开关控制信号，所述第十一晶体管的源极或漏极中的一个接入所述恒压低电平信号，所述第十一晶体管的源极或漏极中的另一个电性连接于所述本级扫描信号输出端。
可选的，在本申请的一些实施例中，所述栅极驱动电路接入第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号、第五时钟信号、第六时钟信号、第七时钟信号以及第八时钟信号；
所述栅极驱动电路包括多个级联设置的奇数级栅极驱动单元以及多个级联设置的偶数级栅极驱动单元；其中，
所述多个级联设置的奇数级栅极驱动单元接入所述第一时钟信号、所述第三时钟信号、所述第五时钟信号以及所述第七时钟信号；
所述多个级联设置的偶数级栅极驱动单元接入所述第二时钟信号、所述第四时钟信号、所述第六时钟信号以及所述第八时钟信号。
可选的，在本申请的一些实施例中，每一级所述栅极驱动单元还电性连接于第二时钟信号端、第三时钟信号端以及第四时钟信号端；
在所述多级级联设置的奇数级栅极驱动单元中，第1+8k级栅极驱动单元的第一时钟信号端接入所述第三时钟信号，所述第1+8k级栅极驱动单元的第二时钟信号端接入所述第五时钟信号，所述第1+8k级栅极驱动单元的第三时钟信号端接入所述第一时钟信号，所述第1+8k级栅极驱动单元的第四时钟信号端接入所述第七时钟信号；
第3+8k级栅极驱动单元的第一时钟信号端接入所述第五时钟信号，所述第3+8k级栅极驱动单元的第二时钟信号端接入所述第七时钟信号，所述第3+8k级栅极驱动单元的第三时钟信号端接入所述第三时钟信号，所述第3+8k级栅极驱动单元的第四时钟信号端接入所述第一时钟信号；
第5+8k级栅极驱动单元的第一时钟信号端接入所述第七时钟信号，所述第5+8k级栅极驱动单元的第二时钟信号端接入所述第一时钟信号，所述第5+8k级栅极驱动单元的第三时钟信号端接入所述第五时钟信号，所述第5+8k级栅极驱动单元的第四时钟信号端接入所述第三时钟信号；
第7+8k级栅极驱动单元的第一时钟信号端接入所述第一时钟信号，所述第7+8k级栅极驱动单元的第二时钟信号端接入所述第三时钟信号，所述第7+8k级栅极驱动单元的第三时钟信号端接入所述第七时钟信号，所述第7+8k级栅极驱动单元的第四时钟信号端接入所述第五时钟信号；
在所述多级级联设置的偶数级栅极驱动单元中，第2+8k级栅极驱动单元的第一时钟信号端接入所述第四时钟信号，所述第2+8k级栅极驱动单元的第二时钟信号端接入所述第六时钟信号，所述第2+8k级栅极驱动单元的第三时钟信号端接入所述第二时钟信号，所述第2+8k级栅极驱动单元的第四时钟信号端接入所述第八时钟信号；
第4+8k级栅极驱动单元的第一时钟信号端接入所述第六时钟信号，所述第4+8k级栅极驱动单元的第二时钟信号端接入所述第八时钟信号，所述第4+8k级栅极驱动单元的第三时钟信号端接入所述第四时钟信号，所述第4+8k级栅极驱动单元的第四时钟信号端接入所述第二时钟信号；
第6+8k级栅极驱动单元的第一时钟信号端接入所述第八时钟信号，所述第6+8k级栅极驱动单元的第二时钟信号端接入所述第二时钟信号，所述第6+8k级栅极驱动单元的第三时钟信号端接入所述第六时钟信号，所述第6+8k级栅极驱动单元的第四时钟信号端接入所述第四时钟信号；
第8+8k级栅极驱动单元的第一时钟信号端接入所述第二时钟信号，所述第8+8k级栅极驱动单元的第二时钟信号端接入所述第四时钟信号，所述第8+8k级栅极驱动单元的第三时钟信号端接入所述第八时钟信号，所述第8+8k级栅极驱动单元的第四时钟信号端接入所述第六时钟信号；其中，k为大于或等于零的整数。
可选的，在本申请的一些实施例中，所述栅极驱动电路接入第一时钟信号、第二时钟信号、第三时钟信号以及第四时钟信号。
可选的，在本申请的一些实施例中，每一级所述栅极驱动单元还电性连接于第二时钟信号端、第三时钟信号端以及第四时钟信号端；
第1+4k级栅极驱动单元的第一时钟信号端接入所述第一二时钟信号，所述第1+4k级栅极驱动单元的第二时钟信号端接入所述第四三时钟信号，所述第1+4k级栅极驱动单元的第三时钟信号端接入所述第二一时钟信号，所述第1+4k级栅极驱动单元的第四时钟信号端接入所述第三四时钟信号；
第2+4k级栅极驱动单元的第一时钟信号端接入所述第二三时钟信号，所述第2+4k级栅极驱动单元的第二时钟信号端接入所述第一四时钟信号，所述第2+4k级栅极驱动单元的第三时钟信号端接入所述第三二时钟信号，所述第2+4k级栅极驱动单元的第四时钟信号端接入所述第四一时钟信号；
第3+4k级栅极驱动单元的第一时钟信号端接入所述第三四时钟信号，所述第3+4k级栅极驱动单元的第二时钟信号端接入所述第二一时钟信号，所述第3+4k级栅极驱动单元的第三时钟信号端接入所述第四三时钟信号，所述第3+4k级栅极驱动单元的第四时钟信号端接入所述第一二时钟信号；
第4+4k级栅极驱动单元的第一时钟信号端接入所述第四一时钟信号，所述第4+4k级栅极驱动单元的第二时钟信号端接入所述第三二时钟信号，所述第4+4k级栅极驱动单元的第三时钟信号端接入所述第一四时钟信号，所述第4+4k级栅极驱动单元的第四时钟信号端接入所述第二三时钟信号；其中，k为大于或等于零的整数。
可选的，在本申请的一些实施例中，所述栅极驱动电路的驱动时序包括：
充电阶段，对所述第一节点进行充电；
输出阶段，所述本级扫描信号输出端输出本级扫描信号；
下拉阶段，将所述第一节点的电位以及所述本级扫描信号输出端的电位下拉；
维持阶段，维持所述第一节点的电位以及所述本级扫描信号输出端的电位，并间歇性拉低所述第二节点的电位。
可选的，在本申请的一些实施例中，所述维持阶段包括第一维持阶段和第二维持阶段，所述栅极驱动电路还连接于第四时钟信号端；
在所述第一维持阶段，所述第四时钟信号端接入高电平信号，用于将所述第二节点的电位上拉；
在所述第二维持阶段，所述第一时钟信号端接入高电平信号，用于将所述第二节点的电位下拉，以间歇性拉低所述第二节点的电位。
可选的，在本申请的一些实施例中，包括多级级联设置的栅极驱动单元，其中，每一级所述栅极驱动单元均包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管以及第八晶体管；
所述第一晶体管的栅极电性连接于第二时钟信号端，所述第一晶体管的源极或漏极中的一个电性连接于上一级扫描信号输出端，所述第一晶体管的源极或漏极中的另一个电性连接于第一节点；
所述第二晶体管的栅极电性连接于所述第一节点，所述第二晶体管的源极或漏极中的一个电性连接于第三时钟信号端，所述第二晶体管的源极或漏极中的另一个电性连接于本级扫描信号输出端；
所述第三晶体管的栅极电性连接于所述第二时钟信号端，所述第三晶体管的源极或漏极中的一个接入恒压低电平信号，所述第三晶体管的源极或漏极中的另一个电性连接于所述本级扫描信号输出端；
所述第四晶体管的栅极电性连接于所述第一时钟信号端，所述第四晶体管的源极或漏极中的一个接入所述恒压低电平信号，所述第四晶体管的源极或漏极中的另一个电性连接于第二节点；
所述第五晶体管的栅极电性连接于所述第二节点，所述第五晶体管的源极或漏极中的一个接入所述恒压低电平信号，所述第五晶体管的源极或漏极中的另一个电性连接于所述第一节点；
所述第六晶体管的栅极电性连接于所述第一节点，所述第六晶体管的源极或漏极中的一个接入所述恒压低电平信号，所述第六晶体管的源极或漏极中的另一个电性连接于所述第二节点；
所述第七晶体管的栅极和源极或漏极中的一个均电性连接于第四时钟信号端，所述第七晶体管的源极或漏极中的另一个电性连接于所述第二节点；
所述第八晶体管的栅极电性连接于所述第二节点，所述第八晶体管的源极或漏极中的一个接入所述恒压低电平信号，所述第八晶体管的源极或漏极中的另一个电性连接于所述本级扫描信号输出端。
可选的，在本申请的一些实施例中，所述栅极驱动电路还包括第九晶体管和第十晶体管；
所述第九晶体管的栅极接入复位信号，所述第九晶体管的源极或漏极中的一个接入所述恒压低电平信号，所述第九晶体管的源极或漏极中的另一个电性连接于所述第二节点；
所述第十晶体管的栅极接入所述复位信号，所述第十晶体管的源极或漏极中的一个接入所述恒压低电平信号，所述第十晶体管的源极或漏极中的另一个电性连接于所述第一节点。
可选的，在本申请的一些实施例中，所述栅极驱动电路的驱动时序包括：
充电阶段，对所述第一节点进行充电；
输出阶段，所述本级扫描信号输出端输出本级扫描信号；
下拉阶段，将所述第一节点的电位以及所述本级扫描信号输出端的电位下拉；
维持阶段，维持所述第一节点的电位以及所述本级扫描信号输出端的电位，并间歇性拉低所述第二节点的电位。
可选的，在本申请的一些实施例中，所述维持阶段包括第一维持阶段和第二维持阶段；
在所述第一维持阶段，所述第四时钟信号端接入高电平信号，用于将所述第二节点的电位上拉；
在所述第二维持阶段，所述第一时钟信号端接入高电平信号，用于将所述第二节点的电位下拉，以间歇性拉低所述第二节点的电位。
相应的，本申请还提供一种显示面板，包括以上所述的栅极驱动电路。
 有益效果
本申请提供的栅极驱动电路通过下拉控制模块对第二节点的电位进行间歇性上拉和下拉，使得第二节点的电位间歇性为高电位，有效减小了第二节点处于高电位的时间，使得与第二节点电性连接的薄膜晶体管在受到正向偏压后，能够有足够的恢复时间。该方案有效改善了下拉控制模块中薄膜晶体管的偏压情况，使得电路更加稳定，提升了电路的信赖能力。另外，本申请提供的显示面板减少了栅极驱动单元中薄膜晶体管的数量，可以减小显示面板的边框宽度，更易于实现窄边框显示面板。
 附图说明
为了更清楚地说明本申请中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请提供的栅极驱动电路中一栅极驱动单元的第一种电路示意图；
图2是本申请提供的栅极驱动电路中一栅极驱动单元的第二种电路示意图；
图3是本申请提供的栅极驱动电路的第一种结构示意图；
图4是本申请提供的栅极驱动电路的第二种结构示意图；
图5是本申请提供的栅极驱动电路对应的第3级栅极驱动单元的一种电路示意图；
图6是本申请提供的栅极驱动电路对应的第3级栅极驱动单元的时序示意图；
图7为本申请提供的显示面板的一种结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的晶体管的源极或漏极中的一个、源极或漏极中的另一个是对称的，所以其源极或漏极中的一个、源极或漏极中的另一个是可以互换的。在本申请实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极或漏极中的一个，另一极称为源极或漏极中的另一个。按附图中的形态规定开关晶体管的中间端为栅极、信号输入端为源极或漏极中的一个、输出端为源极或漏极中的另一个。此外本申请实施例所采用的晶体管可以包括P型晶体管和/或N型晶体管两种，其中，P型晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型晶体管为在栅极为高电平时导通，在栅极为低电平时截止。
本申请提供一种栅极驱动电路及显示面板。以下分别进行详细说明。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
本申请提供一种栅极驱动电路，包括多级级联设置的栅极驱动单元。其中，第n级栅极驱动单元用于输出第n级扫描驱动信号以对显示区域中对应的第n条扫描线进行充电，从而实现显示面板的正常显示。
请参阅图1，图1是本申请提供的栅极驱动电路中一栅极驱动单元的第一种电路示意图。其中，每一级栅极驱动单元100均包括上拉控制模块101、上拉模块102、下拉模块103以及下拉控制模块104。上拉控制模块101电性连接于第一节点Q。上拉控制模块101用于控制第一节点Q的电位。上拉模块102电性连接于第一节点Q以及本级扫描信号输出端Gn。上拉模块102用于在第一节点Q的电位的控制下，拉高本级扫描信号输出端Gn的电位。下拉模块103电性连接于本级扫描信号输出端Gn。下拉模块103用于拉低本级扫描信号输出端Gn的电位。下拉控制模块104电性连接于第二节点P、第一节点Q、第一时钟信号端CKa以及本级扫描信号输出端Gn。下拉控制模块104用于在第一时钟信号端CKa输入的信号的控制下，间歇性拉低第二节点P的电位，维持第一节点Q的电位以及本级扫描信号输出端Gn的电位。
本申请提供的栅极驱动单元100中的下拉控制模块104可在第一时钟信号端CKa输入的信号控制下，间歇性拉低第二节点P的电位。从而降低第二节点P的高电位持续时间，减弱下拉控制模块104中薄膜晶体管受到的偏压。进而提高栅极驱动电路的稳定性。
具体的，上拉控制模块101包括第一晶体管T1以及自举电容C。其中，第一晶体管T1的栅极电性连接于第二时钟信号端CKb。第一晶体管T1的源极或漏极中的一个电性连接于上一级扫描信号输出端Gn-2。第一晶体管T1的源极或漏极中的另一个电性连接于第一节点Q。自举电容C的一端电性连接于第一节点Q。自举电容C的另一端电性连接于本级扫描信号输出端Gn。需要说明的是，当栅极驱动单元100为第1级栅极驱动单元时，上一级扫描信号输出端Gn-2接入一起始信号，以触发栅极驱动单元该GOA单元100输出扫描驱动信号。
具体的，上拉模块102包括第二晶体管T2。其中，第二晶体管T2的栅极电性连接于第一节点Q。第二晶体管T2的源极或漏极中的一个电性连接于第三时钟信号端CKc。第二晶体管T2的源极或漏极中的另一个电性连接于本级扫描信号输出端Gn。
具体的，下拉模块103包括第三晶体管T3。其中，第三晶体管T3的栅极电性连接于第二时钟信号端CKb。第三晶体管T3的源极或漏极中的一个接入恒压低电平信号VGL。第三晶体管T3的源极或漏极中的另一个电性连接于本级扫描信号输出端Gn。
具体的，下拉控制模块104包括第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7以及第八晶体管T8。
其中，第四晶体管T4的栅极电性连接于第一时钟信号端CKa。第四晶体管T4的源极或漏极中的一个接入恒压低电平信号VGL。第四晶体管T4的源极或漏极中的另一个电性连接于第二节点P。第五晶体管T5的栅极电性连接于第二节点P。第五晶体管T5的源极或漏极中的一个接入恒压低电平信号VGL。第五晶体管T5的源极或漏极中的另一个电性连接于第一节点Q。第六晶体管T6的栅极电性连接于第一节点Q。第六晶体管T6的源极或漏极中的一个接入恒压低电平信号VGL。第六晶体管T6的源极或漏极中的另一个电性连接于第二节点P。第七晶体管T7的栅极和源极或漏极中的一个均电性连接于第四时钟信号端CKd。第七晶体管T7的源极或漏极中的另一个电性连接于第二节点P。第八晶体管T8的栅极电性连接于第二节点P。第八晶体管T8的源极或漏极中的一个接入恒压低电平信号VGL。第八晶体管T8的源极或漏极中的另一个电性连接于本级扫描信号输出端Gn。
需要说明的是，本申请提供的栅极驱动单元100，通过在下拉控制模块104中增加第一时钟信号端CKa以控制第二节点P的电位，减少第二节点P的高电位持续时间，进而减弱第五晶体管T5和第八晶体管T8在工作时受到的偏压，进而提高电路的稳定性。
请参阅图2，图2是本申请提供的栅极驱动电路中一栅极驱动单元的第二种电路示意图。图2所示的栅极驱动单元100中还包括复位模块105，复位模块105接入复位信号RE以及恒压低电平信号VGL，并电性连接于第一节点Q以及第二节点P，用于复位第一节点Q以及第二节点P的电位。
具体的，复位模块105包括第九晶体管T9和第十晶体管T10。
其中，第九晶体管T9的栅极接入复位信号RE。第九晶体管T9的源极或漏极中的一个接入恒压低电平信号VGL。第九晶体管T9的源极或漏极中的另一个电性连接于第二节点P。第十晶体管T10的栅极接入复位信号RE。第十晶体管T10的源极或漏极中的一个接入恒压低电平信号VGL。第十晶体管T10的源极或漏极中的另一个电性连接于第一节点Q。
请继续参阅图2，图2所示的栅极驱动单元100中还包括全开关控制模块106。全开关控制模块106接入全开关控制信号GAS、恒压低电平信号VGL，并电性连接于本级扫描信号输出端Gn。全开关控制模块106用于基于全开关控制信号GAS以及恒压低电平信号VGL同时控制每一栅极驱动单元100的扫描信号输出端的电位。
具体的，全开关控制模块106包括第十一晶体管T11。第十一晶体管T11的栅极接入全开关控制信号GAS。第十一晶体管T11的源极或漏极中的一个接入恒压低电平信号VGL。第十一晶体管T11的源极或漏极中的另一个电性连接于本级扫描信号输出端Gn。
本申请提供的栅极驱动电路可以采用双边驱动，也可以采用单边驱动，本申请对此不作限制。
请参阅图3，图3是本申请提供的栅极驱动电路的第一种结构示意图。栅极驱动电路接入第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3、第四时钟信号CK4、第五时钟信号CK5、第六时钟信号CK6、第七时钟信号CK7以及第八时钟信号CK8。
具体的，栅极驱动电路包括多个级联设置的奇数级栅极驱动单元以及多个级联设置的偶数级栅极驱动单元。其中，多个级联设置的奇数级栅极驱动单元接入第一时钟信号CK1、第三时钟信号CK3、第五时钟信号CK5以及第七时钟信号CK7。多个级联设置的偶数级栅极驱动单元接入第二时钟信号CK2、第四时钟信号CK4、第六时钟信号CK6以及第八时钟信号CK8。
其中，每一级栅极驱动单元100电性连接于第一时钟信号端CKa、第二时钟信号端CKb、第三时钟信号端CKc以及第四时钟信号端CKd。
在多级级联设置的奇数级栅极驱动单元中，第1+8k级栅极驱动单元的第一时钟信号端CKa接入第三时钟信号CK3。第1+8k级栅极驱动单元的第二时钟信号端CKb接入第五时钟信号CK5。第1+8k级栅极驱动单元的第三时钟信号端CKc接入第一时钟信号CK1。第1+8k级栅极驱动单元的第四时钟信号端CKd接入第七时钟信号CK7。
在一些实施例中，第3+8k级栅极驱动单元的第一时钟信号端CKa接入第五时钟信号CK5。第3+8k级栅极驱动单元的第二时钟信号端CKb接入第七时钟信号CK7。第3+8k级栅极驱动单元的第三时钟信号端CKc接入第三时钟信号CK3。第3+8k级栅极驱动单元的第四时钟信号端CKd接入第一时钟信号CK1。
在一些实施例中，第5+8k级栅极驱动单元的第一时钟信号端CKa接入第七时钟信号CK7。第5+8k级栅极驱动单元的第二时钟信号端CKb接入第一时钟信号CK1。第5+8k级栅极驱动单元的第三时钟信号端CKc接入第五时钟信号CK5。第5+8k级栅极驱动单元的第四时钟信号端CKd接入第三时钟信号CK3。
在一些实施例中，第7+8k级栅极驱动单元的第一时钟信号端CKa接入第一时钟信号CK1。第7+8k级栅极驱动单元的第二时钟信号端CKb接入第三时钟信号CK3。第7+8k级栅极驱动单元的第三时钟信号端CKc接入第七时钟信号CK7。第7+8k级栅极驱动单元的第四时钟信号端CKd接入第五时钟信号CK5。
在多级级联设置的偶数级栅极驱动单元中，第2+8k级栅极驱动单元的第一时钟信号端CKa接入第四时钟信号CK4。第2+8k级栅极驱动单元的第二时钟信号端CKb接入第六时钟信号CK6。第2+8k级栅极驱动单元的第三时钟信号端CKc接入第二时钟信号CK2。第2+8k级栅极驱动单元的第四时钟信号端CKd接入第八时钟信号CK8。
在一些实施例中，第4+8k级栅极驱动单元的第一时钟信号端CKa接入第六时钟信号CK6。第4+8k级栅极驱动单元的第二时钟信号端CKb接入第八时钟信号CK8。第4+8k级栅极驱动单元的第三时钟信号端CKc接入第四时钟信号CK4。第4+8k级栅极驱动单元的第四时钟信号端CKd接入第二时钟信号CK2。
在一些实施例中，第6+8k级栅极驱动单元的第一时钟信号端CKa接入第八时钟信号CK8。第6+8k级栅极驱动单元的第二时钟信号端CKb接入第二时钟信号CK2。第6+8k级栅极驱动单元的第三时钟信号端CKc接入第六时钟信号CK6。第6+8k级栅极驱动单元的第四时钟信号端CKd接入第四时钟信号CK4。
在一些实施例中，第8+8k级栅极驱动单元的第一时钟信号端CKa接入第二时钟信号CK2。第8+8k级栅极驱动单元的第二时钟信号端CKb接入第四时钟信号CK4。第8+8k级栅极驱动单元的第三时钟信号端CKc接入第八时钟信号CK8。第8+8k级栅极驱动单元的第四时钟信号端CKd接入第六时钟信号CK6。其中，k为大于或等于零的整数。
请参阅图4，图4是本申请提供的栅极驱动电路的第二种结构示意图。多个级联设置的栅极驱动电路接入第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3以及第四时钟信号CK4。
其中，每一级栅极驱动单元100电性连接于第一时钟信号端CKa、第二时钟信号端CKb、第三时钟信号端CKc以及第四时钟信号端CKd。
在一些实施例中，第1+4k级栅极驱动单元的第一时钟信号端CKa接入第二时钟信号CK2。第1+4k级栅极驱动单元的第二时钟信号端CKb接入第三时钟信号CK3。第1+4k级栅极驱动单元的第三时钟信号端CKc接入第一时钟信号CK1。第1+4k级栅极驱动单元的第四时钟信号端CKd接入第四时钟信号CK4。
在一些实施例中，第2+4k级栅极驱动单元的第一时钟信号端CKa接入第三时钟信号CK3。第2+4k级栅极驱动单元的第二时钟信号端CKb接入第四时钟信号CK4。第2+4k级栅极驱动单元的第三时钟信号端CKc接入第二时钟信号CK2。第2+4k级栅极驱动单元的第四时钟信号端CKd接入第一时钟信号CK1。
在一些实施例中，第3+4k级栅极驱动单元的第一时钟信号端CKa接入第四时钟信号CK4。第3+4k级栅极驱动单元的第二时钟信号端CKb接入第一时钟信号CK1。第3+4k级栅极驱动单元的第三时钟信号端CKc接入第三时钟信号CK3。第3+4k级栅极驱动单元的第四时钟信号端CKd接入第二时钟信号CK2。
在一些实施例中，第4+4k级栅极驱动单元的第一时钟信号端CKa接入第一时钟信号CK1。第4+4k级栅极驱动单元的第二时钟信号端CKb接入第二时钟信号CK2。第4+4k级栅极驱动单元的第三时钟信号端CKc接入第四时钟信号CK4。第4+4k级栅极驱动单元的第四时钟信号端CKd接入第三时钟信号CK3。其中，k为大于或等于零的整数。
需要说明的是，本申请提供的栅极驱动电路的驱动时序包括充电阶段、输出阶段、下拉阶段以及维持阶段。在充电阶段，对第一节点进行充电。在输出阶段，本级扫描信号输出端输出本级扫描信号。在下拉阶段，将第一节点的电位以及本级扫描信号输出端的电位下拉。在维持阶段，维持第一节点的电位以及本级扫描信号输出端的电位，并间歇性拉低第二节点的电位。
其中，维持阶段包括第一维持阶段和第二维持阶段。在第一维持阶段，第四时钟信号端接入高电平信号，用于将第二节点的电位上拉。在第二维持阶段，第一时钟信号端接入高电平信号，用于将第二节点的电位下拉，以间歇性拉低第二节点的电位。
下面以第3级栅极驱动单元为例说明图3所示的栅极驱动电路对应的第3级栅极驱动单元的工作原理。请参阅图5和图6，图5是本申请提供的栅极驱动电路对应的第3级栅极驱动单元的一种电路示意图。图6是本申请提供的栅极驱动电路对应的第3级栅极驱动单元的时序示意图。其中，第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3、第四时钟信号CK4、第五时钟信号CK5、第六时钟信号CK6、第七时钟信号CK7以及第八时钟信号CK8为周期相同、且具有相位差的时钟信号。
在第3级栅极驱动单元100中，第一时钟信号端CKa接入第五时钟信号CK5。第二时钟信号端CKb接入第七时钟信号CK7。第三时钟信号端CKc接入第三时钟信号CK3。第四时钟信号端CKd接入第一时钟信号CK1。
在充电阶段t1，上一级扫描信号输出端接入第1级扫描信号G1，第1级扫描信号G1和第七时钟信号CK7均为高电位。此时第一晶体管T1打开，第1级扫描信号G1经第一晶体管T1输出至第一节点Q，并向自举电容C充电，使得第一节点Q的电位为高电位。此时，由于第一节点Q的电位为高电位，使得第二晶体管T2打开。与此同时，第三时钟信号CK3为低电位，进而使得第3级扫描信号输出端G3的电位为低电位。并且第1级扫描信号G1将第六晶体管T6打开，恒压低电平信号VGL经第六晶体管T6输出至第二节点P，将第二节点P的电位下拉。
需要说明的是，在充电阶段t1，第一时钟信号CK1也为高电平。此时需要对第一时钟信号CK1或第七晶体管T7进行调整，使流经第七晶体管T7的电流较小，无法打开第七晶体管T7，从而保证电路的工作。
在输出阶段t2，由于自举电容C的作用，此时第一节点Q的电位仍为高电位。第三时钟信号CK3为高电位。第一节点Q为高电位使第二晶体管T2打开，第三时钟信号CK3经第二晶体管T2输出至第3级扫描信号输出端G3。此时，第3级扫描信号输出端G3的电位为高电位。与此同时，由于自举电容C的耦合作用，使得第一节点Q的电位进一步被拉高，从而可以进一步保障第二晶体管T2打开。
在下拉阶段t3，此时第1级扫描信号G1为低电位，第七时钟信号CK7为高电位。第三晶体管T3打开，恒压低电平信号VGL经第三晶体管T3输出至第一节点Q和第3级扫描信号输出端G3。恒压低电平信号VGL将第一节点Q的电位下拉。此时，第3级扫描信号输出端G3的电位被下拉至恒压低电平信号VGL的电位。
在维持阶段t4，第一时钟信号CK1为高电位，第七晶体管T7打开。第一时钟信号CK1经第七晶体管T7输出至第二节点P，将第二节点P的电位上拉。同时，由于第二节点P的电位为高电位，第五晶体管T5和第八晶体管T8打开。恒压低电平信号输出至第一节点Q。此时，第一节点Q和第3级扫描信号输出端G3维持为低电位。
其中，维持阶段t4包括第一维持阶段t41和第二维持阶段t42。在第一维持阶段t41，第一时钟信号CK1为高电平，第七晶体管T7打开。第一时钟信号CK1经第七晶体管T7输出至第二节点P，将第二节点P的电位上拉。在第二维持阶段t42，第五时钟信号CK5为高电位，第四晶体管T4打开。恒压低电平信号VGL经第四晶体管T4输出至第二节点P，将第二节点P的电位下拉。通过第二维持阶段t42将第二节点P的电位下拉，使第二节点P的电位间歇性为高电位。从而减少第五晶体管T5和第八晶体管T8受到高电位作用的时间，减弱第五晶体管T5和第八晶体管T8的偏压，增强电路的稳定性。
需要说明的是，可以将第一维持阶段t41和第二维持阶段t42的时间均设置为维持阶段t4的一半。从而在保证电路维持正常工作的情况下，减弱第五晶体管T5和第八晶体管T8的偏压。当然，第一维持阶段t41和第二维持阶段t42也可以以其他时长比例进行设置，本申请对此不做限制。
本申请通过下拉控制模块104对第二节点P的电位进行间歇性上拉和下拉，使得第二节点P的电位间歇性为高电位。大大减小了第二节点P的高电位时间，使第五晶体管T5和第八晶体管T8受到正向偏压后能够有足够的恢复时间。有效减弱了下拉控制模块104中薄膜晶体管的偏压情况，使得电路更加稳定，提升电路的信赖能力。
本申请提供一种显示面板，包括以上所述的栅极驱动电路。具体的，请参阅图7，图7为本申请提供的显示面板的一种结构示意图。如图7所示，显示面板1000包括显示区域10以及集成设置在显示区域10边缘上的栅极驱动电路20。其中，栅极驱动电路20与上述的栅极驱动电路的结构和原理类似，这里不再赘述。
本申请提供的显示面板1000采用一种栅极驱动电路。本申请提供的栅极驱动电路通过下拉控制模块对第二节点的电位进行间歇性上拉和下拉，使得第二节点的电位间歇性为高电位，有效减小了第二节点处于高电位的时间。使得与第二节点电性连接的薄膜晶体管在受到正向偏压后，能够有足够的恢复时间，从而使得电路更加稳定，提升电路的信赖能力。另外，本申请提供的显示面板1000减少了栅极驱动单元中薄膜晶体管的数量，可以减小显示面板1000的边框宽度，更易于实现窄边框显示面板。
以上对本申请所提供的一种栅极驱动电路及显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种栅极驱动电路，其中，包括多级级联设置的栅极驱动单元，其中，每一级所述栅极驱动单元均包括：
    上拉控制模块，所述上拉控制模块电性连接于第一节点，所述上拉控制模块用于控制所述第一节点的电位；
    上拉模块，所述上拉模块电性连接于所述第一节点以及所述本级扫描信号输出端，所述上拉模块用于在所述第一节点的电位的控制下，拉高所述本级扫描信号输出端的电位；
    下拉模块，所述下拉模块电性连接于本级扫描信号输出端，所述下拉模块用于拉低所述本级扫描信号输出端的电位；以及
    下拉控制模块，所述下拉控制模块电性连接于第二节点、所述第一节点、第一时钟信号端以及所述本级扫描信号输出端，所述下拉控制模块用于在所述第一时钟信号端输入的信号的控制下，间歇性拉低所述第二节点的电位，维持所述第一节点的电位以及所述本级扫描信号输出端的电位。
  2. 根据权利要求1所述的栅极驱动电路，其中，所述上拉控制模块包括第一晶体管以及自举电容，所述第一晶体管的栅极电性连接于第二时钟信号端，所述第一晶体管的源极或漏极中的一个电性连接于上一级扫描信号输出端，所述第一晶体管的源极或漏极中的另一个电性连接于所述第一节点；所述自举电容的一端电性连接于所述第一节点，所述自举电容的另一端电性连接于所述本级扫描信号输出端。
  3. 根据权利要求1所述的栅极驱动电路，其中，所述上拉模块包括第二晶体管，所述第二晶体管的栅极电性连接于所述第一节点，所述第二晶体管的源极或漏极中的一个电性连接于第三时钟信号端，所述第二晶体管的源极或漏极中的另一个电性连接于所述本级扫描信号输出端。
  4. 根据权利要求1所述的栅极驱动电路，其中，所述下拉模块包括第三晶体管，所述第三晶体管的栅极电性连接于第二时钟信号端，所述第三晶体管的源极或漏极中的一个接入恒压低电平信号，所述第三晶体管的源极或漏极中的另一个电性连接于所述本级扫描信号输出端。
  5. 根据权利要求1所述的栅极驱动电路，其中，所述下拉控制模块包括第四晶体管、第五晶体管、第六晶体管、第七晶体管以及第八晶体管；
    所述第四晶体管的栅极电性连接于所述第一时钟信号端，所述第四晶体管的源极或漏极中的一个接入恒压低电平信号，所述第四晶体管的源极或漏极中的另一个电性连接于所述第二节点；
    所述第五晶体管的栅极电性连接于所述第二节点，所述第五晶体管的源极或漏极中的一个接入所述恒压低电平信号，所述第五晶体管的源极或漏极中的另一个电性连接于所述第一节点；
    所述第六晶体管的栅极电性连接于所述第一节点，所述第六晶体管的源极或漏极中的一个接入所述恒压低电平信号，所述第六晶体管的源极或漏极中的另一个电性连接于所述第二节点；
    所述第七晶体管的栅极和源极或漏极中的一个均电性连接于第四时钟信号端，所述第七晶体管的源极或漏极中的另一个电性连接于所述第二节点；
    所述第八晶体管的栅极电性连接于所述第二节点，所述第八晶体管的源极或漏极中的一个接入所述恒压低电平信号，所述第八晶体管的源极或漏极中的另一个电性连接于所述本级扫描信号输出端。
  6. 根据权利要求1所述的栅极驱动电路，其中，还包括复位模块，所述复位模块接入复位信号以及恒压低电平信号，并电性连接于所述第一节点以及所述第二节点，用于复位所述第一节点以及所述第二节点的电位。
  7. 根据权利要求6所述的栅极驱动电路，其中，所述复位模块包括第九晶体管和第十晶体管；
    所述第九晶体管的栅极接入所述复位信号，所述第九晶体管的源极或漏极中的一个接入所述恒压低电平信号，所述第九晶体管的源极或漏极中的另一个电性连接于所述第二节点；
    所述第十晶体管的栅极接入所述复位信号，所述第十晶体管的源极或漏极中的一个接入所述恒压低电平信号，所述第十晶体管的源极或漏极中的另一个电性连接于所述第一节点。
  8. 根据权利要求1所述的栅极驱动电路，其中，还包括全开关控制模块，所述全开关控制模块接入全开关控制信号、恒压低电平信号，并电性连接于所述本级扫描信号输出端；所述全开关控制模块用于基于所述全开关控制信号以及所述恒压低电平信号同时控制每一所述栅极驱动单元的扫描信号输出端的电位。
  9. 根据权利要求8所述的栅极驱动电路，其中，所述全开关控制模块包括第十一晶体管，所述第十一晶体管的栅极接入所述全开关控制信号，所述第十一晶体管的源极或漏极中的一个接入所述恒压低电平信号，所述第十一晶体管的源极或漏极中的另一个电性连接于所述本级扫描信号输出端。
  10. 根据权利要求1所述的栅极驱动电路，其中，所述栅极驱动电路接入第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号、第五时钟信号、第六时钟信号、第七时钟信号以及第八时钟信号；
    所述栅极驱动电路包括多个级联设置的奇数级栅极驱动单元以及多个级联设置的偶数级栅极驱动单元；其中，
    所述多个级联设置的奇数级栅极驱动单元接入所述第一时钟信号、所述第三时钟信号、所述第五时钟信号以及所述第七时钟信号；
    所述多个级联设置的偶数级栅极驱动单元接入所述第二时钟信号、所述第四时钟信号、所述第六时钟信号以及所述第八时钟信号。
  11. 根据权利要求10所述的栅极驱动电路，其中，每一级所述栅极驱动单元还电性连接于第二时钟信号端、第三时钟信号端以及第四时钟信号端；
    在所述多级级联设置的奇数级栅极驱动单元中，第1+8k级栅极驱动单元的第一时钟信号端接入所述第三时钟信号，所述第1+8k级栅极驱动单元的第二时钟信号端接入所述第五时钟信号，所述第1+8k级栅极驱动单元的第三时钟信号端接入所述第一时钟信号，所述第1+8k级栅极驱动单元的第四时钟信号端接入所述第七时钟信号；
    第3+8k级栅极驱动单元的第一时钟信号端接入所述第五时钟信号，所述第3+8k级栅极驱动单元的第二时钟信号端接入所述第七时钟信号，所述第3+8k级栅极驱动单元的第三时钟信号端接入所述第三时钟信号，所述第3+8k级栅极驱动单元的第四时钟信号端接入所述第一时钟信号；
    第5+8k级栅极驱动单元的第一时钟信号端接入所述第七时钟信号，所述第5+8k级栅极驱动单元的第二时钟信号端接入所述第一时钟信号，所述第5+8k级栅极驱动单元的第三时钟信号端接入所述第五时钟信号，所述第5+8k级栅极驱动单元的第四时钟信号端接入所述第三时钟信号；
    第7+8k级栅极驱动单元的第一时钟信号端接入所述第一时钟信号，所述第7+8k级栅极驱动单元的第二时钟信号端接入所述第三时钟信号，所述第7+8k级栅极驱动单元的第三时钟信号端接入所述第七时钟信号，所述第7+8k级栅极驱动单元的第四时钟信号端接入所述第五时钟信号；
    在所述多级级联设置的偶数级栅极驱动单元中，第2+8k级栅极驱动单元的第一时钟信号端接入所述第四时钟信号，所述第2+8k级栅极驱动单元的第二时钟信号端接入所述第六时钟信号，所述第2+8k级栅极驱动单元的第三时钟信号端接入所述第二时钟信号，所述第2+8k级栅极驱动单元的第四时钟信号端接入所述第八时钟信号；
    第4+8k级栅极驱动单元的第一时钟信号端接入所述第六时钟信号，所述第4+8k级栅极驱动单元的第二时钟信号端接入所述第八时钟信号，所述第4+8k级栅极驱动单元的第三时钟信号端接入所述第四时钟信号，所述第4+8k级栅极驱动单元的第四时钟信号端接入所述第二时钟信号；
    第6+8k级栅极驱动单元的第一时钟信号端接入所述第八时钟信号，所述第6+8k级栅极驱动单元的第二时钟信号端接入所述第二时钟信号，所述第6+8k级栅极驱动单元的第三时钟信号端接入所述第六时钟信号，所述第6+8k级栅极驱动单元的第四时钟信号端接入所述第四时钟信号；
    第8+8k级栅极驱动单元的第一时钟信号端接入所述第二时钟信号，所述第8+8k级栅极驱动单元的第二时钟信号端接入所述第四时钟信号，所述第8+8k级栅极驱动单元的第三时钟信号端接入所述第八时钟信号，所述第8+8k级栅极驱动单元的第四时钟信号端接入所述第六时钟信号；其中，k为大于或等于零的整数。
  12. 根据权利要求1所述的栅极驱动电路，其中，所述栅极驱动电路接入第一时钟信号、第二时钟信号、第三时钟信号以及第四时钟信号。
  13. 根据权利要求12所述的栅极驱动电路，其中，每一级所述栅极驱动单元还电性连接于第二时钟信号端、第三时钟信号端以及第四时钟信号端；
    第1+4k级栅极驱动单元的第一时钟信号端接入所述第二时钟信号，所述第1+4k级栅极驱动单元的第二时钟信号端接入所述第三时钟信号，所述第1+4k级栅极驱动单元的第三时钟信号端接入所述第一时钟信号，所述第1+4k级栅极驱动单元的第四时钟信号端接入所述第四时钟信号；
    第2+4k级栅极驱动单元的第一时钟信号端接入所述第三时钟信号，所述第2+4k级栅极驱动单元的第二时钟信号端接入所述第四时钟信号，所述第2+4k级栅极驱动单元的第三时钟信号端接入所述第二时钟信号，所述第2+4k级栅极驱动单元的第四时钟信号端接入所述第一时钟信号；
    第3+4k级栅极驱动单元的第一时钟信号端接入所述第四时钟信号，所述第3+4k级栅极驱动单元的第二时钟信号端接入所述第一时钟信号，所述第3+4k级栅极驱动单元的第三时钟信号端接入所述第三时钟信号，所述第3+4k级栅极驱动单元的第四时钟信号端接入所述第二时钟信号；
    第4+4k级栅极驱动单元的第一时钟信号端接入所述第一时钟信号，所述第4+4k级栅极驱动单元的第二时钟信号端接入所述第二时钟信号，所述第4+4k级栅极驱动单元的第三时钟信号端接入所述第四时钟信号，所述第4+4k级栅极驱动单元的第四时钟信号端接入所述第三时钟信号；其中，k为大于或等于零的整数。
  14. 根据权利要求1所述的栅极驱动电路，其中，所述栅极驱动电路的驱动时序包括：
    充电阶段，对所述第一节点进行充电；
    输出阶段，所述本级扫描信号输出端输出本级扫描信号；
    下拉阶段，将所述第一节点的电位以及所述本级扫描信号输出端的电位下拉；
    维持阶段，维持所述第一节点的电位以及所述本级扫描信号输出端的电位，并间歇性拉低所述第二节点的电位。
  15. 根据权利要求14所述的栅极驱动电路，其中，所述维持阶段包括第一维持阶段和第二维持阶段，所述栅极驱动电路还连接于第四时钟信号端；
    在所述第一维持阶段，所述第四时钟信号端接入高电平信号，用于将所述第二节点的电位上拉；
    在所述第二维持阶段，所述第一时钟信号端接入高电平信号，用于将所述第二节点的电位下拉，以间歇性拉低所述第二节点的电位。
  16. 一种栅极驱动电路，其中，包括多级级联设置的栅极驱动单元，其中，每一级所述栅极驱动单元均包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管以及第八晶体管；
    所述第一晶体管的栅极电性连接于第二时钟信号端，所述第一晶体管的源极或漏极中的一个电性连接于上一级扫描信号输出端，所述第一晶体管的源极或漏极中的另一个电性连接于第一节点；
    所述第二晶体管的栅极电性连接于所述第一节点，所述第二晶体管的源极或漏极中的一个电性连接于第三时钟信号端，所述第二晶体管的源极或漏极中的另一个电性连接于本级扫描信号输出端；
    所述第三晶体管的栅极电性连接于所述第二时钟信号端，所述第三晶体管的源极或漏极中的一个接入恒压低电平信号，所述第三晶体管的源极或漏极中的另一个电性连接于所述本级扫描信号输出端；
    所述第四晶体管的栅极电性连接于所述第一时钟信号端，所述第四晶体管的源极或漏极中的一个接入所述恒压低电平信号，所述第四晶体管的源极或漏极中的另一个电性连接于第二节点；
    所述第五晶体管的栅极电性连接于所述第二节点，所述第五晶体管的源极或漏极中的一个接入所述恒压低电平信号，所述第五晶体管的源极或漏极中的另一个电性连接于所述第一节点；
    所述第六晶体管的栅极电性连接于所述第一节点，所述第六晶体管的源极或漏极中的一个接入所述恒压低电平信号，所述第六晶体管的源极或漏极中的另一个电性连接于所述第二节点；
    所述第七晶体管的栅极和源极或漏极中的一个均电性连接于第四时钟信号端，所述第七晶体管的源极或漏极中的另一个电性连接于所述第二节点；
    所述第八晶体管的栅极电性连接于所述第二节点，所述第八晶体管的源极或漏极中的一个接入所述恒压低电平信号，所述第八晶体管的源极或漏极中的另一个电性连接于所述本级扫描信号输出端。
  17. 根据权利要求16所述的栅极驱动电路，其中，所述栅极驱动电路还包括第九晶体管和第十晶体管；
    所述第九晶体管的栅极接入复位信号，所述第九晶体管的源极或漏极中的一个接入所述恒压低电平信号，所述第九晶体管的源极或漏极中的另一个电性连接于所述第二节点；
    所述第十晶体管的栅极接入所述复位信号，所述第十晶体管的源极或漏极中的一个接入所述恒压低电平信号，所述第十晶体管的源极或漏极中的另一个电性连接于所述第一节点。
  18. 根据权利要求16所述的栅极驱动电路，其中，所述栅极驱动电路的驱动时序包括：
    充电阶段，对所述第一节点进行充电；
    输出阶段，所述本级扫描信号输出端输出本级扫描信号；
    下拉阶段，将所述第一节点的电位以及所述本级扫描信号输出端的电位下拉；
    维持阶段，维持所述第一节点的电位以及所述本级扫描信号输出端的电位，并间歇性拉低所述第二节点的电位。
  19. 根据权利要求18所述的栅极驱动电路，其中，所述维持阶段包括第一维持阶段和第二维持阶段，所述栅极驱动电路还连接于第四时钟信号端；
    在所述第一维持阶段，所述第四时钟信号端接入高电平信号，用于将所述第二节点的电位上拉；
    在所述第二维持阶段，所述第一时钟信号端接入高电平信号，用于将所述第二节点的电位下拉，以间歇性拉低所述第二节点的电位。
  20. 一种显示面板，其中，包括权利要求1所述的栅极驱动电路。
PCT/CN2021/097130 2021-05-18 2021-05-31 一种栅极驱动电路及显示面板 WO2022241821A1 (zh)

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