WO2021213122A1 - 像素电路及其驱动方法、显示装置 - Google Patents

像素电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2021213122A1
WO2021213122A1 PCT/CN2021/082569 CN2021082569W WO2021213122A1 WO 2021213122 A1 WO2021213122 A1 WO 2021213122A1 CN 2021082569 W CN2021082569 W CN 2021082569W WO 2021213122 A1 WO2021213122 A1 WO 2021213122A1
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Prior art keywords
reset
module
terminal
light
electrically connected
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PCT/CN2021/082569
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English (en)
French (fr)
Inventor
赵东方
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昆山国显光电有限公司
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Publication of WO2021213122A1 publication Critical patent/WO2021213122A1/zh
Priority to US17/717,427 priority Critical patent/US11735114B2/en

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G2300/0421—Structural details of the set of electrodes
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    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
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    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
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    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the embodiments of the present application relate to the field of display technology, for example, to a pixel circuit and a driving method thereof, and a display device.
  • a conventional display panel usually includes a plurality of pixel circuits and light-emitting devices, and the light-emitting devices are driven to emit light through the pixel circuits to perform display.
  • the present application provides a pixel circuit, a driving method thereof, and a display device, so as to improve the short-term image retention phenomenon and improve the display effect.
  • an embodiment of the present invention provides a pixel circuit.
  • the pixel circuit includes a data writing module, a second reset module, a first reset module, a driving transistor, and a light emitting module; wherein the data writing module is set in the first In the reset phase, the constant first voltage signal input from the data signal terminal is written to the first pole of the drive transistor; the first reset module is set to write the reset voltage signal input from the reset signal terminal to the drive transistor during the first reset phase Gate; the data writing module is set to write the data voltage signal input from the data signal terminal to the gate of the driving transistor during the data writing stage.
  • an embodiment of the present invention also provides a pixel circuit driving method for driving the pixel circuit provided in the first aspect.
  • the driving method of the pixel circuit includes: in the first reset stage, providing a constant signal to the data signal terminal The first voltage signal controls the data writing module to be turned on.
  • the data writing module writes the constant first voltage signal input from the data signal terminal to the first pole of the drive transistor; controls the first reset module to turn on to turn on the reset signal
  • the reset voltage signal input from the terminal is written to the gate of the drive transistor; in the data writing stage, a data voltage signal is provided to the data signal terminal, the data writing module is controlled to be turned on, and the data voltage signal input from the data signal terminal is written to Drive the gate of the transistor.
  • an embodiment of the present invention also provides a display device, including the pixel circuit provided in the first aspect; and further including a driving chip and a plurality of data lines, each data line is connected to at least one column of pixel circuits, and the driving chip is set in In the first reset phase, a constant first voltage signal is output to the multiple data lines, and it is set to output data voltage signals to the multiple data lines during the data writing phase.
  • a constant first voltage signal and a data voltage signal are provided to the data signal terminal in the first reset stage and the data writing stage, respectively.
  • the data writing module writes a constant first voltage signal to the first pole of the drive transistor; and in the first reset stage, the reset voltage signal input from the reset signal terminal is written to the drive transistor through the first reset module.
  • the driving transistor will return to The same initial state, in turn, makes the active layer, gate insulating layer, and the active layer and gate insulating layer interface of the driving transistor within the driving transistor capture and release the same degree of carrier capture and release during the gray-scale switching process, so that When switching from different gray levels to the same gray level, the driving transistors can generate the same driving current, and the light-emitting brightness of the light-emitting module is basically the same, thereby reducing the afterimage phenomenon and improving the display effect.
  • FIG. 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG. 4 is a driving timing diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 5 is a driving timing diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG. 7 is a driving timing diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG. 9 is a driving timing diagram of another pixel circuit provided by an embodiment of the present application.
  • FIG. 10 is a flowchart of a method for driving a pixel circuit according to an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • conventional display panels have short-term image retention problems. For example, when light-emitting devices that originally displayed different gray levels in the display panel switch to the same gray level, the brightness of the light is different, which makes the display effect poor.
  • the reason for the above problems is that conventional display panels usually include multiple pixel circuits.
  • the pixel circuits include driving transistors that drive the light-emitting devices to emit light.
  • the driving transistors control the light-emitting brightness of the light-emitting devices by controlling the driving current flowing through the light-emitting devices. .
  • the driving current generated by the driving transistor is related to the gate-source voltage difference of the driving transistor. In different display gray scales, the gate-source voltage difference of the driving transistor is different.
  • the difference in the gate-source voltage difference of the driving transistor causes the working state of the driving transistor to be different, which in turn causes the trapping of carriers at the active layer, the gate insulating layer, and the interface between the active layer and the gate insulating layer inside the driving transistor.
  • the source of the driving transistor is usually in a floating state, so that the change of the gate potential will also cause the change of the source potential, making the reset of the driving transistor insufficient, and short-term The afterimage phenomenon still exists.
  • a pixel circuit which includes a data writing module, a first reset module, a driving transistor, and a light emitting module; wherein the data writing module is configured to perform data writing in the first reset stage.
  • the constant first voltage signal input from the signal terminal is written to the first pole of the drive transistor;
  • the first reset module is configured to write the reset voltage signal input from the reset signal terminal to the gate of the drive transistor during the first reset stage;
  • data The writing module is configured to write the data voltage signal input from the data signal terminal to the gate of the driving transistor during the data writing stage.
  • the first reset stage may be performed before the data writing stage.
  • the data writing module writes the constant first voltage signal input from the data signal terminal to the first pole of the drive transistor
  • the first reset module writes the reset voltage signal input from the reset signal terminal to the
  • the gate of the driving transistor is reset so that in the first reset stage, the gate and the first pole of the driving transistor are reset, so that the gate-source voltage difference of the driving transistors in multiple pixel circuits after the first reset stage can be equalized, that is,
  • the initial states of the driving transistors in the multiple pixel circuits are completely the same, and the driving transistors can be completely reset. Therefore, in a display panel including multiple pixel circuits, the driving transistors in the multiple pixel circuits can all be reset in the first reset stage.
  • the driving transistors will be restored to the same initial state, thereby making the gray level
  • the active layer, the gate insulating layer, and the carriers at the interface between the active layer and the gate insulating layer of the driving transistor tend to be captured and released to the same degree, making the switch from different gray scales to the same gray scale
  • the driving transistor can generate the same driving current, the light-emitting brightness of the light-emitting module is basically the same, thereby reducing the afterimage phenomenon.
  • the pixel circuit provided by the embodiment of the present application realizes the resetting of the first pole of the driving transistor by inputting a signal at the data signal terminal, thereby eliminating the need to separately provide a module for resetting the first pole of the driving transistor, thereby facilitating the simplification of the structure of the pixel circuit.
  • the area of the pixel circuit is reduced and the pixel density is increased.
  • the pixel circuit provided in the embodiment of the present application provides a constant first voltage signal and a data voltage signal to the data signal terminal in the first reset phase and the data write phase, respectively.
  • the data write module will A constant first voltage signal is written to the first pole of the drive transistor; and in the first reset phase, the reset voltage signal input from the reset signal terminal is written to the gate of the drive transistor through the first reset module;
  • the first voltage signal input from the data signal terminal is used as the reset signal for the first pole of the drive transistor, and the reset voltage signal input from the reset signal terminal is used as the reset signal for the gate of the drive transistor.
  • the driving transistor will be restored to the same initial state, thus making the gray scale switching process
  • the capture and release of carriers at the active layer, gate insulating layer, and the interface between the active layer and the gate insulating layer of the middle drive transistor tend to be the same, so that when switching from different gray levels to the same gray level,
  • the driving transistors can generate the same driving current, and the light-emitting brightness of the light-emitting module is basically the same, thereby reducing the afterimage phenomenon and improving the display effect.
  • the pixel circuit further includes a second reset module, and the second reset module is configured to write the reset voltage signal input from the reset signal terminal to the second pole of the driving transistor in the first reset stage.
  • the second reset module writes the reset signal input from the reset signal terminal to the second pole of the drive transistor, so that the second pole of the drive transistor can also be reset, that is, in the first reset stage, the drive transistor
  • the first pole, the second pole and the gate can all be reset.
  • the first pole drives the gate of the transistor and the second pole drives the drain of the transistor.
  • the absolute value of the difference between the reset voltage signal input from the reset signal terminal and the first voltage signal input from the drive data signal terminal is greater than the absolute value of the difference between the threshold voltage of the drive transistor, thereby ensuring that during the first reset stage ,
  • the driving transistor can be turned on, so that a current path is formed between the data signal terminal and the reset signal terminal to realize the on-state current type reset of the driving transistor.
  • FIG. 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present application.
  • the pixel circuit includes a data writing module 110, a first reset module 130, a driving transistor DT, and a light emitting module 140; a data writing module 110 It includes a writing transistor T1 and a compensation transistor T2.
  • the writing transistor T1 is configured to control the connection state between the data signal terminal Vdata and the first pole of the driving transistor DT according to the signal of the first scan signal terminal Scan1, and the gate of the writing transistor T1 is connected to
  • the first scan signal terminal Scan1 is electrically connected
  • the first electrode of the writing transistor T1 is electrically connected to the data signal terminal Vdata
  • the second electrode of the writing transistor T1 is electrically connected to the first electrode of the driving transistor DT
  • the compensation transistor T2 is set according to The signal of the first scan signal terminal Scan1 controls the connection state between the second electrode of the driving transistor DT and the gate of the driving transistor DT
  • the gate of the compensation transistor T2 is electrically connected to the first scan signal terminal Scan1
  • the first scan signal terminal Scan1 of the compensation transistor T2 is electrically connected.
  • One pole is electrically connected to the second pole of the driving transistor DT, the second pole of the compensation transistor T2 is electrically connected to the gate of the driving transistor DT; the control terminal of the first reset module 130 is electrically connected to the third scan signal terminal Scan3, the first The first terminal of the reset module 130 is electrically connected to the reset signal terminal Vref, and the second terminal of the first reset module 130 is electrically connected to the gate of the driving transistor DT.
  • FIG. 2 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • the pixel circuit further includes a second reset module 120.
  • the control terminal of 120 is electrically connected to the second scan signal terminal Scan2
  • the first terminal of the second reset module 120 is electrically connected to the reset signal terminal Vref
  • the second terminal of the second reset module 120 is electrically connected to the second terminal of the driving transistor DT .
  • the pixel circuit further includes a first light-emission control module 150, a second light-emission control module 160, and a storage module.
  • the first light-emission control module 150 is configured to control the first light-emission control signal terminal EM1 according to the signal from the first light-emission control signal terminal EM1.
  • the second terminal of the light-emitting module 140 is electrically connected to the second power supply voltage terminal Vss; the first light-emitting control module 150 is also set to be at the first light-emitting control signal terminal EM1 during the first reset stage and the data writing stage.
  • the second light-emitting control module 160 is also set to be turned off under the control of the second light-emitting control signal terminal EM2 during the first reset stage and the data writing stage; the memory module is set to store the gate of the drive transistor DT ⁇ Voltage.
  • the control terminal of the first light emission control module 150 is electrically connected to the first light emission control signal terminal EM1, and the first terminal of the first light emission control module 150 is electrically connected to the first power supply voltage terminal Vdd ,
  • the second end of the first light emission control module 150 is electrically connected to the first electrode of the driving transistor DT;
  • the control end of the second light emission control module 160 is electrically connected to the second light emission control signal terminal EM2, and the second end of the second light emission control module 160 is electrically connected to the second light emission control signal terminal EM2.
  • One end is electrically connected to the second electrode of the driving transistor DT, the second end of the second light emitting control module 160 is electrically connected to the first end of the light emitting module 140, and the second end of the light emitting module 140 is electrically connected to the second power supply voltage terminal Vss .
  • the pixel circuit may correspond to the exemplary circuit of the pixel circuit shown in FIG. 2.
  • the second reset module 120 may include a first reset transistor T3.
  • the module 130 may include a second reset transistor T4, the first light emitting control module 150 may include a first light emitting control transistor T5, the second light emitting control module 160 may include a second light emitting control transistor T6, and the light emitting module 140 may include an organic light emitting device D1,
  • the storage module includes a storage capacitor Cst, one end of the storage capacitor Cst is electrically connected to the first power supply voltage terminal Vdd, and the other end is electrically connected to the gate of the driving transistor DT.
  • FIG. 4 is a driving timing diagram of a pixel circuit provided by an embodiment of the present application.
  • the driving timing can be applied to the pixel circuit shown in FIG. 2 and FIG. 3, and the operation of the pixel circuit shown in FIG. 3 is taken as an example for illustration .
  • the multiple transistors included in the pixel circuit provided in this embodiment may be P-type transistors or N-type transistors.
  • the transistors included in the pixel circuit are all P-type transistors (for P The conduction control signal of the type transistor is a low-level signal) as an example for description.
  • the working process of the pixel circuit includes a first reset phase t00, a second reset phase t01, a data writing phase t02, and a light emitting phase t03.
  • the first scan signal terminal Scan1 inputs a low-level signal
  • the write transistor T1 and the compensation transistor T2 are turned on;
  • the data signal terminal Vdata inputs a constant first voltage signal, and the first voltage signal passes through the conduction
  • the write transistor T1 that is turned on writes to the first pole of the drive transistor DT;
  • the second scan signal terminal Scan2 inputs a low-level signal, and the second reset module 120 (the first reset transistor T3) is turned on ,
  • the reset voltage signal input from the reset signal terminal Vref is written to the second pole of the driving transistor DT through the turned-on first reset transistor T3;
  • the third scan signal terminal Scan3 inputs a low level, the first The reset module 130 (the second reset transistor T4) is turned on, and the reset voltage signal input from the reset signal terminal Vref is written to the gate of the driving transistor DT through the turned-on second reset transistor T4, and then the first reset stage t00 is realized
  • the second reset stage t01 the second scan signal terminal Scan2 inputs a low-level signal, the second reset module 120 (the first reset transistor T3) is turned on, and the reset voltage signal input from the reset signal terminal Vref passes through the first reset that is turned on
  • the transistor T3 is written into the second pole of the driving transistor DT; in the second reset phase t01, the third scan signal terminal Scan3 inputs a low level, the first reset module 130 (the second reset transistor T4) is turned on, and the reset signal terminal Vref is input
  • the reset voltage signal is written to the gate of the driving transistor DT through the turned-on second reset transistor T4.
  • the first reset stage t00 can already reset the gate of the driving transistor DT, so the second reset stage t01 can also be omitted.
  • the first scan signal terminal Scan1 inputs a low-level signal
  • the write transistor T1 and the compensation transistor T2 are turned on
  • the data signal terminal Vdata inputs a data voltage signal.
  • the data voltage signal is written through the conduction
  • the transistor T1, the driving transistor DT, and the compensation transistor T2 are written to the gate of the driving transistor DT to realize the compensation of the data voltage signal and the threshold voltage of the driving transistor DT.
  • the first reset stage t00, the second reset stage t01 and the data writing stage t02, the first light-emitting control signal terminal EM1 and the second light-emitting control signal terminal EM2 input high-level signals, and the first light-emitting control module 150 (fifth transistor T5) and the second light emission control module 160 (sixth transistor T6) are turned off.
  • the first light-emitting control signal terminal EM1 and the second light-emitting control signal terminal EM2 input low-level signals, and the first light-emitting control module 150 (the fifth transistor T5) and the second light-emitting control module 160 (the sixth transistor T6) ) Is turned on, and the driving transistor DT drives the light-emitting module 140 to emit light.
  • the input signals of the first light-emitting control signal terminal EM1 and the second light-emitting control signal terminal EM2 are the same, so the first light-emitting control signal terminal EM1 and the second light-emitting control signal terminal EM2 can be the same light-emitting control signal
  • the control terminals of the first lighting control module 150 and the second lighting control module 160 can be connected to the same port, that is, the control terminals of the first lighting control module 150 and the second lighting control module 160 can be connected to the same lighting control signal Therefore, the number of light-emitting control signal lines in the display panel including the pixel circuit of the present embodiment can be saved, thereby simplifying wiring.
  • the driving timing of the pixel circuit shown in FIG. 1 it is only necessary to delete the timing of the second scan signal input terminal Scan2 in the driving timing shown in FIG. 4, other timings remain unchanged, and the pixel circuit shown in FIG. 1 does not include the second reset Except for the module, the working process of other modules is the same as the working process of the pixel circuit shown in FIG. The transistor DT is restored to the same initial state in the first reset stage, thereby improving the afterimage.
  • FIG. 5 is a driving timing diagram of another pixel circuit provided by an embodiment of the application.
  • the driving timing can be used to drive the pixel circuit shown in FIG. 2 and FIG. 3.
  • the second reset module 120 is also set to be turned on under the control of the input signal from the second scan signal terminal Scan2 during the second reset stage t11
  • the second light-emitting control module 160 is also set to be turned on at the second light-emitting control signal terminal during the second reset stage t11
  • the EM2 input signal is turned on under the control, so that the reset voltage signal input from the reset signal terminal Vref is written to the first terminal of the light-emitting module 140 through the second reset module 120 and the second light-emitting control module 160; the first light-emitting control module 150 It is also set to turn off under the control of the input signal from the first light-emitting control signal terminal EM1 in the second reset stage.
  • the second reset stage t11 is between the first reset stage t10 and the data writing stage t12.
  • the working process of the pixel circuit includes a first reset stage t10, a second reset stage t11, a data writing stage t12, and a light emitting stage t13.
  • the working process of the pixel circuit in the first reset stage t10 is the same as the working process of the driving sequence shown in FIG. 4 in the first reset stage t00, and will not be repeated here.
  • the forced complete reset of the driving transistor DT is realized, which is beneficial to improve the short-term image sticking phenomenon.
  • the second scan signal terminal Scan2 inputs a low-level signal
  • the second reset module 120 (the first reset transistor T3) is turned on
  • the second light emission control signal terminal EM2 is input Low level signal
  • the reset voltage signal input from the reset signal terminal Vref is written to the first terminal of the light emitting module 140 (the anode of the organic light emitting device D1) through the turned-on first reset transistor T3 and the second light emitting control module 160, and then Avoid the influence of the residual charge at the first terminal of the light-emitting module 140 on the display effect
  • the third scan signal terminal Scan3 inputs a low level
  • the first reset module 130 (the second reset transistor T4) is turned on
  • the reset signal The reset voltage signal input from the terminal Vref is written to the gate of the driving transistor DT through the turned-on second reset transistor T4.
  • the first scan signal terminal Scan1 inputs a low-level signal
  • the write transistor T1 and the compensation transistor T2 are turned on
  • the data signal terminal Vdata inputs a data voltage signal, which is written through the conduction
  • the transistor T1, the driving transistor DT, and the compensation transistor T2 are written to the gate of the driving transistor DT to realize the compensation of the data voltage signal and the threshold voltage of the driving transistor DT.
  • the first light emission control signal terminal EM1 inputs a high level signal, and the first light emission control transistor T5 is turned off; in the light emission stage t13, the first light emission control The signal terminal EM1 inputs a low level signal, the first light emission control module 150 (first light emission control transistor T5) is turned on, the second light emission control signal terminal EM2 inputs a low level signal, and the second light emission control module 160 (second light emission control The transistor T6) is turned on, and the driving transistor DT drives the light-emitting module 140 to emit light.
  • the difference between the driving timing shown in FIG. 5 and the driving timing shown in FIG. 4 is that the timings of the first light-emitting control signal terminal EM1 and the second light-emitting control signal terminal EM2 are different. Accordingly, the first light-emitting control signal terminal EM1 and the second light-emitting control signal terminal EM2 of the pixel circuit are different.
  • the second lighting control signal terminal EM2 is a different lighting control signal terminal, that is, the control terminal of the first lighting control module 150 and the control terminal of the second lighting control module 160 are connected to different ports.
  • the first emission control module 150 and the second emission control module 160 are controlled by different emission control signals, which can be achieved through The second reset module 120 and the second light-emitting control module 160 reset the first end of the light-emitting module 140 to avoid the influence of residual charges on the first end of the light-emitting module 140 on the display effect.
  • the pixel circuit includes a data writing module 110, a second reset module 120, a first reset module 130, a driving transistor DT, and a light emitting module 140;
  • the data writing module 110 includes a writing transistor T1 and a compensation transistor T2.
  • the writing transistor T1 is configured to control the connection state between the data signal terminal Vdata and the first pole of the driving transistor DT according to the signal of the first scan signal terminal Scan1, and write
  • the gate of the input transistor T1 is electrically connected to the first scan signal terminal Scan1
  • the first electrode of the write transistor T1 is electrically connected to the data signal terminal Vdata
  • the second electrode of the write transistor T1 is electrically connected to the first electrode of the drive transistor DT
  • the compensation transistor T2 is set to control the connection state of the second electrode of the driving transistor DT and the gate of the driving transistor DT according to the signal of the first scan signal terminal Scan1
  • the gate of the compensation transistor T2 is electrically connected to the second scan signal terminal Scan2
  • the first pole of the compensation transistor T2 is electrically connected to the second pole of the driving transistor DT
  • the second pole of the compensation transistor T2 is electrically connected to the gate of the driving transistor DT
  • the control terminal of the second reset module 120 is electrically connected to the third scan signal
  • the pixel circuit further includes a first light emission control module 150, a second light emission control module 160, and a third reset module 170.
  • the first light emission control module 150 is configured to control the first power supply voltage terminal according to the signal from the light emission control signal terminal.
  • the second light emitting control module 160 is configured to control the connection state of the second pole of the driving transistor DT and the first end of the light emitting module 140 according to the signal from the light emitting control signal terminal, and the second end of the light emitting module 140 is electrically connected to the second power supply voltage terminal Vss .
  • the control terminal of the first light emission control module 150 is electrically connected to the light emission control signal terminal EM, the first terminal of the first light emission control module 150 is electrically connected to the first power supply voltage terminal Vdd, and the second terminal of the first light emission control module 150 is electrically connected to the driver
  • the first electrode of the transistor DT is electrically connected; the control end of the second light emission control module 160 is electrically connected to the light emission control signal terminal EM, the first end of the second light emission control module 160 is electrically connected to the second electrode of the driving transistor DT, and the second light emission control module 160 is electrically connected to the second electrode of the driving transistor DT.
  • the second end of the light-emitting control module 160 is electrically connected to the first end of the light-emitting module 140, and the second end of the light-emitting module 140 is electrically connected to the second power supply voltage terminal Vss;
  • the third reset module 170 is set according to the third scan signal terminal Scan3 The signal controls the connection state between the reset signal terminal Vref and the first terminal of the light-emitting module, the control terminal of the third reset module 170 is electrically connected with the third scan signal terminal Scan3, and the first terminal of the third reset module 170 is electrically connected with the reset signal terminal Vref ,
  • the second end of the third reset module 160 is electrically connected to the first end of the light-emitting module 140, and the second end of the light-emitting module 140 is electrically connected to the second power supply voltage terminal Vss;
  • the third reset module 170 is also set to reset in the first At this stage, it is turned on under the control of the input signal from the third scan signal terminal Scan3 to reset the
  • the light emission control module includes a first light emission control module 150 and a second light emission control module 160.
  • the control terminals of the first light emission control module 150 and the second light emission control module 160 are connected to the same light emission control signal terminal EM.
  • FIG. 7 is a driving timing diagram of another pixel circuit provided by an embodiment of the present application.
  • the driving timing can be applied to the pixel circuit shown in FIG.
  • the control module 150, the second light emission control module 160, and the third reset module 170 all include P-type transistors, and the transistors included in other modules in FIG. 6 are also P-type transistors as an example for illustration. 6 and 7, the working process of the pixel circuit shown in FIG. 6 includes a first reset stage t21, a data writing stage t22, and a light-emitting stage t23.
  • the first scan signal terminal Scan1 inputs a low-level signal
  • the write transistor T1 is turned on
  • the data signal terminal Vdata inputs a constant first voltage signal, which passes through the turned-on write transistor T1 is written to the first pole of the driving transistor DT
  • the third scan signal terminal Scan3 inputs a low level signal
  • the second reset module 120 is turned on
  • the reset voltage signal input from the reset signal terminal Vref passes through the The second reset module 120 that is turned on is written to the second pole of the driving transistor DT
  • the second scan signal terminal Scan2 inputs a low level
  • the compensation transistor T2 is turned on
  • the first reset module 130 formed by the transistor T2 is turned on, and the reset voltage signal input from the reset signal terminal Vref is written to the gate of the driving transistor DT through the turned-on first reset module 130, thereby realizing the correction in the first reset stage t21
  • the first reset module 130 formed by the transistor T2 is turned on, and the reset voltage
  • the third reset module 170 is turned on according to the low-level signal input from the third scan signal terminal Scan3, and the reset voltage signal input from the reset signal terminal Vref is transmitted to the light-emitting module through the turned-on third reset module 170
  • the first end of the light-emitting module 140 can be reset to the first end of the light-emitting module 140, thereby eliminating the residual charge on the first end of the light-emitting module 140, which is beneficial to improve the display effect.
  • the first scan signal terminal Scan1 and the second scan signal terminal Scan2 input low-level signals
  • the write transistor T1 and the compensation transistor T2 are turned on
  • the data signal terminal Vdata inputs a data voltage signal.
  • the signal is written to the gate of the driving transistor DT through the turned-on writing transistor T1, the driving transistor DT, and the compensation transistor T2, so that the data voltage signal and the threshold voltage of the driving transistor DT are compensated.
  • the light emission control signal terminal EM inputs a high level signal, and the first light emission control module 150 and the second light emission control module 160 are turned off; in the light emission stage t23, the light emission control signal terminal EM A low-level signal is input, the first light-emitting control module 150 and the second light-emitting control module 160 are turned on, and the driving transistor DT drives the light-emitting module 140 to emit light.
  • FIG. 8 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application.
  • the difference between this pixel circuit and the pixel circuit shown in FIG. 6 is that the control terminal of the first light emission control module 150 is connected to the first light emission control
  • the signal terminal EM1 and the control terminal of the second lighting control module 160 are connected to the second lighting control signal terminal EM2.
  • the first lighting control signal terminal EM1 and the second lighting control signal terminal EM2 are different lighting control signal terminals.
  • the pixel circuit shown in FIG. 8 does not include the third reset module.
  • the first light emission control module 150 is configured to control the connection state of the first power supply voltage terminal Vdd and the first pole of the driving transistor DT according to the signal of the first light emission control signal terminal EM1;
  • the second light emission control module 160 is configured to The signal of the second light emission control signal terminal EM2 controls the connection state between the second electrode of the driving transistor DT and the first terminal of the light emitting module 140.
  • the control terminal of the first light emission control module 150 is electrically connected to the first light emission control signal terminal EM1, the first terminal of the first light emission control module 150 is electrically connected to the first power supply voltage terminal Vdd, and the second terminal of the first light emission control module 150 Is electrically connected to the first electrode of the driving transistor DT; the control end of the second light emission control module 160 is electrically connected to the second light emission control signal terminal EM2, and the first end of the second light emission control module 160 is electrically connected to the second electrode of the drive transistor DT. Connected, the second end of the second light-emitting control module 160 is electrically connected to the first end of the light-emitting module 140, and the second end of the light-emitting module 140 is electrically connected to the second power voltage terminal Vss.
  • the second reset module 120 is also set to be turned on under the control of the input signal from the second scan signal terminal Scan2 in the second reset stage, and the second light-emitting control module 160 is also set to be turned on during the second reset stage during the second light-emitting control
  • the signal terminal EM2 is turned on under the control of the input signal, so that the reset voltage signal input from the reset signal terminal Vref is written to the first terminal of the light-emitting module 140 through the second reset module 120 and the second light-emitting control module 160;
  • the module 150 is also configured to be turned off under the control of the input signal from the first light emission control signal terminal EM1 in the second reset stage.
  • FIG. 9 is a driving timing diagram of another pixel circuit provided by an embodiment of the application.
  • the driving timing can be used to drive the pixel circuit shown in FIG. 8.
  • the working process of the pixel circuit includes the The working process includes a first reset stage t30, a second reset stage t31, a data writing stage t32, and a light-emitting stage t33.
  • the first scan signal terminal Scan1 inputs a low-level signal
  • the write transistor T1 is turned on
  • the data signal terminal Vdata inputs a constant first voltage signal, which passes through the turned-on write transistor T1 is written to the first pole of the driving transistor DT
  • the third scan signal terminal Scan3 inputs a low-level signal
  • the second reset module 120 first reset transistor T3
  • the reset signal terminal Vref The input reset voltage signal is written to the second pole of the driving transistor DT through the turned-on first reset transistor T3
  • the second scan signal terminal Scan2 inputs a low level
  • the compensation transistor T2 is turned on
  • the The first reset module 130 formed by the second reset module 120 and the compensation transistor T2 is turned on, and the reset voltage signal input from the reset signal terminal Vref is written to the gate of the driving transistor DT through the turned-on first reset module 130, and then the first reset module 130 is turned on.
  • the third scan signal terminal Scan3 inputs a low level signal
  • the second reset module 120 (the first reset transistor T3) is turned on
  • the second light emission control signal terminal EM2 is input low level
  • the second light emission control The module 160 is turned on, and the reset voltage signal input from the reset signal terminal Vref is written to the first terminal of the light-emitting module 140 through the turned-on first reset transistor T3 and the second light-emitting control module 160. That is, the pixel circuit of this embodiment can realize the resetting of the first end of the light-emitting module 140 through the second reset module 120 and the second light-emitting control module 160 under the driving timing shown in FIG.
  • the third reset module reduces the number of modules included in the pixel circuit, and the third reset module usually includes thin film transistors, so the number of thin film transistors in the pixel circuit can be reduced, which is beneficial to reduce the area of the pixel circuit and increase the pixel density.
  • the first scan signal terminal Scan1 and the second scan signal terminal Scan2 input low-level signals
  • the write transistor T1 and the compensation transistor T2 are turned on
  • the data signal terminal Vdata inputs a data voltage signal.
  • the signal is written to the gate of the driving transistor DT through the turned-on writing transistor T1, the driving transistor DT, and the compensation transistor T2, so that the data voltage signal and the threshold voltage of the driving transistor DT are compensated.
  • the first light emission control signal terminal EM1 inputs a high level signal, and the first light emission control module 150 is turned off; in the light emission stage t33, the first light emission control The signal terminal EM1 inputs a low level signal, the first light emitting control module 150 is turned on, the second light emitting control signal terminal EM2 inputs a low level signal, the second light emitting control module 160 is turned on, and the driving transistor DT drives the light emitting module 140 to emit light.
  • the pixel circuit provided in this embodiment can realize complete reset of the driving transistor and reset of the first end of the light-emitting module by using a small number of thin film transistors. While improving the afterimage phenomenon, the area of the pixel circuit can be reduced. In turn, it is beneficial to increase the pixel density.
  • any two scan signal terminals of the first scan signal terminal, the second scan signal terminal, and the third scan signal terminal in the pixel circuit have the same timing in a frame (
  • the two scan signal terminals can be connected to the same scan line in the display panel, thereby reducing the number of wiring.
  • the reset voltage signal input from the reset signal terminal is always constant, so it is no longer shown in the timing diagram.
  • FIG. 10 is a flowchart of a method for driving a pixel circuit provided by an embodiment of the present application.
  • the driving method of the pixel circuit includes:
  • Step 210 In the first reset stage, provide a constant first voltage signal to the data signal terminal, and control the data writing module to turn on, so that the data writing module writes the constant first voltage signal input from the data signal terminal to the
  • the first pole of the driving transistor is controlled to turn on the first reset module, and the reset voltage signal input from the reset signal terminal is written to the gate of the driving transistor.
  • Step 220 In the data writing stage, a data voltage signal is provided to the data signal terminal, the data writing module is controlled to be turned on, and the data voltage signal input from the data signal terminal is written to the gate of the driving transistor.
  • a constant first voltage signal and a data voltage signal are respectively provided to the data signal terminal in the first reset stage and the data write stage.
  • the data write The input module writes a constant first voltage signal to the first pole of the drive transistor; and in the first reset phase, the reset voltage signal input from the reset signal terminal is written to the gate of the drive transistor through the first reset module; that is, In the first reset stage, the first voltage signal input from the data signal terminal is used as the reset signal for the first pole of the driving transistor, and the reset voltage signal input from the reset signal terminal is used as the reset signal for the gate of the driving transistor.
  • the data writing module and the first reset module of the pixel circuit are turned on, so that the first voltage signal can be transmitted to the first pole of the driving transistor, and the reset voltage signal can be transmitted to the gate of the driving transistor, thereby realizing the driving transistor in the first pole.
  • a complete reset in the reset stage when switching the gray scales in different frames, regardless of whether the gray scales displayed in the previous frame are the same, in the first reset stage of this frame, the driving transistors will be restored to the same initial state, thus making the gray scale
  • the levels of trapping and releasing of carriers in the active layer, the gate insulating layer, and the interface between the active layer and the gate insulating layer of the driving transistor tend to be the same, making the transition from different gray levels to the same gray level
  • the driving transistors can generate the same driving current, so that the light-emitting brightness of the light-emitting module is basically the same, thereby reducing the afterimage phenomenon.
  • the driving method of the pixel circuit further includes: in the first reset stage, controlling the second reset module to be turned on, and writing the reset voltage signal input from the reset signal terminal to the first reset stage of the driving transistor. Two poles.
  • the pixel circuit includes a data writing module 110, a second reset module 120, a first reset module 130, a driving transistor DT, and a light emitting module 140; optionally, the data
  • the writing module 110 includes a writing transistor T1 and a compensation transistor T2.
  • the gate of the writing transistor T1 is electrically connected to the first scan signal terminal Scan1, the first electrode of the writing transistor T1 is electrically connected to the data signal terminal Vdata, and the writing transistor
  • the second electrode of T1 is electrically connected to the first electrode of the driving transistor DT;
  • the gate of the compensation transistor T2 is electrically connected to the first scan signal terminal Scan1, and the first electrode of the compensation transistor T2 is electrically connected to the second electrode of the driving transistor DT,
  • the second terminal of the compensation transistor T2 is electrically connected to the gate of the driving transistor DT;
  • the control terminal of the second reset module 120 is electrically connected to the second scan signal terminal Scan2, and the first terminal of the second reset module 120 is electrically connected to the reset signal terminal Vref.
  • the second terminal of the second reset module 120 is electrically connected with the second terminal of the driving transistor DT;
  • the control terminal of the first reset module 130 is electrically connected with the third scan signal terminal Scan3, and the first terminal of the first reset module 130 is electrically connected with
  • the reset signal terminal Vref is electrically connected, and the second terminal of the first reset module 130 is electrically connected to the gate of the driving transistor DT.
  • a constant first voltage signal is provided to the data signal terminal, the data writing module is controlled to be turned on, and the data writing module writes the constant first voltage signal input from the data signal terminal to the first drive transistor.
  • a conduction control signal is provided to the first scan signal terminal, the second scan signal terminal and the third scan signal terminal, and the write transistor and the compensation transistor of the data writing module respond to the conduction of the first scan signal input terminal
  • the control signal is turned on, and the constant first voltage signal input from the data signal terminal is written to the first pole of the driving transistor through the write transistor;
  • the second reset module turns on in response to the conduction control signal input from the second scan signal terminal, and resets
  • the reset voltage signal input from the signal terminal is written to the second pole of the driving transistor through the second reset module;
  • the first reset module is turned on in response to the conduction control signal input from the third scan signal terminal, and the reset voltage signal input from the reset signal terminal passes
  • the first reset module writes to the gate of the driving transistor.
  • the data voltage signal is provided to the data signal terminal, the data writing module is controlled to be turned on, and the data voltage signal input from the data signal terminal is written to the gate of the driving transistor, including:
  • the data signal is provided to the data signal terminal, the conduction control signal is input to the first scan signal terminal, the write transistor and the compensation transistor are turned on in response to the conduction control signal of the first scan signal terminal, and the data signal terminal is input.
  • the data voltage signal is written to the gate of the driving transistor through the writing transistor, the driving transistor, and the compensation transistor.
  • Control the on or off of the data writing module, the second reset module and the first reset module in the pixel circuit by controlling the signals input to the first scan signal input terminal, the second scan signal input terminal and the third scan signal terminal In the first reset stage, the drive transistor is completely reset and the data voltage signal is written in the data writing stage.
  • the pixel circuit includes a data writing module 110, a second reset module 120, a first reset module 130, a driving transistor DT, and a light emitting module 140; optionally, the data writing module 110 includes a writing transistor T1 and compensation In the transistor T2, the gate of the writing transistor T1 is electrically connected to the first scan signal terminal Scan1, the first electrode of the writing transistor T1 is electrically connected to the data signal terminal Vdata, and the second electrode of the writing transistor T1 is electrically connected to the first scan signal terminal Scan1 of the driving transistor DT.
  • One pole is electrically connected; the gate of the compensation transistor T2 is electrically connected to the second scan signal terminal Scan2, the first pole of the compensation transistor T2 is electrically connected to the second pole of the driving transistor DT, and the second electrode of the compensation transistor T2 is electrically connected to the driving transistor DT
  • the control terminal of the second reset module 120 is electrically connected to the third scan signal terminal Scan3, the first terminal of the second reset module 120 is electrically connected to the reset signal terminal Vref, and the second terminal of the second reset module 120 is electrically connected It is electrically connected to the second pole of the driving transistor DT; the second reset module 120 and the compensation transistor T2 constitute the first reset module 130.
  • a constant first voltage signal is provided to the data signal terminal, the data writing module is controlled to be turned on, and the data writing module writes the constant first voltage signal input from the data signal terminal to the first drive transistor.
  • a turn-on control signal is provided to the first scan signal terminal, the second scan signal terminal, and the third scan signal terminal.
  • the write transistor is turned on in response to the turn-on control signal input from the first scan signal terminal, and the compensation transistor
  • the constant first voltage signal input from the data signal terminal is written to the first pole of the driving transistor through the write transistor
  • the second reset module responds to the third scan signal
  • the conduction control signal input from the terminal is turned on, the reset voltage signal input from the reset signal terminal is written to the second pole of the driving transistor through the second reset module; the reset voltage signal input from the reset signal terminal is written through the second reset module and the compensation transistor Into the gate of the drive transistor.
  • the data voltage signal is provided to the data signal terminal, the data writing module is controlled to be turned on, and the data voltage signal input from the data signal terminal is written to the gate of the driving transistor, including:
  • the data signal is provided to the data signal terminal, the conduction control signal is input to the first scan signal terminal, the write transistor and the compensation transistor are turned on in response to the conduction control signal of the first scan signal terminal, and the data signal terminal is input.
  • the data voltage signal is written to the gate of the driving transistor through the writing transistor, the driving transistor, and the compensation transistor.
  • Control the on or off of the data writing module, the second reset module and the first reset module in the pixel circuit by controlling the signals input to the first scan signal input terminal, the second scan signal input terminal and the third scan signal terminal In the first reset stage, the drive transistor is completely reset and the data voltage signal is written in the data writing stage.
  • the pixel circuit provided in this embodiment further includes a first light-emitting control module and a second light-emitting control module.
  • the control terminal of the first light-emitting control module is electrically connected to the first light-emitting control signal terminal, and the first terminal of the first light-emitting control module is electrically connected to the first light-emitting control signal terminal.
  • the first power supply voltage terminal is electrically connected, the second terminal of the first light-emitting control module is electrically connected with the first electrode of the driving transistor; the control terminal of the second light-emitting control module is electrically connected with the second light-emitting control signal terminal, and the second light-emitting control module
  • the first terminal of the light-emitting module is electrically connected with the second terminal of the driving transistor, the second terminal of the second light-emitting control module is electrically connected with the first terminal of the light-emitting module, and the second terminal of the light-emitting module is electrically connected with the second power supply voltage terminal;
  • the driving method further includes: in the first reset stage and the data writing stage, providing a turn-off control signal to the first light-emitting control signal terminal and the second light-emitting control signal terminal, so that the first light-emitting control module and the second light-emitting control module are in The first reset phase and the data write phase are turned off.
  • FIG. 11 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • the display device 11 includes the pixel circuit 100 provided by any of the foregoing embodiments of the present application; It also includes a driving chip 200 and multiple data lines (DL1, DL2, DL3, DL4...), each data line is connected to at least one column of pixels 100, and the driving chip 200 is set to output a constant output to the multiple data lines in the first reset stage And in the data writing stage, output data voltage signals to a plurality of data lines.
  • each data line is connected to a column of pixel circuits, and the data line is electrically connected to the data signal terminal of the pixel circuit.
  • the pixel circuit further includes a gate driving circuit 300, a plurality of scan lines (S1, S2, S3...), and a plurality of reset signal lines (Vr1, Vr2, Vr3, Vr4...) As well as the reference voltage source 400, a plurality of scan lines are electrically connected to the output terminals of the gate driving circuit.
  • a plurality of scan lines are electrically connected to the output terminals of the gate driving circuit.
  • each row of pixel circuits can be connected to three scan lines (for example, referred to as the first Scan line, second scan line and third scan line), the first scan line is connected to the first scan signal terminal of the pixel circuit, the second scan line is connected to the second scan signal terminal of the pixel circuit, and the third scan line is connected to the pixel circuit The third scan signal terminal.
  • the reference voltage line is electrically connected to the reference voltage source 400.
  • the reference voltage source 400 may be provided separately from the driving chip 200, and the reference voltage source 400 may also be integrated inside the driving chip 200, which is not limited in this embodiment.
  • Each reference voltage line can be connected to the reset signal terminal of a column of pixel circuits.
  • the display device provided by this embodiment includes the pixel circuit provided by any of the embodiments of the present application.
  • the drive chip outputs a constant first voltage signal to the data line in the first reset stage, and outputs to the data line in the data writing stage.
  • the data voltage signal realizes that the reset signal of the first electrode of the driving transistor is provided to the pixel circuit through the data signal terminal, and then the second reset module and the first reset module in the pixel circuit are used to reset the second electrode and the gate of the driving transistor, respectively, Realization of the complete reset of the driving transistor is beneficial to improve the afterimage phenomenon.

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Abstract

本申请实施例公开了一种像素电路及其驱动方法、显示装置，其中像素电路包括数据写入模块、第一复位模块、驱动晶体管和发光模块；数据写入模块设置为在第一复位阶段将数据信号端输入的恒定的第一电压信号写入到驱动晶体管的第一极；第一复位模块设置为在第一复位阶段将复位信号端输入的复位电压信号写入到驱动晶体管的栅极；数据写入模块设置为在数据写入阶段，将数据信号端输入的数据电压信号写入到驱动晶体管的栅极。

Description

像素电路及其驱动方法、显示装置
本申请要求在2020年04月20日提交中国专利局、申请号为202010312773.9的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及显示技术领域，例如涉及一种像素电路及其驱动方法、显示装置。
背景技术
随着显示技术的发展，人们对显示效果的要求也越来越高。
常规显示面板中，通常包括多个像素电路和发光器件，通过像素电路驱动发光器件发光来进行显示。
然而常规显示面板中存在短期残影的问题，使得显示效果较差。
发明内容
本申请提供一种像素电路及其驱动方法、显示装置，以实现改善短期残影现象，提高显示效果。
第一方面，本发明实施例提供了一种像素电路，像素电路包括数据写入模块、第二复位模块、第一复位模块、驱动晶体管和发光模块；其中，数据写入模块设置为在第一复位阶段将数据信号端输入的恒定的第一电压信号写入到驱动晶体管的第一极；第一复位模块设置为在第一复位阶段将复位信号端输入的复位电压信号写入到驱动晶体管的栅极；数据写入模块设置为在数据写入阶段，将数据信号端输入的数据电压信号写入到驱动晶体管的栅极。第二方面，本发明实施例还提供了一种像素电路的驱动方法，用于驱动第一方面提供的像素电路，像素电路的驱动方法包括：在第一复位阶段，向数据信号端提供恒定的第一电压信号，控制数据写入模块导通，数据写入模块将数据信号端输入的恒定的第一电压信号写入到驱动晶体管的第一极；控制第一复位模块导通，将复位信号端输入的复位电压信号写入到驱动晶体管的栅极；在数据写入阶段，向数据信号端提供数据电压信号，控制数据写入模块导通，将数据信号端输入的数据电压信号写入到驱动晶体管的栅极。
第三方面，本发明实施例还提供了一种显示装置，包括第一方面提供的像素电路；还包括驱动芯片和多条数据线，每条数据线连接至少一列像素电路， 驱动芯片设置为在第一复位阶段，向多条数据线输出恒定的第一电压信号，以及设置为在数据写入阶段，向多条数据线输出数据电压信号。
本申请实施例的提供的像素电路及其驱动方法、显示装置，通过在第一复位阶段和数据写入阶段，分别向数据信号端提供恒定的第一电压信号和数据电压信号，在第一复位阶段，数据写入模块将恒定的第一电压信号写入到驱动晶体管的第一极；并且在第一复位阶段，通过第一复位模块将复位信号端输入的复位电压信号写入到驱动晶体管的栅极；实现驱动晶体管在第一复位阶段的完全复位，则在不同帧中进行灰阶切换时，无论上一帧显示灰阶是否相同，在本帧的第一复位阶段，驱动晶体管都会恢复到相同的初始状态，进而使得灰阶切换过程中驱动晶体管内部的有源层、栅极绝缘层、以及有源层和栅极绝缘层界面处的载流子的捕获和释放程度趋于一致，使得由不同灰阶向同一灰阶切换时，驱动晶体管可以产生相同的驱动电流，则发光模块的发光亮度基本一致，进而减轻残影现象，提高显示效果。
附图说明
图1是本申请实施例提供的一种像素电路的结构示意图。
图2是本申请实施例提供的另一种像素电路的结构示意图。
图3是本申请实施例提供的另一种像素电路的结构示意图。
图4是本申请实施例提供的一种像素电路的驱动时序图。
图5是本申请实施例提供的另一种像素电路的驱动时序图。
图6是本申请实施例提供的另一种像素电路的结构示意图。
图7是本申请实施例提供的另一种像素电路的驱动时序图。
图8是本申请实施例提供的另一种像素电路的结构示意图。
图9是本申请实施例提供的另一种像素电路的驱动时序图。
图10是本申请实施例提供的一种像素电路的驱动方法的流程图。
图11是本申请实施例提供的一种显示装置的结构示意图。
具体实施方式
下面结合附图和实施例对本申请进行说明。此处所描述的实施例仅仅用于解释本申请，而非对本申请的限定。
正如背景技术中所述，常规显示面板中存在短期残影的问题，例如显示面板中原来显示不同灰阶的发光器件向同一灰阶切换时发光亮度不同，使得显示效果较差。经研究发现，出现上述问题的原因在于，常规显示面板通常包括多个像素电路，像素电路包括驱动发光器件发光的驱动晶体管，驱动晶体管通过控制流过发光器件的驱动电流来控制发光器件的发光亮度。驱动晶体管产生的驱动电流大小与驱动晶体管的栅源电压差相关，不同显示灰阶下，驱动晶体管的栅源电压差大小不同。驱动晶体管栅源电压差的不同，使得驱动晶体管的工作状态存在差异，进而使得在驱动晶体管内部的有源层、栅极绝缘层以及有源层和栅极绝缘层的界面处载流子的捕获和释放程度存在差异，导致由不同灰阶向同一灰阶转换时，由于初始状态下驱动晶体管栅源电压差不同导致驱动晶体管的驱动电流大小不同，最终导致发光亮度的差异，形成残影。并且相关技术中，对驱动晶体管栅极进行初始化时，驱动晶体管的源极通常处于浮置状态，进而使得栅极电位的改变也会引起源极电位的改变，使得驱动晶体管的复位不充分，短期残影现象仍然存在。
基于上述问题，本申请实施例提供了一种像素电路，该像素电路包括数据写入模块、第一复位模块、驱动晶体管、发光模块；其中，数据写入模块设置为在第一复位阶段将数据信号端输入的恒定的第一电压信号写入到驱动晶体管的第一极；第一复位模块设置为在第一复位阶段将复位信号端输入的复位电压信号写入到驱动晶体管的栅极；数据写入模块设置为在数据写入阶段，将数据信号端输入的数据电压信号写入到驱动晶体管的栅极。
可选的，一帧内，第一复位阶段可以在数据写入阶段之前进行。
通过在第一复位阶段，数据写入模块将数据信号端输入的恒定的第一电压信号写入到驱动晶体管的第一极，以及第一复位模块将复位信号端输入的复位电压信号写入到驱动晶体管的栅极，使得在第一复位阶段，驱动晶体管的栅极、第一极都得到复位，进而可以使得在第一复位阶段后多个像素电路中驱动晶体管栅源电压差相等，即使得多个像素电路中驱动晶体管的初始状态完全一致，可以实现对驱动晶体管的完全复位，因此在包括多个像素电路的显示面板中，多个像素电路中的驱动晶体管在第一复位阶段都可以被恢复为相同的状态，则在不同帧中进行灰阶切换时，无论上一帧显示灰阶是否相同，在本帧的第一复位阶段，驱动晶体管都会恢复到相同的初始状态，进而使得灰阶切换过程中驱动晶体管内部的有源层、栅极绝缘层、以及有源层和栅极绝缘层界面处的载流子的捕获和释放程度趋于一致，使得由不同灰阶向同一灰阶切换时，驱动晶体管可以产生相同的驱动电流，则发光模块的发光亮度基本一致，进而减轻残影现象。并且，本申请实施例提供的像素电路，通过数据信号端输入信号实现对驱动晶体管第一极的复位，进而无需单独设置对驱动晶体管第一极进行复位的 模块，进而有利于简化像素电路结构，进而减小像素电路面积，提高像素密度。
本申请实施例的提供的像素电路，通过在第一复位阶段和数据写入阶段，分别向数据信号端提供恒定的第一电压信号和数据电压信号，在第一复位阶段，数据写入模块将恒定的第一电压信号写入到驱动晶体管的第一极；并且在第一复位阶段，通过第一复位模块将复位信号端输入的复位电压信号写入到驱动晶体管的栅极；即在第一复位阶段，数据信号端输入的第一电压信号作为驱动晶体管第一极的复位信号，复位信号端输入的复位电压信号作为驱动晶体管栅极的复位信号，相应的，通过控制在第一复位阶段像素电路中数据写入模块和第一复位模块导通，使得第一电压信号可传输到驱动晶体管的第一极，复位电压信号可传输至驱动晶体管的栅极，进而实现驱动晶体管在第一复位阶段的完全复位，则在不同帧中进行灰阶切换时，无论上一帧显示灰阶是否相同，在本帧的第一复位阶段，驱动晶体管都会恢复到相同的初始状态，进而使得灰阶切换过程中驱动晶体管内部的有源层、栅极绝缘层、以及有源层和栅极绝缘层界面处的载流子的捕获和释放程度趋于一致，使得由不同灰阶向同一灰阶切换时，驱动晶体管可以产生相同的驱动电流，则发光模块的发光亮度基本一致，进而减轻残影现象，提高显示效果。
可选的，像素电路还包括第二复位模块，第二复位模块设置为在第一复位阶段，将复位信号端输入的复位电压信号写入到驱动晶体管的第二极。
在第一复位阶段，第二复位模块将复位信号端输入的复位信号写入到驱动晶体管的第二极，使得在驱动晶体管第二极也可以得到复位，即在第一复位阶段，驱动晶体管的第一极、第二极和栅极都可得到复位，可选的，第一极为驱动晶体管的栅极，第二极为驱动晶体管的漏极。并且，可选的，复位信号端输入的复位电压信号与驱动数据信号端输入的第一电压信号的差值的绝对值大于驱动晶体管阈值电压的差值的绝对值，进而保证在第一复位阶段，驱动晶体管可以导通，进而使得数据信号端和复位信号端之间形成电流通路，实现对驱动晶体管的开态电流型复位。
下面将继续结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。
图1是本申请实施例提供的一种像素电路的结构示意图，参考图1，该像素电路包括数据写入模块110、第一复位模块130、驱动晶体管DT和发光模块140；数据写入模块110包括写入晶体管T1和补偿晶体管T2，写入晶体管T1设置为根据第一扫描信号端Scan1的信号控制数据信号端Vdata与驱动晶体管DT的第一极的连接状态，写入晶体管T1的栅极与第一扫描信号端Scan1电连接，写入 晶体管T1的第一极与数据信号端Vdata电连接，写入晶体管T1的第二极与驱动晶体管DT的第一极电连接；补偿晶体管T2设置为根据所述第一扫描信号端Scan1的信号控制驱动晶体管DT的第二极与驱动晶体管DT的栅极的连接状态，补偿晶体管T2的栅极与第一扫描信号端Scan1电连接，补偿晶体管T2的第一极与驱动晶体管DT的第二极电连接，补偿晶体管T2的第二极与驱动晶体管DT的栅极电连接；第一复位模块130的控制端与第三扫描信号端Scan3电连接，第一复位模块130的第一端与复位信号端Vref电连接，第一复位模块130的第二端与驱动晶体管DT的栅极电连接。
图2是本申请实施例提供的另一种像素电路的结构示意图，参考图2，在图1所示像素电路基础上，可选的，像素电路还包括第二复位模块120，第二复位模块120的控制端与第二扫描信号端Scan2电连接，第二复位模块120的第一端与复位信号端Vref电连接，第二复位模块120的第二端与驱动晶体管DT的第二极电连接。
继续参考图1和图2，该像素电路还包括第一发光控制模块150、第二发光控制模块160和存储模块，第一发光控制模块150设置为根据第一发光控制信号端EM1的信号控制第一电源电压端Vdd与驱动晶体管DT的第一极的连接状态；第二发光控制模块160设置为根据第二发光控制信号端EM2的信号控制驱动晶体管DT的第二极与发光模块140的第一端的连接状态，发光模块140的第二端与第二电源电压端Vss电连接；第一发光控制模块150还设置为在第一复位阶段和数据写入阶段，在第一发光控制信号端EM1的控制下关断，第二发光控制模块160还设置为在第一复位阶段和数据写入阶段，在第二发光控制信号端EM2的控制下关断；存储模块设置为存储驱动晶体管DT的栅极电压。
参考图1和图2，可选的，第一发光控制模块150的控制端与第一发光控制信号端EM1电连接，第一发光控制模块150的第一端与第一电源电压端Vdd电连接，第一发光控制模块150的第二端与驱动晶体管DT的第一极电连接；第二发光控制模块160的控制端与第二发光控制信号端EM2电连接，第二发光控制模块160的第一端与驱动晶体管DT的第二极电连接，第二发光控制模块160的第二端与发光模块140的第一端电连接，发光模块140的第二端与第二电源电压端Vss电连接。
图3是本申请实施例提供的另一种像素电路的结构示意图，该像素电路可对应图2所示像素电路的示例性电路，第二复位模块120可包括第一复位晶体管T3，第一复位模块130可包括第二复位晶体管T4，第一发光控制模块150可包括第一发光控制晶体管T5，第二发光控制模块160可包括第二发光控制晶体管T6，发光模块140可包括有机发光器件D1，存储模块包括存储电容Cst，存 储电容Cst的一端与第一电源电压端Vdd电连接，另一端与驱动晶体管DT的栅极电连接。
图4是本申请实施例提供的一种像素电路的驱动时序图，该驱动时序可适用于图2和图3所示的像素电路，以图3所示像素电路的工作为例进行示例性说明。本实施例提供的像素电路中包括的多个晶体管可以是P型晶体管，也可以是N型晶体管，本实施例及以下实施例均以像素电路中所包括的晶体管均为P型晶体管(对于P型晶体管的导通控制信号为低电平信号)为例进行说明。
参考图3和图4，该像素电路的工作过程包括第一复位阶段t00、第二复位阶段t01、数据写入阶段t02和发光阶段t03。
在第一复位阶段t00，第一扫描信号端Scan1输入低电平信号，写入晶体管T1和补偿晶体管T2的导通；数据信号端Vdata输入恒定的第一电压信号，该第一电压信号通过导通的写入晶体管T1写入到驱动晶体管DT的第一极；在第一复位阶段t00，第二扫描信号端Scan2输入低电平信号，第二复位模块120(第一复位晶体管T3)导通，复位信号端Vref输入的复位电压信号通过导通的第一复位晶体管T3写入到驱动晶体管DT的第二极；在第一复位阶段t00，第三扫描信号端Scan3输入低电平，第一复位模块130(第二复位晶体管T4)导通，复位信号端Vref输入的复位电压信号通过导通的第二复位晶体管T4写入到驱动晶体管DT的栅极，进而在第一复位阶段t00实现了对驱动晶体管DT的强制完全复位，进而有利于改善短期残影现象。
在第二复位阶段t01，第二扫描信号端Scan2输入低电平信号，第二复位模块120(第一复位晶体管T3)导通，复位信号端Vref输入的复位电压信号通过导通的第一复位晶体管T3写入驱动晶体管DT的第二极；在第二复位阶段t01，第三扫描信号端Scan3输入低电平，第一复位模块130(第二复位晶体管T4)导通，复位信号端Vref输入的复位电压信号通过导通的第二复位晶体管T4写入到驱动晶体管DT的栅极。需要说明的是，第一复位阶段t00已经可以实现对驱动晶体管DT的栅极的复位，因此该第二复位阶段t01也可省略。
在数据写入阶段t02，第一扫描信号端Scan1输入低电平信号，写入晶体管T1和补偿晶体管T2的导通，数据信号端Vdata输入数据电压信号，该数据电压信号通过导通的写入晶体管T1、驱动晶体管DT和补偿晶体管T2写入到驱动晶体管DT的栅极，实现数据电压的信号和驱动晶体管DT阈值电压的补偿。
在第一复位阶段t00、第二复位阶段t01和数据写入阶段t02，第一发光控制信号端EM1和第二发光控制信号端EM2输入高电平信号，第一发光控制模块150(第五晶体管T5)和第二发光控制模块160(第六晶体管T6)关断。
在发光阶段t03，第一发光控制信号端EM1和第二发光控制信号端EM2输入低电平信号，第一发光控制模块150(第五晶体管T5)和第二发光控制模块160(第六晶体管T6)导通，驱动晶体管DT驱动发光模块140发光。
图4所示驱动时序中，第一发光控制信号端EM1和第二发光控制信号端EM2输入信号相同，因此第一发光控制信号端EM1和第二发光控制信号端EM2可以是相同的发光控制信号端，即第一发光控制模块150和第二发光控制模块160的控制端可连接相同的端口，也即第一发光控制模块150和第二发光控制模块160的控制端可连接相同的发光控制信号线，进而节省包括本实施例像素电路的显示面板中发光控制信号线的数量，进而有利于简化布线。
对于图1所示像素电路的驱动时序，只需将图4所示驱动时序中第二扫描信号输入端Scan2的时序删除，其他时序不变，并且图1所示像素电路除不包括第二复位模块外，其他多个模块的工作工程与图3所示像素电路的工作过程均相同，通过在第一复位阶段对驱动晶体管DT的栅极和第一极进行复位，使得多个像素电路中驱动晶体管DT在第一复位阶段被恢复到相同初始状态，进而改善残影。
图5是本申请实施例提供的另一种像素电路的驱动时序图，该驱动时序可用于驱动图2和图3所示的像素电路，参考图2、图3和图5，第二复位模块120还设置为在第二复位阶段t11，在第二扫描信号端Scan2输入信号的控制下导通，以及第二发光控制模块160还设置为在第二复位阶段t11，在第二发光控制信号端EM2输入信号的控制下导通，以使复位信号端Vref输入的复位电压信号通过第二复位模块120和第二发光控制模块160写入到发光模块140的第一端；第一发光控制模块150还设置为在第二复位阶段，在第一发光控制信号端EM1输入信号的控制下关断。
一帧内，第二复位阶段t11介于第一复位阶段t10和数据写入阶段t12之间。
参考图2、图3和图5，该像素电路的工作过程包括第一复位阶段t10、第二复位阶段t11、数据写入阶段t12和发光阶段t13。
像素电路在第一复位阶段t10的工作过程与图4所示驱动时序在第一复位阶段t00的工作过程相同，在此不再赘述。在第一复位阶段t10实现了对驱动晶体管DT的强制完全复位，进而有利于改善短期残影现象。
在第二复位阶段t11，第二扫描信号端Scan2输入低电平信号，第二复位模块120(第一复位晶体管T3)导通，并且在第二复位阶段t11，第二发光控制信号端EM2输入低电平信号，复位信号端Vref输入的复位电压信号通过导通的第 一复位晶体管T3和第二发光控制模块160写入到发光模块140的第一端(有机发光器件D1的阳极)，进而避免发光模块140第一端残留电荷对显示效果的影响；在第二复位阶段t11，第三扫描信号端Scan3输入低电平，第一复位模块130(第二复位晶体管T4)导通，复位信号端Vref输入的复位电压信号通过导通的第二复位晶体管T4写入到驱动晶体管DT的栅极。
在数据写入阶段t12，第一扫描信号端Scan1输入低电平信号，写入晶体管T1和补偿晶体管T2的导通，数据信号端Vdata输入数据电压信号，该数据电压信号通过导通的写入晶体管T1、驱动晶体管DT和补偿晶体管T2写入到驱动晶体管DT的栅极，实现数据电压的信号和驱动晶体管DT阈值电压的补偿。
在第一复位阶段t10、第二复位阶段t11和数据写入阶段t12，第一发光控制信号端EM1输入高电平信号，第一发光控制晶体管T5关断；在发光阶段t13，第一发光控制信号端EM1输入低电平信号，第一发光控制模块150(第一发光控制晶体管T5)导通，第二发光控制信号端EM2输入低电平信号，第二发光控制模块160(第二发光控制晶体管T6)导通，驱动晶体管DT驱动发光模块140发光。
图5所示驱动时序与图4所示驱动时序的区别在于，第一发光控制信号端EM1和第二发光控制信号端EM2的时序不同，相应的，像素电路的第一发光控制信号端EM1和第二发光控制信号端EM2为不同的发光控制信号端，即第一发光控制模块150控制端和第二发光控制模块160的控制端连接不同的端口。通过设置第一发光控制信号端EM1和第二发光控制信号端EM2为不同的发光控制信号端，使第一发光控制模块150和第二发光控制模块160由不同的发光控制信号控制，可以实现通过第二复位模块120和第二发光控制模块160对发光模块140第一端的复位，避免发光模块140第一端残留电荷对显示效果的影响。
图6是本申请实施例提供的另一种像素电路的结构示意图，参考图6，该像素电路包括数据写入模块110、第二复位模块120、第一复位模块130、驱动晶体管DT和发光模块140；数据写入模块110包括写入晶体管T1和补偿晶体管T2，写入晶体管T1设置为根据第一扫描信号端Scan1的信号控制数据信号端Vdata与驱动晶体管DT的第一极的连接状态，写入晶体管T1的栅极与第一扫描信号端Scan1电连接，写入晶体管T1的第一极与数据信号端Vdata电连接，写入晶体管T1的第二极与驱动晶体管DT的第一极电连接；补偿晶体管T2设置为根据所述第一扫描信号端Scan1的信号控制驱动晶体管DT的第二极与驱动晶体管DT的栅极的连接状态，补偿晶体管T2的栅极与第二扫描信号端Scan2 电连接，补偿晶体管T2的第一极与驱动晶体管DT的第二极电连接，补偿晶体管T2的第二极与驱动晶体管DT的栅极电连接；第二复位模块120的控制端与第三扫描信号端Scan3电连接，第二复位模块120的第一端与复位信号端Vref电连接，第二复位模块120的第二端与驱动晶体管DT的第二极电连接；第二复位模块120和补偿晶体管T2构成第一复位模块130。
继续参考图6，该像素电路还包括第一发光控制模块150、第二发光控制模块160和第三复位模块170，第一发光控制模块150设置为根据发光控制信号端的信号控制第一电源电压端Vdd与驱动晶体管DT的第一极的连接状态；
第二发光控制模块160设置为根据发光控制信号端的信号控制驱动晶体管DT的第二极与发光模块140的第一端的连接状态，发光模块140的第二端与第二电源电压端Vss电连接。
第一发光控制模块150的控制端与发光控制信号端EM电连接，第一发光控制模块150的第一端与第一电源电压端Vdd电连接，第一发光控制模块150的第二端与驱动晶体管DT的第一极电连接；第二发光控制模块160的控制端与发光控制信号端EM电连接，第二发光控制模块160的第一端与驱动晶体管DT的第二极电连接，第二发光控制模块160的第二端与发光模块140的第一端电连接，发光模块140的第二端与第二电源电压端Vss电连接；第三复位模块170设置为根据第三扫描信号端Scan3的信号控制复位信号端Vref与发光模块第一端的连接状态，第三复位模块170的控制端与第三扫描信号端Scan3电连接，第三复位模块170第一端与复位信号端Vref电连接，第三复位模块160的第二端与发光模块140的第一端电连接，发光模块140的第二端与第二电源电压端Vss电连接；第三复位模块170还设置为在第一复位阶段，在第三扫描信号端Scan3输入信号的控制下导通，以对发光模块140的第一端进行复位。
发光控制模块包括第一发光控制模块150和第二发光控制模块160，该第一发光控制模块150和第二发光控制模块160的控制端连接相同的发光控制信号端EM。
图7是本申请实施例提供的另一种像素电路的驱动时序图，该驱动时序可适用于图6所示的像素电路，以图6所示像素电路中第二复位模块120、第一发光控制模块150、第二发光控制模块160、第三复位模块170均包括P型晶体管，且图6中其他模块所包括的晶体管也为P型晶体管为例进行示例性说明。参考图6和图7，图6所示像素电路的工作过程包括括第一复位阶段t21、数据写入阶段t22和发光阶段t23。
在第一复位阶段t21，第一扫描信号端Scan1输入低电平信号，写入晶体管T1导通，数据信号端Vdata输入恒定的第一电压信号，该第一电压信号通过导 通的写入晶体管T1写入到驱动晶体管DT的第一极；在第一复位阶段t21，第三扫描信号端Scan3输入低电平信号，第二复位模块120导通，复位信号端Vref输入的复位电压信号通过导通的第二复位模块120写入到驱动晶体管DT的第二极；在第一复位阶段t21，第二扫描信号端Scan2输入低电平，补偿晶体管T2导通，由第二复位模块120和补偿晶体管T2构成的第一复位模块130导通，复位信号端Vref输入的复位电压信号通过导通的第一复位模块130写入到驱动晶体管DT的栅极，进而在第一复位阶段t21实现了对驱动晶体管DT的强制完全复位，进而有利于改善短期残影现象。第一复位阶段t21，第三复位模块170根据第三扫描信号端Scan3输入的低电平信号而导通，复位信号端Vref输入的复位电压信号通过导通的第三复位模块170传输到发光模块140的第一端，进而实现对发光模块140第一端的复位，进而消除发光模块140第一端的电荷残留，有利于提高显示效果。
在数据写入阶段t22，第一扫描信号端Scan1和第二扫描信号端Scan2输入低电平信号，写入晶体管T1和补偿晶体管T2的导通，数据信号端Vdata输入数据电压信号，该数据电压信号通过导通的写入晶体管T1、驱动晶体管DT和补偿晶体管T2写入到驱动晶体管DT的栅极，实现数据电压的信号和驱动晶体管DT阈值电压的补偿。
在第一复位阶段t21和数据写入阶段t22，发光控制信号端EM输入高电平信号，第一发光控制模块150和第二发光控制模块160关断；在发光阶段t23，发光控制信号端EM输入低电平信号，第一发光控制模块150和第二发光控制模块160导通，驱动晶体管DT驱动发光模块140发光。
图8是本申请实施例提供的另一种像素电路的结构示意图，参考图8，该像素电路与图6所示像素电路的区别在于，第一发光控制模块150的控制端连接第一发光控制信号端EM1，第二发光控制模块160的控制端连接第二发光控制信号端EM2，第一发光控制信号端EM1和第二发光控制信号端EM2为不同发光控制信号端。并且，图8所示像素电路中，不包括第三复位模块。
参考图8，第一发光控制模块150设置为根据第一发光控制信号端EM1的信号控制第一电源电压端Vdd与驱动晶体管DT的第一极的连接状态；第二发光控制模块160设置为根据第二发光控制信号端EM2的信号控制驱动晶体管DT的第二极与发光模块140的第一端的连接状态。
第一发光控制模块150的控制端与第一发光控制信号端EM1电连接，第一发光控制模块150的第一端与第一电源电压端Vdd电连接，第一发光控制模块150的第二端与驱动晶体管DT的第一极电连接；第二发光控制模块160的控制 端与第二发光控制信号端EM2电连接，第二发光控制模块160的第一端与驱动晶体管DT的第二极电连接，第二发光控制模块160的第二端与发光模块140的第一端电连接，发光模块140的第二端与第二电源电压端Vss电连接。
第二复位模块120还设置为在第二复位阶段，在第二扫描信号端Scan2输入信号的控制下导通，以及第二发光控制模块160还设置为在第二复位阶段，在第二发光控制信号端EM2输入信号的控制下导通，以使复位信号端Vref输入的复位电压信号通过第二复位模块120和第二发光控制模块160写入到发光模块140的第一端；第一发光控制模块150还设置为在第二复位阶段，在第一发光控制信号端EM1输入信号的控制下关断。
图9是本申请实施例提供的另一种像素电路的驱动时序图，该驱动时序可用于驱动图8所示像素电路，参考图8和图9，该像素电路的工作过程包括该像素电路的工作过程包括第一复位阶段t30、第二复位阶段t31、数据写入阶段t32和发光阶段t33。
在第一复位阶段t30，第一扫描信号端Scan1输入低电平信号，写入晶体管T1导通，数据信号端Vdata输入恒定的第一电压信号，该第一电压信号通过导通的写入晶体管T1写入到驱动晶体管DT的第一极；在第一复位阶段t30，第三扫描信号端Scan3输入低电平信号，第二复位模块120(第一复位晶体管T3)导通，复位信号端Vref输入的复位电压信号通过导通的第一复位晶体管T3写入到驱动晶体管DT的第二极；在第一复位阶段t30，第二扫描信号端Scan2输入低电平，补偿晶体管T2导通，由第二复位模块120和补偿晶体管T2构成的第一复位模块130导通，复位信号端Vref输入的复位电压信号通过导通的第一复位模块130写入到驱动晶体管DT的栅极，进而在第一复位阶段t30实现了对驱动晶体管DT的强制完全复位，进而有利于改善短期残影现象。
在第二复位阶段t31，第三扫描信号端Scan3输入低电平信号，第二复位模块120(第一复位晶体管T3)导通，第二发光控制信号端EM2输入低电平，第二发光控制模块160导通，复位信号端Vref输入的复位电压信号通过导通的第一复位晶体管T3和第二发光控制模块160写入到发光模块140的第一端。即本实施例的像素电路，在图9所示驱动时序下，可实现通过第二复位模块120和第二发光控制模块160对发光模块140第一端的复位，进而无需设置图6中所示的第三复位模块，使得像素电路所包括的模块数量减少，且第三复位模块通常包括薄膜晶体管，因此可以减少像素电路中薄膜晶体管的数量，有利于减小像素电路的面积，提高像素密度。
在数据写入阶段t32，第一扫描信号端Scan1和第二扫描信号端Scan2输入低电平信号，写入晶体管T1和补偿晶体管T2的导通，数据信号端Vdata输入 数据电压信号，该数据电压信号通过导通的写入晶体管T1、驱动晶体管DT和补偿晶体管T2写入到驱动晶体管DT的栅极，实现数据电压的信号和驱动晶体管DT阈值电压的补偿。
在第一复位阶段t30、第二复位阶段t31和数据写入阶段t32，第一发光控制信号端EM1输入高电平信号，第一发光控制模块150关断；在发光阶段t33，第一发光控制信号端EM1输入低电平信号，第一发光控制模块150导通，第二发光控制信号端EM2输入低电平信号，第二发光控制模块160导通，驱动晶体管DT驱动发光模块140发光。
本实施例提供的像素电路，通过较少数量的薄膜晶体管即可实现对驱动晶体管的完全复位以及对发光模块第一端的复位，在改善残影现象的同时，可以减小像素电路的面积，进而有利于提高像素密度。
本申请的上述任意实施例中，对于在一帧内，像素电路中第一扫描信号端、第二扫描信号端和第三扫描信号端的任意两个扫描信号端在一帧内的时序相同时(例如对于图2和图3所示像素电路中的第二扫描信号端和第三扫描信号端)，两个扫描信号端可连接显示面板中相同的扫描线，进而减少布线条数。
本申请的上述任意实施例中，复位信号端输入的复位电压信号始终恒定，因此在时序图中不再示出。
本申请实施例还提供了一种像素电路的驱动方法，该驱动方法可用于驱动本申请上述任意实施例提供的像素电路，图10是本申请实施例提供的一种像素电路的驱动方法的流程图，参考图10，该像素电路的驱动方法包括：
步骤210、在第一复位阶段，向数据信号端提供恒定的第一电压信号，控制数据写入模块导通，以使数据写入模块将数据信号端输入的恒定的第一电压信号写入到驱动晶体管的第一极；控制第一复位模块导通，将复位信号端输入的复位电压信号写入到驱动晶体管的栅极。
步骤220、在数据写入阶段，向数据信号端提供数据电压信号，控制数据写入模块导通，将数据信号端输入的数据电压信号写入到驱动晶体管的栅极。
本申请实施例的提供的像素电路的驱动方法，通过在第一复位阶段和数据写入阶段，分别向数据信号端提供恒定的第一电压信号以及数据电压信号，在第一复位阶段，数据写入模块将恒定的第一电压信号写入到驱动晶体管的第一极；并且在第一复位阶段，通过第一复位模块将复位信号端输入的复位电压信号写入到驱动晶体管的栅极；即在第一复位阶段，数据信号端输入的第一电压 信号作为驱动晶体管第一极的复位信号，复位信号端输入的复位电压信号作为驱动晶体管栅极的复位信号，相应的，通过控制在第一复位阶段像素电路中数据写入模块和第一复位模块导通，使得第一电压信号可传输到驱动晶体管的第一极，复位电压信号可传输至驱动晶体管的栅极，进而实现驱动晶体管在第一复位阶段的完全复位，则在不同帧中进行灰阶切换时，无论上一帧显示灰阶是否相同，在本帧的第一复位阶段，驱动晶体管都会恢复到相同的初始状态，进而使得灰阶切换过程中驱动晶体管内部的有源层、栅极绝缘层、以及有源层和栅极绝缘层界面处的载流子的捕获和释放程度趋于一致，使得由不同灰阶向同一灰阶切换时，驱动晶体管可以产生相同的驱动电流，从而发光模块的发光亮度基本一致，进而减轻残影现象。
在上述技术方案的基础上，可选的，像素电路的驱动方法还包括：在第一复位阶段，控制第二复位模块导通，将复位信号端输入的复位电压信号写入到驱动晶体管的第二极。
在上述技术方案的基础上，参考图2，可选的，像素电路包括数据写入模块110、第二复位模块120、第一复位模块130、驱动晶体管DT和发光模块140；可选的，数据写入模块110包括写入晶体管T1和补偿晶体管T2，写入晶体管T1的栅极与第一扫描信号端Scan1电连接，写入晶体管T1的第一极与数据信号端Vdata电连接，写入晶体管T1的第二极与驱动晶体管DT的第一极电连接；补偿晶体管T2的栅极与第一扫描信号端Scan1电连接，补偿晶体管T2的第一极与驱动晶体管DT的第二极电连接，补偿晶体管T2的第二极与驱动晶体管DT的栅极电连接；第二复位模块120的控制端与第二扫描信号端Scan2电连接，第二复位模块120的第一端与复位信号端Vref电连接，第二复位模块120的第二端与驱动晶体管DT的第二极电连接；第一复位模块130的控制端与第三扫描信号端Scan3电连接，第一复位模块130的第一端与复位信号端Vref电连接，第一复位模块130的第二端与驱动晶体管DT的栅极电连接。
在第一复位阶段，向数据信号端提供恒定的第一电压信号，控制数据写入模块导通，数据写入模块将数据信号端输入的恒定的第一电压信号写入到驱动晶体管的第一极；控制第二复位模块导通，将复位信号端输入的复位电压信号写入到驱动晶体管的第二极；控制第一复位模块导通，将复位信号端输入的复位电压信号写入到驱动晶体管的栅极，包括：
在第一复位阶段，向第一扫描信号端、第二扫描信号端和第三扫描信号端提供导通控制信号，数据写入模块的写入晶体管和补偿晶体管响应第一扫描信号输入端的导通控制信号导通，数据信号端输入的恒定的第一电压信号通过写 入晶体管写入到驱动晶体管的第一极；第二复位模块响应第二扫描信号端输入的导通控制信号导通，复位信号端输入的复位电压信号通过第二复位模块写入到驱动晶体管的第二极；第一复位模块响应第三扫描信号端输入的导通控制信号导通，复位信号端输入的复位电压信号通过第一复位模块写入到驱动晶体管的栅极。
在数据写入阶段，向数据信号端提供数据电压信号，控制数据写入模块导通，将数据信号端输入的数据电压信号写入到驱动晶体管的栅极，包括：
在数据写入阶段，向数据信号端提供数据信号，向第一扫描信号端输入导通控制信号，写入晶体管和补偿晶体管响应第一扫描信号端的导通控制信号导通，数据信号端输入的数据电压信号通过写入晶体管、驱动晶体管和补偿晶体管写入到驱动晶体管的栅极。
通过控制向第一扫描信号输入端、第二扫描信号输入端和第三扫描信号端输入的信号来控制像素电路中数据写入模块、第二复位模块和第一复位模块的导通或关断状态，进而实现在第一复位阶段对驱动晶体管的完全复位，以及数据写入阶段数据电压信号的写入。
参考图8，该像素电路包括数据写入模块110、第二复位模块120、第一复位模块130、驱动晶体管DT和发光模块140；可选的，数据写入模块110包括写入晶体管T1和补偿晶体管T2，写入晶体管T1的栅极与第一扫描信号端Scan1电连接，写入晶体管T1的第一极与数据信号端Vdata电连接，写入晶体管T1的第二极与驱动晶体管DT的第一极电连接；补偿晶体管T2的栅极与第二扫描信号端Scan2电连接，补偿晶体管T2的第一极与驱动晶体管DT的第二极电连接，补偿晶体管T2的第二极与驱动晶体管DT的栅极电连接；第二复位模块120的控制端与第三扫描信号端Scan3电连接，第二复位模块120的第一端与复位信号端Vref电连接，第二复位模块120的第二端与驱动晶体管DT的第二极电连接；第二复位模块120和补偿晶体管T2构成第一复位模块130。
在第一复位阶段，向数据信号端提供恒定的第一电压信号，控制数据写入模块导通，数据写入模块将数据信号端输入的恒定的第一电压信号写入到驱动晶体管的第一极；控制第二复位模块导通，将复位信号端输入的复位电压信号写入到驱动晶体管的第二极；控制第一复位模块导通，将复位信号端输入的复位电压信号写入到驱动晶体管的栅极，包括：
在第一复位阶段，向第一扫描信号端、第二扫描信号端和第三扫描信号端提供导通控制信号，写入晶体管响应第一扫描信号端输入是导通控制信号导通， 补偿晶体管响应第二扫描信号端输入的导通控制信号信号导通，数据信号端输入的恒定的第一电压信号通过写入晶体管写入到驱动晶体管的第一极；第二复位模块响应第三扫描信号端输入的导通控制信号导通，复位信号端输入的复位电压信号通过第二复位模块写入到驱动晶体管的第二极；复位信号端输入的复位电压信号通过第二复位模块和补偿晶体管写入到驱动晶体管的栅极。
在数据写入阶段，向数据信号端提供数据电压信号，控制数据写入模块导通，将数据信号端输入的数据电压信号写入到驱动晶体管的栅极，包括：
在数据写入阶段，向数据信号端提供数据信号，向第一扫描信号端输入导通控制信号，写入晶体管和补偿晶体管响应第一扫描信号端的导通控制信号导通，数据信号端输入的数据电压信号通过写入晶体管、驱动晶体管和补偿晶体管写入到驱动晶体管的栅极。
通过控制向第一扫描信号输入端、第二扫描信号输入端和第三扫描信号端输入的信号来控制像素电路中数据写入模块、第二复位模块和第一复位模块的导通或关断状态，进而实现在第一复位阶段对驱动晶体管的完全复位，以及数据写入阶段数据电压信号的写入。
本实施例提供的像素电路，还包括第一发光控制模块和第二发光控制模块，第一发光控制模块的控制端与第一发光控制信号端电连接，第一发光控制模块的第一端与第一电源电压端电连接，第一发光控制模块的第二端与驱动晶体管的第一极电连接；第二发光控制模块的控制端与第二发光控制信号端电连接，第二发光控制模块的第一端与驱动晶体管的第二极电连接，第二发光控制模块的第二端与发光模块的第一端电连接，发光模块的第二端与第二电源电压端电连接；像素电路的驱动方法还包括：在第一复位阶段和数据写入阶段，向第一发光控制信号端和第二发光控制信号端提供关断控制信号，使得第一发光控制模块和第二发光控制模块在第一复位阶段和数据写入阶段关断。
本申请实施例还提供了一种显示装置，图11是本申请实施例提供的一种显示装置的结构示意图，参考图11，该显示装置11包括本申请上述任意实施例提供的像素电路100；还包括驱动芯片200和多条数据线(DL1、DL2、DL3、DL4……)，每条数据线连接至少一列像素100，驱动芯片200设置为在第一复位阶段，向多条数据线输出恒定的第一电压信号，以及在数据写入阶段，向多条数据线输出数据电压信号。可选的，每条数据线连接一列像素电路，数据线与像素电路的数据信号端电连接。
继续参考图11，可选的，该像素电路还包括栅极驱动电路300、多条扫描 线(S1、S2、S3……)、多条复位信号线(Vr1、Vr2、Vr3、Vr4……)以及参考电压源400，多条扫描线分别与栅极驱动电路的输出端电连接，示例性的，对于图2所示像素电路，每行像素电路可连接三条扫描线(例如称之为第一扫描线、第二扫描线和第三扫描线)，第一扫描线连接像素电路的第一扫描信号端，第二扫描线连接像素电路的第二扫描信号端，第三扫描线连接像素电路的第三扫描信号端。参考电压线与参考电压源400电连接，可选的，该参考电压源400可与驱动芯片200分立设置，参考电压源400也可集成在驱动芯片200内部，本实施例在此不做限定，每条参考电压线可以连接一列像素电路的复位信号端。
本实施例提供的显示装置，包括本申请任意实施例提供的像素电路，通过驱动芯片在第一复位阶段，向数据线输出恒定的第一电压信号，以及在数据写入阶段，向数据线输出数据电压信号，实现通过数据信号端向像素电路提供驱动晶体管第一极的复位信号，进而配合像素电路中第二复位模块和第一复位模块分别将驱动晶体管的第二极和栅极进行复位，实现对驱动晶体管的完全复位，进而有利于改善残影现象。

Claims (19)

  1. 一种像素电路，包括：
    驱动晶体管；
    发光模块；
    数据写入模块，设置为在第一复位阶段将数据信号端输入的恒定的第一电压信号写入到所述驱动晶体管的第一极，以及在数据写入阶段，将所述数据信号端输入的数据电压信号写入到所述驱动晶体管的栅极；以及
    第一复位模块，设置为在所述第一复位阶段将复位信号端输入的复位电压信号写入到所述驱动晶体管的栅极。
  2. 根据权利要求1所述的像素电路，还包括第二复位模块，所述第二复位模块设置为在所述第一复位阶段，将所述复位信号端输入的复位电压信号写入到所述驱动晶体管的第二极。
  3. 根据权利要求2所述的像素电路，其中，所述数据写入模块包括写入晶体管和补偿晶体管，所述写入晶体管设置为根据第一扫描信号端的信号控制所述数据信号端与所述驱动晶体管的第一极的连接状态；所述补偿晶体管设置为根据所述第一扫描信号端的信号控制所述驱动晶体管的第二极与所述驱动晶体管的栅极的连接状态；
    所述第二复位模块的控制端与第二扫描信号端电连接，所述第二复位模块的第一端与所述复位信号端电连接，所述第二复位模块的第二端与所述驱动晶体管的第二极电连接；
    所述第一复位模块的控制端与第三扫描信号端电连接，所述第一复位模块的第一端与所述复位信号端电连接，所述第一复位模块的第二端与所述驱动晶体管的栅极电连接。
  4. 根据权利要求2所述的像素电路，其中，所述数据写入模块包括写入晶体管和补偿晶体管，所述写入晶体管设置为根据第一扫描信号端的信号控制所述数据信号端与所述驱动晶体管的第一极的连接状态；所述补偿晶体管设置为根据第二扫描信号端的信号控制所述驱动晶体管的第二极与所述驱动晶体管的栅极的连接状态；
    所述第二复位模块的控制端与第三扫描信号端电连接，所述第二复位模块的第一端与所述复位信号端电连接，所述第二复位模块的第二端与所述驱动晶体管的第二极电连接；
    其中，所述第二复位模块和所述补偿晶体管构成所述第一复位模块。
  5. 根据权利要求2-4任一项所述的像素电路，还包括第一发光控制模块、 第二发光控制模块和存储模块，所述第一发光控制模块设置为根据第一发光控制信号端的信号控制第一电源电压端与所述驱动晶体管的第一极的连接状态；
    所述第二发光控制模块设置为根据第二发光控制信号端的信号控制所述驱动晶体管的第二极与所述发光模块的第一端的连接状态，所述发光模块的第二端与第二电源电压端电连接；
    所述第一发光控制模块还设置为在所述第一复位阶段和所述数据写入阶段，在所述第一发光控制信号端的控制下关断，所述第二发光控制模块还设置为在所述第一复位阶段和所述数据写入阶段，在所述第二发光控制信号端的控制下关断；
    所述存储模块设置为存储所述驱动晶体管的栅极电压。
  6. 根据权利要求5所述的像素电路，其中，所述第二复位模块还设置为在第二复位阶段，在第二扫描信号端的输入信号的控制下导通，以及所述第二发光控制模块还设置为在所述第二复位阶段，在所述第二发光控制信号端的输入信号的控制下导通，以使所述复位信号端输入的复位电压信号通过所述第二复位模块和所述第二发光控制模块写入到所述发光模块的第一端；
    所述第一发光控制模块还设置为在所述第二复位阶段，在所述第一发光控制信号端的输入信号的控制下关断；
    其中所述第二复位阶段介于所述第一复位阶段和所述数据写入阶段之间。
  7. 根据权利要求4所述像素电路，还包括第一发光控制模块、第二发光控制模块和第三复位模块；
    所述第一发光控制模块设置为根据发光控制信号端的信号控制第一电源电压端与所述驱动晶体管的第一极的连接状态；
    所述第二发光控制模块设置为根据所述发光控制信号端的信号控制所述驱动晶体管的第二极与所述发光模块的第一端的连接状态，所述发光模块的第二端与第二电源电压端电连接；
    所述第三复位模块的控制端设置为根据所述第三扫描信号端的信号控制所述复位信号端与所述发光模块的第一端的连接状态，所述发光模块的第二端与所述第二电源电压端电连接；所述第三复位模块设置为在所述第一复位阶段，在所述第三扫描信号端的输入信号的控制下导通，以对所述发光模块的第一端进行复位。
  8. 根据权利要求5所述的像素电路，其中，所述第一发光控制模块的控制端与所述第一发光控制信号端电连接，所述第一发光控制模块的第一端与所述 第一电源电压端电连接，所述第一发光控制模块的第二端与所述驱动晶体管的第一极电连接；所述第二发光控制模块的控制端与所述第二发光控制信号端电连接，所述第二发光控制模块的第一端与所述驱动晶体管的第二极电连接，所述第二发光控制模块的第二端与所述发光模块的第一端电连接。
  9. 根据权利要求7所述的像素电路，其中，所述第一发光控制模块的控制端与所述发光控制信号端电连接，所述第一发光控制模块的第一端与所述第一电源电压端电连接，所述第一发光控制模块的第二端与所述驱动晶体管的第一极电连接；所述第二发光控制模块的控制端与所述发光控制信号端电连接，所述第二发光控制模块的第一端与所述驱动晶体管的第二极电连接，所述第二发光控制模块的第二端与所述发光模块的第一端电连接；所述第三复位模块的控制端与所述第三扫描信号端电连接，所述第三复位模块第一端与所述复位信号端电连接，所述第三复位模块的第二端与所述发光模块的第一端电连接。
  10. 根据权利要求5所述的像素电路，其中，所述存储模块包括存储电容，所述存储电容的一端与所述第一电源电压端电连接，所述存储电容的另一端与所述驱动晶体管的栅极电连接。
  11. 根据权利要求7或9所述的像素电路，其中，所述第一发光控制模块包括第一发光控制晶体管，第二发光控制模块包括第二发光控制晶体管。
  12. 根据权利要求1所述的像素电路，其中，所述第一复位模块包括第二复位晶体管。
  13. 根据权利要求2所述的像素电路，其中，所述第二复位模块包括第一复位晶体管。
  14. 一种像素电路的驱动方法，用于驱动权利要求1-13任一项所述的像素电路，包括：
    在第一复位阶段，向数据信号端提供恒定的第一电压信号，控制数据写入模块导通，以使所述数据写入模块将所述数据信号端输入的恒定的第一电压信号写入到驱动晶体管的第一极；控制第一复位模块导通，将复位信号端输入的复位电压信号写入到所述驱动晶体管的栅极；
    在数据写入阶段，向所述数据信号端提供数据电压信号，控制所述数据写入模块导通，将所述数据信号端输入的数据电压信号写入到所述驱动晶体管的栅极。
  15. 根据权利要求14所述的像素电路的驱动方法，还包括：
    在所述第一复位阶段，控制第二复位模块导通，将复位信号端输入的复位电压信号写入到所述驱动晶体管的第二极。
  16. 一种显示装置，包括权利要求1-13任一项所述的像素电路；还包括驱动芯片和多条数据线，每条数据线连接至少一列像素电路，所述驱动芯片设置为在第一复位阶段，向所述多条数据线输出恒定的第一电压信号，以及在数据写入阶段，向所述多条数据线输出数据电压信号。
  17. 根据权利要求16所述的显示装置，还包括：栅极驱动电路、多条扫描线、多条复位信号线以及参考电压源；所述多条扫描线与所述栅极驱动电路的输出端电连接，所述多条复位信号线与所述参考电压源电连接。
  18. 根据权利要求17所述的显示装置，其中，每行像素电路连接三条扫描线，所述三条扫描线分别为第一扫描线、第二扫描线和第三扫描线；
    所述第一扫描线连接所述每行像素电路的第一扫描信号端，所述第二扫描线连接所述每行像素电路的第二扫描信号端，所述第三扫描线连接所述每行像素电路的第三扫描信号端。
  19. 根据权利要求17所述的显示装置，还包括：多条参考电压线，所述多条参考电压线与所述参考电压源电连接，每条参考电压线连接一列像素电路的复位信号端。
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Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111445858A (zh) * 2020-04-20 2020-07-24 昆山国显光电有限公司 像素电路及其驱动方法、显示装置
CN114586091B (zh) * 2020-09-28 2024-03-19 京东方科技集团股份有限公司 像素驱动电路及显示面板
WO2022109984A1 (zh) * 2020-11-27 2022-06-02 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板、显示装置
CN112908258B (zh) 2021-03-23 2022-10-21 武汉天马微电子有限公司 像素驱动电路、驱动方法、显示面板与显示装置
CN113299243B (zh) * 2021-06-18 2022-09-02 合肥京东方卓印科技有限公司 一种像素电路及其驱动方法、显示装置
CN115512631A (zh) * 2021-06-22 2022-12-23 荣耀终端有限公司 像素驱动电路及其驱动方法、显示面板及终端设备
CN113539176B (zh) * 2021-07-29 2022-12-30 武汉天马微电子有限公司 像素电路及其驱动方法、显示面板和显示装置
CN114222615B (zh) * 2021-07-30 2022-08-23 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板
KR20230064708A (ko) * 2021-11-03 2023-05-11 삼성디스플레이 주식회사 화소 및 이를 포함하는 표시 장치
CN114120909B (zh) * 2021-12-07 2023-02-10 云谷（固安）科技有限公司 像素电路及显示面板
CN114283744A (zh) * 2021-12-30 2022-04-05 重庆惠科金渝光电科技有限公司 显示单元的驱动方法、显示面板及显示装置
KR20230110412A (ko) 2022-01-14 2023-07-24 삼성디스플레이 주식회사 화소 및 이를 포함하는 표시 장치
CN114495825B (zh) * 2022-01-28 2023-09-01 武汉天马微电子有限公司 一种像素驱动电路、驱动方法及显示面板、显示装置
CN114863875B (zh) * 2022-05-25 2023-05-05 武汉天马微电子有限公司 显示面板及其驱动方法、显示装置
CN115171590A (zh) * 2022-07-28 2022-10-11 惠科股份有限公司 像素驱动电路和显示面板
CN115240582B (zh) * 2022-09-23 2022-12-13 昆山国显光电有限公司 像素电路及其驱动方法、显示面板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102222465A (zh) * 2011-03-17 2011-10-19 友达光电股份有限公司 具临界电压补偿机制的有机发光显示装置及其驱动方法
KR20120043301A (ko) * 2010-10-26 2012-05-04 엘지디스플레이 주식회사 유기발광다이오드 표시장치 및 그 구동방법
CN107358917A (zh) * 2017-08-21 2017-11-17 上海天马微电子有限公司 一种像素电路、其驱动方法、显示面板及显示装置
CN109509433A (zh) * 2019-01-30 2019-03-22 京东方科技集团股份有限公司 像素电路、显示装置和像素驱动方法
CN111445858A (zh) * 2020-04-20 2020-07-24 昆山国显光电有限公司 像素电路及其驱动方法、显示装置

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4240059B2 (ja) * 2006-05-22 2009-03-18 ソニー株式会社 表示装置及びその駆動方法
JP2008139520A (ja) * 2006-12-01 2008-06-19 Sony Corp 表示装置
JP4600780B2 (ja) * 2007-01-15 2010-12-15 ソニー株式会社 表示装置及びその駆動方法
JP4337897B2 (ja) * 2007-03-22 2009-09-30 ソニー株式会社 表示装置及びその駆動方法と電子機器
JP5186888B2 (ja) * 2007-11-14 2013-04-24 ソニー株式会社 表示装置及びその駆動方法と電子機器
KR101517110B1 (ko) * 2007-11-14 2015-05-04 소니 주식회사 표시장치 및 그 구동 방법과 전자기기
JP4655085B2 (ja) * 2007-12-21 2011-03-23 ソニー株式会社 表示装置及び電子機器
JP5236324B2 (ja) * 2008-03-19 2013-07-17 グローバル・オーエルイーディー・テクノロジー・リミテッド・ライアビリティ・カンパニー 表示パネル
KR101596978B1 (ko) * 2010-04-05 2016-02-23 가부시키가이샤 제이올레드 유기 ｅｌ 표시 장치 및 그 제어 방법
JP5738270B2 (ja) * 2011-08-09 2015-06-24 株式会社Ｊｏｌｅｄ 表示装置
CN104078005B (zh) * 2014-06-25 2017-06-09 京东方科技集团股份有限公司 像素电路及其驱动方法和显示装置
CN104809989A (zh) * 2015-05-22 2015-07-29 京东方科技集团股份有限公司 一种像素电路、其驱动方法及相关装置
CN104851392B (zh) * 2015-06-03 2018-06-05 京东方科技集团股份有限公司 一种像素驱动电路及方法、阵列基板和显示装置
CN105185305A (zh) * 2015-09-10 2015-12-23 京东方科技集团股份有限公司 一种像素电路、其驱动方法及相关装置
CN106952618B (zh) * 2017-05-26 2019-11-29 京东方科技集团股份有限公司 显示装置以及像素电路及其控制方法
CN107316613B (zh) * 2017-07-31 2019-07-09 上海天马有机发光显示技术有限公司 像素电路、其驱动方法、有机发光显示面板及显示装置
CN107342044B (zh) * 2017-08-15 2020-03-03 上海天马有机发光显示技术有限公司 像素电路、显示面板和像素电路的驱动方法
US10304378B2 (en) * 2017-08-17 2019-05-28 Apple Inc. Electronic devices with low refresh rate display pixels
CN107274825B (zh) * 2017-08-18 2020-11-24 上海天马微电子有限公司 显示面板、显示装置、像素驱动电路及其控制方法
CN107481676B (zh) * 2017-09-30 2020-09-08 上海天马有机发光显示技术有限公司 一种像素电路的驱动方法、显示面板以及显示装置
CN109872692B (zh) * 2017-12-04 2021-02-19 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN108493350B (zh) 2018-03-09 2021-02-05 上海天马有机发光显示技术有限公司 一种有机发光显示面板及其显示装置
CN108735155A (zh) * 2018-06-01 2018-11-02 京东方科技集团股份有限公司 一种像素电路、其驱动方法及显示面板、显示装置
CN109036279B (zh) 2018-10-18 2020-04-17 京东方科技集团股份有限公司 阵列基板、驱动方法、有机发光显示面板及显示装置
CN109677091B (zh) 2019-02-14 2021-01-29 京东方科技集团股份有限公司 贴合装置及贴合方法
CN109903724B (zh) * 2019-04-29 2021-01-19 昆山国显光电有限公司 一种像素电路、像素电路的驱动方法和显示面板
CN110223636B (zh) * 2019-06-17 2021-01-15 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示装置
CN110299107B (zh) * 2019-06-28 2021-01-29 上海天马有机发光显示技术有限公司 一种有机发光显示面板及有机发光显示装置
CN110246462A (zh) * 2019-07-26 2019-09-17 云谷（固安）科技有限公司 一种像素电路及其驱动方法、显示装置及其驱动方法
CN110675815A (zh) * 2019-09-26 2020-01-10 武汉天马微电子有限公司 像素驱动电路及其驱动方法、显示装置
CN110570813A (zh) 2019-09-30 2019-12-13 昆山国显光电有限公司 像素电路、驱动方法及显示面板
CN110942743B (zh) * 2019-12-26 2021-04-13 云谷（固安）科技有限公司 像素电路的驱动方法、显示面板和显示装置
KR20210111945A (ko) * 2020-03-03 2021-09-14 삼성디스플레이 주식회사 표시장치
CN112331134A (zh) * 2020-10-23 2021-02-05 厦门天马微电子有限公司 显示面板及显示装置
CN112687227A (zh) * 2021-01-08 2021-04-20 厦门天马微电子有限公司 显示面板和显示装置
CN112634812A (zh) * 2021-01-08 2021-04-09 厦门天马微电子有限公司 显示面板和显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120043301A (ko) * 2010-10-26 2012-05-04 엘지디스플레이 주식회사 유기발광다이오드 표시장치 및 그 구동방법
CN102222465A (zh) * 2011-03-17 2011-10-19 友达光电股份有限公司 具临界电压补偿机制的有机发光显示装置及其驱动方法
CN107358917A (zh) * 2017-08-21 2017-11-17 上海天马微电子有限公司 一种像素电路、其驱动方法、显示面板及显示装置
CN109509433A (zh) * 2019-01-30 2019-03-22 京东方科技集团股份有限公司 像素电路、显示装置和像素驱动方法
CN111445858A (zh) * 2020-04-20 2020-07-24 昆山国显光电有限公司 像素电路及其驱动方法、显示装置

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