WO2022109984A1 - 像素电路及其驱动方法、显示基板、显示装置 - Google Patents

像素电路及其驱动方法、显示基板、显示装置 Download PDF

Info

Publication number
WO2022109984A1
WO2022109984A1 PCT/CN2020/132090 CN2020132090W WO2022109984A1 WO 2022109984 A1 WO2022109984 A1 WO 2022109984A1 CN 2020132090 W CN2020132090 W CN 2020132090W WO 2022109984 A1 WO2022109984 A1 WO 2022109984A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
pole
signal terminal
gate
pixel circuit
Prior art date
Application number
PCT/CN2020/132090
Other languages
English (en)
French (fr)
Inventor
张竞文
肖云升
王苗
曹丹
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202410064244.XA priority Critical patent/CN117711325A/zh
Priority to CN202080003064.0A priority patent/CN114902321B/zh
Priority to PCT/CN2020/132090 priority patent/WO2022109984A1/zh
Priority to US17/424,965 priority patent/US11721286B2/en
Publication of WO2022109984A1 publication Critical patent/WO2022109984A1/zh
Priority to US18/346,157 priority patent/US20230351969A1/en

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
    • G09G3/325—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror the data current flowing through the driving transistor during a setting phase, e.g. by using a switch for connecting the driving transistor to the data driver
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the embodiments of the present disclosure relate to the technical field of pixel circuits, and in particular, to a pixel circuit and a driving method thereof, a display substrate, and a display device.
  • an organic light-emitting diode (OLED) display substrate in the light-emitting stage, by applying a certain driving voltage to the gate of the driving transistor, the organic light-emitting diode emits corresponding brightness for display.
  • the voltage of the gate of the driving transistor may change due to the existence of leakage current, thereby causing the brightness of the organic light emitting diode to change, resulting in a flicker (Flicker) phenomenon and affecting the display quality.
  • Embodiments of the present disclosure provide a pixel circuit and a driving method thereof, a display substrate, and a display device.
  • a pixel circuit which includes:
  • a light-emitting module configured to emit light
  • a driving module configured to drive the light-emitting module to emit light according to the driving voltage in the light-emitting stage
  • the storage module is configured to maintain the driving voltage during the light-emitting phase, and provide the driving voltage to the driving module;
  • the first pole of the first transistor is connected to the position where the driving module obtains the driving voltage, and the second pole of the first transistor is not directly connected to the signal source;
  • the second transistor the first electrode of the second transistor is connected to the first electrode of the first transistor, and the structure of connecting the second electrode of the second transistor is different from the structure of connecting the second electrode of the first transistor ; in the light-emitting phase, the voltage of the second electrode of the first transistor is lower than the voltage of the first electrode of the first transistor, and the voltage of the second electrode of the second transistor is higher than that of the first transistor The voltage of the first pole;
  • a stabilizing capacitor the first pole of the stabilizing capacitor is connected to the second pole of the first transistor, and the second pole of the stabilizing capacitor is connected to the constant voltage signal source.
  • the pixel circuit further includes:
  • the first pole of the third transistor is connected to the second pole of the first transistor, and the gate of the third transistor is connected to the gate of the first transistor;
  • the first pole of the fourth transistor is connected to the second pole of the second transistor, and the gate of the fourth transistor is connected to the gate of the second transistor;
  • the light-emitting module includes a light-emitting device
  • the driving module includes a driving transistor, and the driving transistor is configured to drive the light-emitting device to emit light according to the voltage of the gate thereof;
  • the storage module includes a storage capacitor, a first electrode of the storage capacitor is connected to the gate of the driving transistor, the storage capacitor is configured to maintain the drive voltage at the first electrode of the storage capacitor during the light-emitting phase, and transmits the drive voltage to the drive transistor.
  • the driving module provides the driving voltage.
  • the pixel circuit includes a first reset module and a write module
  • the first reset module is configured to reset the voltage of the gate of the driving transistor according to the signals of the initialization signal terminal and the first reset signal terminal; the first reset module includes:
  • the first electrode of the third transistor is connected to the second electrode of the first transistor, the second electrode of the third transistor is connected to the initialization signal terminal, and the gate of the third transistor is connected connecting the gate of the first transistor and the first reset signal terminal;
  • the writing module is configured to write the driving voltage to the first pole of the storage capacitor according to the signals of the gate signal terminal and the data signal terminal; the writing module includes:
  • the first pole of the fourth transistor is connected to the second pole of the second transistor, the second pole of the fourth transistor is connected to the second pole of the driving transistor, and the fourth transistor
  • the gate of the second transistor is connected to the gate of the second transistor and the gate signal terminal;
  • the first pole of the fifth transistor is connected to the first pole of the driving transistor, the second pole of the fifth transistor is connected to the data signal terminal, and the gate of the fifth transistor is connected to the gate signal terminal;
  • the first pole of the sixth transistor is connected to the first power supply signal terminal, the second pole of the sixth transistor is connected to the first pole of the driving transistor, and the gate of the sixth transistor is connected control signal terminal;
  • the driving transistor and the light-emitting device are connected in series between the first power supply signal terminal and the second power supply signal terminal;
  • the second pole of the storage capacitor is connected to the first power signal terminal
  • the second pole of the light emitting device is connected to the second power signal terminal.
  • the constant voltage signal source is any one of the initialization signal terminal, the first power signal terminal, and the second power signal terminal.
  • the pixel circuit further includes:
  • control module is configured to control whether the light-emitting device emits light according to the signal of the control signal terminal;
  • the control module includes: a seventh transistor, the first pole of the seventh transistor is connected to the first pole of the driving transistor Diode, the second pole of the seventh transistor is connected to the first pole of the light emitting device, and the gate of the seventh transistor is connected to the control signal terminal;
  • the second reset module is configured to reset the voltage of the first electrode of the light emitting device according to the second reset signal terminal and the signal of the initialization signal terminal;
  • the second reset module includes : an eighth transistor, the first pole of the eighth transistor is connected to the first pole of the light-emitting device, the second pole of the eighth transistor is connected to the initialization signal terminal, and the gate of the eighth transistor is connected to the the second reset signal terminal.
  • the driving transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor , the eighth transistor is a P-type transistor
  • the drive transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor Both are N-type transistors.
  • an embodiment of the present disclosure provides a method for driving a pixel circuit, wherein the pixel circuit is any of the above-mentioned pixel circuits, and the driving method for the pixel circuit includes:
  • the storage module is made to maintain the driving voltage, and the driving voltage is provided to the driving module.
  • the driving method of the pixel circuit includes:
  • a turn-on signal is provided to the first reset signal terminal, a turn-off signal is provided to the gate signal terminal, and a turn-off signal is provided to the control signal terminal;
  • an off signal is provided to the first reset signal terminal, an on signal is provided to the gate signal terminal, an off signal is provided to the control signal terminal, and a data signal is provided to the data signal terminal ;
  • an off signal is provided to the first reset signal terminal, an off signal is provided to the gate signal terminal, and an on signal is provided to the control signal terminal.
  • the driving method of the pixel circuit further includes:
  • a shutdown signal is provided to the second reset signal terminal
  • a turn-on signal is provided to the second reset signal terminal
  • an off signal is provided to the second reset signal terminal.
  • a display substrate including:
  • the first pole of the stabilizing capacitor includes: a connection part connected between the first pole of the third transistor and the second pole of the first transistor; connected to the connection part add-on.
  • the first pole of the stabilizing capacitor and the second pole of the first transistor are disposed in the same layer and connected as a whole.
  • the first electrode of the voltage stabilization capacitor is disposed in the same layer as the active region of the driving transistor, and the first electrode of the voltage stabilization capacitor is made of conductive semiconductor material;
  • the second electrode of the first transistor is disposed in the same layer as the active region of the driving transistor, and the second electrode of the first transistor is made of conductive semiconductor material.
  • the second pole of the stabilizing capacitor and the initialization signal terminal are disposed on the same layer and connected as a whole.
  • the display substrate sequentially includes:
  • the initialization signal terminal includes a first initialization signal terminal and a second initialization signal terminal set at the same layer, and the first initialization signal terminal and the second initialization signal terminal are arranged in parallel and spaced apart;
  • the second pole of the eighth transistor is connected to the first initialization signal terminal
  • the second electrode of the third transistor is connected to the second initialization signal terminal.
  • the first pole of the stabilizing capacitor extends along the first direction
  • the data signal terminal and/or the first power signal terminal extend along a second direction; the first direction intersects the second direction.
  • the first reset signal terminal extends along a first direction
  • At least part of the first reset signal terminal of the pixel circuit is multiplexed into the second reset signal terminal of the pixel circuit adjacent to the pixel circuit along the second direction; The second direction intersects.
  • the second pole of the storage capacitor includes a horizontal connection structure extending along a first direction; at least part of the horizontal connection structures of the pixel circuits adjacent to each other along the first direction are connected to each other;
  • the first power signal terminal extends along a second direction; the first direction intersects with the second direction.
  • the display substrate further includes:
  • the auxiliary conductive structure is arranged overlapping with the first power signal terminal; at least one insulating layer is arranged between the auxiliary conductive structure and the first power signal terminal, and the auxiliary conductive structure passes through the insulating layer.
  • the via hole is connected to the first power signal terminal.
  • the display substrate sequentially includes:
  • a semiconductor layer comprising: a first electrode, a second electrode, and an active region of the driving transistor, a first electrode, a second electrode, and an active region of the first transistor, and a first electrode of the second transistor , the second pole, the active area, the first pole, the second pole, the active area of the third transistor, the first pole, the second pole, the active area of the fourth transistor, the fifth transistor
  • the first gate layer includes: the gate of the driving transistor, the gate of the first transistor, the gate of the second transistor, the gate of the third transistor, the gate of the fourth transistor gate, the gate of the fifth transistor, the gate of the sixth transistor, the gate of the seventh transistor, the gate of the eighth transistor, the first reset signal terminal, the the second reset signal terminal, the control signal terminal, the first pole of the storage capacitor;
  • the second gate layer includes: the initialization signal terminal, the second pole of the stabilizing capacitor, and the second pole of the storage capacitor; wherein, the second pole of the stabilizing capacitor and the initialization signal connected together;
  • the first source and drain layer includes: the first power signal terminal, the data signal terminal, and a first light-emitting access structure; wherein, the first power signal terminal passes through the second interlayer insulating layer.
  • a via hole is connected to the second electrode of the storage capacitor, and the gate insulating layer, the first interlayer insulating layer, and the via hole in the second interlayer insulating layer are connected to the first electrode of the sixth transistor. pole;
  • the data signal terminal is connected to the second pole of the fifth transistor through the gate insulating layer, the first interlayer insulating layer, and the via hole in the second interlayer insulating layer.
  • the light emitting access structure connects the second pole of the seventh transistor through the gate insulating layer, the first interlayer insulating layer, and the via hole in the second interlayer insulating layer;
  • the second source-drain layer includes: an auxiliary conductive structure and a second light-emitting access structure; wherein, the auxiliary conductive structure and the first power signal terminal are overlapped and disposed, and pass through the first planarization layer.
  • the via hole is connected to the first power signal terminal; the second light emitting access structure is connected to the first light emitting access structure through the via hole in the first planarization layer;
  • the first pole of the light emitting device is connected to the second light emitting access structure through a via hole in the second planarization layer.
  • the second gate layer further includes:
  • a shielding structure wherein the shielding structure is connected to the first power supply signal terminal through a via hole in the second interlayer insulating layer, and the shielding structure is connected to the first pole of the first transistor and the terminal of the fifth transistor.
  • the second poles are overlapped and insulated.
  • the first source-drain layer further includes:
  • first connection structure connects the second electrode of the eighth transistor through the gate insulating layer, the first interlayer insulating layer, and the via hole in the second interlayer insulating layer, and connecting the initialization signal terminal through the via hole in the second interlayer insulating layer;
  • the second connection structure connects the second electrode of the third transistor through the gate insulating layer, the first interlayer insulating layer, and the via hole in the second interlayer insulating layer, and connecting the initialization signal terminal through the via hole in the second interlayer insulating layer;
  • a third connection structure wherein the third connection structure is connected to the gate of the driving transistor through the first interlayer insulating layer and the via hole in the second interlayer insulating layer, and is connected to the gate of the driving transistor through the gate insulating layer,
  • the via holes in the first interlayer insulating layer and the second interlayer insulating layer are connected to the first electrodes of the first transistors.
  • the capacitance value of the stabilizing capacitor is not lower than 8fF, and is not more than a quarter of the capacitance value of the storage capacitor.
  • a display device which includes:
  • FIG. 1 is a circuit diagram of a pixel circuit in the related art
  • Fig. 2 is a simulation result diagram of the variation of some signals with time in a pixel circuit in the related art
  • Fig. 3 is a simulation result diagram of the variation of light-emitting luminance with time in a pixel circuit in the related art
  • FIG. 4 is a circuit diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 5 is a driving timing diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 6 is a simulation result diagram of changes of some signals over time when the capacitance values of the voltage regulator capacitors are different in a pixel circuit provided by an embodiment of the present disclosure
  • FIG. 7 is a circuit diagram of another pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 8 is a driving timing diagram of another pixel circuit according to an embodiment of the present disclosure.
  • FIG. 9 is a simulation result diagram of the change of the Flicker value with the capacitance value of the stabilizing capacitor in a pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 10 is a perspective structural schematic diagram of a partial structure of a pixel circuit in a display substrate according to an embodiment of the present disclosure
  • FIG. 11 is a schematic structural diagram of a POLY layer of a pixel circuit in a display substrate according to an embodiment of the present disclosure
  • FIG. 12 is a schematic structural diagram of a first gate layer of a pixel circuit in a display substrate according to an embodiment of the present disclosure
  • FIG. 13 is a schematic structural diagram of a second gate layer of a pixel circuit in a display substrate according to an embodiment of the present disclosure
  • FIG. 14 is a perspective structural schematic diagram of a structure constituting a voltage stabilizing capacitor in a pixel circuit in a display substrate according to an embodiment of the present disclosure
  • FIG. 15 is a schematic structural diagram of a first source-drain layer of a pixel circuit in a display substrate according to an embodiment of the present disclosure
  • 16 is a schematic structural diagram of a second source-drain layer of a pixel circuit in a display substrate according to an embodiment of the present disclosure
  • 17 is a schematic diagram of a via hole subdivision of a gate insulating layer of a pixel circuit in a display substrate according to an embodiment of the present disclosure
  • FIG. 18 is a schematic diagram of a via hole subsection of a first interlayer insulating layer of a pixel circuit in a display substrate according to an embodiment of the present disclosure
  • FIG. 19 is a schematic diagram of a partial via hole of a second interlayer insulating layer of a pixel circuit in a display substrate according to an embodiment of the present disclosure
  • FIG. 20 is a schematic diagram of a partial via hole of a first planarization layer (also a passivation layer) of a pixel circuit in a display substrate according to an embodiment of the present disclosure
  • 21 is a schematic diagram of a via hole subsection of a second planarization layer of a pixel circuit in a display substrate according to an embodiment of the present disclosure
  • TD driving transistor
  • T1 first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, first transistor Eight transistors;
  • OLED organic light-emitting diode
  • Cst storage capacitor
  • C1 voltage regulator capacitor
  • N1 the first node; N2, the first node; N3, the third node;
  • GATE gate signal terminal; DATA, data signal terminal; RESET1, first reset signal terminal; RESET2, second reset signal terminal; INIT, initialization signal terminal; INIT1, first initialization signal terminal; INIT2, second initialization signal terminal; EM, control signal terminal; VDD, first power signal terminal; VSS, second power signal terminal; VDC, constant voltage signal source;
  • Light-emitting device 31. Auxiliary conductive structure; 32. Horizontal connection structure; 331. First light-emitting access structure; 332, Second light-emitting access structure; 351, the first connection structure; 352, the second connection structure; 353, the third connection structure.
  • Embodiments of the present disclosure may be described with reference to plan views and/or cross-sectional views with the aid of idealized schematic illustrations of the present disclosure. Accordingly, example illustrations may be modified according to manufacturing techniques and/or tolerances.
  • Embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of configurations formed based on manufacturing processes.
  • the regions illustrated in the figures have schematic properties and the shapes of regions illustrated in the figures are illustrative of the specific shapes of regions of elements and are not intended to be limiting.
  • Transistor may specifically be “Thin Film Transistor (TFT, Thin Film Transistor)", which refers to at least three terminals including a gate, a drain, and a source, and an active source connected between the source and the drain.
  • TFT Thin Film Transistor
  • the drain and the source can be insulated and the current cannot flow (that is, the transistor is turned off), and the current can be transferred from the source to the source. Flow through the active region to the drain (ie the transistor is turned on).
  • the “drain and source of the transistor” are distinguished by the current flow, so for the transistor device itself, there is no clear source and drain when there is no signal; therefore, in the embodiments of the present disclosure, the first electrode is used , the second electrode represents the source and drain electrodes of the transistor, but the first electrode and the second electrode do not necessarily correspond to the source electrode and the drain electrode.
  • Signal terminal refers to a structure in the pixel circuit that is connected to other external signal sources to provide corresponding signals. Therefore, the signal terminal is not necessarily a “terminal” or “connection terminal”, but can include all structures connected to the corresponding signal source.
  • the signal terminal can be integrated with the corresponding signal line, or the signal line can be The part in the pixel circuit is the signal terminal.
  • the signal terminal and the structure connected to it can also be integrated. For example, if the signal terminal (such as the gate signal terminal) provides the gate signal for the transistor, the part of the signal terminal that overlaps with the active area of the transistor can be simultaneously Also the gate of the transistor.
  • Signal source refers to any “source” capable of providing the desired signal, which may be the above "signal terminal”.
  • Tro structures are connected means that the two structures are directly connected to each other, or indirectly connected through other conductive structures; however, in the embodiments of the present disclosure, the structures indirectly connected through non-essentially conductive devices such as transistors are not regarded as connected to each other.
  • Node refers to all structures in the pixel circuit that can be regarded as a whole electrically; for example, the interconnected electrodes and the connection structure between electrodes are all a “node", but the first and second poles of a transistor If they are not connected to each other, they are different nodes.
  • a “turn-on signal” refers to a signal that, when applied to the gate of a transistor, causes the transistor to turn on; for example, for a P-type transistor, the turn-on signal is a low-level signal, while for an N-type transistor, the turn-on signal is a high level signal.
  • a “turn-off signal” refers to a signal that, when applied to the gate of a transistor, causes the transistor to turn off; for example, for a P-type transistor, the turn-off signal is a high-level signal, while for an N-type transistor, the turn-off signal is a low level signal.
  • Multiple structures "arranged on the same layer” means that multiple structures are formed from the same material layer, so they are in the same layer in a stacking relationship, but it does not mean that the distance between them and the substrate is equal, nor does it mean that they are in the same layer with the substrate.
  • the other layer structures between the substrates are identical.
  • Patterning process refers to the step of forming a structure with a specific pattern, which can be a photolithography process.
  • the photolithography process includes the steps of forming a material layer, coating photoresist, exposing, developing, etching, and stripping photoresist.
  • the patterning process can also be an imprinting process, an inkjet printing process, and other processes.
  • each sub-pixel of an organic light-emitting diode (OLED) display substrate includes a pixel circuit including an organic light-emitting diode for emitting light, ie, the organic light-emitting diode emits light required by each sub-pixel.
  • the structure of a feasible pixel circuit can be referred to FIG. 1, wherein the driving transistor TD controls the current flowing through it according to the voltage of its own gate, and this current is also the driving current Ioled of the organic light emitting diode OLED to emit light, so the driving transistor TD is driven according to the driving current Ioled.
  • the voltage drives the organic light emitting diode OLED to emit light.
  • the storage capacitor Cst keeps the gate of the driving transistor TD at a required driving voltage.
  • the first pole of the gate of the driving transistor TD is further connected to the second node N2 and the third node N3 through the first transistor T1 and the second transistor T2, respectively.
  • the voltages of the second node N2 and the third node N3 are usually different, for example, the voltage of the second node N2 may be lower than the voltage of the first node N1, and the voltage of the third node N3 may be higher than the voltage of the first node N1 .
  • the second node N2 will gradually “pull down” the voltage of the first node N1 due to the leakage current of the first transistor T1, and the second node N2 will gradually “pull down” the voltage of the first node N1
  • the three-node N3 will gradually “pull up” the voltage of the first node N1 due to the leakage current of the second transistor T2. Also, generally the "pull high” of the third node N3 is stronger than the "pull low" of the second node N2.
  • the simulation result of the change of some signals with time in the light-emitting stage is shown in FIG. 2. It can be seen that in the light-emitting stage, the voltage of the first node N1 will gradually increase, that is, the driving voltage will be between increases, so that the driving current Ioled flowing through the organic light emitting diode OLED decreases. Further, with reference to FIG. 3, it can be seen that in each frame (in each light-emitting stage), the light-emitting luminance of the organic light emitting diode OLED decreases.
  • an embodiment of the present disclosure provides a pixel circuit, which includes:
  • a light-emitting module configured to emit light
  • a driving module configured to drive the light-emitting module to emit light according to the driving voltage in the light-emitting stage
  • the storage module is configured to maintain the driving voltage during the light-emitting phase, and provide the driving voltage to the driving module;
  • the first pole of the first transistor T1 is connected to the position where the driving module obtains the driving voltage, and the second pole of the first transistor T1 is not directly connected to the signal source; in the light-emitting stage, the second pole of the first transistor T1 The voltage is lower than the voltage of the first electrode of the first transistor T1, and the voltage of the second electrode of the second transistor T2 is higher than the voltage of the first electrode of the first transistor T1;
  • the first electrode of the second transistor T2 is connected to the first electrode of the first transistor T1, and the structure of the connection between the second electrode of the second transistor T2 is different from that of the second electrode of the first transistor T1;
  • the voltage stabilization capacitor C1, the first pole of the voltage stabilization capacitor C1 is connected to the second electrode of the first transistor T1, and the second electrode of the voltage stabilization capacitor C1 is connected to the constant voltage signal source VDC.
  • the driving module drives the light-emitting module to emit light according to the driving voltage (eg, the gate voltage of the driving transistor TD) in the light-emitting stage, and the storage module is used to maintain and provide the driving voltage in the light-emitting stage.
  • the driving voltage eg, the gate voltage of the driving transistor TD
  • the first poles of the first transistor T1 and the second transistor T2 are both connected to the position where the driving module provides the driving voltage (such as the first node N1, that is, the gate of the driving transistor TD), and their second poles are connected differently position (such as connecting the second node N2 and the third node N3 respectively); thus, the second node N2 will change the voltage of the first node N1 due to the leakage current of the first transistor T1, and the third node N3 will be due to the second The leakage current of the transistor T2 changes the voltage of the first node N1.
  • the voltage of the second node N2 (the second pole of the first transistor T1 ) and the voltage of the third node N3 (the second pole of the second transistor T2 ) are usually higher than the voltage of the first node N1.
  • the voltage (driving voltage) is low, and the latter is higher than the voltage (driving voltage) of the first node N1, so the two “pull down” and “pull up” the voltage of the first node N1 respectively.
  • the "pull-up" capability of the third node N3 is stronger than the "pull-down" capability of the second node N2, so referring to FIG. 2 and FIG. 3 , in the light-emitting phase, the first node N1 The voltage (driving voltage) will gradually increase, resulting in changes in display brightness.
  • the second pole (the second node N2 ) of the first transistor T1 is not directly connected to the signal source, so the voltage of the first transistor T1 is also variable during the light-emitting stage.
  • a voltage stabilizing capacitor C1 is connected to the second pole (second node N2) of the first transistor T1, and the other pole (second pole) of the voltage stabilizing capacitor C1 is connected to the constant voltage signal source VDC, That is, connect any signal source that provides a constant voltage in a frame.
  • the second pole of the stabilizing capacitor C1 is a constant voltage signal, it can prevent the voltage of the first pole of the capacitor (that is, the second node N2) from changing, and the larger the capacitance value of the stabilizing capacitor C1, The blocking effect is also stronger.
  • the structure at the second node N2 may also have a certain parasitic capacitance.
  • the capacitance of the parasitic capacitance is very small, generally not exceeding 1.5fF (flying method) at the maximum, and the other pole is also It is not connected to the constant voltage signal source VDC, so the parasitic capacitance is different from the above voltage stabilization capacitor C1.
  • the signal stability of the second node N2 can be enhanced, so that the light is emitted stage to maintain a "lower” voltage to enhance its "pull-down” capability to the voltage of the first node N1, so that the "pull-down” and “pull-up” effects of the first node N1 tend to be balanced, thereby making the first node N1 more balanced.
  • the voltage (driving voltage) of the node N1 can be better kept stable during the light-emitting stage, and the change of the brightness of the light emitted by the light-emitting device 2 can be reduced, so as to improve or avoid the flickering phenomenon and improve the display quality.
  • the voltage of the second node N2 may "jump" higher due to the coupling effect with other signals (such as the signal of the first reset signal terminal RESET1), resulting in a higher initial voltage in the light-emitting stage; refer to Fig. 6 It can be seen that the larger the capacitance value of the voltage-stabilizing capacitor C1, the lower the initial voltage of the second node N2 in the light-emitting stage, which shows that by increasing the voltage-stabilizing capacitor C1, the resistance of the second node N2 against the above “jumps” can be improved.
  • the initial voltage of the second node N2 in the light-emitting stage is reduced, that is, the voltage of the second node N2 can be relatively maintained at a “lower” level during the light-emitting stage, and the voltage of the first node N1 is increased to “pull down” the first node N1.
  • the second node N2 when the second node N2 "pulls down” the voltage of the first node N1, its own voltage must also be “pulled up”, but it can be seen from FIG. 6 that the larger the capacitance value of the voltage stabilization capacitor C1 , the smaller the “slope” of the line corresponding to the voltage of the second node N2 is, that is, the degree to which the voltage of the second node N2 is “pulled up” is smaller, which shows that by increasing the voltage stabilization capacitor C1, the second node can also be The rate at which the voltage of N2 is “pulled up” is reduced, which further enhances its ability to "pull down” the voltage of the first node N1, making the voltage change of the first node N1 smaller, and further improving the display quality.
  • the pixel circuit further includes:
  • the third transistor T3, the first electrode of the third transistor T3 is connected to the second electrode of the first transistor T1, and the gate of the third transistor T3 is connected to the gate of the first transistor T1.
  • the above-mentioned second node N2 may be a node between the first transistor T1 and the third transistor T3, and the gates of the first transistor T1 and the third transistor T3 are connected to each other, so that the two constitute one "Dual gate transistor", that is, the second node N2 may be an intermediate node of the dual gate transistor.
  • the intermediate node of the dual-gate transistor is usually not directly connected to other signal sources, so its ability to maintain its own voltage is weak, and it is more suitable to use the voltage stabilizing capacitor C1 of the embodiment of the present disclosure.
  • the pixel circuit further includes:
  • the fourth transistor T4 the first electrode of the fourth transistor T4 is connected to the second electrode of the second transistor T2, and the gate of the fourth transistor T4 is connected to the gate of the second transistor T2.
  • the above third node N3 may be a node between the second transistor T2 and the fourth transistor T4, and the gates of the second transistor T2 and the fourth transistor T4 are connected to each other, so that the two constitute one "Dual-gate transistor", that is, the third node N3 may be an intermediate node of the dual-gate transistor.
  • the light emitting module includes a light emitting device 2;
  • the driving module includes a driving transistor TD, and the driving transistor TD is configured to drive the light-emitting device 2 to emit light according to the voltage of its gate;
  • the storage module includes a storage capacitor Cst, the first electrode of which is connected to the gate of the driving transistor TD, and the storage capacitor Cst is configured to maintain the driving voltage at the first electrode during the light-emitting phase and provide the driving voltage to the driving module.
  • the light emitting device 2 is an organic light emitting diode OLED.
  • the above driving module may include a driving transistor TD
  • the storage module may include a storage capacitor Cst
  • the light emitting device 2 may be an organic light emitting diode (OLED).
  • OLED organic light emitting diode
  • the light emitting device 2 is an organic light emitting diode OLED as an example for description. Of course, other forms of the light emitting device 2 are also feasible.
  • the pixel circuit includes a first reset module and a write module
  • the first reset module is configured to reset the voltage of the gate of the driving transistor TD according to the signals of the initialization signal terminal INIT and the first reset signal terminal RESET1; the first reset module includes:
  • the third transistor T3, the first pole of the third transistor T3 is connected to the second pole of the first transistor T1, the second pole of the third transistor T3 is connected to the initialization signal terminal INIT, and the gate of the third transistor T3 is connected to the first transistor T1 the gate and the first reset signal terminal RESET1;
  • the writing module is configured to write a driving voltage to the first pole of the storage capacitor Cst according to the signals of the gate signal terminal GATE and the data signal terminal DATA; the writing module includes:
  • the fourth transistor T4 the first electrode of the fourth transistor T4 is connected to the second electrode of the second transistor T2, the second electrode of the fourth transistor T4 is connected to the second electrode of the driving transistor TD, and the gate of the fourth transistor T4 is connected to the second electrode of the second transistor T4. the gate of the transistor T2 and the gate signal terminal GATE;
  • the fifth transistor T5 the first pole of the fifth transistor T5 is connected to the first pole of the driving transistor TD, the second pole of the fifth transistor T5 is connected to the data signal terminal DATA, and the gate of the fifth transistor T5 is connected to the gate signal terminal GATE;
  • the sixth transistor T6 the first pole of the sixth transistor T6 is connected to the first power supply signal terminal VDD, the second pole of the sixth transistor T6 is connected to the first pole of the driving transistor TD, and the gate of the sixth transistor T6 is connected to the control signal terminal EM ;
  • the driving transistor TD and the light-emitting device 2 are connected in series between the first power supply signal terminal VDD and the second power supply signal terminal VSS;
  • the second pole of the storage capacitor Cst is connected to the first power signal terminal VDD;
  • the second pole of the light emitting device 2 is connected to the second power signal terminal VSS.
  • first power supply signal terminal VDD and second power supply signal terminal VSS are used to provide the light-emitting device 2 with an operating voltage for display.
  • the first power signal terminal VDD can provide the first power signal Vdd, or a positive voltage signal
  • the second power signal terminal VSS can provide the second power signal Vdd, or a negative voltage signal (eg, a ground signal).
  • the first electrode of the light emitting device 2 can be its positive electrode (eg, the anode of the organic light emitting diode OLED)
  • the second electrode of the light emitting device 2 can be its negative electrode (eg, the cathode electrode of the organic light emitting diode OLED).
  • the pixel circuit further includes a control module, and the control module is configured to control whether the light-emitting device 2 emits light according to the signal of the control signal terminal EM; the control module includes:
  • the seventh transistor T7 the first pole of the seventh transistor T7 is connected to the second pole of the driving transistor TD, the second pole of the seventh transistor T7 is connected to the first pole of the light emitting device 2, and the gate of the seventh transistor T7 is connected to the control signal terminal em.
  • the pixel circuit further includes a second reset module, and the second reset module is configured to reset the voltage of the first pole of the light-emitting device 2 according to the signals of the second reset signal terminal RESET2 and the initialization signal terminal INIT;
  • the second reset module includes:
  • the eighth transistor T8 the first pole of the eighth transistor T8 is connected to the first pole of the light emitting device 2, the second pole of the eighth transistor T8 is connected to the initialization signal terminal INIT, and the gate of the eighth transistor T8 is connected to the second reset signal terminal RESET2.
  • the pixel circuit may further include other modules such as a control module, a second reset module, and the like.
  • the driving transistor TD, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are all is a P-type transistor;
  • the driving transistor TD, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are all N-type transistors.
  • each of the transistors may be an N-type transistor or a P-type transistor.
  • the constant voltage signal source VDC is any one of the initialization signal terminal INIT, the first power signal terminal VDD, and the second power signal terminal VSS.
  • the constant voltage signal source VDC connected to the second pole of the stabilizing capacitor C1 may be the existing signal source in the pixel circuit, such as the initialization signal terminal INIT (stabilized as the initialization signal Vinit), The first power signal terminal VDD (stabilized as the first power signal Vdd), the second power signal terminal VSS (stabilized as the second power signal Vss), etc. will not be described in detail here.
  • an embodiment of the present disclosure provides a method for driving a pixel circuit, where the pixel circuit is any of the above-mentioned pixel circuits, and the driving method for the pixel circuit includes:
  • the memory module is kept at the driving voltage, and the driving voltage is provided to the driving module.
  • the storage module maintains the driving voltage during the light-emitting stage, and provides the driving voltage to the driving module, so as to drive the light-emitting device 2 to emit light.
  • the voltage-stabilizing capacitor C1 is added to the pixel circuit, the driving voltage in the light-emitting stage has better stability, the change of the light-emitting brightness of the light-emitting device 2 is small, the flickering phenomenon can be improved or avoided, and the Display quality.
  • the driving process (driving method) of the pixel circuit may be performed multiple times, and each driving process includes multiple stages.
  • the driving method of the pixel circuit includes:
  • a turn-on signal is provided to the first reset signal terminal RESET1, an off signal is provided to the gate signal terminal GATE, and an off signal is provided to the control signal terminal EM;
  • a turn-off signal is provided to the first reset signal terminal RESET1, a turn-on signal is provided to the gate signal terminal GATE, a turn-off signal is provided to the control signal terminal EM, and a data signal is provided to the data signal terminal DATA;
  • a turn-off signal is provided to the first reset signal terminal RESET1, a turn-off signal is provided to the gate signal terminal GATE, and a turn-on signal is provided to the control signal terminal EM.
  • the driving method of the pixel circuit includes:
  • a shutdown signal is provided to the second reset signal terminal RESET2;
  • a turn-on signal is provided to the second reset signal terminal RESET2;
  • a turn-off signal is provided to the second reset signal terminal RESET2.
  • corresponding signals may be provided to each signal terminal in the above manner to drive the pixel circuit.
  • the signal of the second reset signal terminal RESET2 and the signal of the gate signal terminal GATE are always the same, so the second reset signal terminal RESET2 of the pixel circuit and the gate signal terminal GATE can be connected to the same signal source, for example, connected to the driving chip ( Driver IC) on the same pin (Pin).
  • the following uses the driving transistor TD, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor
  • the transistor T6 , the seventh transistor T7 , and the eighth transistor T8 are all P-type transistors as an example to illustrate the driving method of the pixel circuit according to the embodiment of the present disclosure.
  • the initialization signal Vinit is continuously provided to the initialization signal terminal INIT
  • the first power signal Vdd is continuously provided to the first power signal terminal VDD
  • the second power signal terminal is continuously provided VSS provides the second power supply signal Vss; and the signal conditions provided to other signal terminals in each stage are as follows:
  • S101 reset stage a low-level signal is provided to the first reset signal terminal RESET1, a high-level signal is provided to the gate signal terminal GATE, a high-level signal is provided to the control signal terminal EM, and a second reset signal terminal RESET2 is provided high level signal.
  • the low level signal of the first reset signal terminal RESET1 turns on the first transistor T1 and the third transistor T3, so that the initialization signal Vinit is written into the first node N1 and the second node N2.
  • a high-level signal is provided to the first reset signal terminal RESET1
  • a low-level signal is provided to the gate signal terminal GATE
  • a high-level signal is provided to the control signal terminal EM
  • a data signal is provided to the data signal terminal DATA
  • a low level signal is provided to the second reset signal terminal RESET2.
  • the low level signal of the gate signal terminal GATE makes the second transistor T2, the fourth transistor T4 and the fifth transistor T5 turn on, so that the data signal Vdata of the data signal terminal DATA is written into the driving transistor TD through the fifth transistor T5 and after passing through the driving transistor TD, the voltage of the first node N1 (the first pole of the storage capacitor Cst) becomes Vdata-Vth, where Vth is the threshold voltage of the driving transistor TD.
  • the above data signal refers to the data signal corresponding to the pixel circuit, and at other times of the driving process, the data signal terminal DATA will actually acquire the data signal corresponding to other pixel circuits (because other pixel circuits may be in the writing stage), However, because the fifth transistor T5 is turned off at other times, these data signals will not be written into the pixel circuit.
  • the initialization signal Vinit of the initialization signal terminal INIT is written into the first pole of the light emitting device 2 through the eighth transistor T8 to reset the voltage at the position.
  • a high level signal is provided to the first reset signal terminal RESET1
  • a high level signal is provided to the gate signal terminal GATE
  • a low level signal is provided to the control signal terminal EM
  • a high level signal is provided to the second reset signal terminal RESET2 level signal.
  • control signal terminal EM is a low level signal, so that the sixth transistor T6 and the seventh transistor T7 are both turned on, so the current can flow from the first power supply signal terminal VDD to the second power supply signal terminal VSS, and the light-emitting device 2 can Keep glowing until the next reset phase (as in the next frame) comes.
  • the voltage (driving voltage) of the gate (first node N1) of the driving transistor TD in this stage is kept at Vdata-Vth; and the voltage of the first electrode of the driving transistor TD is the first The power supply signal Vdd, so its gate-source voltage Vgs is Vdata-Vth.
  • the second node N2 in the light-emitting phase, should theoretically maintain the initialization signal Vinit, and the voltage of the initialization signal Vinit is usually lower than the voltage Vdata-Vth of the first node N1, so the second node N2 will The leakage current of a transistor T1 "pulls down" the voltage of the first node N1; and the voltage of the third node N3 is higher than the voltage of the first node N1, so the third node N3 will be affected by the leakage current of the second transistor T2.
  • the voltage of the first node N1 is "pulled up", and, generally, the "pulled up” capability of the third node N3 is stronger than the "pulled down” capability of the second node N2, resulting in the voltage of the first node N1 in the light-emitting phase As it increases gradually, the brightness of the light emitting device 2 gradually decreases.
  • the voltage stabilization capacitor C1 is provided, the voltage of the second node N2 is more stable and can be kept at a “lower” level, so that the first node N1 has a stronger “pull-down” capability.
  • the brightness of the light-emitting device 2 is also more stable.
  • the signal of the first reset signal terminal RESET1 "jumps" from a low-level signal to a high-level signal, so that the first transistor T1 and the third transistor T3 are turned off.
  • the first reset signal terminal RESET1 is connected to the gates of the first transistor T1 and the third transistor T3, and the second node N2 is the second pole of the first transistor T1 and the first pole of the third transistor T3, so the second The distance between the node N2 and the first reset signal terminal RESET1 is usually very close; therefore, the above “jump” of the signal of the first reset signal terminal RESET1 will also increase the voltage of the second node N2 through the coupling effect, The initial voltage of the second node N2 at the beginning of the light-emitting phase is made actually higher than the voltage of the initialization signal Vinit.
  • the voltage stabilization capacitor C1 is provided in the embodiment of the present disclosure, the influence of the “jump” of the signal of the first reset signal terminal RESET1 on the voltage of the second node N2 is weakened, and the initial voltage of the second node N2 at the beginning of the light-emitting phase is weakened A lower level can enhance its "pull-down" capability to the voltage of the first node N1 and improve the display quality.
  • the following uses the driving transistor TD, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the
  • the six transistors T6, the seventh transistor T7, and the eighth transistor T8 are all N-type transistors as an example to illustrate the driving method of the pixel circuit according to the embodiment of the present disclosure.
  • the initialization signal Vinit is continuously provided to the initialization signal terminal INIT
  • the first power signal Vdd is continuously provided to the first power signal terminal VDD
  • the second power signal terminal is continuously provided VSS provides the second power supply signal Vss; and the signal conditions provided to other signal terminals in each stage are as follows:
  • S201 reset stage provide a high-level signal to the first reset signal terminal RESET1, provide a low-level signal to the gate signal terminal GATE, provide a low-level signal to the control signal terminal EM, and provide a second reset signal terminal RESET2 low level signal.
  • the high level signal of the first reset signal terminal RESET1 turns on the first transistor T1 and the third transistor T3, so that the initialization signal Vinit is written into the first node N1 and the second node N2.
  • a low-level signal is provided to the first reset signal terminal RESET1
  • a high-level signal is provided to the gate signal terminal GATE
  • a low-level signal is provided to the control signal terminal EM
  • a data signal is provided to the data signal terminal DATA
  • a high level signal is provided to the second reset signal terminal RESET2.
  • the high-level signal of the gate signal terminal GATE turns on the second transistor T2, the fourth transistor T4, and the fifth transistor T5, so that the data signal Vdata of the data signal terminal DATA is written into the driving transistor TD through the fifth transistor T5
  • the voltage of the first node N1 (the first pole of the storage capacitor Cst) becomes Vdata-Vth, where Vth is the threshold voltage of the driving transistor TD.
  • the above data signal refers to the data signal corresponding to this pixel circuit, and at other times of the driving process, the data signal terminal DATA will actually acquire the data signal corresponding to other pixel circuits (because other pixel circuits may be in the writing stage), However, because the fifth transistor T5 is turned off at other times, these data signals will not be written into the pixel circuit.
  • the initialization signal Vinit of the initialization signal terminal INIT is written into the first pole of the light emitting device 2 through the eighth transistor T8 to reset the voltage at this position.
  • a low-level signal is provided to the first reset signal terminal RESET1
  • a low-level signal is provided to the gate signal terminal GATE
  • a high-level signal is provided to the control signal terminal EM
  • a low-level signal is provided to the second reset signal terminal RESET2 level signal.
  • control signal terminal EM is a high level signal, so that the sixth transistor T6 and the seventh transistor T7 are both turned on, so the current can flow from the first power supply signal terminal VDD to the second power supply signal terminal VSS, and the light emitting device 2 can Keep glowing until the next reset phase (as in the next frame) comes.
  • the voltage (driving voltage) of the gate (first node N1) of the driving transistor TD in this stage is kept at Vdata-Vth; and the voltage of the first electrode of the driving transistor TD is the first The power supply signal Vdd, so its gate-source voltage Vgs is Vdata-Vth.
  • an embodiment of the present disclosure provides a display substrate, which includes:
  • At least some of the sub-pixels include any one of the above-mentioned pixel circuits.
  • the substrate is the basis for carrying other structures on the display substrate, which is a basically sheet-like structure composed of materials such as glass, silicon (such as monocrystalline silicon), and polymer materials (such as polyimide). It can be rigid or flexible, and the thickness can be on the order of millimeters.
  • the sub-pixel refers to the smallest structure that can be used to independently display the desired content, that is, the smallest "dot" that can be individually controlled in the display device.
  • different sub-pixels can have different colors, so that color display can be realized through light mixing of different sub-pixels: for example, a plurality of sub-pixels of different colors arranged together can form a "pixel (or pixel unit)" , that is, the light emitted by these sub-pixels is mixed together to form a visual "point", such as three sub-pixels of red, green, and blue colors to form a pixel; or, there may be no clear pixel (or pixel unit) , but through the "common" between adjacent sub-pixels to achieve color display.
  • the above components of the pixel circuit can be arranged on the substrate, and each pixel circuit corresponds to a sub-pixel, that is, the light emitted by the light-emitting device 2 in the pixel circuit is used as the light emitted by the sub-pixel.
  • the light-emitting device 2 may directly emit light of different colors, or the light-emitting devices 2 may all emit white light, and then pass through color filter films (CF) of different colors. color light.
  • CF color filter films
  • the display substrate of the embodiment of the present disclosure has stable brightness, no flicker phenomenon, and good display quality.
  • the sub-pixels can be arranged in an array on the display substrate, and signals are provided to the pixel circuits in each sub-pixel through a plurality of signal lines to control the display.
  • the signal lines may include a plurality of gate signal lines extending along a first direction (eg, row direction), a plurality of first reset signal lines extending along the first direction, and a plurality of second reset signal lines extending along the first direction a signal line, a plurality of control signal lines extending along the first direction, and a plurality of initialization signal lines extending along the first direction; each gate signal line is connected to the gate signal terminal GATE of the pixel circuit of each sub-pixel in a row, and each A reset signal line is connected to the first reset signal terminal RESET1 of the pixel circuit of each sub-pixel in a row, and each second reset signal line is connected to the second reset signal terminal RESET2 of the pixel circuit of each sub-pixel in a row (and The second reset signal line can be connected to the same signal source as the gate signal line of the corresponding sub-pixels in the same row), each control signal line is connected to the control signal terminal EM of the pixel circuit of each sub-pixel in a row, and each initialization signal line
  • the signal line may further include a plurality of data lines extending along the second direction (eg, the column direction); each data line is connected to the data signal terminal DATA of the pixel circuit of each sub-pixel in a row.
  • the signal lines may further include a first power signal line, a second power signal line, an initialization signal line, etc. These signal lines may extend in the row direction or the column direction, or may form a grid, and are respectively connected with the sub-pixels.
  • the first power signal terminal VDD, the second power signal terminal VSS, and the initialization signal terminal INIT of the pixel circuit are connected to each other.
  • the capacitance value of the stabilizing capacitor C1 is not lower than 8 fF (femto-farad), and not more than a quarter of the capacitance value of the storage capacitor Cst.
  • the capacitance value of the voltage-stabilizing capacitor C1 is too small, it will not be able to provide a sufficient voltage-stabilizing effect. After research, it is found that it should be at least 8fF, such as 8fF, 10fF, 12fF, and so on.
  • the Flicker value obtained by simulation is shown in FIG. 9 .
  • the Flicker value is a dimensionless value calculated according to the brightness-time change curve in the light-emitting stage, which is used to indicate the degree of flicker of the display. The lower the value, the smaller the degree of flicker, that is, the more stable the brightness and the better the display quality. .
  • the capacitance value of the voltage stabilizing capacitor C1 cannot be too high, otherwise the "pull-down" capability of the second node N2 will be stronger than the "pull-up” capability of the third node N3, causing the voltage of the first node N1 to be in the light-emitting stage.
  • the "reverse” change (reduction) will also lead to unstable brightness. Therefore, the capacitance value of the stabilizing capacitor C1 generally cannot exceed 1/4 of the capacitance value of the storage capacitor Cst, and can be 1/4 of the capacitance value of the storage capacitor Cst. 5 or so.
  • the first pole of the stabilizing capacitor C1 and the second pole of the first transistor T1 are disposed in the same layer and connected as a whole.
  • the structures of the pixel circuits arranged on the substrate can be arranged in different layers, and since the first pole of the stabilizing capacitor C1 needs to be connected to the second pole of the first transistor T1, referring to FIG. 10 and FIG. In one way of disclosing the embodiment, the two may be an integrated structure provided in the same layer, so as to simplify the structure and preparation method of the display substrate.
  • the first pole of the third transistor T3 when the first pole of the third transistor T3 is also connected to the first pole of the stabilizing capacitor C1, referring to FIG. 10 and FIG. 11 , the first pole of the stabilizing capacitor C1, the second pole of the first transistor T1, the third pole
  • the three first electrodes of the transistor T3 can be integrated.
  • the first pole of the stabilizing capacitor C1 is disposed in the same layer as the active region of the driving transistor TD, and the first pole of the stabilizing capacitor C1 is a conductive semiconductor material;
  • the second electrode of the first transistor T1 is disposed in the same layer as the active region of the driving transistor TD, and the second electrode of the first transistor T1 is made of conductive semiconductor material.
  • the above-mentioned integrated structure composed of the first pole of the voltage stabilizing capacitor C1 and the second pole of the first transistor T1 (and also the first pole of the third transistor T3 ) can also be It is also integrated with the active region of the first transistor T1 (it can also be integrated with the active region of the third transistor T3), that is, these structures are all semiconductor materials (such as polysilicon materials), but the first one corresponding to the voltage stabilizing capacitor C1. Parts of one pole, the second pole of the first transistor T1 and the first pole of the third transistor T3 need to be subjected to conductorization treatment to form conductors.
  • first pole of the stabilizing capacitor C1, the second pole of the first transistor T1, the first pole of the third transistor T3, the active area of the first transistor T1, the active area of the third transistor T3, etc. are respectively set It is also feasible to place them in different layers and connect them through structures such as vias in the insulating layer.
  • the first pole of the stabilizing capacitor C1 includes: a connection part 11 connected between the first pole of the third transistor T3 and the second pole of the first transistor T1; an additional part connected to the connection part 11 12.
  • the first pole of the third transistor T3 and the second pole of the first transistor T1 should be connected to form a “dual gate transistor”, so referring to FIGS. 10 and 11 , the first pole of the third transistor T3 and the second pole of the The connection structure (connection part 11 ) between the second electrodes of the transistor T1 serves as the first electrode of the voltage stabilization capacitor C1, that is, the first electrode of the third transistor T3 and the second electrode of the first transistor T1 pass through the voltage stabilization capacitor C1.
  • the first pole is connected.
  • the area of the structure (connecting part 11 ) in which the first electrode of the third transistor T3 is directly connected to the second electrode of the first transistor T1 is relatively small, so if only the connecting part 11 is used as a stabilizing capacitor
  • the first pole of C1 the capacitance value of the voltage stabilization capacitor C1 is small, and the voltage stabilization effect is not good enough.
  • the first pole of the stabilizing capacitor C1 may include an additional part (additional part 12 ) “extended” from the connection part 11 in addition to the connecting part 11 , although the additional part 12 does not directly play a connection role , but the capacitance value of the voltage regulator capacitor C1 can be increased.
  • the second pole of the stabilizing capacitor C1 and the initialization signal terminal INIT are disposed in the same layer and connected as a whole.
  • the second pole of the stabilizing capacitor C1 should be overlapped and insulated from the first pole of the stabilizing capacitor C1, that is, the first pole of the stabilizing capacitor C1 and the second pole of the stabilizing capacitor C1 are on the positive side of the substrate.
  • the projections should overlap, and the first pole of the stabilizing capacitor C1 and the second pole of the stabilizing capacitor C1 should be separated by at least one insulating layer.
  • a structure arranged in the same layer as the initialization signal terminal INIT can be used as the second pole of the voltage stabilization capacitor C1 , and the voltage stabilization capacitor The second pole of C1 is directly connected to the initialization signal terminal INIT.
  • the second pole of the stabilizing capacitor C1 may be located in the initialization signal terminal INIT, that is, a part of the initialization signal terminal INIT is also the second pole of the stabilizing capacitor C1;
  • the initialization signal terminal INIT is made to cover the position of the first pole of the voltage-stabilizing capacitor C1.
  • the display substrate sequentially includes:
  • GI gate insulating layer
  • the layer where the initialization signal terminal INIT is located (such as the GATE2 layer) is relatively close to the layer (POLY) where the active region of the transistor is located (there are fewer insulating layers in between), so these two layers are used as the two poles of the voltage stabilizing capacitor C1 respectively.
  • the distance between the two poles of the voltage-stabilizing capacitor C1 can be reduced to increase the capacitance value of the voltage-stabilizing capacitor C1; at the same time, the second pole of the voltage-stabilizing capacitor C1 is directly integrated with the initialization signal terminal INIT set on the same layer, so it can be It is very convenient to use the initialization signal terminal INIT as the constant voltage signal source VDC.
  • the layers (such as SD1 layer) that are farther from the substrate than the initialization signal terminal INIT are farther from the layer where the active area of the transistor is located. If they are used as the second pole of the voltage stabilization capacitor C1, it is easy to cause the capacitance of the voltage stabilization capacitor C1.
  • the layer where the gate signal end GATE is located (such as the GATE1 layer) is relatively close to the layer where the active area of the transistor is located, the signal of the gate signal end GATE changes, so if you want to use the layer where the gate signal end GATE is located As the second pole of the voltage-stabilizing capacitor C1, the structure of 1 also needs to introduce a constant-voltage signal into the structure separately from other layers, which is rather troublesome.
  • the initialization signal terminal INIT includes a first initialization signal terminal INIT1 and a second initialization signal terminal INIT2 set at the same layer, and the first initialization signal terminal INIT1 and the second initialization signal terminal INIT2 are arranged in parallel and spaced apart;
  • the second pole of the eighth transistor T8 is connected to the first initialization signal terminal INIT1;
  • the second electrode of the third transistor T3 is connected to the second initialization signal terminal INIT2.
  • the initialization signal terminal INIT can be divided into two structures (the first initialization signal terminal INIT1 and the second initialization signal terminal INIT2 ), which are arranged in the same layer but are independent of each other, which are respectively connected to the second pole and the second pole of the third transistor T3. Eight second poles of the transistors T8, so that the signals of the second pole of the third transistor T3 and the second pole of the eighth transistor T8 can be the same or different according to needs, so as to achieve more complex control.
  • the initialization signal terminal INIT connecting the second pole of the third transistor T3 and the second pole of the eighth transistor T8 is an integrated structure (ie, the first initialization signal terminal INIT1 and the second initialization signal terminal INIT2 are not distinguished), it is also feasible of.
  • the first pole of the stabilizing capacitor C1 extends along the first direction
  • the data signal terminal DATA and/or the first power signal terminal VDD extend along the second direction; the first direction crosses the second direction.
  • the first pole of the voltage stabilizing capacitor C1 may extend along the first direction as a whole (laterally in FIG. 11 ); and referring to FIG. 15 , the data signal terminal DATA and the first power signal terminal VDD may cross the first direction along the (It may further be vertical) extending in the second direction (vertical direction in FIG. 15 ); therefore, referring to FIG. 10 , the first pole of the voltage stabilizing capacitor C1 may overlap with the data signal terminal DATA and the first power supply signal terminal VDD (of course mutually insulation).
  • the first reset signal terminal RESET1 extends along the first direction
  • the first reset signal terminal RESET1 of at least part of the pixel circuit is multiplexed into the second reset signal terminal RESET2 of the pixel circuit adjacent to the pixel circuit along the second direction; the first direction and the second direction intersect.
  • the difference between the signal of the first reset signal terminal RESET1 and the signal of the second reset signal terminal RESET2 is one cycle. Therefore, in the adjacent pixel circuits in the second direction (as shown in the vertical direction in FIG. 12 ), the signal of the second reset signal terminal RESET2 of the pixel circuit of the previous row is the same as the signal of the first reset signal terminal RESET1 of the pixel circuit of the current row. The signal is the same.
  • the first reset signal terminal RESET1 of each pixel circuit may extend along the first direction (the horizontal direction in FIG. 12 ), and at the same time, its multiplexing is along the second direction (as shown in FIG. 12) the second reset signal terminal RESET2 of the adjacent pixel circuits; that is, referring to FIG. 10, the eighth transistor T8 of the pixel circuit in the previous row can be located in a rectangular area with other structures of the pixel circuit in the row, so as to use
  • the first reset signal terminal RESET1 of the pixel circuit of the current row ie the second reset signal terminal RESET2 of the pixel circuit of the previous row
  • the second pole of the storage capacitor Cst includes a horizontal connection structure 32 extending along the first direction; at least part of the horizontal connection structures 32 of adjacent pixel circuits along the first direction are connected to each other;
  • the first power signal terminal VDD extends along the second direction; the first direction intersects the second direction.
  • the second pole of the storage capacitor Cst has a structure extending along the first direction (the horizontal direction in FIG. 13 ) in addition to the structure overlapping the first pole of the storage capacitor Cst (a rectangle with a gap in FIG. 13 ).
  • the horizontal connection structure 32 so that the plurality of storage capacitors Cst in the same row can be connected together through the horizontal connection structure 32 .
  • the first power signal terminal VDD extends along the second direction (vertical direction in FIG. 15 ) crossing the first direction, and the first power signal terminal VDD must be connected to the storage capacitor Cst in the respective pixel circuit .
  • first power signal terminals VDD of the multiple columns are actually electrically connected to the second poles of the storage capacitors Cst in the same row, that is, electrically, the structure for providing the first power signal Vdd forms a "grid-like", Thereby reducing its supply resistance.
  • the display substrate further includes:
  • the auxiliary conductive structure 31 is arranged overlapping the first power signal terminal VDD; at least one insulating layer is provided between the auxiliary conductive structure 31 and the first power signal terminal VDD, and the auxiliary conductive structure 31 is connected to the first power supply signal terminal VDD through the via hole in the insulating layer.
  • the power signal terminal VDD is connected.
  • the display substrate may further include an auxiliary conductive structure 31 overlapping with the first power signal terminal VDD (eg, extending along the second direction), and the auxiliary conductive structure 31 is connected to the first power signal terminal VDD, In order to further reduce the power supply resistance of the first power supply signal Vdd.
  • the display substrate sequentially includes:
  • the semiconductor layer is composed of a semiconductor material, for example, a polysilicon material (poly-Si).
  • the semiconductor layer includes: a first electrode, a second electrode, and an active region of the driving transistor TD, a first electrode, a second electrode, and an active region of the first transistor T1, and a first electrode, a second electrode, and an active region of the second transistor T2. Active region, the first electrode, the second electrode, and the active region of the third transistor T3, the first electrode, the second electrode, and the active region of the fourth transistor T4, the first electrode, the second electrode of the fifth transistor T5 , the active area, the first pole, the second pole, the active area of the sixth transistor T6, the first pole, the second pole, and the active area of the seventh transistor T7, the first pole, the second pole of the eighth transistor T8 pole, active area, and the first pole of the voltage-stabilizing capacitor C1.
  • the first electrode of the voltage-stabilizing capacitor C1 is connected to the second electrode of the first transistor T1 as a whole, and both are made of conductive semiconductor materials.
  • the active region, the first electrode, and the second electrode of each transistor can be located in the semiconductor layer;
  • the second pole is connected as a whole and is also located in the semiconductor layer.
  • the electrodes of all transistors and the first electrode of the voltage-stabilizing capacitor C1 are made of conductive semiconductor materials.
  • the gate insulating layer is made of insulating material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., and is used to separate the active region of each transistor from the gate.
  • each transistor is a "bottom-gate transistor".
  • the gate insulating layer may include: a via for connecting the first power signal terminal VDD and the first pole of the sixth transistor T1, a via for connecting the data signal terminal DATA and the second pole of the fifth transistor T5 A via hole for connecting the first light emitting access structure 331 and the second pole of the seventh transistor T7, a via hole for connecting the first connection structure 351 and the second pole of the eighth transistor T8, for connecting The second connection structure 352 and the via hole of the second pole of the third transistor T3 are used to connect the third connection structure 353 and the via hole of the first pole of the first transistor T1 (details will be described later).
  • the first gate layer is made of a conductive material, for example, a metal material.
  • the first gate layer includes: the gate of the driving transistor TD, the gate of the first transistor T1, the gate of the second transistor T2, the gate of the third transistor T3, the gate of the fourth transistor T4, the gate of the fifth transistor T5 , the gate of the sixth transistor T6, the gate of the seventh transistor T7, the gate of the eighth transistor T8, the first reset signal terminal RESET1, the second reset signal terminal RESET2, the control signal terminal EM, the storage The first pole of the capacitor Cst.
  • the gates of all transistors, and the signal terminals for providing signals to the gates may be located in the first gate layer.
  • the first pole of the storage capacitor Cst is also located in the first gate layer because it must drive the gate of the transistor TD (for example, an integrated structure).
  • the first reset signal terminal RESET1 of the pixel circuit in this row can also be multiplexed into the second reset signal terminal RESET2 of the pixel circuit in the previous row, that is, each pixel circuit actually has only one reset signal terminal structure.
  • the first interlayer insulating layer (ILD1) The first interlayer insulating layer (ILD1).
  • the first interlayer insulating layer is made of insulating material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., and is used to separate the structure of the first gate layer from the structure of the subsequent second gate layer.
  • the first interlayer insulating layer may include: a via for connecting the first power signal terminal VDD and the first pole of the sixth transistor T1, for connecting the data signal terminal DATA and the first terminal for connecting the fifth transistor T5 A via hole for two electrodes, a via hole for connecting the first light emitting access structure 331 and a second electrode of the seventh transistor T7, a via hole for connecting the first connection structure 351 and a second electrode of the eighth transistor T8, The via hole for connecting the second connection structure 352 and the second pole of the third transistor T3, the via hole for connecting the third connection structure 353 and the gate of the driving transistor TD, for connecting the third connection structure 353 and the The via hole of the first pole of the first transistor T1 (detailed description later).
  • the second gate layer is made of a conductive material, for example, a metal material.
  • the second gate layer includes: the initialization signal terminal INIT, the second pole of the voltage stabilization capacitor C1, and the second pole of the storage capacitor Cst.
  • the second pole of the stabilizing capacitor C1 is connected to the initialization signal terminal INIT as a whole.
  • the initialization signal terminal INIT, the second pole of the stabilizing capacitor C1, and the second pole of the storage capacitor Cst can be set in the second gate layer, and the second pole of the stabilizing capacitor C1 is connected to the initialization signal terminal INIT. as one.
  • the initialization signal terminal INIT can also be divided into the first initialization signal terminal INIT1 and the second initialization signal terminal INIT2, and the second pole of the voltage stabilization capacitor C1 can be integrated with one of them.
  • the second initialization signal terminal INIT2 has an integrated structure.
  • the second pole of the storage capacitor Cst may also include the above horizontal connection structure 32 .
  • the part of the second pole of the storage capacitor Cst other than the horizontal connection structure 32 may be a rectangle with a gap, and the gap is to allow the first pole of the storage capacitor Cst located below it to interact with the first pole of the storage capacitor Cst.
  • the first pole of the transistor T1 is connected (details will be described later).
  • the second gate layer further includes: a shielding structure 34, the shielding structure 34 is connected to the first power supply signal terminal VDD through a via hole in the second interlayer insulating layer, and the shielding structure 34 is connected to the first power supply signal terminal VDD of the first transistor T1.
  • One pole and the second pole of the fifth transistor T5 are overlapped and insulated.
  • a shielding structure 34 may also be provided in the second gate layer; referring to FIGS. 10 and 15 , the shielding structure 34 is connected to the first power signal terminal VDD (described in detail later), and is connected to the first power supply signal terminal VDD of the first transistor T1 .
  • One pole and the second pole of the fifth transistor T5 are overlapped, so as to shield the influence of other signals (eg, the signal of the data signal terminal DATA) on the two transistors.
  • the second interlayer insulating layer is made of insulating material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., and is used to separate the structure of the second gate layer from the structure of the subsequent first source and drain layers.
  • the second interlayer insulating layer may include: a via hole for connecting the first power signal terminal VDD and the second pole of the storage capacitor Cst, and a via hole for connecting the first power signal terminal VDD and the first power source signal terminal VDD of the sixth transistor T1
  • the via hole of one pole is used to connect the data signal terminal DATA and the via hole of the second pole of the fifth transistor T5, and the via hole used to connect the first light emitting access structure 331 and the second pole of the seventh transistor T7, using A via for connecting the first connection structure 351 and the second pole of the eighth transistor T8, a via for connecting the first connection structure 351 and the initialization signal terminal INIT, for connecting the second connection structure 352 and the third transistor T3
  • the via hole of the second pole is used to connect the second connection structure 352 and the via hole of the initialization signal terminal INIT
  • the via hole used to connect the third connection structure 353 and the gate of the driving transistor TD is used to connect the third connection structure 353.
  • the first source-drain layer is made of conductive material, such as metal material.
  • the first source-drain layer includes: a first power signal terminal VDD, a data signal terminal DATA, and a first light-emitting access structure 331 .
  • the first power signal terminal VDD is connected to the second pole of the storage capacitor Cst through the via hole in the second interlayer insulating layer, and is connected to the second pole of the storage capacitor Cst through the via hole in the gate insulating layer, the first interlayer insulating layer and the second interlayer insulating layer
  • the hole is connected to the first pole of the sixth transistor T1;
  • the data signal terminal DATA is connected to the second pole of the fifth transistor T5 through the gate insulating layer, the first interlayer insulating layer, and the via hole in the second interlayer insulating layer, and the first light-emitting
  • the access structure 331 is connected to the second electrode of the seventh transistor T7 through the gate insulating layer, the first interlayer insulating layer, and the via hole in the second interlayer insulating layer.
  • the first power signal terminal VDD and the data signal terminal DATA can be set in the first source-drain layer, the first power signal terminal VDD is connected to the second pole of the storage capacitor Cst, and the data signal terminal DATA is connected to the fifth transistor The second pole of T5 to form the above pixel circuit.
  • the second pole of the seven transistor T7 needs to be connected to the first pole of the light-emitting device 2, but there are many layers between the two, and the distance is large. Therefore, referring to FIG. 15, the first source and drain layer can also include and the seventh transistor
  • the first light-emitting access structure 331 to which the second pole of T7 is connected in order to realize the second pole of the seventh transistor T7 through multiple structures, the connection of the first pole of the light-emitting device 2 needs to be connected (described in detail later) to avoid disconnection. Wire.
  • the first power signal terminal VDD is also connected to it through the via hole in the second interlayer insulating layer.
  • the first source-drain layer further includes:
  • the first connection structure 351 is connected to the second pole of the eighth transistor T8 through the gate insulating layer, the first interlayer insulating layer, and the via hole in the second interlayer insulating layer, and is connected through the second interlayer insulating layer.
  • the vias in the layer connect the initialization signal terminal INIT;
  • the second connection structure 352 is connected to the second electrode of the third transistor T3 through the gate insulating layer, the first interlayer insulating layer, and the via hole in the second interlayer insulating layer, and is insulated by the second interlayer
  • the vias in the layer connect the initialization signal terminal INIT;
  • the third connection structure 353 is connected to the gate of the driving transistor TD through the first interlayer insulating layer and the via hole in the second interlayer insulating layer, and is connected to the gate of the driving transistor TD through the gate insulating layer, the first interlayer insulating layer, The via hole in the second interlayer insulating layer connects the first electrode of the first transistor T1.
  • a plurality of corresponding connection structures may also be provided in the first source-drain layer.
  • connection structure may specifically include a first connection structure 351 connecting the second pole of the eighth transistor T8 with the initialization signal terminal INIT (eg, the first initialization signal terminal INIT1 ); connecting the second pole of the third transistor T3 with the initialization signal terminal A second connection structure 352 connecting the terminal INIT (eg, the second initialization signal terminal INIT2); and, connecting the driving transistor TD (ie, the first pole of the storage capacitor Cst) with the first pole of the first transistor T1 (eg, through the above storage The third connection structure 353 of the gap in the capacitor Cst) and so on.
  • first connection structure 351 connecting the second pole of the eighth transistor T8 with the initialization signal terminal INIT (eg, the first initialization signal terminal INIT1 ); connecting the second pole of the third transistor T3 with the initialization signal terminal
  • a second connection structure 352 connecting the terminal INIT (eg, the second initialization signal terminal INIT2); and, connecting the driving transistor TD (ie, the first pole of the storage capacitor Cst) with
  • connection structures are provided in other layers, or if the forms of the electrodes of the transistors and capacitors are changed so that different connection structures are required.
  • the first planarization layer (PLN1).
  • the first planarization layer is made of an organic insulating material and is used to eliminate the level difference of the underlying structure.
  • the first planarization layer may include via holes for connecting the first light emitting access structure 331 and the second light emitting access structure 332 , and a via hole for connecting the first power signal terminal VDD and the auxiliary conductive structure 31 Vias (described in detail later).
  • the passivation layer is made of insulating material, for example, made of silicon nitride, silicon oxide, silicon oxynitride, etc., so as to avoid direct contact between the subsequently formed structure and the first planarization layer.
  • the passivation layer and the first planarization layer are two continuous insulating layers (or considered as two sub-layers of one insulating layer), so referring to FIG. 20 , the via holes in the passivation layer are connected to the first planarization layer.
  • the vias in are exactly the same.
  • the via hole in the first planarization layer may also include the via hole in the passivation layer, which will not be described in detail here.
  • the second source and drain layers are made of conductive material, such as metal material.
  • the second source-drain layer includes: an auxiliary conductive structure 31 and a second light-emitting access structure 332 .
  • the auxiliary conductive structure 31 overlaps with the first power signal terminal VDD, and is connected to the first power signal terminal VDD through the via hole in the first planarization layer; and the second light emitting access structure 332 passes through the first planarization Vias in the layers connect the first light emitting access structures 331 .
  • the above auxiliary conductive structure 31 for reducing the power supply resistance of the first power supply signal Vdd may be located in the second source-drain layer and connected to the first power supply signal terminal VDD.
  • the second source-drain layer may further include a second light-emitting access structure 332 connected to the first light-emitting access structure 331, so that the first pole of the subsequent light-emitting device 2 can pass through the second light-emitting access structure 332, the first light-emitting access structure 332, and the first light-emitting access structure 332.
  • the light emitting access structure 331 is connected to the second pole of the seventh transistor T7.
  • the second planarization layer is made of an organic insulating material and is used to eliminate the level difference of the underlying structure.
  • the second planarization layer may include a via hole for connecting the second light emitting access structure 332 and the first pole of the light emitting device 2 (described in detail later).
  • the first pole of the light emitting device 2 is connected to the second light emitting access structure 332 through the via hole in the second planarization layer.
  • the first electrode of the light emitting device 2 can be disposed on the second planarization layer, and is connected to the second electrode of the seventh transistor T7 through the second light emitting access structure 332 and the first light emitting access structure 331 above.
  • the first electrode of the light emitting device 2 may be an anode (Anode) of an organic light emitting diode OLED, which may be formed of a metal oxide conductive material such as indium tin oxide (ITO).
  • Anode anode of an organic light emitting diode OLED
  • ITO indium tin oxide
  • the display substrate in the direction away from the substrate, may further include the following structures in sequence:
  • the pixel-defining layer is composed of an organic insulating material and serves to define the range of the light-emitting device 2 (eg, an organic light-emitting diode OLED) through openings therein.
  • the light-emitting device 2 eg, an organic light-emitting diode OLED
  • the light-emitting layer is the light-emitting layer actually used in the light-emitting device 2 .
  • the light-emitting layer of the light-emitting device 2 may be the light-emitting layer of the organic light-emitting diode OLED.
  • the light-emitting layer of the organic light-emitting diode OLED is composed of organic materials, which at least include an organic light-emitting layer (EML), and may also include an electron injection layer (EIL), an electron transport layer (ETL), a hole injection layer (HIL), and a hole transport layer. layer (HTL) and other auxiliary layers provided in layers.
  • the light emitting layer of the organic light emitting diode OLED may be a whole-layer structure, which is in contact with the anode of the organic light emitting diode OLED at the opening of the pixel defining layer, thereby forming the organic light emitting diode OLED.
  • the second electrode of the light emitting device 2 may be the cathode of the organic light emitting diode OLED, and the cathode of the organic light emitting diode OLED may be composed of a metal conductive material such as aluminum.
  • the cathode of the organic light emitting diode OLED can be a whole-layer structure, so it is also the second power signal terminal VSS at the same time.
  • the encapsulation layer can be a stacked structure in which organic layers and inorganic layers are alternated, and is used to encapsulate other structures therein, so as to avoid aging of other structures (especially the light-emitting layer) in contact with water and oxygen in the environment.
  • the complete film layers in the above layer structures can be formed by solution process, deposition process, etc.; and if the above layer structures have structures with specific shapes, they can be formed by a patterning process.
  • each specific structure may be different; for another example, the gate of each transistor may also be located in a layer closer to the substrate than its active region, that is, each transistor may not be the above “bottom gate transistor”. ", but "top-gate transistor” etc.
  • a display device which includes:
  • the above display substrates can be combined with other devices (eg, cell cover plates, flexible circuit boards, driving chips, power supply components, etc.) to form a display device with a display function.
  • other devices eg, cell cover plates, flexible circuit boards, driving chips, power supply components, etc.
  • the display device is an organic light emitting diode (OLED) display device.
  • OLED organic light emitting diode
  • the display device Since the above display substrate is used, the display device according to the embodiment of the present disclosure has stable brightness, no flicker phenomenon, and good display quality.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of El Displays (AREA)

Abstract

一种像素电路及其驱动方法、显示基板、显示装置，其中，像素电路包括：发光模块，配置为进行发光；驱动模块，配置为在发光阶段根据驱动电压驱动发光模块发光；存储模块，存储模块配置为在发光阶段保持驱动电压，并向驱动模块提供驱动电压；第一晶体管（T1），第一晶体管（T1）的第一极连接驱动模块获取驱动电压的位置，第一晶体管（T1）的第二极不与信号源直接连接；第二晶体管（T2），第二晶体管（T2）的第一极连接第一晶体管（T1）的第一极，第二晶体管（T2）的第二极连接的结构与第一晶体管（T1）的第二极连接的结构不同；在发光阶段，第一晶体管（T1）的第二极的电压低于第一晶体管（T1）的第一极的电压，第二晶体管（T2）的第二极的电压高于第一晶体管（T1）的第一极的电压；稳压电容（C1），稳压电容（C1）的第一极连接第一晶体管（T1）的第二极，稳压电容（C1）的第二极连接定压信号源（VDC）。

Description

像素电路及其驱动方法、显示基板、显示装置 技术领域
本公开实施例涉及像素电路技术领域，特别涉及一种像素电路及其驱动方法、显示基板、显示装置。
背景技术
在有机发光二极管(OLED)显示基板中，在发光阶段，通过向驱动晶体管的栅极施加一定的驱动电压，使有机发光二极管发出相应亮度的，以进行显示。但是，在显示阶段，驱动晶体管的栅极的电压可能因为漏电流的存在而变化，从而引起有机发光二极管的亮度变化，导致闪烁(Flicker)现象，影响显示质量。
发明内容
本公开实施例提供一种像素电路及其驱动方法、显示基板、显示装置。
第一方面，本公开实施例提供一种像素电路，其包括：
发光模块，配置为进行发光；
驱动模块，配置为在发光阶段根据驱动电压驱动所述发光模块发光；
存储模块，所述存储模块配置为在所述发光阶段保持所述驱动电压，并向所述驱动模块提供所述驱动电压；
第一晶体管，所述第一晶体管的第一极连接所述驱动模块获取所述驱动电压的位置，所述第一晶体管的第二极不与信号源直接连接；
第二晶体管，所述第二晶体管的第一极连接所述第一晶体管的第一极，所述第二晶体管的第二极连接的结构与所述第一晶体管的第二极连接的结构不同；在所述发光阶段，所述第一晶体管的第二极的电 压低于所述第一晶体管的第一极的电压，所述第二晶体管的第二极的电压高于所述第一晶体管的第一极的电压；
稳压电容，所述稳压电容的第一极连接所述第一晶体管的第二极，所述稳压电容的第二极连接定压信号源。
在一些实施例中，所述像素电路还包括：
第三晶体管，所述第三晶体管的第一极连接所述第一晶体管的第二极，所述第三晶体管的栅极连接所述第一晶体管的栅极；
第四晶体管，所述第四晶体管的第一极连接所述第二晶体管的第二极，所述第四晶体管的栅极连接所述第二晶体管的栅极；
所述发光模块包括发光器件；
所述驱动模块包括驱动晶体管，所述驱动晶体管配置为根据其栅极的电压驱动所述发光器件发光；
所述存储模块包括存储电容，所述存储电容的第一极连接所述驱动晶体管的栅极，所述存储电容配置为在所述发光阶段使其第一极保持所述驱动电压，并向所述驱动模块提供所述驱动电压。
在一些实施例中，所述像素电路包括第一重置模块和写入模块；
所述第一重置模块配置为根据初始化信号端和第一重置信号端的信号重置所述驱动晶体管的栅极的电压；所述第一重置模块包括：
所述第一晶体管；
所述第三晶体管，所述第三晶体管的第一极连接所述第一晶体管的第二极，所述第三晶体管的第二极连接所述初始化信号端，所述第三晶体管的栅极连接所述第一晶体管的栅极以及所述第一重置信号端；
所述写入模块配置为根据栅信号端和数据信号端的信号向所述存储电容的第一极写入所述驱动电压；所述写入模块包括：
所述第二晶体管；
所述第四晶体管，所述第四晶体管的第一极连接所述第二晶体管 的第二极，所述第四晶体管的第二极连接所述驱动晶体管的第二极，所述第四晶体管的栅极连接所述第二晶体管的栅极以及所述栅信号端；
第五晶体管，所述第五晶体管的第一极连接所述驱动晶体管的第一极，所述第五晶体管的第二极连接所述数据信号端，所述第五晶体管的栅极连接所述栅信号端；
第六晶体管，所述第六晶体管的第一极连接所述第一电源信号端，所述第六晶体管的第二极连接所述驱动晶体管的第一极，所述第六晶体管的栅极连接控制信号端；
其中，
所述驱动晶体管和发光器件串联在第一电源信号端与第二电源信号端之间；
所述存储电容的第二极连接所述第一电源信号端；
所述发光器件的第二极连接所述第二电源信号端。
在一些实施例中，所述定压信号源为所述初始化信号端、所述第一电源信号端、所述第二电源信号端中的任意一者。
在一些实施例中，所述像素电路还包括：
控制模块，所述控制模块配置为根据所述控制信号端的信号控制所述发光器件是否发光；所述控制模块包括：第七晶体管，所述第七晶体管的第一极连接所述驱动晶体管的第二极，所述第七晶体管的第二极连接所述发光器件的第一极，所述第七晶体管的栅极连接所述控制信号端；
第二重置模块，所述第二重置模块配置为根据第二重置信号端和所述初始化信号端的信号重置所述发光器件的第一极的电压；所述第二重置模块包括：第八晶体管，所述第八晶体管的第一极连接所述发光器件的第一极，所述第八晶体管的第二极连接所述初始化信号端，所述第八晶体管的栅极连接所述第二重置信号端。
在一些实施例中，所述驱动晶体管、第一晶体管、所述第二晶体 管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第八晶体管均为P型晶体管；
或者，
所述驱动晶体管、第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第八晶体管均为N型晶体管。
第二方面，本公开实施例提供一种像素电路的驱动方法，其中，所述像素电路为上述的任意一种像素电路，所述像素电路的驱动方法包括：
在发光阶段，使所述存储模块保持所述驱动电压，并向所述驱动模块提供所述驱动电压。
在一些实施例中，所述像素电路的驱动方法包括：
持续向所述初始化信号端提供初始化信号，持续向所述第一电源信号端提供第一电源信号，持续向所述第二电源信号端提供第二电源信号；
在重置阶段，向所述第一重置信号端提供导通信号，向所述栅信号端提供关断信号，向所述控制信号端提供关断信号；
在写入阶段，向所述第一重置信号端提供关断信号，向所述栅信号端提供导通信号，向所述控制信号端提供关断信号，向所述数据信号端提供数据信号；
在所述发光阶段，向所述第一重置信号端提供关断信号，向所述栅信号端提供关断信号，向所述控制信号端提供导通信号。
在一些实施例中，所述像素电路的驱动方法还包括：
在所述重置阶段，向所述第二重置信号端提供关断信号；
在所述写入阶段，向所述第二重置信号端提供导通信号；
在所述发光阶段，向所述第二重置信号端提供关断信号。
第三方面，本公开实施例提供一种显示基板，其中，包括：
基底；
设于所述基底上的多个子像素，至少部分所述子像素包括上述的像素电路。
在一些实施例中，所述稳压电容的第一极包括：连接在所述第三晶体管的第一极与所述第一晶体管的第二极之间的连接部；与所述连接部相连的附加部。
在一些实施例中，所述稳压电容的第一极与所述第一晶体管的第二极同层设置并连为一体。
在一些实施例中，所述稳压电容的第一极与所述驱动晶体管的有源区同层设置，所述稳压电容的第一极为导体化的半导体材料；
所述第一晶体管的第二极与所述驱动晶体管的有源区同层设置，所述第一晶体管的第二极为导体化的半导体材料。
在一些实施例中，所述稳压电容的第二极与所述初始化信号端同层设置并连为一体。
在一些实施例中，在逐渐远离所述基底的方向上，所述显示基板依次包括：
所述驱动晶体管的有源区和所述稳压电容的第一极；
栅绝缘层；
所述驱动晶体管的栅极；
第一层间绝缘层；
所述稳压电容的第二极和所述初始化信号端。
在一些实施例中，所述初始化信号端包括同层设置的第一初始化信号端和第二初始化信号端，所述第一初始化信号端和第二初始化信号端平行且间隔设置；
所述第八晶体管的第二极连接所述第一初始化信号端；
所述第三晶体管的第二极连接所述第二初始化信号端。
在一些实施例中，所述稳压电容的第一极沿第一方向延伸；
所述数据信号端和/或所述第一电源信号端沿第二方向延伸；所述第一方向与所述第二方向交叉。
在一些实施例中，所述第一重置信号端沿第一方向延伸；
至少部分所述像素电路的所述第一重置信号端，复用为沿第二方向与该像素电路相邻的所述像素电路的所述第二重置信号端；所述第一方向与所述第二方向交叉。
在一些实施例中，所述存储电容的第二极包括沿第一方向延伸的横连结构；至少部分沿第一方向相邻的所述像素电路的所述横连结构相互连接；
所述第一电源信号端沿第二方向延伸；所述第一方向与所述第二方向交叉。
在一些实施例中，所述显示基板还包括：
与所述第一电源信号端交叠设置的辅助导电结构；所述辅助导电结构与所述第一电源信号端间设有至少一个绝缘层，且所述辅助导电结构通过所述绝缘层中的过孔与所述第一电源信号端连接。
在一些实施例中，在逐渐远离所述基底的方向上，所述显示基板依次包括：
半导体层，其包括：所述驱动晶体管的第一极、第二极、有源区，所述第一晶体管的第一极、第二极、有源区，所述第二晶体管的第一极、第二极、有源区，所述第三晶体管的第一极、第二极、有源区，所述第四晶体管的第一极、第二极、有源区，所述第五晶体管的第一极、第二极、有源区，所述第六晶体管的第一极、第二极、有源区，所述第七晶体管的第一极、第二极、有源区，所述第八晶体管的第一极、第二极、有源区，所述稳压电容的第一极；其中，所述稳压电容的第一极与所述第一晶体管的第二极连为一体，且均为导体化的半导体材料；
栅绝缘层；
第一栅极层，其包括：所述驱动晶体管的栅极，所述第一晶体管的栅极，所述第二晶体管的栅极，所述第三晶体管的栅极，所述第四晶体管的栅极，所述第五晶体管的栅极，所述第六晶体管的栅极，所述第七晶体管的栅极，所述第八晶体管的栅极，所述第一重置信号端，所述第二重置信号端，所述控制信号端，所述存储电容的第一极；
第一层间绝缘层；
第二栅极层，其包括：所述初始化信号端，所述稳压电容的第二极，所述存储电容的第二极；其中，所述稳压电容的第二极与所述初始化信号端连为一体；
第二层间绝缘层；
第一源漏层，其包括：所述第一电源信号端，所述数据信号端，第一发光接入结构；其中，所述第一电源信号端通过所述第二层间绝缘层中的过孔连接所述存储电容的第二极，且通过所述栅绝缘层、所述第一层间绝缘层、所述第二层间绝缘层中的过孔连接所述第六晶体管的第一极；所述数据信号端通过所述栅绝缘层、所述第一层间绝缘层、所述第二层间绝缘层中的过孔连接所述第五晶体管的第二极，所述第一发光接入结构通过所述栅绝缘层、所述第一层间绝缘层、所述第二层间绝缘层中的过孔连接所述第七晶体管的第二极；
第一平坦化层；
第二源漏层，其包括：辅助导电结构、第二发光接入结构；其中，所述辅助导电结构与所述第一电源信号端交叠设置，且通过所述第一平坦化层中的过孔与所述第一电源信号端连接；所述第二发光接入结构通过所述第一平坦化层中的过孔连接所述第一发光接入结构；
第二平坦化层；
所述发光器件的第一极，所述发光器件的第一极通过所述第二平坦化层中的过孔连接所述第二发光接入结构。
在一些实施例中，所述第二栅极层还包括：
屏蔽结构，所述屏蔽结构通过所述第二层间绝缘层中的过孔连接所述第一电源信号端，所述屏蔽结构与所述第一晶体管的第一极、所述第五晶体管的第二极存在交叠且绝缘。
在一些实施例中，所述第一源漏层还包括：
第一连接结构，所述第一连接结构通过所述栅绝缘层、所述第一层间绝缘层、所述第二层间绝缘层中的过孔连接所述第八晶体管的第二极，并通过所述第二层间绝缘层中的过孔连接所述初始化信号端；
第二连接结构，所述第二连接结构通过所述栅绝缘层、所述第一层间绝缘层、所述第二层间绝缘层中的过孔连接所述第三晶体管的第二极，并通过所述第二层间绝缘层中的过孔连接所述初始化信号端；
第三连接结构，所述第三连接结构通过所述第一层间绝缘层、所述第二层间绝缘层中的过孔连接所述驱动晶体管的栅极，并通过所述栅绝缘层、所述第一层间绝缘层、所述第二层间绝缘层中的过孔连接所述第一晶体管的第一极。
在一些实施例中，所述稳压电容的电容值不低于8fF，且不超过所述存储电容的电容值的四分之一。
第四方面，本公开实施例提供一种显示装置，其包括：
上述的任意一种显示基板。
附图说明
附图用来提供对本公开实施例的进一步理解，并且构成说明书的一部分，与本公开实施例一起用于解释本公开，并不构成对本公开的限制。通过参考附图对详细示例实施例进行描述，以上和其它特征和优点对本领域技术人员将变得更加显而易见，在附图中：
图1为相关技术中的一种像素电路的电路图；
图2为相关技术中的一种像素电路中部分信号随时间的变化的模拟结果图；
图3为相关技术中的一种像素电路中的发光亮度随时间的变化的模拟结果图；
图4为本公开实施例提供的一种像素电路的电路图；
图5为本公开实施例提供的一种像素电路的驱动时序图；
图6为本公开实施例提供的一种像素电路中，在稳压电容的电容值不同时部分信号随时间的变化的模拟结果图；
图7为本公开实施例提供的另一种像素电路的电路图；
图8为本公开实施例提供的另一种像素电路的驱动时序图；
图9为本公开实施例提供的一种像素电路中的Flicker值随稳压电容的电容值的变化的模拟结果图；
图10为本公开实施例提供的一种显示基板中的像素电路的部分结构的透视结构示意图；
图11为本公开实施例提供的一种显示基板中的像素电路的POLY层的结构示意图；
图12为本公开实施例提供的一种显示基板中的像素电路的第一栅极层的结构示意图；
图13为本公开实施例提供的一种显示基板中的像素电路的第二栅极层的结构示意图；
图14为本公开实施例提供的一种显示基板中的像素电路中构成稳压电容的结构的透视结构示意图；
图15为本公开实施例提供的一种显示基板中的像素电路的第一源漏层的结构示意图；
图16为本公开实施例提供的一种显示基板中的像素电路的第二源漏层的结构示意图；
图17为本公开实施例提供的一种显示基板中的像素电路的栅绝缘层的过孔分部示意图；
图18为本公开实施例提供的一种显示基板中的像素电路的第一 层间绝缘层的过孔分部示意图；
图19为本公开实施例提供的一种显示基板中的像素电路的第二层间绝缘层的过孔分部示意图；
图20为本公开实施例提供的一种显示基板中的像素电路的第一平坦化层(也是钝化层)的过孔分部示意图；
图21为本公开实施例提供的一种显示基板中的像素电路的第二平坦化层的过孔分部示意图；
本公开实施例中使用的附图标记的意义如下：
TD、驱动晶体管；T1、第一晶体管；T2、第二晶体管；T3、第三晶体管；T4、第四晶体管；T5、第五晶体管；T6、第六晶体管；T7、第七晶体管；T8、第八晶体管；OLED、有机发光二极管；
Cst、存储电容；C1、稳压电容；
N1、第一节点；N2、第一节点；N3、第三节点；
GATE、栅信号端；DATA、数据信号端；RESET1、第一重置信号端；RESET2、第二重置信号端；INIT、初始化信号端；INIT1、第一初始化信号端；INIT2、第二初始化信号端；EM、控制信号端；VDD、第一电源信号端；VSS、第二电源信号端；VDC、定压信号源；
11、连接部；12、附加部；2、发光器件；31、辅助导电结构；32、横连结构；331、第一发光接入结构；332、第二发光接入结构；34、屏蔽结构；351、第一连接结构；352、第二连接结构；353、第三连接结构。
具体实施方式
为使本领域的技术人员更好地理解本公开实施例的技术方案，下面结合附图对本公开实施例提供的像素电路及其驱动方法、显示基板、显示装置进行详细描述。
在下文中将参考附图更充分地描述本公开实施例，但是所示的实施例可以以不同形式来体现，且不应当被解释为限于本公开阐述的实 施例。反之，提供这些实施例的目的在于使本公开透彻和完整，并将使本领域技术人员充分理解本公开的范围。
本公开实施例可借助本公开的理想示意图而参考平面图和/或截面图进行描述。因此，可根据制造技术和/或容限来修改示例图示。
在不冲突的情况下，本公开各实施例及实施例中的各特征可相互组合。
本公开所使用的术语仅用于描述特定实施例，且不意欲限制本公开。如本公开所使用的术语“和/或”包括一个或多个相关列举条目的任何和所有组合。如本公开所使用的单数形式“一个”和“该”也意欲包括复数形式，除非上下文另外清楚指出。如本公开所使用的术语“包括”、“由……制成”，指定存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或添加一个或多个其它特征、整体、步骤、操作、元件、组件和/或其群组。
除非另外限定，否则本公开所用的所有术语(包括技术和科学术语)的含义与本领域普通技术人员通常理解的含义相同。还将理解，诸如那些在常用字典中限定的那些术语应当被解释为具有与其在相关技术以及本公开的背景下的含义一致的含义，且将不解释为具有理想化或过度形式上的含义，除非本公开明确如此限定。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
本公开实施例不限于附图中所示的实施例，而是包括基于制造工 艺而形成的配置的修改。因此，附图中例示的区具有示意性属性，并且图中所示区的形状例示了元件的区的具体形状，但并不是旨在限制性的。
技术术语说明
在本公开中，如无特殊说明，则以下技术术语应按照以下解释理解：
“晶体管(Transistor)”具体可为“薄膜晶体管(TFT，Thin Film Transistor)”，其是指至少包括栅极、漏极、源极三个端子，以及连接在源极与漏极间的有源区的器件；其中，通过控制栅极、源极、漏极间的电压关系，可以使漏极、源极间绝缘而电流无法流过(即晶体管关断)，也可使电流能从源极经有源区而流到漏极(即晶体管导通)。
“晶体管的漏极和源极”是以电流的流向区分的，故对晶体管器件本身而言，在没有信号时不存在明确的源极和漏极；故本公开实施例中，用第一极、第二极代表晶体管的源极、漏极这两个极，但其中第一极、第二极与源极、漏极没有必然的对应关系。
“信号端”是指像素电路中，与外界的其它信号源连接从而提供相应信号的结构。由此，信号端不一定是一个“端头”或“连接端”，而可以包括所有与相应信号源连接的结构，例如，信号端可与相应信号线为一体结构，或者说信号线中处于像素电路中的部分即为信号端。同时，信号端和与其连接的结构也可为一体，例如，信号端(如栅信号端)若是为晶体管提供栅极信号的，则信号端中与晶体管的有源区叠置的部分就可以同时也是晶体管的栅极。
“信号源”是指任何能提供所需的信号的“源头”，其可以是以上“信号端”。
“两个结构连接”是指两个结构直接相互接触而相连，也可以是通过其它的导电结构间接相连；但本公开实施例中，通过晶体管等非必然导电的器件间接相连的结构不视为相互连接。
“节点”是指像素电路中，可在电学上视为一体的所有结构；例如，相互连接的电极以及电极间的连接结构均为一个“节点”，但一个晶体管的第一极和第二极若不相互连接，则是不同的节点。
“导通信号”是指当被加载到晶体管的栅极时，可使晶体管导通的信号；例如，对于P型晶体管，导通信号为低电平信号，而对于N型晶体管，导通信号为高电平信号。
“关断信号”是指当被加载到晶体管的栅极时，可使晶体管关断的信号；例如，对于P型晶体管，关断信号为高电平信号，而对于N型晶体管，关断信号为低电平信号。
多个结构“同层设置”是指多个结构是由同一个材料层形成的，故它们在层叠关系上处于相同层中，但并不代表它们与基底间的距离相等，也不代表它们与基底间的其它层结构完全相同。
“构图工艺”是指形成具有特定的图形的结构的步骤，其可为光刻工艺，光刻工艺包括形成材料层、涂布光刻胶、曝光、显影、刻蚀、光刻胶剥离等步骤中的一步或多步；当然，构图工艺也可为压印工艺、喷墨打印工艺等其它工艺。
相关技术
在一些相关技术中，有机发光二极管(OLED)显示基板的每个子像素包括像素电路，像素电路包括用于进行发光的有机发光二极管，即有机发光二极管发出每个子像素所需的光。
一种可行的像素电路的结构可参照图1，其中，驱动晶体管TD根据自身栅极的电压控制流过的电流，该电流也就是有机发光二极管OLED发光的驱动电流Ioled，故驱动晶体管TD根据驱动电压驱动有机发光二极管OLED发光。而在发光阶段，存储电容Cst使驱动晶体管TD的栅极保持所需的驱动电压。
参照图1，驱动晶体管TD的栅极的第一极还分别通过第一晶体管T1和第二晶体管T2连接第二节点N2和第三节点N3。在发光阶段， 第二节点N2和第三节点N3的电压通常不同，例如第二节点N2的电压可低于第一节点N1的电压，而第三节点N3的电压高于第一节点N1的电压。而由于第一晶体管T1和第二晶体管T2不可避免的存在一定的漏电流，故第二节点N2会因为第一晶体管T1的漏电流而将第一节点N1的电压逐渐“拉低”，而第三节点N3会因为第二晶体管T2的漏电流而将第一节点N1的电压逐渐“拉高”。而且，通常第三节点N3的“拉高”比第二节点N2的“拉低”更强。
由此，相关技术的像素电路中，发光阶段中部分信号随时间的变化的模拟结果参照图2，可见，在发光阶段中，第一节点N1的电压会逐渐升高，即驱动电压会之间升高，从而使流过有机发光二极管OLED的驱动电流Ioled降低。进一步的，在多帧中像素电路发出的光的亮度变化参照图3，可见在每帧(每个发光阶段中)，有机发光二极管OLED的发光亮度降低。
由此，当以上亮度降低达到人眼可察觉的程度时，则会导致闪烁(Flicker)现象，影响显示质量。
本公开实施例的具体实施方式
第一方面，参照图4至图8，本公开实施例提供一种像素电路，其包括：
发光模块，配置为进行发光；
驱动模块，配置为在发光阶段根据驱动电压驱动发光模块发光；
存储模块，存储模块配置为在发光阶段保持驱动电压，并向所述驱动模块提供驱动电压；
第一晶体管T1，第一晶体管T1的第一极连接驱动模块获取驱动电压的位置，第一晶体管T1的第二极不与信号源直接连接；在发光阶段，第一晶体管T1的第二极的电压低于第一晶体管T1的第一极的电压，第二晶体管T2的第二极的电压高于第一晶体管T1的第一极的电压；
第二晶体管T2，第二晶体管T2的第一极连接第一晶体管T1的第一极，第二晶体管T2的第二极连接的结构与第一晶体管T1的第二极连接的结构不同；
稳压电容C1，稳压电容C1的第一极连接第一晶体管T1的第二极，稳压电容C1的第二极连接定压信号源VDC。
本公开实施例的像素电路中，驱动模块在发光阶段根据驱动电压(如驱动晶体管TD栅极的电压)驱动发光模块发光，存储模块则用于在发光阶段保持并提供驱动电压。
其中，第一晶体管T1和第二晶体管T2的第一极均连接驱动模块提供驱动电压的位置(如第一节点N1，也就是驱动晶体管TD的栅极)，而它们的第二极则连接不同位置(如分别连接第二节点N2和第三节点N3)；由此，第二节点N2会因为第一晶体管T1的漏电流使第一节点N1的电压变化，而第三节点N3会因为第二晶体管T2的漏电流使第一节点N1的电压变化。
其中，在发光阶段，第二节点N2(第一晶体管T1的第二极)的电压和第三节点N3(第二晶体管T2的第二极)的电压中，通常是前者比第一节点N1的电压(驱动电压)低，后者比第一节点N1的电压(驱动电压)高，故二者分别将第一节点N1的电压“拉低”和“拉高”。
如前，在一些相关技术中，第三节点N3的“拉高”能力比第二节点N2的“拉低”能力更强，从而参照图2、图3，在发光阶段中，第一节点N1的电压(驱动电压)会逐渐升高，从而引起显示亮度的变化。
本公开实施例中，第一晶体管T1的第二极(第二节点N2)没有直接连接信号源，故在发光阶段其本身的电压也是可变的。本公开实施例中，在第一晶体管T1的第二极(第二节点N2)处连接了稳压电容C1，该稳压电容C1的另一极(第二极)连接定压信号源VDC，即连接任意一个在一帧中提供恒定不变的电压的信号源。显然，由于稳压电容C1的第二极为定压信号，故其可起到阻止电容的第一极(也就是第二节点N2)电压变化的作用，且稳压电容C1的电容值越大，阻止作用也越强。
当然，在实际中，第二节点N2处的结构本身也可能具有一定的寄生电容，但是，该寄生电容的电容值很小，一般最大不超过1.5fF(飞法)，且其另一极也不是连接定压信号源VDC，故该寄生电容不同于以上稳压电容C1。
可见，本公开实施例中，通过在第一晶体管T1的第二极(第二节点N2)增加“电容(稳压电容C1)”，可使第二节点N2的信号稳定性增强，从而在发光阶段保持“更低”的电压，以增强其对第一节点N1的电压的“拉低”能力，使第一节点N1受到的“拉低”和“拉高”作用趋向平衡，进而使第一节点N1的电压(驱动电压)在发光阶段能更好的保持稳定，降低发光器件2发出的光的亮度的变化，以改善或避免闪烁现象，提高显示质量。
由此，本公开实施例的像素电路中，在稳压电容的电容值分别为3.5fF、5fF、10fF时，发光阶段中部分信号随时间的变化的模拟结果参照图6。
其中，第二节点N2的电压可能因为与其它信号(如第一重置信号端RESET1的信号)的耦合作用而“跳变”的更高，导致其在发光阶段的初始电压更高；参照图6可见，稳压电容C1的电容值越大，则第二节点N2在发光阶段的初始电压越低，这表明，通过增加稳压电容C1，可提高第二节点N2抵御以上“跳变”的能力，从而使第二节点N2在发光阶段的初始电压降低，即，使第二节点N2的电压在发光阶段可相对保持在“更低”的水平，提升其“拉低”第一节点N1的电压(驱动电压)的能力，使第一节点N1的电压的变化减小，使驱动电流Ioled稳定，也就是使发光阶段中发光器件2的发光亮度的稳定，以改善或避免闪烁现象，提高显示质量。
而且，在第二节点N2将第一节点N1的电压“拉低”的同时，其本身的电压必然也会被“拉高”，但从图6中可见，稳压电容C1的电容值越大时，第二节点N2电压对应的线的“斜率”越小，即第二节点N2的电压被“拉高”的程度约小，这表明，通过增加稳压电容C1，还可使第二节点N2的电压被“拉高”的速率降低，从进一步增强其“拉 低”第一节点N1的电压的能力，使第一节点N1的电压的变化更小，进一步提高显示质量。
参照图4、图7，下面对本公开实施例的像素电路一些可用的具体形式进行介绍。
在一些实施例中，像素电路还包括：
第三晶体管T3，第三晶体管T3的第一极连接第一晶体管T1的第二极，第三晶体管T3的栅极连接第一晶体管T1的栅极。
本公开实施例中，以上第二节点N2可以是在第一晶体管T1与第三晶体管T3之间的节点，且该第一晶体管T1与第三晶体管T3的栅极相互连接，从而二者构成一个“双栅晶体管”，即第二节点N2可为双栅晶体管的中间节点。
双栅晶体管的中间节点通常不直接连接其它信号源，从而其保持自身电压的能力较弱，更适于采用本公开实施例的稳压电容C1。
在一些实施例中，像素电路还包括：
第四晶体管T4，第四晶体管T4的第一极连接第二晶体管T2的第二极，第四晶体管T4的栅极连接第二晶体管T2的栅极。
本公开实施例中，以上第三节点N3可以是在第二晶体管T2与第四晶体管T4之间的节点，且该第二晶体管T2与第四晶体管T4的栅极相互连接，从而二者构成一个“双栅晶体管”，即第三节点N3可为双栅晶体管的中间节点。
在一些实施例中，发光模块包括发光器件2；
驱动模块包括驱动晶体管TD，驱动晶体管TD配置为根据其栅极的电压驱动发光器件2发光；
存储模块包括存储电容Cst，存储电容Cst的第一极连接驱动晶体管TD的栅极，存储电容Cst配置为在发光阶段使其第一极保持驱动电压，并向驱动模块提供驱动电压。
在一些实施例中，发光器件2为有机发光二极管OLED。
作为本公开实施例的一种方式，以上驱动模块可包括驱动晶体管TD，而存储模块则包括存储电容Cst，发光器件2则可为有机发光二极管OLED(OLED)。
本公开实施例中，以发光器件2则为有机发光二极管OLED为例进行说明。当然，若发光器件2为其它形式，也是可行的。
在一些实施例中，像素电路包括第一重置模块和写入模块；
第一重置模块配置为根据初始化信号端INIT和第一重置信号端RESET1的信号重置驱动晶体管TD的栅极的电压；第一重置模块包括：
第一晶体管T1；
第三晶体管T3，第三晶体管T3的第一极连接第一晶体管T1的第二极，第三晶体管T3的第二极连接初始化信号端INIT，第三晶体管T3的栅极连接第一晶体管T1的栅极以及第一重置信号端RESET1；
写入模块配置为根据栅信号端GATE和数据信号端DATA的信号向存储电容Cst的第一极写入驱动电压；写入模块包括：
第二晶体管T2；
第四晶体管T4，第四晶体管T4的第一极连接第二晶体管T2的第二极，第四晶体管T4的第二极连接驱动晶体管TD的第二极，第四晶体管T4的栅极连接第二晶体管T2的栅极以及栅信号端GATE；
第五晶体管T5，第五晶体管T5的第一极连接驱动晶体管TD的第一极，第五晶体管T5的第二极连接数据信号端DATA，第五晶体管T5的栅极连接栅信号端GATE；
第六晶体管T6，第六晶体管T6的第一极连接第一电源信号端VDD，第六晶体管T6的第二极连接驱动晶体管TD的第一极，第六晶体管T6的栅极连接控制信号端EM；
其中，
驱动晶体管TD和发光器件2串联在第一电源信号端VDD与第二电源信号端VSS之间；
存储电容Cst的第二极连接第一电源信号端VDD；
发光器件2的第二极连接第二电源信号端VSS。
其中，以上第一电源信号端VDD和第二电源信号端VSS用于为发光器件2提供显示用的工作电压。
例如，第一电源信号端VDD可提供第一电源信号Vdd，或者说提供正极电压信号，而第二电源信号端VSS可提供第二电源信号Vdd，或者说提供负极电压信号(如接地信号)。从而，发光器件2的第一极可为其正极(如有机发光二极管OLED的阳极)，而发光器件2的第二极可为其负极(如有机发光二极管OLED的阴极)。
在一些实施例中，像素电路还包括控制模块，控制模块配置为根据控制信号端EM的信号控制发光器件2是否发光；控制模块包括：
第七晶体管T7，第七晶体管T7的第一极连接驱动晶体管TD的第二极，第七晶体管T7的第二极连接发光器件2的第一极，第七晶体管T7的栅极连接控制信号端EM。
在一些实施例中，像素电路还包括第二重置模块，第二重置模块配置为根据第二重置信号端RESET2和初始化信号端INIT的信号重置发光器件2的第一极的电压；第二重置模块包括：
第八晶体管T8，第八晶体管T8的第一极连接发光器件2的第一极，第八晶体管T8的第二极连接初始化信号端INIT，第八晶体管T8的栅极连接第二重置信号端RESET2。
作为本公开实施例的一种方式，像素电路还可包括控制模块、第二重置模块等其它的模块。
在一些实施例中，驱动晶体管TD、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、 第七晶体管T7、第八晶体管T8均为P型晶体管；
或者，
驱动晶体管TD、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8均为N型晶体管。
当像素电路为以上具体形式时，为了简便，其中的各晶体管可以均是N型晶体管，或均是P型晶体管。
在一些实施例中，定压信号源VDC为初始化信号端INIT、第一电源信号端VDD、第二电源信号端VSS中的任意一者。
当像素电路为以上具体形式时，稳压电容C1的第二极连接的定压信号源VDC可以就是该像素电路中的已有信号源，例如是初始化信号端INIT(稳定为初始化信号Vinit)、第一电源信号端VDD(稳定为第一电源信号Vdd)、第二电源信号端VSS(稳定为第二电源信号Vss)等，在此不再详细描述。
其中，以上像素电路的驱动方法和工作原理等，在后续介绍。
第二方面，参照图4至图8，本公开实施例提供一种像素电路的驱动方法，像素电路为上述的任意一种像素电路，像素电路的驱动方法包括：
在发光阶段，使存储模块保持驱动电压，并向驱动模块提供驱动电压。
本公开实施例中，在发光阶段使存储模块保持驱动电压，并向驱动模块提供驱动电压，以驱动发光器件2发光。
本公开实施例中，由于像素电路中增加了稳压电容C1，故发光阶段中的驱动电压具有更好的稳定性，发光器件2的发光亮度的变化程度小，可改善或避免闪烁现象，提高显示质量。
在显示过程中，像素电路的驱动过程(驱动方法)可以是多次进 行的，每次驱动过程均包括多个阶段。
在一些实施例中，像素电路的驱动方法包括：
持续向初始化信号端INIT提供初始化信号，持续向第一电源信号端VDD提供第一电源信号，持续向第二电源信号端VSS提供第二电源信号；
在重置阶段，向第一重置信号端RESET1提供导通信号，向栅信号端GATE提供关断信号，向控制信号端EM提供关断信号；
在写入阶段，向第一重置信号端RESET1提供关断信号，向栅信号端GATE提供导通信号，向控制信号端EM提供关断信号，向数据信号端DATA提供数据信号；
在发光阶段，向第一重置信号端RESET1提供关断信号，向栅信号端GATE提供关断信号，向控制信号端EM提供导通信号。
在一些实施例中，像素电路的驱动方法包括：
在重置阶段，向第二重置信号端RESET2提供关断信号；
在写入阶段，向第二重置信号端RESET2提供导通信号；
在重置阶段，向第二重置信号端RESET2提供关断信号。
在一些实施例中，在驱动过程的各个阶段中，可按照以上的方式向各信号端提供相应的信号，以驱动像素电路。
其中，以上第二重置信号端RESET2的信号与栅信号端GATE的信号一直相同，故像素电路的第二重置信号端RESET2与栅信号端GATE可以连接同一个信号源，例如连接驱动芯片(Driver IC)上的同一个引脚(Pin)。
参照图4、图5，作为本公开实施例的一种方式，下面以驱动晶体管TD、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8均为P型晶体管为例，说明本公开实施例的像素电路的驱动方法。
在本公开实施例的像素电路的驱动过程的各个阶段中，都持续向初始化信号端INIT提供初始化信号Vinit，持续向第一电源信号端VDD提供第一电源信号Vdd，持续向第二电源信号端VSS提供第二电源信号Vss；而各阶段中向其它各信号端提供的信号状况如下：
S101重置阶段：向第一重置信号端RESET1提供低电平信号，向栅信号端GATE提供高电平信号，向控制信号端EM提供高电平信号，向第二重置信号端RESET2提供高电平信号。
本阶段中，第一重置信号端RESET1的低电平信号使第一晶体管T1和第三晶体管T3导通，从而将初始化信号Vinit写入第一节点N1和第二节点N2。
S102写入阶段，向第一重置信号端RESET1提供高电平信号，向栅信号端GATE提供低电平信号，向控制信号端EM提供高电平信号，向数据信号端DATA提供数据信号，向第二重置信号端RESET2提供低电平信号。
本阶段中，栅信号端GATE的低电平信号使第二晶体管T2、第四晶体管T4、第五晶体管T5导通，从而数据信号端DATA的数据信号Vdata通过第五晶体管T5写入驱动晶体管TD的第一极；且经过驱动晶体管TD后，使第一节点N1(存储电容Cst的第一极)的电压变为Vdata-Vth，其中Vth为驱动晶体管TD的阈值电压。
其中，以上数据信号是指对应本像素电路的数据信号，而驱动过程的其它时间，数据信号端DATA实际也会获取对应其它像素电路的数据信号(因为其它像素电路可能正处于写入阶段)，但因其它时间中第五晶体管T5均关断，故这些数据信号不会写入本像素电路。
同时，由于第二重置信号端RESET2为低电平信号，故初始化信号端INIT的初始化信号Vinit经第八晶体管T8写入发光器件2的第一极，重置该位置的电压。
S103发光阶段，向第一重置信号端RESET1提供高电平信号，向栅信号端GATE提供高电平信号，向控制信号端EM提供低电平信号，向第二重置信号端RESET2提供高电平信号。
本阶段中，控制信号端EM为低电平信号，从而第六晶体管T6、第七晶体管T7均导通，故电流可从第一电源信号端VDD流向第二电源信号端VSS，发光器件2可以持续发光，直到下一次(如下一帧中的)重置阶段来到。
由于存储电容Cst的保持作用，故本阶段中驱动晶体管TD的栅极(第一节点N1)的电压(驱动电压)保持为Vdata-Vth；而由于驱动晶体管TD的第一极的电压为第一电源信号Vdd，故其栅源电压Vgs为Vdata-Vth。而流过驱动晶体管TD的驱动电流Ioled与其栅源电压Vgs和阈值电压Vth的差成正比，即驱动电流Ioled正比于Vdd-(Vdata-Vth)-Vth＝Vdd-Vdata。可见，该驱动电流Ioled仅与数据电压Vdata有关，而与驱动晶体管TD的阈值电压Vth无关，即消除了阈值电压漂移的影响。
本公开实施例中，在发光阶段中，第二节点N2理论上应保持初始化信号Vinit，该初始化信号Vinit的电压通常低于第一节点N1的电压Vdata-Vth，故第二节点N2会因第一晶体管T1的漏电流而将第一节点N1的电压“拉低”；而第三节点N3的电压比第一节点N1的电压高，故第三节点N3会因第二晶体管T2的漏电流而将第一节点N1的电压“拉高”，而且，通常第三节点N3的“拉高”能力比第二节点N2的“拉低”能力更强，从而导致发光阶段中第一节点N1的电压逐渐升高，发光器件2的亮度逐渐降低。
本公开实施例中，因为设有稳压电容C1，故第二节点N2的电压更加稳定，可保持在“更低”的水平，从而对第一节点N1有更强的“拉低”能力，以使第一节点N1的电压在发光阶段中更加稳定，发光器件2的亮度也更加稳定。
具体的，在进入写入阶段时，第一重置信号端RESET1的信号从低电平信号“跳变”为高电平信号，以使第一晶体管T1和第三晶体管T3关断。可见，第一重置信号端RESET1连接第一晶体管T1和第三晶体管T3的栅极，而第二节点N2为第一晶体管T1的第二极和第三 晶体管T3的第一极，故第二节点N2与第一重置信号端RESET1的距离通常很接近；由此，以上第一重置信号端RESET1的信号的“跳变”，也会通过耦合作用使第二节点N2的电压升高，使第二节点N2在发光阶段开始时的初始电压实际高于初始化信号Vinit的电压。
而本公开实施例因设有稳压电容C1，故第一重置信号端RESET1的信号的“跳变”对第二节点N2电压的影响减弱，第二节点N2在发光阶段开始时的初始电压更低的水平，可增强其对第一节点N1电压的“下拉”能力，改善显示质量。
参照图7、图8，作为本公开实施例的另一种方式，下面以驱动晶体管TD、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8均为N型晶体管为例，说明本公开实施例的像素电路的驱动方法。
在本公开实施例的像素电路的驱动过程的各个阶段中，都持续向初始化信号端INIT提供初始化信号Vinit，持续向第一电源信号端VDD提供第一电源信号Vdd，持续向第二电源信号端VSS提供第二电源信号Vss；而各阶段中向其它各信号端提供的信号状况如下：
S201重置阶段：向第一重置信号端RESET1提供高电平信号，向栅信号端GATE提供低电平信号，向控制信号端EM提供低电平信号，向第二重置信号端RESET2提供低电平信号。
本阶段中，第一重置信号端RESET1的高电平信号使第一晶体管T1和第三晶体管T3导通，从而将初始化信号Vinit写入第一节点N1和第二节点N2。
S202写入阶段，向第一重置信号端RESET1提供低电平信号，向栅信号端GATE提供高电平信号，向控制信号端EM提供低电平信号，向数据信号端DATA提供数据信号，向第二重置信号端RESET2提供高电平信号。
本阶段中，栅信号端GATE的高电平信号使第二晶体管T2、第四晶体管T4、第五晶体管T5导通，从而数据信号端DATA的数据信号 Vdata通过第五晶体管T5写入驱动晶体管TD的第一极；且经过驱动晶体管TD后，使第一节点N1(存储电容Cst的第一极)的电压变为Vdata-Vth，其中Vth为驱动晶体管TD的阈值电压。
其中，以上数据信号是指对应本像素电路的数据信号，而驱动过程的其它时间，数据信号端DATA实际也会获取对应其它像素电路的数据信号(因为其它像素电路可能正处于写入阶段)，但因其它时间中第五晶体管T5均关断，故这些数据信号不会写入本像素电路。
同时，由于第二重置信号端RESET2为高电平信号，故初始化信号端INIT的初始化信号Vinit经第八晶体管T8写入发光器件2的第一极，重置该位置的电压。
S203发光阶段，向第一重置信号端RESET1提供低电平信号，向栅信号端GATE提供低电平信号，向控制信号端EM提供高电平信号，向第二重置信号端RESET2提供低电平信号。
本阶段中，控制信号端EM为高电平信号，从而第六晶体管T6、第七晶体管T7均导通，故电流可从第一电源信号端VDD流向第二电源信号端VSS，发光器件2可以持续发光，直到下一次(如下一帧中的)重置阶段来到。
由于存储电容Cst的保持作用，故本阶段中驱动晶体管TD的栅极(第一节点N1)的电压(驱动电压)保持为Vdata-Vth；而由于驱动晶体管TD的第一极的电压为第一电源信号Vdd，故其栅源电压Vgs为Vdata-Vth。而流过驱动晶体管TD的驱动电流Ioled与其栅源电压Vgs和阈值电压Vth的差成正比，即驱动电流Ioled正比于Vdd-(Vdata-Vth)-Vth＝Vdd-Vdata。可见，该驱动电流Ioled仅与数据电压Vdata有关，而与驱动晶体管TD的阈值电压Vth无关，即消除了阈值电压漂移的影响。
可见，当晶体管的形式不同时，只是导通信号和关断信号的电平相互对换，本公开实施例的像素电路的具体驱动过程和原理并无变化，故在此不再详细描述。
第三方面，参照图4至图21，本公开实施例提供一种显示基板，其包括：
基底；
设于基底上的多个子像素，至少部分子像素包括上述的任意一种的像素电路。
其中，基底是用于承载显示基板上的其它结构的基础，其是由玻璃、硅(如单晶硅)、聚合物材料(如聚酰亚胺)等材料构成的基本为片状的结构，可为刚性，也可为柔性，厚度可在毫米量级。
其中，子像素是指可用于独立显示所需内容的最小的结构，即显示装置中可被单独控制的最小的“点”。其中，不同的子像素可具有不同的颜色，从而通过不同子像素的混光可实现彩色显示：例如，可以是多个排在一起的不同颜色的子像素组成一个“像素(或像素单元)”，即这些子像素发出的光混在一起成为视觉上的一个“点”，如红色、绿色、蓝色三种颜色的三个子像素组成一个像素；或者，也可不存在明确的像素(或像素单元)，而是通过临近子像素间的“公用”实现彩色显示。
本公开实施例中，可将以上的像素电路的各器件设于基底上，从每个像素电路对应一个子像素，即像素电路中发光器件2发出的光作为该子像素发出的光。
其中，对应不同颜色的子像素的像素电路中，可以是发光器件2直接发出不同颜色的光，也可以是发光器件2都发出白光，再经过不同颜色的彩色滤光膜(CF)后成为不同颜色的光。
由于采用了以上的像素电路，故本公开实施例的显示基板显示时亮度稳定，无闪烁现象，显示质量好。
在一些实施例中，子像素在显示基板上可排成阵列，且通过多条信号线为各子像素中的像素电路提供信号，以控制其进行显示。
其中，信号线可包括多条沿第一方向(如行方向)延伸的栅信号线、多条沿第一方向延伸的第一重置信号线、多条沿第一方向延伸的第二重置信号线、多条沿第一方向延伸的控制信号线、多条沿第一方向延伸的初始化信号线；每条栅信号线连接一行中各子像素的像素电路的栅信号端GATE，每条第一重置信号线连接一行中各子像素的像素电路的第一重置信号端RESET1，每条第二重置信号线连接一行中各子像素的像素电路的第二重置信号端RESET2(且第二重置信号线可与对应同行子像素的栅信号线连接同一个信号源)，每条控制信号线连接一行中各子像素的像素电路的控制信号端EM、每条初始化信号线连接一行中各子像素的像素电路的初始化信号端INIT。
其中，信号线还可包括多条沿第二方向(如列方向)延伸的数据线；每条数据线连接一行中各子像素的像素电路的数据信号端DATA。
其中，信号线还可包括第一电源信号线、第二电源信号线、初始化信号线等，这些信号线可沿行方向或列方向延伸，也可形成网格状，且分别与各子像素的像素电路的第一电源信号端VDD、第二电源信号端VSS、初始化信号端INIT相连。
在一些实施例中，稳压电容C1的电容值不低于8fF(飞法)，且不超过存储电容Cst的电容值的四分之一。
稳压电容C1的电容值如果过小，则不能起到足够的稳压作用，经过研究发现，至少应为8fF，例如为8fF、10fF、12fF等。
如图6，当稳压电容C1的电容值不同时，对第一节点N1的电压的变化的阻值能力不同，且稳压电容C1的电容值越大第一节点N1的电压的变化的阻值能力越强。
进一步的，当稳压电容C1的电容值不同时，模拟得到的Flicker值参照图9。其中，Flicker值是根据发光阶段中亮度-时间变化曲线计算得到的无量纲的数值，其用于表示显示的闪烁程度，其值越低表示闪烁程度越小，即亮度越稳定，显示质量越好。
当然，稳压电容C1的电容值也不能太高，否则会使第二节点N2 的“下拉”能力比第三节点N3的“上拉”能力更强，引起第一节点N1的电压在发光阶段“反向”变化(降低)，同样会导致亮度不稳定，由此稳压电容C1的电容值一般不能超过存储电容Cst的电容值的1/4，可在存储电容Cst的电容值的1/5左右。
在一些实施例中，稳压电容C1的第一极与第一晶体管T1的第二极同层设置并连为一体。
设于基底上的像素电路的各结构可设于不同的层中，而由于稳压电容C1的第一极需要和第一晶体管T1的第二极相连，故参照图10、图11，作为本公开实施例的一种方式，二者可以是同层设置的一体结构，以简化显示基板的结构和制备方法。
其中，当第三晶体管T3的第一极也连接稳压电容C1的第一极时，参照图10、图11，稳压电容C1的第一极、第一晶体管T1的第二极、第三晶体管T3的第一极三者可为一体结构。
在一些实施例中，稳压电容C1的第一极与驱动晶体管TD的有源区同层设置，稳压电容C1的第一极为导体化的半导体材料；
第一晶体管T1的第二极与驱动晶体管TD的有源区同层设置，第一晶体管T1的第二极为导体化的半导体材料。
参照图10、图11，为了进一步简化结构，以上稳压电容C1的第一极、第一晶体管T1的第二极(也可有第三晶体管T3的第一极)构成的一体结构，还可与第一晶体管T1的有源区也连成一体(也可与第三晶体管T3的有源区一体)，即这些结构均为半导体材料(如多晶硅材料)，但其中对应稳压电容C1的第一极、第一晶体管T1的第二极、第三晶体管T3的第一极的部分需要经过导体化处理而形成导体。
当然，如果第一晶体管T1的第一极、第三晶体管T3的第二极等结构也与以上各结构连成一体，也是可行的。
当然，如果稳压电容C1的第一极、第一晶体管T1的第二极、第三晶体管T3的第一极、第一晶体管T1的有源区、第三晶体管T3的 有源区等分别设于不同层中，并通过绝缘层中的过孔等结构连接，也是可行的。
在一些实施例中，稳压电容C1的第一极包括：连接在第三晶体管T3的第一极与第一晶体管T1的第二极之间的连接部11；与连接部11相连的附加部12。
显然，第三晶体管T3的第一极与第一晶体管T1的第二极应当相连以构成“双栅晶体管”，从而可参照图10、图11，直接用第三晶体管T3的第一极与第一晶体管T1的第二极间的连接结构(连接部11)作为稳压电容C1的第一极，即第三晶体管T3的第一极与第一晶体管T1的第二极通过稳压电容C1的第一极连接。
参照图10、图11，直接将第三晶体管T3的第一极与第一晶体管T1的第二极连接的结构(连接部11)的面积比较小，故若仅用连接部11作为稳压电容C1的第一极，则稳压电容C1的电容值较小，稳压效果不够好。为此，稳压电容C1的第一极除了包括连接部11外，还可包括从连接部11上“扩展”出的额外部分(附加部12)，而附加部12虽然不直接起到连接作用，但可以增大稳压电容C1的电容值。
在一些实施例中，稳压电容C1的第二极与初始化信号端INIT同层设置并连为一体。
显然，稳压电容C1的第二极应当是与稳压电容C1的第一极叠置且绝缘的，即稳压电容C1的第一极和稳压电容C1的第二极在基底上的正投影应当有重叠，且稳压电容C1的第一极与稳压电容C1的第二极之间通过至少一个绝缘层隔开。
为此，作为本公开实施例的一种方式，参照图10、图13、图14，可以用与初始化信号端INIT同层设置的结构作为稳压电容C1的第二极，并且该稳压电容C1的第二极直接连接初始化信号端INIT。
在一些实施例中，如参照图13，稳压电容C1的第二极可位于初始化信号端INIT内，即初始化信号端INIT的一部分同时也是稳压电容C1的第二极；或者说，可直接使初始化信号端INIT覆盖稳压电容C1的第一极所在位置。
在一些实施例中，在逐渐远离基底的方向上，显示基板依次包括：
驱动晶体管TD的有源区和稳压电容C1的第一极；
栅绝缘层(GI)；
驱动晶体管TD的栅极；
第一层间绝缘层(ILD1)；
稳压电容C1的第二极和初始化信号端INIT。
其中，初始化信号端INIT所在层(如GATE2层)与晶体管的有源区所在层(POLY)比较接近(之间的绝缘层比较少)，故用这两个层分别作为稳压电容C1的两极所在层，可缩小稳压电容C1的两极间的距离，以提高稳压电容C1的电容值；同时，稳压电容C1的第二极直接与同层设置的初始化信号端INIT为一体，故可很方便的用初始化信号端INIT作为定压信号源VDC。
相对的，比初始化信号端INIT更远离基底的各层(如SD1层)与晶体管的有源区所在层比较远，若用它们作为稳压电容C1的第二极容易导致稳压电容C1的电容值降低；而栅信号端GATE所在层(如GATE1层)虽然与晶体管的有源区所在层也比较接近，但栅信号端GATE的信号是变化的，故若要用栅信号端GATE所在层中的结构作为稳压电容C1的第二极，还需要从其它层中向该结构单独引入定压信号，比较麻烦。
当然，如果是用与其它结构(如第一电源信号端VDD、第二电源信号端VSS等)同层设置的结构作为作为稳压电容C1的第二极，也是可行的。
在一些实施例中，初始化信号端INIT包括同层设置的第一初始化信号端INIT1和第二初始化信号端INIT2，第一初始化信号端INIT1和第二初始化信号端INIT2平行且间隔设置；
第八晶体管T8的第二极连接第一初始化信号端INIT1；
第三晶体管T3的第二极连接第二初始化信号端INIT2。
参照图13，初始化信号端INIT可分为两个同层设置但相互独立 的结构(第一初始化信号端INIT1和第二初始化信号端INIT2)，它们分别连接第三晶体管T3的第二极和第八晶体管T8的第二极，从而根据需要，第三晶体管T3的第二极和第八晶体管T8的第二极它们的信号可以相同，也可以不同，以实现更复杂的控制。
当然，如果连接第三晶体管T3的第二极和第八晶体管T8的第二极的初始化信号端INIT是一体结构(即不区分第一初始化信号端INIT1和第二初始化信号端INIT2)，也是可行的。
在一些实施例中，稳压电容C1的第一极沿第一方向延伸；
数据信号端DATA和/或第一电源信号端VDD沿第二方向延伸；第一方向与第二方向交叉。
参照图11，稳压电容C1的第一极可整体上沿第一方向(图11中横向)延伸；而参照图15，数据信号端DATA、第一电源信号端VDD可沿与第一方向交叉(进一步可为垂直)的第二方向(图15中纵向)延伸；从而参照图10，稳压电容C1的第一极可与数据信号端DATA、第一电源信号端VDD有交叠(当然相互绝缘)。
在一些实施例中，第一重置信号端RESET1沿第一方向延伸；
至少部分像素电路的第一重置信号端RESET1，复用为沿第二方向与该像素电路相邻的像素电路的第二重置信号端RESET2；第一方向与第二方向交叉。
参照图5、图8，第一重置信号端RESET1的信号与第二重置信号端RESET2的信号间相差一个周期。由此，沿第二方向(如图12中纵向)相邻的像素电路中，上一行像素电路的第二重置信号端RESET2的信号，与本一行像素电路的第一重置信号端RESET1的信号是相同的。
由此，参照图12，为了简化结构，每个像素电路的第一重置信号端RESET1可以是沿第一方向(图12中横向)延伸的，同时，其复用沿第二方向(如图12中纵向)相邻的像素电路的第二重置信号端RESET2；即参照图10，上一行像素电路的第八晶体管T8，可与行像素电路的其它结构处在一个矩形区域内，以便用本行像素电路的第一 重置信号端RESET1(即上一行像素电路的第二重置信号端RESET2)作为其栅极。
在一些实施例中，存储电容Cst的第二极包括沿第一方向延伸的横连结构32；至少部分沿第一方向相邻的像素电路的横连结构32相互连接；
第一电源信号端VDD沿第二方向延伸；第一方向与第二方向交叉。
参照图13，存储电容Cst的第二极除了与存储电容Cst的第一极交叠的结构(图13中内有缺口的矩形)外，还有沿第一方向(图13中横向)延伸的横连结构32，从而同行中的多个存储电容Cst可通过横连结构32连为一体。
同时，参照图15，第一电源信号端VDD是沿与第一方向交叉的第二方向(图15中纵向)延伸的，且第一电源信号端VDD必然与各自像素电路中的存储电容Cst连接。
由此可见，多列的第一电源信号端VDD，实际分别与同行的存储电容Cst的第二极电连接，即在电学上，提供第一电源信号Vdd的结构形成了“网格状”，从而降低其供电电阻。
在一些实施例中，显示基板还包括：
与第一电源信号端VDD交叠设置的辅助导电结构31；辅助导电结构31与第一电源信号端VDD间设有至少一个绝缘层，且辅助导电结构31通过绝缘层中的过孔与第一电源信号端VDD连接。
参照图16，显示基板中还可包括与第一电源信号端VDD有交叠(如也沿第二方向延伸且)的辅助导电结构31，且辅助导电结构31与第一电源信号端VDD连接，以起到进一步降低第一电源信号Vdd的供电电阻的作用。
下面用以上的像素电路为例，对其中结构的具体分层进行示例性的介绍。
在一些实施例中，在逐渐远离基底的方向上，显示基板依次包括：
(1)半导体层(POLY)。
半导体层由半导体材料构成，例如由多晶硅材料(poly-Si)构成。
半导体层包括：驱动晶体管TD的第一极、第二极、有源区，第一晶体管T1的第一极、第二极、有源区，第二晶体管T2的第一极、第二极、有源区，第三晶体管T3的第一极、第二极、有源区，第四晶体管T4的第一极、第二极、有源区，第五晶体管T5的第一极、第二极、有源区，第六晶体管T6的第一极、第二极、有源区，第七晶体管T7的第一极、第二极、有源区，第八晶体管T8的第一极、第二极、有源区，稳压电容C1的第一极。
其中，稳压电容C1的第一极与第一晶体管T1的第二极连为一体，且均为导体化的半导体材料。
即参照图11，各晶体管的有源区、第一极、第二极均可位于半导体层中；且稳压电容C1的第一极(连接部11和附加部12)与第一晶体管T1的第二极连为一体，也位于半导体层中。
当然，所有晶体管的电极以及稳压电容C1的第一极，均是由导体化的半导体材料构成的。
(2)栅绝缘层(GI)。
栅绝缘层由绝缘材料构成，例如由氮化硅、氧化硅、氮氧化硅等构成，用于将各晶体管的有源区与栅极隔开。
其中，由于此时各晶体管的有源区比其栅极更靠近基底，故各晶体管均为“底栅型晶体管”。
参照图17，栅绝缘层可包括：用于连接第一电源信号端VDD和第六晶体管T1的第一极的过孔，用于连接数据信号端DATA和连接第五晶体管T5的第二极的过孔，用于连接第一发光接入结构331和第七晶体管T7的第二极的过孔，用于连接第一连接结构351和第八晶体管T8的第二极的过孔，用于连接第二连接结构352和第三晶体管T3的第二极的过孔，用于连接第三连接结构353和第一晶体管T1的第一 极的过孔(后续详细说明)。
(3)第一栅极层(GATE1)。
第一栅极层由导电材料构成，例如由金属材料构成。
第一栅极层包括：驱动晶体管TD的栅极，第一晶体管T1的栅极，第二晶体管T2的栅极，第三晶体管T3的栅极，第四晶体管T4的栅极，第五晶体管T5的栅极，第六晶体管T6的栅极，第七晶体管T7的栅极，第八晶体管T8的栅极，第一重置信号端RESET1，第二重置信号端RESET2，控制信号端EM，存储电容Cst的第一极。
即参照图12，所有晶体管的栅极，以及用于为栅极提供信号的各信号端，均可位于第一栅极层中。
另外，存储电容Cst的第一极因必然驱动晶体管TD的栅极(例如是一体结构)，故也位于第一栅极层中。
如前，本行像素电路的第一重置信号端RESET1也可复用为上一行的像素电路的第二重置信号端RESET2，即每个像素电路中，实际只有一个重置信号端结构。
(4)第一层间绝缘层(ILD1)。
第一层间绝缘层由绝缘材料构成，例如由氮化硅、氧化硅、氮氧化硅等构成，其用于将第一栅极层的结构与后续的第二栅极层的结构隔开。
参照图18，第一层间绝缘层可包括：用于连接第一电源信号端VDD和第六晶体管T1的第一极的过孔，用于连接数据信号端DATA和连接第五晶体管T5的第二极的过孔，用于连接第一发光接入结构331和第七晶体管T7的第二极的过孔，用于连接第一连接结构351和第八晶体管T8的第二极的过孔，用于连接第二连接结构352和第三晶体管T3的第二极的过孔，用于连接第三连接结构353和连接驱动晶体管TD的栅极的过孔，用于连接第三连接结构353和第一晶体管T1的第一极的过孔(后续详细说明)。
(5)第二栅极层(GATE2)。
第二栅极层由导电材料构成，例如由金属材料构成。
第二栅极层包括：初始化信号端INIT，稳压电容C1的第二极，存储电容Cst的第二极。
其中，稳压电容C1的第二极与初始化信号端INIT连为一体。
参照图13，初始化信号端INIT、稳压电容C1的第二极、存储电容Cst的第二极可设于第二栅极层中，且稳压电容C1的第二极与初始化信号端INIT连为一体。
其中，参照图13，初始化信号端INIT也可分为以上第一初始化信号端INIT1和第二初始化信号端INIT2，此时稳压电容C1的第二极可与其中一者为一体结构，例如与第二初始化信号端INIT2为一体结构。
其中，参照图13，存储电容Cst的第二极也可包括以上横连结构32。
其中，参照图13，存储电容Cst的第二极除了横连结构32外的部分，可为有缺口的矩形，该缺口是为了让位于其下方的存储电容Cst的第一极能与第一晶体管T1的第一极连接(后续详细说明)。
在一些实施例中，第二栅极层还包括：屏蔽结构34，屏蔽结构34通过第二层间绝缘层中的过孔连接第一电源信号端VDD，屏蔽结构34与第一晶体管T1的第一极、第五晶体管T5的第二极存在交叠且绝缘。
参照图13，第二栅极层中还可设有屏蔽结构34；参照图10、图15，该屏蔽结构34连接第一电源信号端VDD(后续详细描述)，且与第一晶体管T1的第一极、第五晶体管T5的第二极有交叠，以屏蔽其它信号(如数据信号端DATA的信号)对这两个晶体管的影响。
(6)第二层间绝缘层(ILD2)。
第二层间绝缘层由绝缘材料构成，例如由氮化硅、氧化硅、氮氧化硅等构成，其用于将第二栅极层的结构与后续的第一源漏层的结构隔开。
参照图19，第二层间绝缘层可包括：用于连接第一电源信号端 VDD和存储电容Cst的第二极的过孔，用于连接第一电源信号端VDD和第六晶体管T1的第一极的过孔用于连接数据信号端DATA和连接第五晶体管T5的第二极的过孔，用于连接第一发光接入结构331和第七晶体管T7的第二极的过孔，用于连接第一连接结构351和第八晶体管T8的第二极的过孔，用于连接第一连接结构351和初始化信号端INIT的过孔，用于连接第二连接结构352和第三晶体管T3的第二极的过孔，用于连接第二连接结构352和初始化信号端INIT的过孔，用于连接第三连接结构353和连接驱动晶体管TD的栅极的过孔，用于连接第三连接结构353和第一晶体管T1的第一极的过孔，用于连接第一电源信号端VDD与屏蔽结构34的过孔(后续详细说明)。
(7)第一源漏层(SD1)。
第一源漏层由导电材料构成，例如由金属材料构成。
第一源漏层包括：第一电源信号端VDD，数据信号端DATA，第一发光接入结构331。
其中，第一电源信号端VDD通过第二层间绝缘层中的过孔连接存储电容Cst的第二极，且通过栅绝缘层、第一层间绝缘层、第二层间绝缘层中的过孔连接第六晶体管T1的第一极；数据信号端DATA通过栅绝缘层、第一层间绝缘层、第二层间绝缘层中的过孔连接第五晶体管T5的第二极，第一发光接入结构331通过栅绝缘层、第一层间绝缘层、第二层间绝缘层中的过孔连接第七晶体管T7的第二极。
参照图15，第一电源信号端VDD和数据信号端DATA可设于第一源漏层中，且第一电源信号端VDD连接存储电容Cst的第二极，而数据信号端DATA连接第五晶体管T5的第二极，以形成以上像素电路。
其中，七晶体管T7的第二极需要连接发光器件2的第一极，但二者之间的层很多，距离较大，故参照图15，第一源漏层中还可包括与第七晶体管T7的第二极连接的第一发光接入结构331，以通过多个结构实现第七晶体管T7的第二极需要连接发光器件2的第一极的连接(后续详细描述)，以避免产生断线。
其中，如果具有以上屏蔽结构34，则第一电源信号端VDD还通过第二层间绝缘层中的过孔与其连接。
在一些实施例中，第一源漏层还包括：
第一连接结构351，第一连接结构351通过栅绝缘层、第一层间绝缘层、第二层间绝缘层中的过孔连接第八晶体管T8的第二极，并通过第二层间绝缘层中的过孔连接初始化信号端INIT；
第二连接结构352，第二连接结构352通过栅绝缘层、第一层间绝缘层、第二层间绝缘层中的过孔连接第三晶体管T3的第二极，并通过第二层间绝缘层中的过孔连接初始化信号端INIT；
第三连接结构353，第三连接结构353通过第一层间绝缘层、第二层间绝缘层中的过孔连接驱动晶体管TD的栅极，并通过栅绝缘层、第一层间绝缘层、第二层间绝缘层中的过孔连接第一晶体管T1的第一极。
参照图10、图15，为实现像素电路中一些不同层的结构的电连接，还可在第一源漏层中设置多个相应的连接结构。
其中，连接结构具体可包括将第八晶体管T8的第二极与初始化信号端INIT(如第一初始化信号端INIT1)连接的第一连接结构351；将第三晶体管T3的第二极与初始化信号端INIT(如第二初始化信号端INIT2)连接的第二连接结构352；以及，将驱动晶体管TD(即存储电容Cst的第一极)与第一晶体管T1的第一极连接(如通过以上存储电容Cst中的缺口)的第三连接结构353等。
当然，如果以上连接结构设于其它层中，或者个晶体管和电容的各电极的形式改变从而需要不同的连接结构，也均是可行的。
(8)第一平坦化层(PLN1)。
第一平坦化层由有机绝缘材料构成，用于消除下方结构的段差。
参照图20，第一平坦化层可包括：用于连接第一发光接入结构331和第二发光接入结构332的过孔，以及用于连接第一电源信号端VDD和辅助导电结构31的过孔(后续详细描述)。
(9)钝化层(PVX)。
钝化层由绝缘材料构成，例如由氮化硅、氧化硅、氮氧化硅等构成，用于避免后续形成的结构与第一平坦化层直接接触。
其中，钝化层与第一平坦化层是两个连续的绝缘层(或者视为一个绝缘层的两个子层)，故参照图20，钝化层中的过孔是与第一平坦化层中的过孔完全一样的。
因此，本公开实施例的所有描述中，第一平坦化层中的过孔也可包括钝化层中的过孔，在此不再详细描述。
(10)第二源漏层(SD2)。
第二源漏层由导电材料构成，例如由金属材料构成。
第二源漏层包括：辅助导电结构31、第二发光接入结构332。
其中，辅助导电结构31与第一电源信号端VDD交叠设置，且通过第一平坦化层中的过孔与第一电源信号端VDD连接；而第二发光接入结构332通过第一平坦化层中的过孔连接第一发光接入结构331。
以上降低第一电源信号Vdd的供电电阻的辅助导电结构31可位于第二源漏层中，并与第一电源信号端VDD连接。
而第二源漏层中还可包括与以上第一发光接入结构331连接的第二发光接入结构332，以供后续发光器件2的第一极通过第二发光接入结构332、第一发光接入结构331连接第七晶体管T7的第二极。
(11)第二平坦化层(PLN2)。
第二平坦化层由有机绝缘材料构成，用于消除下方结构的段差。
参照图21，第二平坦化层可包括：用于连接第二发光接入结构332和发光器件2的第一极的过孔(后续详细描述)。
(12)发光器件2的第一极。
其中，发光器件2的第一极通过第二平坦化层中的过孔连接第二发光接入结构332。
发光器件2的第一极可设于第二平坦化层上，并通过以上第二发 光接入结构332、第一发光接入结构331连接第七晶体管T7的第二极。
具体的，发光器件2的第一极可为有机发光二极管OLED的阳极(Anode)，其可由氧化铟锡(ITO)等金属氧化物导电材料构成。
在一些实施例中，在远离基底的方向上，显示基板还可继续依次包括以下的结构：
(13)像素界定层(PDL)。
像素界定层由有机绝缘材料构成，用于通过其中的开口限定发光器件2(如有机发光二极管OLED)的范围。
(14)发光器件2的发光层。
发光层是发光器件2中实际用于发光层。
具体的，发光器件2的发光层可为有机发光二极管OLED的发光层。有机发光二极管OLED的发光层由有机材料构成，其至少包括有机发光层(EML)，还可包括电子注入层(EIL)、电子传输层(ETL)、空穴注入层(HIL)、空穴传输层(HTL)等其它的层叠设置的辅助层。
其中，有机发光二极管OLED的发光层可为整层的结构，其在像素界定层的开口处与有机发光二极管OLED的阳极接触，从而形成有机发光二极管OLED。
(15)发光器件2的第二电极。
具体的，发光器件2的第二电极可为有机发光二极管OLED的阴极(Cathode)，有机发光二极管OLED的阴极可由铝等金属导电材料构成。
其中，有机发光二极管OLED的阴极可为整层的结构，从而其同时也是第二电源信号端VSS。
(16)封装层。
封装层可为有机层与无机层交替的层叠结构，用于将其它结构封装在其中，避免其它结构(尤其是发光层)与环境中的水、氧接触而老化。
其中，以上各层结构中的完整膜层，则可通过溶液工艺、沉积工艺等形成；而以上各层结构中若具有特定形状的结构，则可通过构图工艺形。
当然，以上介绍的具体层结构只是示意性的，其还可进行很多变化。
例如，各具体结构所处的层可有不同；再如，各晶体管的栅极也可位于比其有源区更靠近基底的层中，即各晶体管的也可以不是以上的“底栅型晶体管”，而是“顶栅型晶体管”等。
第四方面，本公开实施例提供一种显示装置，其包括：
上述的任意一种显示基板。
可将以上显示基板与其它器件(例如对盒盖板、柔性线路板、驱动芯片、电源组件等)组合形成具有显示功能的显示装置。
在一些实施例中，显示装置为有机发光二极管(OLED)显示装置。
由于采用了以上的显示基板，故本公开实施例的显示装置显示时亮度稳定，无闪烁现象，显示质量好。
本公开已经公开了示例实施例，并且虽然采用了具体术语，但它们仅用于并仅应当被解释为一般说明性含义，并且不用于限制的目的。在一些实例中，对本领域技术人员显而易见的是，除非另外明确指出，否则可单独使用与特定实施例相结合描述的特征、特性和/或元素，或可与其它实施例相结合描述的特征、特性和/或元件组合使用。因此，本领域技术人员将理解，在不脱离由所附的权利要求阐明的本公开的范围的情况下，可进行各种形式和细节上的改变。

Claims (25)

  1. 一种像素电路，其包括：
    发光模块，配置为进行发光；
    驱动模块，配置为在发光阶段根据驱动电压驱动所述发光模块发光；
    存储模块，所述存储模块配置为在所述发光阶段保持所述驱动电压，并向所述驱动模块提供所述驱动电压；
    第一晶体管，所述第一晶体管的第一极连接所述驱动模块获取所述驱动电压的位置，所述第一晶体管的第二极不与信号源直接连接；
    第二晶体管，所述第二晶体管的第一极连接所述第一晶体管的第一极，所述第二晶体管的第二极连接的结构与所述第一晶体管的第二极连接的结构不同；在所述发光阶段，所述第一晶体管的第二极的电压低于所述第一晶体管的第一极的电压，所述第二晶体管的第二极的电压高于所述第一晶体管的第一极的电压；
    稳压电容，所述稳压电容的第一极连接所述第一晶体管的第二极，所述稳压电容的第二极连接定压信号源。
  2. 根据权利要求1所述的像素电路，其中，还包括：
    第三晶体管，所述第三晶体管的第一极连接所述第一晶体管的第二极，所述第三晶体管的栅极连接所述第一晶体管的栅极；
    第四晶体管，所述第四晶体管的第一极连接所述第二晶体管的第二极，所述第四晶体管的栅极连接所述第二晶体管的栅极；
    所述发光模块包括发光器件；
    所述驱动模块包括驱动晶体管，所述驱动晶体管配置为根据其栅极的电压驱动所述发光器件发光；
    所述存储模块包括存储电容，所述存储电容的第一极连接所述驱 动晶体管的栅极，所述存储电容配置为在所述发光阶段使其第一极保持所述驱动电压，并向所述驱动模块提供所述驱动电压。
  3. 根据权利要求2所述的像素电路，其中，所述像素电路包括第一重置模块和写入模块；
    所述第一重置模块配置为根据初始化信号端和第一重置信号端的信号重置所述驱动晶体管的栅极的电压；所述第一重置模块包括：
    所述第一晶体管；
    所述第三晶体管，所述第三晶体管的第一极连接所述第一晶体管的第二极，所述第三晶体管的第二极连接所述初始化信号端，所述第三晶体管的栅极连接所述第一晶体管的栅极以及所述第一重置信号端；
    所述写入模块配置为根据栅信号端和数据信号端的信号向所述存储电容的第一极写入所述驱动电压；所述写入模块包括：
    所述第二晶体管；
    所述第四晶体管，所述第四晶体管的第一极连接所述第二晶体管的第二极，所述第四晶体管的第二极连接所述驱动晶体管的第二极，所述第四晶体管的栅极连接所述第二晶体管的栅极以及所述栅信号端；
    第五晶体管，所述第五晶体管的第一极连接所述驱动晶体管的第一极，所述第五晶体管的第二极连接所述数据信号端，所述第五晶体管的栅极连接所述栅信号端；
    第六晶体管，所述第六晶体管的第一极连接所述第一电源信号端，所述第六晶体管的第二极连接所述驱动晶体管的第一极，所述第六晶体管的栅极连接控制信号端；
    其中，
    所述驱动晶体管和发光器件串联在第一电源信号端与第二电源信号端之间；
    所述存储电容的第二极连接所述第一电源信号端；
    所述发光器件的第二极连接所述第二电源信号端。
  4. 根据权利要求3所述的像素电路，其中，
    所述定压信号源为所述初始化信号端、所述第一电源信号端、所述第二电源信号端中的任意一者。
  5. 根据权利要求3所述的像素电路，其中，还包括：
    控制模块，所述控制模块配置为根据所述控制信号端的信号控制所述发光器件是否发光；所述控制模块包括：第七晶体管，所述第七晶体管的第一极连接所述驱动晶体管的第二极，所述第七晶体管的第二极连接所述发光器件的第一极，所述第七晶体管的栅极连接所述控制信号端；
    第二重置模块，所述第二重置模块配置为根据第二重置信号端和所述初始化信号端的信号重置所述发光器件的第一极的电压；所述第二重置模块包括：第八晶体管，所述第八晶体管的第一极连接所述发光器件的第一极，所述第八晶体管的第二极连接所述初始化信号端，所述第八晶体管的栅极连接所述第二重置信号端。
  6. 根据权利要求5所述的像素电路，其中，
    所述驱动晶体管、第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第八晶体管均为P型晶体管；
    或者，
    所述驱动晶体管、第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第八晶体管均为N型晶体管。
  7. 一种像素电路的驱动方法，其中，所述像素电路为权利要求1至6中任意一项所述的像素电路，所述像素电路的驱动方法包括：
    在发光阶段，使所述存储模块保持所述驱动电压，并向所述驱动模块提供所述驱动电压。
  8. 根据权利要求7所述的像素电路的驱动方法，其中，所述像素电路为3至6中任意一项所述的像素电路，所述像素电路的驱动方法包括：
    持续向所述初始化信号端提供初始化信号，持续向所述第一电源信号端提供第一电源信号，持续向所述第二电源信号端提供第二电源信号；
    在重置阶段，向所述第一重置信号端提供导通信号，向所述栅信号端提供关断信号，向所述控制信号端提供关断信号；
    在写入阶段，向所述第一重置信号端提供关断信号，向所述栅信号端提供导通信号，向所述控制信号端提供关断信号，向所述数据信号端提供数据信号；
    在所述发光阶段，向所述第一重置信号端提供关断信号，向所述栅信号端提供关断信号，向所述控制信号端提供导通信号。
  9. 根据权利要求8所述的像素电路的驱动方法，其中，所述像素电路为权利要求5或6所述的像素电路，所述像素电路的驱动方法还包括：
    在所述重置阶段，向所述第二重置信号端提供关断信号；
    在所述写入阶段，向所述第二重置信号端提供导通信号；
    在所述发光阶段，向所述第二重置信号端提供关断信号。
  10. 一种显示基板，其中，包括：
    基底；
    设于所述基底上的多个子像素，至少部分所述子像素包括权利要求1至6中任意一项所述的像素电路。
  11. 根据权利要求10所述的显示基板，其中，
    所述像素电路为权利要求3至6中任意一项所述的像素电路；
    所述稳压电容的第一极包括：连接在所述第三晶体管的第一极与所述第一晶体管的第二极之间的连接部；与所述连接部相连的附加部。
  12. 根据权利要求10所述的显示基板，其中，
    所述稳压电容的第一极与所述第一晶体管的第二极同层设置并连为一体。
  13. 根据权利要求12所述的显示基板，其中，
    所述稳压电容的第一极与所述驱动晶体管的有源区同层设置，所述稳压电容的第一极为导体化的半导体材料；
    所述第一晶体管的第二极与所述驱动晶体管的有源区同层设置，所述第一晶体管的第二极为导体化的半导体材料。
  14. 根据权利要求13所述的显示基板，其中，
    所述像素电路为权利要求3至6中任意一项所述的像素电路；
    所述稳压电容的第二极与所述初始化信号端同层设置并连为一体。
  15. 根据权利要求14所述的显示基板，其中，在逐渐远离所述基底的方向上，所述显示基板依次包括：
    所述驱动晶体管的有源区和所述稳压电容的第一极；
    栅绝缘层；
    所述驱动晶体管的栅极；
    第一层间绝缘层；
    所述稳压电容的第二极和所述初始化信号端。
  16. 根据权利要求10所述的显示基板，其中，
    所述像素电路为权利要求5或6所述的像素电路；
    所述初始化信号端包括同层设置的第一初始化信号端和第二初始化信号端，所述第一初始化信号端和第二初始化信号端平行且间隔设置；
    所述第八晶体管的第二极连接所述第一初始化信号端；
    所述第三晶体管的第二极连接所述第二初始化信号端。
  17. 根据权利要求10所述的显示基板，其中，
    所述像素电路为权利要求3至6中任意一项所述的像素电路；
    所述稳压电容的第一极沿第一方向延伸；
    所述数据信号端和/或所述第一电源信号端沿第二方向延伸；所述第一方向与所述第二方向交叉。
  18. 根据权利要求10所述的显示基板，其中，
    所述像素电路为权利要求5或6所述的像素电路；
    所述第一重置信号端沿第一方向延伸；
    至少部分所述像素电路的所述第一重置信号端，复用为沿第二方向与该像素电路相邻的所述像素电路的所述第二重置信号端；所述第一方向与所述第二方向交叉。
  19. 根据权利要求10所述的显示基板，其中，
    所述像素电路为权利要求3至6中任意一项所述的像素电路；
    所述存储电容的第二极包括沿第一方向延伸的横连结构；至少部分沿第一方向相邻的所述像素电路的所述横连结构相互连接；
    所述第一电源信号端沿第二方向延伸；所述第一方向与所述第二方向交叉。
  20. 根据权利要求10所述的显示基板，其中，所述像素电路为权利要求3至6中任意一项所述的像素电路；所述显示基板还包括：
    与所述第一电源信号端交叠设置的辅助导电结构；所述辅助导电结构与所述第一电源信号端间设有至少一个绝缘层，且所述辅助导电结构通过所述绝缘层中的过孔与所述第一电源信号端连接。
  21. 根据权利要求10所述的显示基板，其中，所述像素电路为权利要求5或6所述的像素电路；在逐渐远离所述基底的方向上，所述显示基板依次包括：
    半导体层，其包括：所述驱动晶体管的第一极、第二极、有源区，所述第一晶体管的第一极、第二极、有源区，所述第二晶体管的第一极、第二极、有源区，所述第三晶体管的第一极、第二极、有源区，所述第四晶体管的第一极、第二极、有源区，所述第五晶体管的第一极、第二极、有源区，所述第六晶体管的第一极、第二极、有源区，所述第七晶体管的第一极、第二极、有源区，所述第八晶体管的第一极、第二极、有源区，所述稳压电容的第一极；其中，所述稳压电容的第一极与所述第一晶体管的第二极连为一体，且均为导体化的半导体材料；
    栅绝缘层；
    第一栅极层，其包括：所述驱动晶体管的栅极，所述第一晶体管 的栅极，所述第二晶体管的栅极，所述第三晶体管的栅极，所述第四晶体管的栅极，所述第五晶体管的栅极，所述第六晶体管的栅极，所述第七晶体管的栅极，所述第八晶体管的栅极，所述第一重置信号端，所述第二重置信号端，所述控制信号端，所述存储电容的第一极；
    第一层间绝缘层；
    第二栅极层，其包括：所述初始化信号端，所述稳压电容的第二极，所述存储电容的第二极；其中，所述稳压电容的第二极与所述初始化信号端连为一体；
    第二层间绝缘层；
    第一源漏层，其包括：所述第一电源信号端，所述数据信号端，第一发光接入结构；其中，所述第一电源信号端通过所述第二层间绝缘层中的过孔连接所述存储电容的第二极，且通过所述栅绝缘层、所述第一层间绝缘层、所述第二层间绝缘层中的过孔连接所述第六晶体管的第一极；所述数据信号端通过所述栅绝缘层、所述第一层间绝缘层、所述第二层间绝缘层中的过孔连接所述第五晶体管的第二极，所述第一发光接入结构通过所述栅绝缘层、所述第一层间绝缘层、所述第二层间绝缘层中的过孔连接所述第七晶体管的第二极；
    第一平坦化层；
    第二源漏层，其包括：辅助导电结构、第二发光接入结构；其中，所述辅助导电结构与所述第一电源信号端交叠设置，且通过所述第一平坦化层中的过孔与所述第一电源信号端连接；所述第二发光接入结构通过所述第一平坦化层中的过孔连接所述第一发光接入结构；
    第二平坦化层；
    所述发光器件的第一极，所述发光器件的第一极通过所述第二平坦化层中的过孔连接所述第二发光接入结构。
  22. 根据权利要求21所述的显示基板，其中，所述第二栅极层还包括：
    屏蔽结构，所述屏蔽结构通过所述第二层间绝缘层中的过孔连接所述第一电源信号端，所述屏蔽结构与所述第一晶体管的第一极、所述第五晶体管的第二极存在交叠且绝缘。
  23. 根据权利要求21所述的显示基板，其中，所述第一源漏层还包括：
    第一连接结构，所述第一连接结构通过所述栅绝缘层、所述第一层间绝缘层、所述第二层间绝缘层中的过孔连接所述第八晶体管的第二极，并通过所述第二层间绝缘层中的过孔连接所述初始化信号端；
    第二连接结构，所述第二连接结构通过所述栅绝缘层、所述第一层间绝缘层、所述第二层间绝缘层中的过孔连接所述第三晶体管的第二极，并通过所述第二层间绝缘层中的过孔连接所述初始化信号端；
    第三连接结构，所述第三连接结构通过所述第一层间绝缘层、所述第二层间绝缘层中的过孔连接所述驱动晶体管的栅极，并通过所述栅绝缘层、所述第一层间绝缘层、所述第二层间绝缘层中的过孔连接所述第一晶体管的第一极。
  24. 根据权利要求10所述的显示基板，其中，
    所述稳压电容的电容值不低于8fF，且不超过所述存储电容的电容值的四分之一。
  25. 一种显示装置，其中，包括：
    权利要求10至24中任意一项所述的显示基板。
PCT/CN2020/132090 2020-11-27 2020-11-27 像素电路及其驱动方法、显示基板、显示装置 WO2022109984A1 (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CN202410064244.XA CN117711325A (zh) 2020-11-27 2020-11-27 像素电路、显示基板和显示装置
CN202080003064.0A CN114902321B (zh) 2020-11-27 2020-11-27 像素电路及其驱动方法、显示基板、显示装置
PCT/CN2020/132090 WO2022109984A1 (zh) 2020-11-27 2020-11-27 像素电路及其驱动方法、显示基板、显示装置
US17/424,965 US11721286B2 (en) 2020-11-27 2020-11-27 Pixel circuit and driving method thereof, display substrate and display device
US18/346,157 US20230351969A1 (en) 2020-11-27 2023-06-30 Pixel circuit and driving method thereof, display substrate and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/132090 WO2022109984A1 (zh) 2020-11-27 2020-11-27 像素电路及其驱动方法、显示基板、显示装置

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US17/424,965 A-371-Of-International US11721286B2 (en) 2020-11-27 2020-11-27 Pixel circuit and driving method thereof, display substrate and display device
US18/346,157 Continuation-In-Part US20230351969A1 (en) 2020-11-27 2023-06-30 Pixel circuit and driving method thereof, display substrate and display device

Publications (1)

Publication Number Publication Date
WO2022109984A1 true WO2022109984A1 (zh) 2022-06-02

Family

ID=81755126

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/132090 WO2022109984A1 (zh) 2020-11-27 2020-11-27 像素电路及其驱动方法、显示基板、显示装置

Country Status (3)

Country Link
US (1) US11721286B2 (zh)
CN (2) CN117711325A (zh)
WO (1) WO2022109984A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120019504A1 (en) * 2010-07-20 2012-01-26 Sam-Il Han Pixel and organic light emitting display device using the same
CN110992880A (zh) * 2019-12-19 2020-04-10 武汉天马微电子有限公司 一种显示面板及显示装置
CN111477179A (zh) * 2020-05-20 2020-07-31 京东方科技集团股份有限公司 一种像素驱动电路及其驱动方法、显示装置
CN111613177A (zh) * 2020-06-28 2020-09-01 上海天马有机发光显示技术有限公司 一种像素电路及其驱动方法、显示面板和显示装置
CN111627387A (zh) * 2020-06-24 2020-09-04 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板及显示装置

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI288900B (en) * 2004-04-30 2007-10-21 Fujifilm Corp Active matrix type display device
JP4846999B2 (ja) * 2004-10-20 2011-12-28 株式会社 日立ディスプレイズ 画像表示装置
WO2013065594A1 (ja) * 2011-11-02 2013-05-10 シャープ株式会社 カラー表示装置
CN104064139B (zh) * 2014-06-05 2016-06-29 上海天马有机发光显示技术有限公司 一种有机发光二极管像素补偿电路、显示面板和显示装置
KR102627074B1 (ko) * 2016-12-22 2024-01-22 엘지디스플레이 주식회사 표시소자, 표시장치 및 데이터 구동부
KR102663039B1 (ko) * 2017-02-28 2024-05-07 엘지디스플레이 주식회사 전계 발광 표시장치
US10504431B2 (en) * 2018-03-27 2019-12-10 Sharp Kabushiki Kaisha TFT pixel threshold voltage compensation circuit with light-emitting device initialization
CN208335702U (zh) * 2018-05-14 2019-01-04 北京京东方技术开发有限公司 显示面板及显示装置
CN108847186B (zh) 2018-06-29 2021-05-25 昆山国显光电有限公司 像素电路及其驱动方法、显示面板及显示装置
KR20200016425A (ko) * 2018-08-06 2020-02-17 삼성디스플레이 주식회사 유기발광 표시 장치
US20200202783A1 (en) * 2018-12-21 2020-06-25 Int Tech Co., Ltd. Pixel compensation circuit
CN110706654B (zh) * 2019-09-12 2020-12-08 深圳市华星光电半导体显示技术有限公司 一种oled像素补偿电路及oled像素补偿方法
CN110610684B (zh) 2019-10-29 2021-03-30 厦门天马微电子有限公司 一种有机电致发光显示面板及显示装置
CN111179859B (zh) 2020-03-16 2021-03-02 京东方科技集团股份有限公司 一种像素电路、显示面板及显示装置
CN111445858A (zh) * 2020-04-20 2020-07-24 昆山国显光电有限公司 像素电路及其驱动方法、显示装置
CN111445848B (zh) 2020-04-30 2021-10-08 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示基板
CN111489701B (zh) 2020-05-29 2021-09-14 上海天马有机发光显示技术有限公司 阵列基板及其驱动方法、显示面板和显示装置
CN113871418A (zh) * 2020-06-30 2021-12-31 京东方科技集团股份有限公司 显示面板和显示装置
CN113963667B (zh) * 2020-07-21 2023-04-18 京东方科技集团股份有限公司 一种显示装置及其驱动方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120019504A1 (en) * 2010-07-20 2012-01-26 Sam-Il Han Pixel and organic light emitting display device using the same
CN110992880A (zh) * 2019-12-19 2020-04-10 武汉天马微电子有限公司 一种显示面板及显示装置
CN111477179A (zh) * 2020-05-20 2020-07-31 京东方科技集团股份有限公司 一种像素驱动电路及其驱动方法、显示装置
CN111627387A (zh) * 2020-06-24 2020-09-04 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板及显示装置
CN111613177A (zh) * 2020-06-28 2020-09-01 上海天马有机发光显示技术有限公司 一种像素电路及其驱动方法、显示面板和显示装置

Also Published As

Publication number Publication date
CN114902321A (zh) 2022-08-12
CN117711325A (zh) 2024-03-15
CN114902321B (zh) 2024-01-30
US11721286B2 (en) 2023-08-08
US20230137937A1 (en) 2023-05-04

Similar Documents

Publication Publication Date Title
KR102034254B1 (ko) 박막 트랜지스터 어레이 기판, 이를 포함하는 유기 발광 표시 장치 및 유기 발광 표시 장치의 제조 방법
US9397124B2 (en) Organic light-emitting diode display with double gate transistors
US9472605B2 (en) Organic light-emitting diode display with enhanced aperture ratio
KR102465435B1 (ko) 표시 장치
JP6031954B2 (ja) 発光素子、表示装置及び電子機器
TWI555182B (zh) 用於顯示像素臨限電壓補償電路之電容結構
JP2005316384A (ja) 発光表示パネル及び発光表示装置
JP2005338754A (ja) 発光表示装置及び発光表示パネル
JP2005338781A (ja) 有機電界発光表示パネル及びその製造方法
WO2021189335A1 (zh) 显示面板和显示装置
CN114093299B (zh) 显示面板和显示装置
US20240135879A1 (en) Display substrate and display apparatus
TW201442221A (zh) 薄膜電晶體及有機發光二極體顯示器
US11925082B2 (en) Display panel and display device
EP4319536A1 (en) Display device
WO2022109984A1 (zh) 像素电路及其驱动方法、显示基板、显示装置
WO2022226882A1 (zh) 显示面板及显示装置
WO2022110015A1 (zh) 显示基板、显示面板、显示装置
WO2022147679A1 (zh) 显示面板、显示装置
US20230351969A1 (en) Pixel circuit and driving method thereof, display substrate and display device
WO2023173411A1 (zh) 像素驱动电路及其驱动方法、显示装置
WO2022052229A1 (zh) 像素电路、显示基板和显示装置
KR20050104605A (ko) 발광 표시 장치
KR100627266B1 (ko) 발광 표시 패널 및 발광 표시 장치
KR100560451B1 (ko) 발광 표시 장치

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20962875

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 19.09.2023)

122 Ep: pct application non-entry in european phase

Ref document number: 20962875

Country of ref document: EP

Kind code of ref document: A1