WO2022147679A1 - 显示面板、显示装置 - Google Patents

显示面板、显示装置 Download PDF

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Publication number
WO2022147679A1
WO2022147679A1 PCT/CN2021/070439 CN2021070439W WO2022147679A1 WO 2022147679 A1 WO2022147679 A1 WO 2022147679A1 CN 2021070439 W CN2021070439 W CN 2021070439W WO 2022147679 A1 WO2022147679 A1 WO 2022147679A1
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WO
WIPO (PCT)
Prior art keywords
light
emitting unit
pixel
signal line
display panel
Prior art date
Application number
PCT/CN2021/070439
Other languages
English (en)
French (fr)
Other versions
WO2022147679A9 (zh
Inventor
黄耀
程羽雕
刘聪
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180000018.XA priority Critical patent/CN115280406A/zh
Priority to PCT/CN2021/070439 priority patent/WO2022147679A1/zh
Priority to EP21916737.6A priority patent/EP4141858A4/en
Priority to US17/620,371 priority patent/US20230157097A1/en
Publication of WO2022147679A1 publication Critical patent/WO2022147679A1/zh
Publication of WO2022147679A9 publication Critical patent/WO2022147679A9/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0216—Interleaved control phases for different scan lines in the same sub-field, e.g. initialization, addressing and sustaining in plasma displays that are not simultaneous for all scan lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • the under-screen camera technology is to set a light-transmitting area on the display panel, and set the camera facing the light-transmitting area to achieve full-screen display.
  • the light-emitting unit in order to improve the light transmittance of the light-transmitting area, generally only the light-emitting unit is provided in the light-transmitting area, and a pixel driving circuit for driving the light-emitting unit is provided outside the light-transmitting area.
  • the data lines for providing data signals to the pixel driving circuit need to be connected to the pixel driving circuit by means of wiring.
  • this wiring method often occupies the edge wiring area of the display panel, thereby increasing the width of the frame of the display panel.
  • a display panel includes a light transmission area, a main display area, a first transition display area and a first wiring area, the first transition display area is located in the light transmission area
  • the first wiring area is located on one side of the first transition display area and the light-transmitting area in the second direction
  • the main display area is located on the first wiring area. A side of the area away from the first transition display area and the light-transmitting area, wherein the first direction and the second direction intersect.
  • the display panel further includes: a first light-emitting unit, a first pixel driving circuit, a first signal line, a second signal line, and a third signal line, the first light-emitting unit is located in the light-transmitting area; the first pixel driving circuit is located in the light-transmitting area.
  • the first transition display area is used for providing driving current to the first light emitting unit; the first signal line extends along the second direction, and at least part of the first signal line is located in the first transition display area, used for providing a potential signal to the first pixel driving circuit;
  • the second signal line extends along the second direction, and the second signal line is at least partially located in the main display area, and is used for connecting with the main display area to the main display area.
  • the pixel driving circuit where the first light-emitting unit is located in the same sub-pixel column provides a potential signal; the third signal line extends along the first direction, at least part of the third signal line is located in the first wiring area, and the third signal line extends along the first direction.
  • the three signal lines are respectively connected to the first signal line and the second signal line through via holes.
  • the display panel further includes a second transition display area, and the second transition display area is disposed adjacent to one side of the first wiring area in the second direction, so
  • the display panel further includes: a second light-emitting unit and a second pixel driving circuit, the second light-emitting unit is located in the first wiring area; the second pixel driving circuit is located in the second transition display area, and is used for sending the second light-emitting unit to the first wiring area.
  • Two light-emitting units provide driving current.
  • the second transitional display area is located between the first wiring area and the first transitional display area or the light-transmitting area, or the second transitional display area is located in any between the first wiring area and the main display area.
  • the second light-emitting unit and the second pixel driving circuit connected thereto are located in the same sub-pixel column.
  • each of the second pixel driving circuits and the second light-emitting units connected thereto are in the first
  • the sub-pixel rows are equally spaced in both directions.
  • the display panel further includes a first sub-pixel, the first sub-pixel is located in the second transition display area, and the first sub-pixel includes: a third light-emitting unit, a first sub-pixel There are three pixel driving circuits, and the third pixel driving circuit is used for providing driving current to the third light emitting unit.
  • the display panel further includes a second sub-pixel, the second sub-pixel is located in the first transition display area, and the second sub-pixel includes: a fourth light-emitting unit, a second sub-pixel A four-pixel driving circuit, the fourth pixel driving circuit is used for providing a driving current to the fourth light-emitting unit; the fourth pixel driving circuit and the first pixel driving circuit are located in different columns.
  • both the first light-emitting unit and the first pixel driving circuit are multiple, and the first pixel driving circuit and the first light-emitting unit connected thereto are located in the same row, Each of the first pixel driving circuits and the first light emitting units connected thereto are spaced apart by the same sub-pixel column in the first direction.
  • the display panel further includes: a base substrate, a first conductive layer, a second conductive layer, and a third conductive layer, and the first conductive layer is disposed on one side of the base substrate
  • the second conductive layer is disposed on the side of the first conductive layer away from the base substrate
  • the third conductive layer is disposed on the side of the second conductive layer away from the base substrate, at least part of the first conductive layer
  • Three conductive layers are used to form the first signal line and the second signal line.
  • the first signal line, the second signal line, and the third signal line are all multiple, and the third signal line is connected to the corresponding first signal line and the third signal line.
  • the plurality of third signal lines include a plurality of first sub-signal lines and a plurality of second sub-signal lines, and at least part of the first conductive layer is used to form the first sub-signal lines; At least part of the second conductive layer is used to form the second sub-signal line; wherein, the orthographic projection of the first sub-signal line on the base substrate and the second sub-signal line on the substrate The orthographic projections of the substrates are alternately distributed in sequence along the second direction.
  • the first signal line, the second signal line, and the third signal line are all multiple, and the third signal line is connected to the corresponding first signal line and the third signal line.
  • the third signal line is formed by at least part of the first conductive layer; wherein, the third signal line is distributed in sequence along the second direction in an orthographic projection of the base substrate.
  • the first signal line, the second signal line, and the third signal line are all multiple, and the third signal line is connected to the corresponding first signal line and the third signal line.
  • the third signal line is formed by at least a part of the second conductive layer; wherein, the third signal line is spaced in sequence along the second direction in the orthographic projection of the base substrate.
  • the first pixel driving circuit includes a driving transistor, and a capacitor connected to a gate of the driving transistor; a part of the first conductive layer is used to form the gate of the driving transistor , part of the second conductive layer is used to form an electrode of the capacitor; the first signal line is used to provide a data signal to the gate of the driving transistor.
  • the display panel further includes a fourth conductive layer, the fourth conductive layer is located on a side of the third conductive layer away from the base substrate, at least part of the fourth conductive layer
  • the fourth conductive layer further includes a first connection line, and the first connection line is used for connecting the second pixel driving circuit and the anode of the second light-emitting unit.
  • the display panel further includes a fifth transparent conductive layer, the fifth transparent conductive layer is located between the third conductive layer and the fourth conductive layer, and the fifth transparent conductive layer is located between the third conductive layer and the fourth conductive layer.
  • the layer includes a second connection line for connecting the first pixel driving circuit and the anode of the first light emitting unit.
  • the pixel density of the main display area is greater than the pixel density of the first wiring area, the first transition display area, the second transition display area, and the light-transmitting area.
  • the pixel density of the first wiring area, the first transition display area, the second transition display area, and the light transmission area are the same.
  • the first direction is a row direction
  • the second direction is a column direction
  • the first wiring area the first transition display area, the second transition display area, the light transmission area
  • the display panel includes a plurality of first pixel units, and the plurality of first pixel units are located in the low pixel density area; wherein, in the row direction, adjacent first pixel units are separated by the same number of pixels.
  • the pixel units, in the column direction are adjacent to the first pixel units separated by the same number of pixel units.
  • adjacent first pixel units are separated by three pixel units, and in the column direction, adjacent first pixel units are separated by one pixel unit.
  • adjacent first pixel units are separated by three pixel units, and in the second direction, adjacent first pixel units are separated by one pixel unit.
  • the first pixel unit includes: an R light-emitting unit, a first G light-emitting unit, a B light-emitting unit, and a second G light-emitting unit, and the first G light-emitting unit and the R light-emitting unit are located in the same row and adjacent to the R light-emitting unit in the first direction; the B light-emitting unit and the R light-emitting unit are located in the same column and adjacent to the R light-emitting unit in the second direction; the second The G light-emitting unit is located in the same row as the B light-emitting unit, and is located in the same column as the first G light-emitting unit, and is arranged adjacent to the B light-emitting unit in the first direction, and is adjacent to the first G light-emitting unit in the second direction.
  • the light emitting units are arranged adjacently.
  • the R light-emitting unit, the first G light-emitting unit, the B light-emitting unit, and the second G light-emitting unit located in the light-transmitting area form the first light-emitting unit;
  • the R light-emitting unit located in the first wiring area The light emitting unit, the first G light emitting unit, the B light emitting unit, and the second G light emitting unit form the second light emitting unit;
  • the R light emitting unit, the first G light emitting unit, and the B light emitting unit located in the second transition display area , the second G light-emitting unit forms the third light-emitting unit;
  • the R light-emitting unit, the first G light-emitting unit, the B light-emitting unit, and the second G light-emitting unit located in the first transition display area form the fourth light-emitting unit unit.
  • the size of the first wiring region in the second direction is equal to the size of the first pixel unit in the second direction.
  • the size of the second transition display area in the second direction is equal to the size of the first pixel unit in the second direction.
  • a display device comprising: the above-mentioned display panel and a camera, wherein the camera is directly opposite to a light-transmitting area of the display panel.
  • FIG. 1 is a schematic structural diagram of a display panel in the related art
  • Fig. 2 is a partial enlarged view of the dotted line frame A in Fig. 1;
  • FIG. 3 is a schematic structural diagram of an exemplary embodiment of a display panel of the present disclosure
  • FIG. 4 is a schematic structural diagram of a first pixel driving circuit in an exemplary embodiment of a display panel of the present disclosure
  • FIG. 5 is a timing diagram of each node in a driving method of the pixel driving circuit of FIG. 4;
  • FIG. 6 is a structural layout of an exemplary embodiment of a display panel of the present disclosure.
  • Fig. 7 is the structural layout of the active layer in Fig. 6;
  • Fig. 8 is the structural layout of the first conductive layer in Fig. 6;
  • Fig. 9 is the structural layout of the second conductive layer in Fig. 6;
  • Fig. 10 is the structural layout of the third conductive layer in Fig. 6;
  • FIG. 11 is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure.
  • FIG. 12 is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure.
  • Fig. 13 is a partial enlarged view of the display panel in Fig. 12;
  • Figure 14 is a partial enlarged view of the dotted line frame C in Figure 13;
  • FIG. 15 is a cross-sectional view taken along the dotted line AA in FIG. 14 .
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • FIG. 1 is a schematic structural diagram of a display panel in the related art
  • FIG. 2 is a partial enlarged view of the dotted frame A in FIG. 1
  • the display panel includes a main display area 1 , a light-transmitting area 3 , a transition display area 2 , and an edge wiring area 9 .
  • the sub-pixel P with the light-emitting unit and the pixel driving circuit D without the light-emitting unit are arranged in the transition display area 2 of the display panel.
  • the display panel can provide driving current to the light-emitting unit A located in the light-transmitting area 3 through the pixel driving circuit D located in the transition display area 2 . Since the light-transmitting area 3 is not provided with a pixel driving circuit, the light-transmitting area has a higher light transmittance. As shown in FIG. 2 , in order to achieve normal driving, the data line d1 located in the same sub-pixel column as the light-emitting unit A needs to be connected to a pixel driving circuit D that provides driving current to the light-emitting unit A. In the related art, as shown in FIG.
  • the data line d1 is connected to the pixel driving circuit D in the transition display area 2, and a plurality of gate lines g are arranged in the edge routing area 9. It is connected with the gate line g one-to-one through the via hole; at the same time, in the transition display area 2, the pixel driving circuit D located in the same sub-pixel column is connected through the data line d2, and the data line d2 can be connected with the gate line g one-to-one through the via hole. corresponding connection.
  • the gate g can be connected to the data line d1 and the data line d2, so that the data line d1 is connected to the pixel driving circuit D.
  • the gate line g will occupy a certain edge routing area 9, thus affecting the realization of the narrow frame; on the other hand, the gathering area B will occupy a certain space, thereby affecting the area of the light transmission area 3; 2, the data line d1 in FIG. 2 needs to be connected to the pixel drive circuit D in the transition display area 2 by winding in the edge routing area 9, so that the connection lines between different data lines d1 and the pixel drive circuit D have different length. Under the action of the same data signal, due to different voltage drops of different connecting lines, different pixel driving circuits D will receive different data signals, thereby affecting the display uniformity of the display panel.
  • the present exemplary embodiment provides a display panel, as shown in FIG. 3 , which is a schematic structural diagram of an exemplary embodiment of the display panel of the present disclosure.
  • the display panel may include a light transmission area 3, a main display area 1, a first transition display area 2 and a first wiring area 4; the first transition display area 2 may be located in the light transmission area 3 in the first direction. Both sides on Y; the first routing area 4 may be located on one side of the first transition display area 2 and the light-transmitting area 3 in the second direction X, wherein the first direction and the second direction intersect,
  • the first direction may be the row direction
  • the second direction may be the column direction;
  • FIG. 3 is a schematic structural diagram of an exemplary embodiment of the display panel of the present disclosure.
  • the display panel may include a light transmission area 3, a main display area 1, a first transition display area 2 and a first wiring area 4; the first transition display area 2 may be located in the light transmission area 3 in the first direction. Both sides on Y; the first routing
  • the display panel may further include: a first light-emitting unit A1, a first pixel driving circuit D1, a first signal line d1, a second signal line d2, a third signal line g3, and a first light-emitting unit A1 is located in the light-transmitting area 3;
  • the first pixel driving circuit D1 is located in the first transition display area 2, and is used to provide driving current to the first light-emitting unit A1;
  • the first signal line d1 extends along the second direction, and the At least part of a signal line d1 may be located in the first transition display area 2 for providing a potential signal to the first pixel driving circuit D1;
  • the second signal line d2 extends along the second direction, and the second signal line d2 At least part of it may be located in the main display area 1, and the second signal line d2 may be used to provide a potential signal to the pixel driving circuit in the main display area.
  • the second signal line d2 may be used to supply the main display area.
  • the pixel driving circuit located in the same sub-pixel column as the first light-emitting unit A1 provides a potential signal;
  • the third signal line g3 may extend along the first direction, and at least part of the third signal line g3 is located in the first wiring area 4.
  • the first signal line d1 and the second signal line d2 can extend to the first wiring area 4, so that the third signal line g3 can pass through the via hole and the corresponding first signal line g3 respectively.
  • the signal line d1 and the second signal line d2 are connected.
  • first light-emitting units A1 and first pixel driving circuits D1 there may be multiple first light-emitting units A1 and first pixel driving circuits D1, multiple first light-emitting units A1 may be located in different sub-pixel columns, and multiple first pixel driving circuits Circuits D1 may be located in different sub-pixel columns.
  • the first signal line d1 and the second signal line d2 can be data lines, and each of the first signal lines d1 can be connected to the first pixel driving circuit D1 located in the same sub-pixel column in the first transition display area 2, and used to connect to the first pixel driving circuit D1.
  • the connected first pixel driving circuit D1 provides data signals.
  • Each of the second signal lines d2 may be connected to pixel driving circuits located in the same sub-pixel column in the main display area 1, and used to provide data signals to the pixel driving circuits connected thereto.
  • the first signal line d1 and the second signal line d2 may be located in the same conductive layer, and the third signal line g3 and the first signal line d1 and the second signal line d2 may be located in a different conductive layer.
  • the first signal line and the second signal line may also be other signal lines, for example, the first signal line and the second signal line may also be sensing lines and the like.
  • the display panel sets the first wiring area 4 between the main display area 1 , the first transition display area 2 , and the light-transmitting area 3 , and the first signal line d1
  • the second signal line d2 can be connected through the third signal line g3 located in the first routing area 4, thereby avoiding the data line winding in the edge routing area, which is beneficial to realize a display panel with a narrow frame.
  • the data lines in the display panel do not need to be wound, and the difference in length of different data lines is small, so that the uniformity of light emission of the display panel can be improved.
  • the display panel does not need to be provided with the cluster area B in the related art, so that a larger space can be reserved for the light transmission area.
  • the display panel may further include: a plurality of second sub-pixels P2 , and the plurality of second sub-pixels P2 may be located in the first transition display area 2 .
  • Each second sub-pixel P2 may include a fourth pixel driving circuit and a fourth light-emitting unit, that is, the second sub-pixel P2 may emit light under the normal driving action of the display panel.
  • the second sub-pixel P2 can realize the normal display of the first transition display area 2 .
  • the pixel density of the first transition display area 2 (that is, formed by the second sub-pixel P2 The density of pixel units) is smaller than the pixel density of the main display area.
  • the pixel density of the light-transmitting area 3 (ie, the density of the pixel units formed by the first light-emitting unit) may also be smaller than the pixel density of the main display area.
  • the pixel density of the light transmission area 3 may be equal to the pixel density of the first transition display area 2 .
  • the second sub-pixel P2 and the first pixel driving circuit D1 may be located in different columns, and this arrangement may enable the first signal line d1 for connecting the first pixel driving circuit D1 to be the same as the first signal line d1 for connecting the second sub-pixel
  • the data lines of the pixel P2 are located in different columns, thereby avoiding the overlapping of the first signal line d1 with the data line for connecting the second sub-pixel P2.
  • the display panel may further include a source driving circuit 5 , and the source driving circuit 5 may be located on a side of the main display area 1 away from the first wiring area 4 .
  • the source driving circuit 5 may be used to supply data signals to the data lines d2 connected thereto.
  • the display panel is located in the light-transmitting area 3, and the side of the first transition display area 2 away from the first wiring area 4 may not be provided with pixel units, so that the first signal line d1 does not need to be looped back directly above the light-transmitting area.
  • FIG. 4 it is a schematic structural diagram of a first pixel driving circuit in an exemplary embodiment of the display panel of the present disclosure.
  • the pixel driving circuit may include: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C.
  • the first pole of the first transistor T1 is connected to the node N, the second pole is connected to the initialization signal terminal Vinit, and the gate is connected to the reset signal terminal Re; the first pole of the second transistor T2 is connected to the first pole of the driving transistor T3, and the second pole is connected
  • the gate is connected to the gate driving signal terminal Gate; the gate of the driving transistor T3 is connected to the node N; the first pole of the fourth transistor T4 is connected to the data signal terminal Da, and the second pole is connected to the second pole of the driving transistor T3, The gate is connected to the gate driving signal terminal Gate;
  • the first pole of the fifth transistor T5 is connected to the first power supply signal terminal VDD, the second pole is connected to the second pole of the driving transistor T3, and the gate is connected to the enable signal terminal EM;
  • the sixth transistor The first pole of T6 is connected to the first pole of the driving transistor T3, and the gate is connected to the enable signal terminal EM; the first pole of the seventh transistor T7 is connected to the initialization signal terminal Vinit, and
  • the pixel driving circuit may be connected to a light-emitting unit OLED for driving the light-emitting unit OLED to emit light, and the light-emitting unit OLED may be connected between the second pole of the sixth transistor T6 and the second power terminal VSS.
  • the transistors T1-T7 may all be P-type transistors.
  • Other pixel driving circuits in the display panel may have the same structure as the first pixel driving circuit.
  • FIG. 5 it is a timing diagram of each node in a driving method of the pixel driving circuit of FIG. 4 .
  • Gate represents the timing of the gate driving signal terminal Gate
  • Re represents the timing of the reset signal terminal Re
  • EM represents the timing of the enable signal terminal EM
  • Da represents the timing of the data signal terminal Da.
  • the driving method of the pixel driving circuit may include a reset stage t1, a compensation stage t2, and a light-emitting stage t3.
  • the reset signal terminal Re outputs a low level signal
  • the first transistor T1 and the seventh transistor T7 are turned on
  • the initialization signal terminal Vinit inputs the initialization signal to the node N and the second pole of the sixth transistor T6.
  • the gate driving signal terminal Gate outputs a low level signal
  • the fourth transistor T4 and the second transistor T2 are turned on, and at the same time the data signal terminal Da outputs a data signal to write the voltage Vdata+Vth to the node N, where Vdata is the voltage of the data signal, and Vth is the threshold voltage of the driving transistor T3.
  • Light-emitting stage t3 the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 emits light under the action of the voltage Vdata+Vth stored in the capacitor C.
  • the driving transistor output current formula I ( ⁇ WCox/2L)(Vgs-Vth) 2 , where ⁇ is the carrier mobility; Cox is the gate capacitance per unit area, W is the channel width of the driving transistor, and L drives The length of the transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor.
  • the output current I ( ⁇ WCox/2L)(Vdata+Vth ⁇ Vdd ⁇ Vth) 2 of the driving transistor in the pixel driving circuit of the present disclosure.
  • the pixel driving circuit can avoid the influence of the threshold value of the driving transistor on its output current.
  • the display panel may include a base substrate 0, an active layer, a first conductive layer, a second conductive layer, and a third conductive layer that are stacked in sequence.
  • FIGS. 6, 7, 8, 9, and 10 FIG. 6 is a structural layout of an exemplary embodiment of a display panel of the present disclosure
  • FIG. 7 is a structural layout of the active layer in FIG. 6,
  • FIG. The structural layout of the first conductive layer FIG. 9 is the structural layout of the second conductive layer in FIG. 6
  • FIG. 10 is the structural layout of the third conductive layer in FIG. 6 .
  • the active layer may include a first active part 61 , a second active part 62 , a third active part 63 , a fourth active part 64 , a fifth active part 65 , a sixth active part
  • the active part 66 the seventh active part 67 , the eighth active part 68 , the tenth active part 610 , the eleventh active part 611 , the twelfth active part 612 , and the thirteenth active part 613 .
  • the second active part 62 can be used to form the first channel region of the second transistor T2
  • the third active part 63 can be used to form the second channel of the second transistor T2 Area.
  • the sixth active part 66 may be used to form the channel region of the driving transistor T3.
  • the seventh active part 67 may be used to form the first channel region of the first transistor T1, and the eighth active part 68 may be used to form the second channel region of the first transistor T1.
  • the tenth active part 610 may be used to form a channel region of the fourth transistor T4.
  • the eleventh active part 611 may be used to form a channel region of the fifth transistor T5.
  • the twelfth active part 612 may be used to form a channel region of the sixth transistor T6.
  • the thirteenth active part 613 may be used to form the channel region of the seventh transistor.
  • the fourth active part 64 may be connected between the second active part 62 and the third active part 63 .
  • the first conductive layer may include: a first conductive portion 11 , a second conductive portion 12 , a first grid line 13 , a second grid line 14 , a third grid line 17 , and a sixth conductive portion Section 16.
  • the first conductive portion 11 may also be a strip-shaped structure extending along the first direction Y, and the orthographic projection of the first conductive portion 11 on the base substrate may cover the orthographic projection of the sixth active portion 66 on the base substrate to form a drive.
  • gate of transistor T3 The second conductive portion 12 may be used to form part of the first electrode of the capacitor C.
  • the first gate line 13 may be used to provide the gate driving signal terminal in FIG. 5 .
  • the orthographic projection of the first grid line 13 on the base substrate may extend along the first direction Y, and the orthographic projection of the first grid line 13 on the base substrate may be located on the first conductive portion 11 Between the orthographic projection of the base substrate and the orthographic projection of the second conductive portion 12 on the base substrate, part of the conductive portion 131 of the first gate line 13 may be used to form the second transistor T2 For the first gate, part of the conductive portion 134 of the first gate line 13 may be used to form the gate of the fourth transistor T4.
  • the second gate line 14 may be used to provide the reset signal terminal in FIG. 1 .
  • the orthographic projection of the second grid line 14 on the base substrate extends along the first direction Y, and the orthographic projection of the second grid line 14 on the base substrate may be located where the second conductive portion 12 is located
  • the orthographic projection of the base substrate is away from the orthographic projection of the first gate line 13 on the side of the base substrate, and part of the conductive portion 141 of the second gate line 14 can be used to form the first gate line of the first transistor T1.
  • a gate, part of the conductive portion 142 of the second gate line 14 can be used to form the second gate of the first transistor T1.
  • the third gate line 17 may be used to provide the enable signal terminal in FIG. 5 .
  • the orthographic projection of the third grid line 17 on the base substrate may be located on the side of the orthographic projection of the first conductive portion 11 on the base substrate away from the orthographic projection of the first grid line 13 on the base substrate.
  • the third gate line 17 may include a conductive portion 175 and a conductive portion 176, the conductive portion 175 may be used to form the gate of the fifth transistor, and the conductive portion 176 may be used to form the gate of the sixth transistor.
  • the gate of the seventh transistor T7 may share the conductive portion 147 in the second gate line 14 corresponding to the next row of pixel units.
  • the orthographic projection of the sixth conductive portion 16 on the base substrate may extend along the second direction X and be connected to the first gate line 13 , and a part of the sixth conductive portion 16 may be used to form the second transistor T2 . second gate.
  • the second conductive layer may include a third conductive portion 23 , and the orthographic projection of the third conductive portion 23 on the base substrate may be the same as that of the second conductive portion 12 on the base substrate.
  • the orthographic projections at least partially overlap, and the third conductive portion 23 is electrically connected to the first conductive portion 11 , and the third conductive portion 23 can be used to form the second electrode of the capacitor C.
  • the third conductive layer may include a fourth conductive part 34 , a first connection part 31 , a power line 321 , a fifth conductive part 35 , seven conductive parts 37 , a second connection part 39 , and a third connection part 310 , data line 311 .
  • the fifth conductive part 35 may be connected between the fourth conductive part 34 and the power line 321.
  • the orthographic projection of the fourth conductive portion 34 on the base substrate may at least partially overlap with the orthographic projection of the third conductive portion 23 on the base substrate, and the fourth conductive portion 34 may be connected to the base substrate through the via hole 93 .
  • the second conductive portion 12 is electrically connected, and the fourth conductive portion 34 may be used to form part of the first electrode of the capacitor C.
  • the orthographic projection of the fifth conductive portion 35 on the base substrate at least partially coincides with the orthographic projection of the first active portion 61 on the base substrate.
  • the seventh conductive portion 37 can be connected to the fourth conductive portion 34, and the orthographic projection of the seventh conductive portion 37 on the base substrate and the orthographic projection of the fourth active portion 64 on the base substrate at least partially overlap.
  • the second connection part 39 may connect the active layer on the side of the eighth active part 68 through the via hole 96 to connect the second electrode of the first transistor T1.
  • the third connection part 310 may connect the active layer between the twelfth active part 612 and the thirteenth active part 613 through the via hole 97 to connect the second electrode of the sixth transistor T6 and the first electrode of the seventh transistor T7 Diode.
  • the first pole of the seventh transistor T7 may be connected to the second connection part 39 in the next row of pixel units.
  • the data line 311 may be connected to the first electrode of the fourth transistor T4 through the via hole 98 .
  • the first connection part 31 can be electrically connected to the first conductive part 11 through the via hole 92 , and the first connection part 31 can be electrically connected to the second sub-conductive part 232 through the via hole 91 .
  • the fifth active part 65 may be electrically connected to the first connection part 31 through the via hole 95 , so that the second electrode of the second transistor T2 is electrically connected to the gate of the driving transistor.
  • the display panel may further include a transparent conductive layer located on the side of the third conductive layer away from the base substrate, and an anode layer located at the side of the transparent conductive layer away from the base substrate, and the anode layer located at the side away from the substrate
  • the organic light-emitting layer of the substrate can be used to form the light-emitting layer of the light-emitting unit in the display panel.
  • the first pixel driving circuit may also have other structures, and correspondingly, the display panel may also have other corresponding layout structures.
  • FIG. 11 it is a schematic structural diagram of another exemplary embodiment of the display panel of the present disclosure.
  • the display panel may further include a second transitional display area 6, and the second transitional display area 6 may be located between the first wiring area 4, the first transitional display area 2, and the light-transmitting area 3, so
  • the display panel may further include: a plurality of second light-emitting units A2, a plurality of second pixel driving circuits D2, the plurality of second light-emitting units A2 may be located in the first wiring area 4; a plurality of second pixel driving circuits D2 It can be located in the second transition display area 6, and the second pixel driving circuit D2 can be used to provide a driving current to the second light emitting unit A2.
  • the second transition display area 6 may also be located between the first wiring area 4 and the main display area 1 .
  • the third signal line g3 may be located in any one or more layers of the first conductive layer, the second conductive layer, and the transparent conductive layer. Since only the second light-emitting unit A2 is arranged in the first wiring area 4, and the light-emitting layer of the second light-emitting unit A2 can be arranged on the side of the anode layer away from the substrate, that is, the second light-emitting unit A2 can be connected with the third signal
  • the line g3 is located in a different structure layer, so that the second light emitting unit A2 will not affect the normal wiring of the third signal line g3.
  • the display panel may further include a plurality of first sub-pixels P1 , and the first sub-pixels P1 may be located in the second transition display area 6 .
  • Each first sub-pixel P1 may include a third pixel driving circuit and a third light-emitting unit, that is, the first sub-pixel P1 may emit light under the normal driving action of the display panel.
  • the first sub-pixel P1 can realize the normal display of the second transition display area 6 .
  • the pixel density of the first wiring area 4 , the second transition display area 6 , the first transition display area 2 , and the light transmission area 3 may be the same.
  • the density of pixel driver circuits can be the same.
  • the first pixel driving circuit D1 and the first light-emitting unit A1 connected thereto may be located in the same row, for connecting the first pixel driving circuit D1 and the first light-emitting unit A1
  • the second connection line 72 of a light-emitting unit A1 may extend along the first direction.
  • the second connection line 72 may be located in the transparent conductive layer.
  • Each of the first pixel driving circuits D1 and the first light emitting units A1 connected thereto may be spaced apart by the same sub-pixel column in the first direction. That is, each of the first pixel driving circuits D1 and the first light emitting unit A1 connected thereto may be spaced apart by the same distance in the first direction.
  • This setting can make the second connecting lines 72 for connecting the first pixel driving circuit D1 and the first light emitting unit A1 to have the same length, that is, each connecting line has the same voltage drop under the action of the same voltage, thereby making the display panel Can have better display uniformity.
  • the second light-emitting unit A2 and the second pixel driving circuit D2 connected thereto may be located in the same sub-pixel column.
  • the first connection line 71 for connecting the second light emitting unit A2 and the second pixel driving circuit D2 connected thereto may extend in the second direction.
  • Each of the second pixel driving circuits D2 and the second light emitting units A2 connected thereto are spaced apart by the same sub-pixel row in the second direction, that is, each of the second pixel driving circuits D2 and the second light emitting units A2 connected thereto
  • the second light emitting units A2 may be spaced apart by the same distance in the first direction.
  • This arrangement can make different first connecting lines 71 have the same length, that is, each first connecting line 71 has the same voltage drop under the action of the same voltage, so that the display panel can have better display uniformity.
  • the plurality of third signal lines g3 may include a plurality of first sub-signal lines g31 and a plurality of second sub-signal lines g32.
  • the first sub-signal line g31 may be formed of a part of the first conductive layer
  • the second sub-signal line g32 may be formed of a part of the second conductive layer.
  • the orthographic projection of the first sub-signal line g31 on the base substrate and the orthographic projection of the second sub-signal line g32 on the base substrate may be alternately distributed along the second direction.
  • the third signal lines g3 are arranged in different conductive layers, so that the integration degree of the third signal lines g3 can be increased, that is, more third signal lines g3 can be integrated in the limited second direction size.
  • FIG. 12 it is a schematic structural diagram of another exemplary embodiment of a display panel of the present disclosure.
  • the first wiring area 4, the first transition display area 2, the second transition display area 6, and the light transmission area 3 may form a low pixel density area, and the display panel may include a plurality of first pixel units P, a plurality of The first pixel units P are located in the low pixel density area, and the first pixel units P are arranged at intervals in the second row direction; wherein, in the first direction, three columns of pixels are spaced between adjacent first pixel units P In the second direction, the adjacent first pixel units P are separated by one row of pixel units.
  • the first pixel unit P can be understood as a pixel point with a light-emitting unit, for example, a pixel point with a light-emitting unit in the light-transmitting area 3, a pixel point in the first transition display area 2 with a light-emitting unit and a pixel driving circuit at the same time,
  • the pixel points in the second transition display area 6 that have both the light-emitting unit and the pixel driving circuit, and the pixel points that have the light-emitting unit in the first wiring area can be understood as the first pixel unit. As shown in FIG.
  • squares with filling patterns may represent sub-pixels with light-emitting units, and squares without filling patterns may represent sub-pixels with pixel driving circuits and no light-emitting units.
  • adjacent first pixel units P may be spaced by other number of pixel units, and in the second direction, adjacent first pixel units P may be spaced by other number of pixel units.
  • adjacent first pixel units may be separated by the same number of pixel units, and in the column direction, adjacent first pixel units may be separated by the same number of pixel units.
  • the first pixel unit P may include: an R light-emitting unit R, a first G light-emitting unit G1, a B light-emitting unit B, and a second G light-emitting unit G2.
  • the first G light-emitting unit G1 and the R light-emitting unit R are located in the same row, and are arranged adjacent to the R light-emitting unit R in the first direction;
  • the B light-emitting unit B and the R light-emitting unit R are located in the same column, and It is arranged adjacent to the R light-emitting unit R in the second direction;
  • the second G light-emitting unit G2 is located in the same row as the B light-emitting unit B, and is located in the same column as the first G light-emitting unit G1, and is in the first It is arranged adjacent to the B light-emitting unit B in the direction, and is arranged adjacent to the first G light-emitting unit G1 in the second direction.
  • the R light-emitting unit, the first G light-emitting unit, the B light-emitting unit, and the second G light-emitting unit located in the light-transmitting area 3 may form the above-mentioned first light-emitting unit;
  • the R light-emitting unit, the first G light-emitting unit, the B light-emitting unit, and the second G light-emitting unit may form the above-mentioned second light-emitting unit;
  • the R light-emitting unit, the first G light-emitting unit, The B light-emitting unit and the second G light-emitting unit may form the above-mentioned third light-emitting unit;
  • the R light-emitting unit, the first G light-emitting unit, the B light-emitting unit, and the second G light-emitting unit located in the first transition display area 2 may be formed The above-mentioned fourth light-emitting unit.
  • the size of the first wiring region 4 in the second direction may be equal to the size of the first pixel unit in the second direction.
  • the size of the second transition display area 6 in the second direction may also be equal to the size of the first pixel unit in the second direction.
  • the dimensions of the first wiring area 4 and the second transition display area 6 in the second direction may also be other values, for example, the first wiring area 4, the second The size of the transition display area 6 in the second direction may be twice, three times, etc., of the size of the first pixel unit in the second direction.
  • the first pixel unit located in the first transition display area 2 may be formed by the above-mentioned four second sub-pixels P2 distributed in an array, and the first pixel unit located in the second transition display area 6 may be formed by four The above-mentioned first sub-pixels P1 distributed in an array are formed.
  • FIG. 13 shows a schematic structural diagram of the sub-pixel regions in columns 7-14 and rows 11-14 in FIG. 12 .
  • the number of rows of sub-pixels gradually increases from top to bottom, and the number of columns of sub-pixels gradually increases from left to right.
  • the pixel driving circuits D3 located in the 9th to 10th columns may be connected by the data lines d3 passing through the first wiring area 4 along the second direction. It should be noted that, the pixel driving circuits located in the same column as the second sub-pixels can all be connected by data lines running through the four ends of the first wiring region.
  • the pixel driving circuit D4 located in the 7th column and the 10th row may be connected to the pixel driving circuit D5 in the 13th column and the 13th row through the first sub-signal line g31.
  • the pixel driving circuit D6 located in the 8th column and the 10th row may be connected to the pixel driving circuit D7 located in the 14th column and the 13th row through the second sub-signal line g32.
  • FIG. 14 is a partial enlarged view at the dotted line frame C in FIG. 13
  • FIG. 15 is a cross-sectional view at the dotted line AA in FIG. 14
  • the display panel may further include a first gate insulating layer 04 located between the first conductive layer and the second conductive layer, a dielectric layer 05 located between the second conductive layer and the third conductive layer, and the active layer A second gate insulating layer 07 between it and the first conductive layer.
  • the first gate insulating layer 04 may be a silicon oxide layer
  • the dielectric layer 05 may be a silicon nitride layer.
  • the first conductive layer, the second conductive layer, and the third conductive layer can all be formed by at least one metal layer.
  • the first conductive layer, the second conductive layer, and the third conductive layer can all be formed by stacking the first titanium layer, the aluminum layer, and the second titanium layer in sequence.
  • the base substrate 0 may be formed of an insulating material, for example, the base substrate may include a first polyimide (PI) layer, a first silicon oxide (SiO) layer, an amorphous silicon layer, a second polyimide layer, which are sequentially arranged Amine (PI) layer, second silicon dioxide layer.
  • the second gate insulating layer 07 can also be a silicon oxide layer.
  • the first sub-signal line g31 may be located in the first conductive layer of the display panel, and the second sub-signal line g32 may be located in the second conductive layer of the display panel.
  • the orthographic projection of the first sub-signal line g31 on the base substrate and the orthographic projection of the second sub-signal line g32 on the base substrate may be alternately distributed along the second direction.
  • the present exemplary embodiment also provides a display device, the display device comprising: the above-mentioned display panel and a camera, wherein the camera is directly opposite to the light-transmitting area of the display panel.
  • the display device may be a display device such as a mobile phone, a tablet computer, or the like.

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Abstract

一种显示面板、显示装置。显示面板包括透光区（3）、主显示区（1）、第一过渡显示区（2）以及第一走线区（4）。显示面板还包括：多个第一发光单元（A1）、多个第一像素驱动电路（D1）、多条第一信号线（d1）、多条第二信号线（d2）、多条第三信号线（g3）。多个第一发光单元（A1）位于透光区（3）；多个第一像素驱动电路（D1）位于第一过渡显示区（2）；多条第一信号线（d1）沿第二方向（X）延伸，且位于第一过渡显示区（2），用于向第一像素驱动电路（D1）提供电位信号；多条第二信号线（d2）与第一信号线（d1）一一对应设置，沿第二方向（X）延伸，且位于主显示区（1）；多条第三信号线（g3）沿第一方向（Y）延伸且位于第一走线区（4），第三信号线（g3）分别通过过孔与相对应的第一信号线（d1）、第二信号线（d2）连接。显示面板能够实现窄边框设计。

Description

显示面板、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板、显示装置。
背景技术
屏下摄像头技术是在显示面板上设置透光区，将摄像头与透光区正对设置，从而实现全屏显示。相关技术中，为了提高透光区的透光率，通常在透光区中仅设置发光单元，在透光区以外设置用于驱动该发光单元的像素驱动电路。用于向该像素驱动电路提供数据信号的数据线需要通过绕线的方式与该像素驱动电路连接。然而，该绕线方式往往会占用显示面板的边沿走线区，从而增加了显示面板边框的宽度。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
根据本公开的一个方面，提供一种显示面板，所述显示面板包括透光区、主显示区、第一过渡显示区以及第一走线区，所述第一过渡显示区位于所述透光区在第一方向上的两侧，所述第一走线区位于所述第一过渡显示区、透光区在第二方向上的一侧，所述主显示区位于所述第一走线区远离所述第一过渡显示区、透光区的一侧，其中，所述第一方向和第二方向相交。所述显示面板还包括：第一发光单元、第一像素驱动电路、第一信号线、第二信号线、第三信号线，第一发光单元位于所述透光区；第一像素驱动电路位于所述第一过渡显示区，用于向所述第一发光单元提供驱动电流；第一信号线沿第二方向延伸，且所述第一信号线的至少部分位于所述第一过渡显示区，用于向所述第一像素驱动电路提供电位信号；第二信号线沿第二方向延伸，且所述第二信号线至少部分位于所述主显示区，用于向所述主显示区中与所述第一发光单元位于同一子像素列的像素驱动电路提供电位信号；第三信号线沿第一方向延伸，所述第三信号线的至少部分位于所述第一走线区，所述第三信号线分别通过过孔与所述第一信号线、第二信号线连接。
本公开一种示例性实施例中，所述显示面板还包括第二过渡显示区，所述第二过渡显示区相邻设置于所述第一走线区在第二方向上的一侧，所述显示面板还包括：第二发光单元、第二像素驱动电路，第二发光单元位于所述第一走线区；第二像素驱动电路位于所述第二过渡显示区，用于向所述第二发光单元提供驱动电流。
本公开一种示例性实施例中，所述第二过渡显示区位于所述第一走线区和所述第一过渡显示区、透光区之间，或所述第二过渡显示区位于所述第一走线区和所述主显示区之间。
本公开一种示例性实施例中，所述第二发光单元和与其连接的所述第二像素驱动电路位于同一子像素列。
本公开一种示例性实施例中，所述第二像素驱动电路和所述第二发光单元均为多个，每个所述第二像素驱动电路和与其连接的所述第二发光单元在第二方向上间隔相同的子像素行。
本公开一种示例性实施例中，所述显示面板还包括第一子像素，所述第一子像素位于所述第二过渡显示区，所述第一子像素包括：第三发光单元、第三像素驱动电路，第三像素驱动电路用于向所述第三发光单元提供驱动电流。
本公开一种示例性实施例中，所述显示面板还包括第二子像素，所述第二子像素位于所述第一过渡显示区，所述第二子像素包括：第四发光单元、第四像素驱动电路，第四像素驱动电路用于向所述第四发光单元提供驱动电流；所述第四像素驱动电路与所述第一像素驱动电路位于不同列。
本公开一种示例性实施例中，所述第一发光单元和所述第一像素驱动电路均为多个，所述第一像素驱动电路和与其连接的所述第一发光单元位于同一行，每个所述第一像素驱动电路和与其连接的所述第一发光单元在第一方向上间隔相同子像素列。
本公开一种示例性实施例中，所述显示面板还包括：衬底基板、第一导电层、第二导电层、第三导电层，第一导电层设置于所述衬底基板的一侧；第二导电层设置于所述第一导电层背离所述衬底基板的一侧；第三导电层设置于所述第二导电层背离所述衬底基板的一侧，至少部分所述第三导电层用于形成所述第一信号线和所述第二信号线。
本公开一种示例性实施例中，所述第一信号线、第二信号线、第三信号线均为多条，所述第三信号线连接于相对应的所述第一信号线和第二信号线之间，多条所述第三信号线包括多条第一子信号线和多条第二子信号线，至少部分所述第一导电层用于形成所述第一子信号线；至少部分所述第二导电层用于形成所述第二子信号线；其中，所述第一子信号线在所述衬底基板的正投影与所述第二子信号线在所述衬底基板的正投影沿第二方向依次交替分布。
本公开一种示例性实施例中，所述第一信号线、第二信号线、第三信号线均为多条，所述第三信号线连接于相对应的所述第一信号线和第二信号线之间；所述第三信号线由至少部分所述第一导电层形成；其中，所述第三信号线在所述衬底基板的正投影沿第二方向依次间隔分布。
本公开一种示例性实施例中，所述第一信号线、第二信号线、第三信号线均为多条，所述第三信号线连接于相对应的所述第一信号线和第二信号线之间；所述第三信号线由至少部分所述第二导电层形成；其中，所述第三信号线在所述衬底基板的正投影沿第二方向依次间隔分布。
本公开一种示例性实施例中，所述第一像素驱动电路包括驱动晶体管，以及连接于所述驱动晶体管栅极的电容；部分所述第一导电层用于形成所述驱动晶体管的栅极，部分所述第二导电层用于形成所述电容的一电极；所述第一信号线用于向所述驱动晶体管的栅极提供数据信号。
本公开一种示例性实施例中，所述显示面板还包括第四导电层，第四导电层位于所述第三导电层背离所述衬底基板的一侧，至少部分所述第四导电层用于形成所述第一发光单元的阳极，所述第四导电层还包括第一连接线，第一连接线用于连接所述第二像素驱动电路和所述第二发光单元的阳极。
本公开一种示例性实施例中，所述显示面板还包括第五透明导电层，第五透明导电层位于所述第三导电层和所述第四导电层之间，所述第五透明导电层包括第二连接线，所述第二连接线用于连接所述第一像素驱动电路和所述第一发光单元的阳极。
本公开一种示例性实施例中，所述主显示区的像素密度大于所述第一走线区、第一过渡显示区、第二过渡显示区、透光区的像素密度。
本公开一种示例性实施例中，所述第一走线区、第一过渡显示区、第二过渡显示区、透光区的像素密度相同。
本公开一种示例性实施例中，所述第一方向为行方向，所述第二方向为列方向，所述第一走线区、第一过渡显示区、第二过渡显示区、透光区形成低像素密度区，所述显示面板包括多个第一像素单元，多个第一像素单元位于低像素密度区；其中，在行方向上，相邻所述第一像素单元间隔相同个数的像素单元，在列方向上，相邻所述第一像素单元间隔相同个数的像素单元。
本公开一种示例性实施例中，其中，在行方向上，相邻所述第一像素单元之间间隔三个像素单元，在列方向上，相邻所述第一像素单元间隔一个像素单元。
在第一方向上，相邻所述第一像素单元之间间隔三个像素单元，在第二方向上，相邻所述第一像素单元间隔一个像素单元。
本公开一种示例性实施例中，所述第一像素单元包括：R发光单元、第一G发光单元、B发光单元、第二G发光单元，第一G发光单元与所述R发光单元位于同一行，且在第一方向上与所述R发光单元相邻设置；B发光单元与所述R发光单元位于同一列，且在第二方向上与所述R发光单元相邻设置；第二G发光单元与所述B发光单元位于同一行，与所述第一G发光单元位于同一列，且在第一方向上与所述B发光单元相邻设置，在第二方向上与第一G发光单元相邻设置。其中，位于所述透光区的所述R发光单元、第一G发光单元、B发光单元、第二G发光单元形成所述第一发光单元；位于所述第一走线区的所述R发光单元、第一G发光单元、B发光单元、第二G发光单元形成所述第二发光单元；位于所述第二过渡显示区的所述R发光单元、第一G发光单元、B发光单元、第二G发光单元形成所述第三发光单元；位于所述第一过渡显示区的所述R发光单元、第一G发光单元、B发光单元、第二G发光单元形成所述第四发光单元。
本公开一种示例性实施例中，所述第一走线区在第二方向上的尺寸等于所述第一像素单元在第二方向的尺寸。
本公开一种示例性实施例中，所述第二过渡显示区在第二方向上的尺寸等于所述第一像素单元在第二方向的尺寸。
根据本公开的一个方面，提供一种显示装置，该显示装置包括：上述的显示面板和摄像头，所述摄像头与所述显示面板的透光区正对。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中一种显示面板的结构示意图；
图2为图1中的虚线框A处的局部放大图；
图3为本公开显示面板一种示例性实施例的结构示意图；
图4为本公开显示面板一种示例性实施例中第一像素驱动电路的结构示意图；
图5为图4像素驱动电路一种驱动方法中各节点的时序图；
图6为本公开显示面板一种示例性实施例的结构版图；
图7为图6中有源层的结构版图；
图8为图6中第一导电层的结构版图；
图9为图6中第二导电层的结构版图；
图10为图6中第三导电层的结构版图；
图11为本公开显示面板另一种示例性实施例的结构示意图；
图12为本公开显示面板另一种示例性实施例中的结构示意图；
图13为图12中显示面板的局部放大图；
图14为图13中虚线框C处的局部放大图；
图15为图14中虚线AA处的剖视图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。其他相对性的用语，例如“高”“低”“顶”“底”“左”“右”等也作具有类似含义。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接” 设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
如图1、2所示，图1为相关技术中一种显示面板的结构示意图，图2为图1中的虚线框A处的局部放大图。如图1、2所示，该显示面板包括主显示区1、透光区3、过渡显示区2、边沿走线区9。如图2所示，显示面板的透光区3中仅设置有发光单元A，显示面板的过渡显示区2中设置有带有发光单元的子像素P和不带发光单元的像素驱动电路D。该显示面板可以通过位于过渡显示区2中的像素驱动电路D向位于透光区3中的发光单元A提供驱动电流。由于透光区3没有设置像素驱动电路，因而透光区具有较高的透光率。如图2所示，为实现正常驱动，与发光单元A位于同一子像素列的数据线d1需要连接向该发光单元A提供驱动电流的像素驱动电路D。相关技术中，实现数据线d1连接过渡显示区2中的像素驱动电路D的方式如图2所示，在边沿走线区9设置多条栅线g，数据线d1可以经过集线区B，并通过过孔与栅线g一一对应连接；同时在过渡显示区2中，通过数据线d2连接位于同一子像素列的像素驱动电路D，数据线d2可以通过过孔与栅线g一一对应连接。栅极g可以连接数据线d1和数据线d2，从而实现数据线d1连接像素驱动电路D。然而，一方面，栅线g会占据一定的边沿走线区9，从而影响窄边框实现；另一方面，集线区B会占据一定的空间，从而影响透光区3的面积；再一方面，图2中的数据线d1需要通过在边沿走线区9绕线的方式连接位于过渡显示区2中的像素驱动电路D，从而不同数据线d1与像素驱动电路D之间的连接线具有不同的长度。在相同数据信号作用下，由于不同连接线自身压降不同，不同像素驱动电路D会接收到不同的数据信号，从而影响显示面板显示的均一性。
基于此，本示例性实施例提供一种显示面板，如图3所示，为本公开显示面板一种示例性实施例的结构示意图。所述显示面板可以包括透光区3、主显示区1、第一过渡显示区2以及第一走线区4；所述第一过渡显示区2可以位于所述透光区3在第一方向Y上的两侧；所述第一走线区4可以位于所述第一过渡显示区2、透光区3在第二方向X上的一侧，其中，第一方向和第二方向相交，例如，第一方向可以为行方向，第二方向可以为列方向；主显示区1可以位于第一走线区4远离透光区3、第一过渡显示区2的一侧。如图3所示，所述显示面板还可以包括：第一发光单元A1、第一像素驱动电路D1、第一信号线d1、第二信号线d2、第三信号线g3，第一发光单元A1位于所述透光区3；第一像素驱动电路D1位于所述第一过渡显示区2，用于向所述第一发光单元A1提供驱动电流；第一信号线d1沿第二方向延伸，第一信号线d1的至少部分可以位于所述第一过渡显示区2，用于向所述第一像素驱动电路D1提供电位信号；第二信号线d2沿第二方向延伸，第二信号线d2的至少部分可以位于所述主显示区1，第二信号线d2可以用于向所述主显示区中的像素驱动电路提供电位信号，例如，第二信号线d2可以用于向所述主显示区中与所述 第一发光单元A1位于同一子像素列的像素驱动电路提供电位信号；第三信号线g3可以沿第一方向延伸，第三信号线g3的至少部分位于所述第一走线区4，如图3所述，第一信号线d1和第二信号线d2可以延伸至第一走线区4，从而所述第三信号线g3可以分别通过过孔与相对应的所述第一信号线d1、第二信号线d2连接。
本示例性实施例中，如图3所示，第一发光单元A1、第一像素驱动电路D1可以为多个，多个第一发光单元A1可以位于不同子像素列，多个第一像素驱动电路D1可以位于不同子像素列。相应的，第一信号线d1、第二信号线d2、第三信号线d3可以为多条。第一信号线d1、第二信号线d2可以为数据线，每条第一信号线d1可以与第一过渡显示区2中位于同一子像素列的第一像素驱动电路D1连接，用于向与其连接的第一像素驱动电路D1提供数据信号。每条第二信号线d2可以与主显示区1中位于同一子像素列的像素驱动电路连接，用于向与其连接的像素驱动电路提供数据信号。第一信号线d1、第二信号线d2可以位于同一导电层，第三信号线g3可以与第一信号线d1、第二信号线d2位于不同导电层。需要说明的是，第一信号线、第二信号线还可以为其他信号线，例如，第一信号线、第二信号线还可以为感测线等。
本示例性实施例中，一方面，该显示面板将第一走线区4设置于所述主显示区1和所述第一过渡显示区2、透光区3之间，第一信号线d1和第二信号线d2可以通过位于第一走线区4的第三信号线g3连接，从而避免了数据线在边沿走线区绕线，有利于实现窄边框的显示面板。另一方面，该显示面板中的数据线不需要绕线设置，不同数据线长度差异较小，从而可以提高显示面板发光的均一性。再一方面，该显示面板不需要设置相关技术中的集线区B，从而可以给透光区预留较大的空间。
本示例性实施例中，如图3所示，所述显示面板还可以包括：多个第二子像素P2，多个第二子像素P2可以位于第一过渡显示区2。每个第二子像素P2可以包括有第四像素驱动电路和第四发光单元，即第二子像素P2可以在显示面板正常驱动作用下发光。第二子像素P2可以实现第一过渡显示区2的正常显示。需要说明的是，由于第一过渡显示区2设置有第二子像素P2同时还设置有第一像素驱动电路D1，因此，第一过渡显示区2的像素密度(即第二子像素P2所形成像素单元的密度)小于主显示区的像素密度。此外，为了增加透光区的透光率，透光区3的像素密度(即第一发光单元所形成像素单元的密度)也可以小于主显示区的像素密度。透光区3的像素密度可以等于第一过渡显示区2的像素密度。
如图3所示，第二子像素P2与第一像素驱动电路D1可以位于不同列，该设置可以使得用于连接第一像素驱动电路D1的第一信号线d1可以与用于连接第二子像素P2的数据线位于不同列，从而避免了第一信号线d1与用于连接第二子像素P2的数据线交叠。如图3所示，该显示面板还可以包括源极驱动电路5，源极驱动电路5可以位于主显示区1远离第一走线区4的一侧。源极驱动电路5可以用于向与其连接的数据线d2提供数据信号。该显示面板位于透光区3、第一过渡显示区2远离第一走线区4的一侧可以不设置像素单 元，从而第一信号线d1可以不需要绕回透光区的正上方。
本示例性实施例中，如图4所示，为本公开显示面板一种示例性实施例中第一像素驱动电路的结构示意图。该像素驱动电路可以包括：第一晶体管T1、第二晶体管T2、驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、电容C。其中，第一晶体管T1的第一极连接节点N，第二极连接初始化信号端Vinit，栅极连接复位信号端Re；第二晶体管T2第一极连接驱动晶体管T3的第一极，第二极连接节点N；栅极连接栅极驱动信号端Gate；驱动晶体管T3的栅极连接节点N；第四晶体管T4的第一极连接数据信号端Da，第二极连接驱动晶体管T3的第二极，栅极连接栅极驱动信号端Gate；第五晶体管T5的第一极连接第一电源信号端VDD，第二极连接驱动晶体管T3的第二极，栅极连接使能信号端EM；第六晶体管T6第一极连接驱动晶体管T3的第一极，栅极连接使能信号端EM；第七晶体管T7的第一极连接初始化信号端Vinit，第二极连接第六晶体管T6的第二极。该像素驱动电路可以连接一发光单元OLED，用于驱动该发光单元OLED发光，发光单元OLED可以连接于第六晶体管T6的第二极和第二电源端VSS之间。其中，晶体管T1-T7可以均为P型晶体管。该显示面板中的其他像素驱动电路可以与第一像素驱动电路具有相同的结构。
如图5所示，为图4像素驱动电路一种驱动方法中各节点的时序图。其中，Gate表示栅极驱动信号端Gate的时序，Re表示复位信号端Re的时序，EM表示使能信号端EM的时序，Da表示数据信号端Da的时序。该像素驱动电路的驱动方法可以包括复位阶段t1、补偿阶段t2，发光阶段t3。在复位阶段t1：复位信号端Re输出低电平信号，第一晶体管T1、第七晶体管T7导通，初始化信号端Vinit向节点N，第六晶体管T6的第二极输入初始化信号。在补偿阶段t2：栅极驱动信号端Gate输出低电平信号，第四晶体管T4、第二晶体管T2导通，同时数据信号端Da输出数据信号以向节点N写入电压Vdata+Vth，其中Vdata为数据信号的电压，Vth为驱动晶体管T3的阈值电压。发光阶段t3：使能信号端EM输出低电平信号，第六晶体管T6、第五晶体管T5导通，驱动晶体管T3在电容C存储的电压Vdata+Vth作用下发光。根据驱动晶体管输出电流公式I＝(μWCox/2L)(Vgs-Vth) 2，其中，μ为载流子迁移率；Cox为单位面积栅极电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压差，Vth为驱动晶体管阈值电压。本公开像素驱动电路中驱动晶体管的输出电流I＝(μWCox/2L)(Vdata+Vth-Vdd-Vth) 2。该像素驱动电路能够避免驱动晶体管阈值对其输出电流的影响。
本示例性实施例中，该显示面板可以包括依次层叠设置的衬底基板0、有源层、第一导电层、第二导电层、第三导电层。如图6、7、8、9、10所示，图6为本公开显示面板一种示例性实施例的结构版图，图7为图6中有源层的结构版图，图8为图6中第一导电层的结构版图，图9为图6中第二导电层的结构版图，图10为图6中第三导电层的结构版图。
如图6、7所示，有源层可以包括第一有源部61、第二有源部62、第三有源部63、第 四有源部64、第五有源部65、第六有源部66、第七有源部67、第八有源部68、第十有源部610、第十一有源部611、第十二有源部612、第十三有源部613。其中，所述第二有源部62可以用于形成所述第二晶体管T2的第一沟道区，所述第三有源部63可以用于形成所述第二晶体管T2的第二沟道区。第六有源部66可以用于形成所述驱动晶体管T3的沟道区。第七有源部67可以用于形成所述第一晶体管T1的第一沟道区，第八有源部68可以用于形成所述第一晶体管T1的第二沟道区。第十有源部610可以用于形成第四晶体管T4的沟道区。第十一有源部611可以用于形成第五晶体管T5的沟道区。第十二有源部612可以用于形成第六晶体管T6的沟道区。第十三有源部613可以用于形成第七晶体管的沟道区。第四有源部64可以连接于所述第二有源部62和所述第三有源部63之间。
如图6、8所示，所述第一导电层可以包括：第一导电部11、第二导电部12、第一栅线13、第二栅线14、第三栅线17、第六导电部16。第一导电部11也可以为沿第一方向Y延伸的条形结构，第一导电部11在衬底基板的正投影可以覆盖第六有源部66在衬底基板的正投影，以形成驱动晶体管T3的栅极。所述第二导电部12可以用于形成电容C的部分第一电极。第一栅线13可以用于提供图5中的栅极驱动信号端。第一栅线13在所述衬底基板的正投影可以沿所述第一方向Y延伸，且所述第一栅线13在所述衬底基板的正投影可以位于所述第一导电部11在所述衬底基板正投影与所述第二导电部12在所述衬底基板正投影之间，所述第一栅线13的部分导电部131可以用于形成所述第二晶体管T2的第一栅极，所述第一栅线13的部分导电部134可以用于形成第四晶体管T4的栅极。第二栅线14可以用于提供图1中的复位信号端。第二栅线14在所述衬底基板的正投影沿所述第一方向Y延伸，且所述第二栅线14在所述衬底基板正投影可以位于所述第二导电部12在所述衬底基板正投影远离所述第一栅线13在所述衬底基板正投影的一侧，所述第二栅线14的部分导电部141可以用于形成所述第一晶体管T1的第一栅极，所述第二栅线14的部分导电部142可以用于形成所述第一晶体管T1的第二栅极。第三栅线17可以用于提供图5中的使能信号端。第三栅线17在衬底基板的正投影可以位于第一导电部11在衬底基板正投影远离第一栅线13在衬底基板正投影的一侧。第三栅线17可以包括导电部175和导电部176，导电部175可以用于形成第五晶体管的栅极，导电部176可以用于形成第六晶体管的栅极。其中，第七晶体管T7的栅极可以共用下一行像素单元对应第二栅线14中的导电部147。第六导电部16在所述衬底基板的正投影可以沿所述第二方向X延伸，且连接于所述第一栅线13，部分第六导电部16可以用于形成第二晶体管T2的第二栅极。
如图6、9所示，第二导电层可以包括第三导电部23，所述第三导电部23在所述衬底基板的正投影可以与所述第二导电部12在衬底基板的正投影至少部分重合，且所述第三导电部23与所述第一导电部11电连接，所述第三导电部23可以用于形成所述电容C的第二电极。
如图6、10所示，第三导电层可以包括第四导电部34、第一连接部31、电源线321、第五导电部35、七导电部37、第二连接部39、第三连接部310、数据线311。第五导电部 35可以连接于所述第四导电部34和所述电源线321之间。所述第四导电部34在所述衬底基板的正投影可以与所述第三导电部23衬底基板的正投影至少部分重合，且所述第四导电部34可以通过过孔93与所述第二导电部12电连接，所述第四导电部34可以用于形成所述电容C的部分第一电极。所述第五导电部35在所述衬底基板的正投影与所述第一有源部61在所述衬底基板的正投影至少部分重合。第七导电部37可以连接所述第四导电部34，且所述第七导电部37在所述衬底基板的正投影与所述第四有源部64在所述衬底基板的正投影至少部分重合。第二连接部39可以通过过孔96连接第八有源部68一侧的有源层以连接第一晶体管T1的第二极。第三连接部310可以通过过孔97连接第十二有源部612和第十三有源部613之间的有源层，以连接第六晶体管T6的第二极和第七晶体管T7的第二极。第七晶体管T7的第一极可以连接下一行像素单元中的第二连接部39。数据线311可以通过过孔98与第四晶体管T4的第一极连接。第一连接部31可以通过过孔92与所述第一导电部11电连接，且所述第一连接部31可以通过过孔91与第二子导电部232电连接。第五有源部65可以通过过孔95与所述第一连接部31电连接，以使得第二晶体管T2的第二极电连接驱动晶体管的栅极。
本示例性实施例中，显示面板还可以包括位于所述第三导电层背离衬底基板一侧的透明导电层以及位于透明导电层背离衬底基板一侧的阳极层、位于阳极层背离衬底基板的有机发光层，有机发光层可以用于形成显示面板中发光单元的发光层。应该理解的是，在其他示例性实施例中，第一像素驱动电路还可以为其他结构，相应的，显示面板还可以有其他对应的版图结构。
本示例性实施例中，如图11所示，为本公开显示面板另一种示例性实施例的结构示意图。所述显示面板还可以包括第二过渡显示区6，所述第二过渡显示区6可以位于所述第一走线区4和所述第一过渡显示区2、透光区3之间，所述显示面板还可以包括：多个第二发光单元A2、多个第二像素驱动电路D2，多个第二发光单元A2可以位于所述第一走线区4；多个第二像素驱动电路D2可以位于所述第二过渡显示区6，第二像素驱动电路D2可以用于向所述第二发光单元A2提供驱动电流。应该理解的是，在其他示例性实施例中，第二过渡显示区6还可以位于第一走线区4和主显示区1之间。
本示例性实施例中，第三信号线g3可以位于第一导电层、第二导电层、透明导电层中的任意一层或多层。由于第一走线区4中仅设置有第二发光单元A2，且第二发光单元A2的发光层可以设置于阳极层背离衬底基板的一侧，即第二发光单元A2可以与第三信号线g3位于不同的结构层，从而第二发光单元A2不会影响第三信号线g3的正常走线。
如图11所示，该显示面板还可以包括多个第一子像素P1，第一子像素P1可以位于第二过渡显示区6中。每个第一子像素P1可以包括有第三像素驱动电路和第三发光单元，即第一子像素P1可以在显示面板正常驱动作用下发光。第一子像素P1可以实现第二过渡显示区6的正常显示。其中，第一走线区4、第二过渡显示区6、第一过渡显示区2、透光区3的像素密度可以相同。此外，为保证第二过渡显示区6、第一过渡显示区2、主显示 区1中像素驱动电路输出特征的均一性，第二过渡显示区6、第一过渡显示区2、主显示区1中像素驱动电路的密度可以相同。
本示例性实施例中，如图3、11所示，所述第一像素驱动电路D1和与其连接的所述第一发光单元A1可以位于同一行，用于连接第一像素驱动电路D1和第一发光单元A1的第二连接线72可以沿第一方向延伸。第二连接线72可以位于透明导电层。每个所述第一像素驱动电路D1和与其连接的所述第一发光单元A1在第一方向上可以间隔相同子像素列。即每个所述第一像素驱动电路D1和与其连接的所述第一发光单元A1在第一方向上可以间隔相同距离。该设置可以使得用于连接第一像素驱动电路D1和第一发光单元A1的第二连接线72具有相同的长度，即每条连接线在相同电压作用下具有相同的压降，从而使得显示面板可以具有更好的显示均一性。
本示例性实施例中，如图11所示，所述第二发光单元A2和与其连接的所述第二像素驱动电路D2可以位于同一子像素列。用于连接所述第二发光单元A2和与其连接的所述第二像素驱动电路D2之间的第一连接线71可以沿第二方向延伸。每个所述第二像素驱动电路D2和与其连接的所述第二发光单元A2在第二方向上间隔相同的子像素行，即每个所述第二像素驱动电路D2和与其连接的所述第二发光单元A2在第一方向上可以间隔相同距离。该设置可以使得不同第一连接线71具有相同的长度，即每条第一连接线71在相同电压作用下具有相同的压降，从而使得显示面板可以具有更好的显示均一性。
本示例性实施例中，如图11所示，多条所述第三信号线g3可以包括多条第一子信号线g31和多条第二子信号线g32。第一子信号线g31可以由部分第一导电层形成，第二子信号线g32可以由部分第二导电层形成。其中，所述第一子信号线g31在所述衬底基板的正投影与所述第二子信号线g32在所述衬底基板的正投影可以沿第二方向依次交替分布。该显示面板将第三信号线g3设置于不同导电层，从而可以增加第三信号线g3的集成度，即可以在有限的第二方向尺寸上集成更多的第三信号线g3。
本示例性实施例中，如图12所示，为本公开显示面板另一种示例性实施例中的结构示意图。所述第一走线区4、第一过渡显示区2、第二过渡显示区6、透光区3可以形成低像素密度区，所述显示面板可以包括多个第一像素单元P，多个第一像素单元P位于低像素密度区，所述第一像素单元P在行第二方向上间隔设置；其中，在第一方向上，相邻所述第一像素单元P之间间隔三列像素单元，在第二方向上，相邻所述第一像素单元P间隔一行像素单元。其中，第一像素单元P可以理解为具有发光单元的像素点，例如，透光区3中具有发光单元的像素点、第一过渡显示区2中同时具有发光单元和像素驱动电路的像素点、第二过渡显示区6中同时具有发光单元和像素驱动电路的像素点、第一走线区中具有发光单元的像素点均可以理解为第一像素单元。如图12所示，具有填充图案的方块可以表示具有发光单元的子像素点，不具有填充图案的方块可以指具有像素驱动电路且不具有发光单元的子像素点。其中，在第一方向上，相邻所述第一像素单元P之间可以间隔其他数量的像素单元，在第二方向上，相邻所述第一像素单元P可以间隔其他数量的像素单 元。在行方向上，相邻所述第一像素单元可以间隔相同个数的像素单元，在列方向上，相邻所述第一像素单元可以间隔相同个数的像素单元。
如图12所示，第一像素单元P可以包括：R发光单元R、第一G发光单元G1、B发光单元B、第二G发光单元G2。第一G发光单元G1与所述R发光单元R位于同一行，且在第一方向上与所述R发光单元R相邻设置；B发光单元B与所述R发光单元R位于同一列，且在第二方向上与所述R发光单元R相邻设置；第二G发光单元G2与所述B发光单元B位于同一行，与所述第一G发光单元G1位于同一列，且在第一方向上与所述B发光单元B相邻设置，在第二方向上与第一G发光单元G1相邻设置。
其中，位于所述透光区3的所述R发光单元、第一G发光单元、B发光单元、第二G发光单元可以形成上述第一发光单元；位于所述第一走线区4的所述R发光单元、第一G发光单元、B发光单元、第二G发光单元可以形成上述第二发光单元；位于所述第二过渡显示区6的所述R发光单元、第一G发光单元、B发光单元、第二G发光单元可以形成上述第三发光单元；位于所述第一过渡显示区2的所述R发光单元、第一G发光单元、B发光单元、第二G发光单元可以形成上述第四发光单元。
本示例性实施例中，如图12所示，所述第一走线区4在第二方向上的尺寸可以等于所述第一像素单元在第二方向的尺寸。所述第二过渡显示区6在第二方向上的尺寸也可以等于所述第一像素单元在第二方向的尺寸。应该理解的是，在其他示例性实施例中，第一走线区4、第二过渡显示区6在第二方向上的尺寸还可以为其他值，例如，第一走线区4、第二过渡显示区6在第二方向上的尺寸可以为第一像素单元在第二方向尺寸的两倍、三倍等。
如图12所示，位于第一过渡显示区2中的第一像素单元可以由四个阵列分布的上述第二子像素P2形成，位于第二过渡显示区6中的第一像素单元可以由四个阵列分布的上述第一子像素P1形成。
如图13所示，为图12中显示面板的局部放大图。图13示出了图12中第7-14列、第11-14行子像素区域的结构示意图。在图12中，子像素的行数自上而下逐渐增加，子像素的列数自左向右逐渐增加。如图13所示，位于第9-10列的像素驱动电路D3可以通过沿第二方向贯穿第一走线区4的数据线d3连接。需要说明的是，与第二子像素位于同一列的像素驱动电路均可以通过贯穿第一走线区4端数据线连接。其中，位于第7列第10行的像素驱动电路D4可以与第13列第13行的像素驱动电路D5通过第一子信号线g31连接。位于第8列第10行的像素驱动电路D6可以与第14列第13行的像素驱动电路D7通过第二子信号线g32连接。
如图14、15所示，图14为图13中虚线框C处的局部放大图，图15为图14中虚线AA处的剖视图。该显示面板还可以包括位于第一导电层和第二导电层之间的第一栅极绝缘层04、以及位于第二导电层和第三导电层之间的介电层05、位于有源层和第一导电层之间第二栅极绝缘层07。其中，第一栅极绝缘层04可以为氧化硅层，介电层05可以为氮 化硅层。第一导电层、第二导电层、第三导电层均可以通过至少一层金属层形成。例如，第一导电层、第二导电层、第三导电层均可以通过第一钛层、铝层、第二钛层依次层叠形成。衬底基板0可以通过绝缘材料形成，例如，衬底基板可以包括依次设置的第一聚酰亚胺(PI)层、第一氧化硅(SiO)层、非晶硅层、第二聚酰亚胺(PI)层、第二氧化硅层。第二栅极绝缘层07同样可以为氧化硅层。其中，所述第一子信号线g31可以位于显示面板第一导电层，第二子信号线g32可以位于显示面板的第二导电层。所述第一子信号线g31在所述衬底基板的正投影与所述第二子信号线g32在所述衬底基板的正投影可以沿第二方向依次交替分布。
本示例性实施例还提供一种显示装置，该显示装置包括：上述的显示面板和摄像头，所述摄像头与所述显示面板的透光区正对。该显示装置可以为手机、平板电脑等显示装置。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (24)

  1. 一种显示面板，其中，所述显示面板包括透光区、主显示区、第一过渡显示区以及第一走线区，所述第一过渡显示区位于所述透光区在第一方向上的两侧，所述第一走线区位于所述第一过渡显示区、透光区在第二方向上的一侧，所述主显示区位于所述第一走线区远离所述第一过渡显示区、透光区的一侧，其中，所述第一方向和第二方向相交；
    所述显示面板还包括：
    第一发光单元，位于所述透光区；
    第一像素驱动电路，位于所述第一过渡显示区，用于向所述第一发光单元提供驱动电流；
    第一信号线，沿第二方向延伸，且所述第一信号线的至少部分位于所述第一过渡显示区，用于向所述第一像素驱动电路提供电位信号；
    第二信号线，沿第二方向延伸，且所述第二信号线的至少部分位于所述主显示区，用于向所述主显示区中的像素驱动电路提供电位信号；
    第三信号线，沿第一方向延伸，且所述第三信号线的至少部分位于所述第一走线区，所述第三信号线分别通过过孔与所述第一信号线、第二信号线连接。
  2. 根据权利要求1所述的显示面板，其中，所述第二信号线用于向所述主显示区中与所述第一发光单元位于同一子像素列的像素驱动电路提供电位信号。
  3. 根据权利要求1所述的显示面板，其中，所述显示面板还包括第二过渡显示区，所述第二过渡显示区相邻设置于所述第一走线区在第二方向上的一侧，所述显示面板还包括：
    第二发光单元，位于所述第一走线区；
    第二像素驱动电路，位于所述第二过渡显示区，用于向所述第二发光单元提供驱动电流。
  4. 根据权利要求3所述的显示面板，其中，所述第二过渡显示区位于所述第一走线区和所述第一过渡显示区、透光区之间，或所述第二过渡显示区位于所述第一走线区和所述主显示区之间。
  5. 根据权利要求3或4所述的显示面板，其中，所述第二发光单元和与其连接的所述第二像素驱动电路位于同一子像素列。
  6. 根据权利要求5所述的显示面板，其中，所述第二像素驱动电路和所述第二发光单元均为多个，每个所述第二像素驱动电路和与其连接的所述第二发光单元在第二方向上间隔相同的子像素行。
  7. 根据权利要求3或4所述的显示面板，其中，所述显示面板还包括第一子像素，所述第一子像素位于所述第二过渡显示区，所述第一子像素包括：
    第三发光单元；
    第三像素驱动电路，用于向所述第三发光单元提供驱动电流。
  8. 根据权利要求7所述的显示面板，其中，所述显示面板还包括第二子像素，所述第二子像素位于所述第一过渡显示区，所述第二子像素包括：
    第四发光单元；
    第四像素驱动电路，用于向所述第四发光单元提供驱动电流；
    所述第四像素驱动电路与所述第一像素驱动电路位于不同列。
  9. 根据权利要求1所述的显示面板，其中，所述第一发光单元和所述第一像素驱动电路均为多个，所述第一像素驱动电路和与其连接的所述第一发光单元位于同一行，每个所述第一像素驱动电路和与其连接的所述第一发光单元在第一方向上间隔相同子像素列。
  10. 根据权利要求3所述的显示面板，其中，所述显示面板还包括：
    衬底基板；
    第一导电层，设置于所述衬底基板的一侧；
    第二导电层，设置于所述第一导电层背离所述衬底基板的一侧；
    第三导电层，设置于所述第二导电层背离所述衬底基板的一侧，至少部分所述第三导电层用于形成所述第一信号线和所述第二信号线。
  11. 根据权利要求10所述的显示面板，其中，所述第一信号线、第二信号线、第三信号线均为多条，所述第三信号线连接于相对应的所述第一信号线和第二信号线之间，多条所述第三信号线包括多条第一子信号线和多条第二子信号线；
    至少部分所述第一导电层用于形成所述第一子信号线；
    至少部分所述第二导电层用于形成所述第二子信号线；
    其中，所述第一子信号线在所述衬底基板的正投影与所述第二子信号线在所述衬底基板的正投影沿第二方向依次交替分布。
  12. 根据权利要求10所述的显示面板，其中，所述第一信号线、第二信号线、第三信号线均为多条，所述第三信号线连接于相对应的所述第一信号线和第二信号线之间；
    所述第三信号线由至少部分所述第一导电层形成；
    其中，所述第三信号线在所述衬底基板的正投影沿第二方向依次间隔分布。
  13. 根据权利要求10所述的显示面板，其中，所述第一信号线、第二信号线、第三信号线均为多条，所述第三信号线连接于相对应的所述第一信号线和第二信号线之间；
    所述第三信号线由至少部分所述第二导电层形成；
    其中，所述第三信号线在所述衬底基板的正投影沿第二方向依次间隔分布。
  14. 根据权利要求10-13任一项所述的显示面板，其中，所述第一像素驱动电路包括驱动晶体管，以及连接于所述驱动晶体管栅极的电容；
    部分所述第一导电层用于形成所述驱动晶体管的栅极，部分所述第二导电层用于形成所述电容的一电极；
    所述第一信号线用于向所述驱动晶体管提供数据信号。
  15. 根据权利要求14所述的显示面板，其中，所述显示面板还包括：
    第四导电层，位于所述第三导电层背离所述衬底基板的一侧，至少部分所述第四导电层用于形成所述第一发光单元的阳极，所述第四导电层还包括：
    第一连接线，用于连接所述第二像素驱动电路和所述第二发光单元的阳极。
  16. 根据权利要求15所述的显示面板，其中，所述显示面板还包括：
    第五透明导电层，位于所述第三导电层和所述第四导电层之间，所述第五透明导电层包括第二连接线，所述第二连接线用于连接所述第一像素驱动电路和所述第一发光单元的阳极。
  17. 根据权利要求8所述的显示面板，其中，所述主显示区的像素密度大于所述第一走线区、第一过渡显示区、第二过渡显示区、透光区的像素密度。
  18. 根据权利要求17所述的显示面板，其中，所述第一走线区、第一过渡显示区、第二过渡显示区、透光区的像素密度相同。
  19. 根据权利要求18所述的显示面板，其中，所述第一方向为行方向，所述第二方向为列方向，所述第一走线区、第一过渡显示区、第二过渡显示区、透光区形成低像素密度区，所述显示面板包括：
    多个第一像素单元，位于低像素密度区；
    其中，在行方向上，相邻所述第一像素单元间隔相同个数的像素单元，在列方向上，相邻所述第一像素单元间隔相同个数的像素单元。
  20. 根据权利要求19所述的显示面板，其中，
    其中，在行方向上，相邻所述第一像素单元之间间隔三个像素单元，在列方向上，相邻所述第一像素单元间隔一个像素单元。
  21. 根据权利要求20所述的显示面板，其中，所述第一像素单元包括：
    R发光单元；
    第一G发光单元，与所述R发光单元位于同一行，且在行方向上与所述R发光单元相邻设置；
    B发光单元，与所述R发光单元位于同一列，且在列方向上与所述R发光单元相邻设置；
    第二G发光单元，与所述B发光单元位于同一行，与所述第一G发光单元位于同一列，且在行方向上与所述B发光单元相邻设置，在列方向上与第一G发光单元相邻设置；
    其中，位于所述透光区的所述R发光单元、第一G发光单元、B发光单元、第二G发光单元形成所述第一发光单元；
    位于所述第一走线区的所述R发光单元、第一G发光单元、B发光单元、第二G发光单元形成所述第二发光单元；
    位于所述第二过渡显示区的所述R发光单元、第一G发光单元、B发光单元、第二G发光单元形成所述第三发光单元；
    位于所述第一过渡显示区的所述R发光单元、第一G发光单元、B发光单元、第二G发光单元形成所述第四发光单元。
  22. 根据权利要求21所述的显示面板，其中，所述第一走线区在第二方向上的尺寸等于所述第一像素单元在第二方向的尺寸。
  23. 根据权利要求21所述的显示面板，其中，所述第二过渡显示区在第二方向上的尺寸等于所述第一像素单元在第二方向的尺寸。
  24. 一种显示装置，其中，包括：
    权利要求1-23任一项所述的显示面板；
    摄像头，所述摄像头与所述显示面板的透光区正对。
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