WO2021196530A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2021196530A1
WO2021196530A1 PCT/CN2020/115075 CN2020115075W WO2021196530A1 WO 2021196530 A1 WO2021196530 A1 WO 2021196530A1 CN 2020115075 W CN2020115075 W CN 2020115075W WO 2021196530 A1 WO2021196530 A1 WO 2021196530A1
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WIPO (PCT)
Prior art keywords
electrode
sub
circuit
light
terminal
Prior art date
Application number
PCT/CN2020/115075
Other languages
English (en)
French (fr)
Inventor
程鸿飞
郝学光
李会
许晨
李盼
Original Assignee
京东方科技集团股份有限公司
北京京东方技术开发有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 北京京东方技术开发有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2021537861A priority Critical patent/JP2023519452A/ja
Priority to US17/293,086 priority patent/US12002422B2/en
Priority to KR1020227034297A priority patent/KR20220160003A/ko
Priority to EP20897628.2A priority patent/EP4131237A4/en
Publication of WO2021196530A1 publication Critical patent/WO2021196530A1/zh

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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • H10K59/10—OLED displays
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    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • H10K59/10—OLED displays
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    • H10K59/131—Interconnections, e.g. wiring lines or terminals
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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Definitions

  • the embodiments of the present disclosure relate to a display substrate and a display device.
  • OLED Organic Light-Emitting Diode, organic light-emitting diode
  • At least one embodiment of the present disclosure provides a display substrate, including a base substrate, a plurality of sub-pixels, a first power line, and an electrical connection layer.
  • the base substrate includes a display area and a non-display area; the plurality of sub-pixels are located in the In the display area of the base substrate, each of the plurality of sub-pixels includes a pixel circuit, and the pixel circuit is used to drive a light-emitting element to emit light; the plurality of pixel circuits of the plurality of sub-pixels are distributed along the first direction and the second direction as Multiple rows and multiple columns, the pixel circuit includes a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, and a storage sub-circuit; the driving sub-circuit includes a control terminal, a first terminal and a second terminal, and is configured to The light-emitting element is connected to and controls the driving current flowing through the light-emitting element; the data writing sub-circuit includes a
  • the first power line is located in the display area, extends along the first direction, is connected to the first voltage terminal, and is configured to provide a first power voltage for the plurality of sub-pixels.
  • the electrical connection layer is located on a side of the pixel circuit away from the base substrate, the electrical connection layer includes a first portion located in the display area, the first portion includes a plurality of first connection electrodes, and the plurality of second A connecting electrode is arranged in one-to-one correspondence with the plurality of sub-pixels, the pixel circuit of each sub-pixel is electrically connected to the corresponding first connecting electrode through the first via hole, and the first connecting electrode corresponding to each sub-pixel is configured to pass through
  • the second via is electrically connected to the light-emitting element, thereby electrically connecting the pixel circuit of the sub-pixel and the light-emitting element; the first via and the second via are in a direction perpendicular to the base substrate
  • the upper part does not overlap; the first part of the electrical connection layer and the first power line do
  • the first via and the second via are arranged along the first direction.
  • the display substrate further includes a power signal line and a gate driving circuit located in the non-display area, and the gate driving circuit is configured to provide the first scan signal and the sub-pixel with the The second scan signal, the power signal line is configured to provide a power signal for the gate driving circuit of the sub-pixel;
  • the electrical connection layer further includes a second portion located in the non-display area, the second portion including An auxiliary signal line, the auxiliary signal line is connected in parallel with the power signal line.
  • the gate driving circuit includes a plurality of shift register units, and the plurality of shift register units are connected to the plurality of rows of sub-pixels in a one-to-one correspondence, and are configured to direct output nodes to a corresponding row of sub-pixels.
  • the sub-pixels output the first scan signal and the second scan signal
  • each shift register unit includes a first capacitor connected to the output node, and the first capacitor includes a first electrode and a second electrode, so
  • the second part of the electrical connection layer further includes an auxiliary capacitor electrode, and the auxiliary capacitor electrode is connected in parallel with the first electrode or the second electrode of the first capacitor.
  • the sub-pixel further includes a first light-emission control sub-circuit.
  • the first light-emission control sub-circuit includes a control terminal, a first terminal, and a second terminal.
  • the first terminal is electrically connected to the driving sub-circuit, and the second terminal is configured
  • the control terminal is configured to receive a first light emission control signal
  • the first light emission control sub-circuit is configured to respond to the first light emission control signal so that a driving current can be applied to the light emission Element; the first via, the second via, and the third via are not overlapped in a direction perpendicular to the base substrate.
  • the display substrate further includes a first light-emitting control line extending along the second direction and connected to the control terminal of the first light-emitting control sub-circuit to provide the The first light-emitting control signal, the orthographic projection of the first via on the base substrate and the orthographic projection of the second via on the base substrate are respectively located on the first light-emitting control line
  • the base substrate is on both sides of the orthographic projection.
  • the portion of the first connection electrode exposed by the second via has an inclined surface with respect to the base substrate.
  • each sub-pixel further includes a second connection electrode, the second connection electrode is located on a side of the storage capacitor that is away from the base substrate, and the second connection electrode is connected to the The second electrode of the storage capacitor is connected to the second end of the compensation sub-circuit.
  • the second connection electrode overlaps the first connection electrode in a direction perpendicular to the base substrate.
  • the driver sub-circuit includes a first transistor, and the gate, first electrode, and second electrode of the first transistor serve as the control terminal, the first terminal, and the second terminal of the driver sub-circuit, respectively.
  • the first electrode of the storage capacitor includes a fourth via hole
  • the second connection electrode is electrically connected to the second electrode of the storage capacitor through the fourth via hole.
  • the fourth via hole and the active layer of the first transistor do not overlap in a direction perpendicular to the base substrate.
  • the active layer of the first transistor includes a bent structure.
  • the active layer of the first transistor is similar to an " ⁇ " shape or a "several" shape, and includes a first part, a second part, and a connecting part.
  • the first part and the second part of the active layer are both It is straight and not on the same horizontal line, and the connecting part of the active layer connects the first part and the second part, and is arc-shaped.
  • the average width of the connection part of the active layer is greater than the average width of the first part or the second part.
  • the display substrate further includes a data line that extends along the first direction and is connected to the first end of the data writing sub-circuit to provide the data signal; the storage The first electrode of the capacitor overlaps the first electrode of the first transistor in a direction perpendicular to the base substrate, and the first electrode of the first transistor has a first electrode near the data line along the first direction.
  • the first electrode of the storage capacitor has a capacitor electrode side in the first direction that is close to the data line.
  • the capacitor electrode side is larger than the first electrode side. The extreme side is closer to the data line.
  • the non-display area includes a binding area
  • the electrical connection layer further includes a second portion located in the non-display area, and the second portion includes a binding electrode located in the non-display area
  • the display substrate further includes an auxiliary binding electrode, and the auxiliary binding electrode is arranged in the same layer and made of the same material as the first power line, and is overlapped with the binding electrode.
  • the second part of the electrical connection layer further includes a wire located in the non-display area, one end of the wire is connected to the bonding electrode, and the other end extends to the display area;
  • the non-display area further includes a bending area, and a part of the wiring is located in the bending area.
  • the display substrate further includes an organic insulating layer, the organic insulating layer is located between the electrical connection layer and the pixel circuit, the first via is located in the organic insulating layer, and the The organic insulating layer includes a bending portion located in a bending area, and the bending portion is located on a side of the wiring close to the base substrate.
  • all patterns of the electrical connection layer in the display area and the first power line do not overlap in a direction perpendicular to the base substrate.
  • the embodiment of the present disclosure also provides a display device, including the above-mentioned display substrate.
  • FIG. 1A is one of the schematic diagrams of the display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 1B is one of the pixel circuit diagrams in the display substrate provided by at least one embodiment of the present disclosure
  • 1C is a second circuit diagram of a pixel in a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 2A is a second schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • 2B is the third schematic diagram of the display substrate provided by at least one embodiment of the present disclosure.
  • Fig. 2C is an example of a cross-sectional view of Fig. 2A along the section line A1-A2;
  • FIG. 3 is a fourth schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 4A is another example of a cross-sectional view of FIG. 2A along the section line A1-A2;
  • FIG. 4B is another example of the cross-sectional view of FIG. 2A along the section line A1-A2;
  • FIG. 5 is a fifth schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • 6A is a schematic diagram of a gate driving circuit provided by at least one embodiment of the present disclosure.
  • FIG. 6B is a sixth diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • Figure 6C is a cross-sectional view of Figure 6B along the section line B1-B2;
  • Figure 6D is a cross-sectional view of Figure 6B along the section line E1-E2;
  • Fig. 7A is an example of a cross-sectional view of Fig. 1A along the section line D1-D2;
  • Fig. 7B is another example of a cross-sectional view of Fig. 1A along the section line D1-D2;
  • FIG. 8 is a schematic diagram of a display panel provided by at least one embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure.
  • OLED Organic Light-Emitting Diode, organic light-emitting diode
  • higher requirements are placed on the structural design of the display substrate, such as the arrangement of pixels and signal lines.
  • OLED display device with a resolution of 4K an OLED display device with a large size and a resolution of 8K has doubled the number of sub-pixel units that need to be installed, and the pixel density has increased correspondingly.
  • the signal line The line width of the signal line has also become smaller, which causes the self resistance of the signal line to increase; on the other hand, the overlap between the signal lines increases, which causes the parasitic capacitance of the signal line to increase, which causes the resistance and capacitance load of the signal line to increase.
  • the signal delay (RC delay), voltage drop (IR drop), and voltage rise (IR rise) caused by the RC load will also become serious. These phenomena will seriously affect the display quality of the display product. For example, when the layout design is more compact, it will affect the flatness of the pixel electrode, thereby affecting the uniformity of light emission and reducing the display effect.
  • FIG. 1A is a schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • the display substrate 20 includes a display area DA and a non-display area NDA outside the display area DA.
  • the display area DA is provided with a plurality of sub-pixels 100, a plurality of gate lines 11, and a plurality of data lines 12 distributed in an array.
  • Each sub-pixel 100 includes a light-emitting element and a pixel circuit that drives the light-emitting element.
  • a plurality of gate lines 11 and a plurality of data lines 12 cross each other to define a plurality of pixel regions distributed in an array in the display region, and a pixel circuit of a sub-pixel 100 is provided in each pixel region.
  • the pixel circuit is, for example, a conventional pixel circuit, such as a 2T1C (ie, two transistors and a capacitor) pixel circuit, 4T2C, 5T1C, 7T1C, etc. nTmC (n, m are positive integers and n is greater than or equal to 2) pixel circuit, and
  • the pixel circuit may further include a compensation sub-circuit.
  • the compensation sub-circuit includes an internal compensation sub-circuit or an external compensation sub-circuit.
  • the compensation sub-circuit may include a transistor, a capacitor, and the like.
  • the pixel circuit may further include a reset circuit, a light emission control sub-circuit, a detection circuit, and the like.
  • the display substrate may further include a gate driving circuit 13 and a data driving circuit (not shown) located in the non-display area NDA.
  • the gate driving circuit 13 is connected to the pixel circuit through the gate line 11 to provide various scan signals (the first scan signal and the second scan signal below), and the data driving sub-circuit is connected to the pixel circuit through the data line 12 to provide Data signal. As shown in FIG.
  • the display substrate 20 includes two gate driving circuits 13, which are respectively located on both sides of the display area DA and connected to the odd-numbered and even-numbered gate lines.
  • the setting can improve the response speed of the gate drive circuit.
  • the positional relationship between the gate driving circuit 13, the gate line 11, and the data line 12 in the display substrate shown in FIG. 1A is only an example, and the actual arrangement position can be designed according to needs.
  • the non-display area NDA of the display substrate 20 further includes a bonding area BP.
  • the bonding area BP is provided with a bonding pad 80, and the bonding electrode is used to interact with external components.
  • the driver chip performs bonding to provide various signals for the pixel array structure of the display area, such as power supply voltage signals, timing signals, and so on.
  • the bonding electrode 80 is in a bare state.
  • FIG. 1A only schematically shows the bonding electrode 80 connected to the gate driving circuit 13 and the data line 12, but the embodiments of the present disclosure are not limited thereto.
  • the pixel array structure in the display area DA is connected to the binding electrode 80 through a wire 81 to realize signal transmission between the pixel array structure and the binding electrode.
  • the display substrate 20 is a flexible substrate, and the non-display area NDA of the display substrate 20 may further include a bending area BA.
  • the bending area BA is located between the display area DA and the binding area BP.
  • the binding area BP can be bent to the back of the display substrate 20 to achieve a narrow frame. show.
  • the bending area BA is located between the display area DA and the binding area BP.
  • the display substrate 20 may further include a control circuit (not shown).
  • the control circuit is configured to control the data driving circuit to apply the data signal and the gate driving circuit to apply the scan signal.
  • An example of this control circuit is a timing control circuit (T-con).
  • the control circuit may be in various forms, for example, including a processor and a memory.
  • the memory includes executable code, and the processor runs the executable code to execute the above detection method.
  • the processor may be a central processing unit (CPU) or other form of processing device with data processing capability and/or instruction execution capability, for example, may include a microprocessor, a programmable logic controller (PLC), and the like.
  • CPU central processing unit
  • PLC programmable logic controller
  • the storage device may include one or more computer program products, and the computer program products may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory.
  • Volatile memory may include random access memory (RAM) and/or cache memory (cache), for example.
  • the non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, and the like.
  • One or more computer program instructions can be stored on a computer-readable storage medium, and the processor can execute functions desired by the program instructions.
  • Various application programs and various data can also be stored in the computer-readable storage medium.
  • the pixel circuit may include a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, and a storage sub-circuit, and may also include a light-emission control sub-circuit, a reset circuit, etc., as required.
  • FIG. 1B shows a schematic diagram of a pixel circuit.
  • the pixel circuit 900 includes a driving sub-circuit 122, a data writing sub-circuit 126, a compensation sub-circuit 128, a storage sub-circuit 127, a first light-emission control sub-circuit 123, a second light-emission control sub-circuit 124, and a reset Circuit 129.
  • the driving sub-circuit 122 includes a control terminal 131, a first terminal 132, and a second terminal 133, which are configured to control the driving current flowing through the light-emitting element 120, and the control terminal 131 of the driving sub-circuit 122 is connected to the first node N1,
  • the first terminal 132 of the driving sub-circuit 122 is connected to the second node N2, and the second terminal 133 of the driving sub-circuit 122 is connected to the third node N3.
  • the data writing sub-circuit 126 includes a control terminal, a first terminal, and a second terminal.
  • the control terminal is configured to receive the first scan signal
  • the first terminal is configured to receive the data signal
  • the second terminal is connected to the second terminal of the driving sub-circuit 122.
  • One end 132 (the second node N2) is connected, and is configured to write the data signal into the first end 132 of the driving sub-circuit 122 in response to the first scan signal Ga1.
  • the first terminal of the data writing sub-circuit 126 is connected to the data line 12 to receive the data signal
  • the control terminal is connected to the gate line 11 to receive the first scan signal Ga1.
  • the data writing sub-circuit 126 can be turned on in response to the first scan signal Ga1, so that the data signal can be written to the first terminal 132 (the second node N2) of the driving sub-circuit 122, and
  • the data signal is stored in the storage sub-circuit 127, so that a driving current for driving the light-emitting element 120 to emit light can be generated according to the data signal during the light-emitting phase, for example.
  • the compensation sub-circuit 128 includes a control terminal, a first terminal, and a second terminal.
  • the control terminal is configured to receive the second scan signal Ga2.
  • the two terminals 133 are electrically connected, and the compensation sub-circuit is configured to perform threshold compensation on the driving sub-circuit 120 in response to the second scan signal.
  • the storage sub-circuit 127 is electrically connected to the control terminal 131 and the first voltage terminal VDD of the driving sub-circuit 122, and is configured to store the data signal written by the data writing sub-circuit 126.
  • the compensation sub-circuit 128 can be turned on in response to the second scan signal Ga2, so that the data signal written by the data writing sub-circuit 126 can be stored in the storage sub-circuit 127.
  • the compensation sub-circuit 128 may electrically connect the control terminal 131 and the second terminal 133 of the driving sub-circuit 122, so that the threshold voltage related information of the driving sub-circuit 122 can be stored accordingly.
  • the stored data signal and the threshold voltage can be used to control the driving sub-circuit 122 during the light-emitting phase, so that the output of the driving sub-circuit 122 is compensated.
  • the first light-emitting control sub-circuit 123 is connected to the first terminal 132 (the second node N2) of the driving sub-circuit 122 and the first voltage terminal VDD, and is configured to change the voltage of the first voltage terminal VDD in response to the first light-emitting control signal.
  • the first power supply voltage is applied to the first terminal 132 of the driving sub-circuit 122.
  • the first light emission control sub-circuit 123 is connected to the first light emission control terminal EM1, the first voltage terminal VDD, and the second node N2.
  • the second emission control sub-circuit 124 and the second emission control terminal EM2 are connected, and are configured to drive current in response to the second emission control signal. It can be applied to the light emitting element 122.
  • the second light-emission control sub-circuit 124 is turned on in response to the second light-emission control signal provided by the second light-emission control terminal EM2, so that the driving sub-circuit 122 can be electrically connected to the light-emitting element 120 through the second light-emission control sub-circuit 124 Connected to drive the light-emitting element 120 to emit light under the control of the driving current; and in the non-light-emitting phase, the second light-emission control sub-circuit 124 is turned off in response to the second light-emission control signal, so as to avoid current flowing through the light-emitting element 120 to cause it to emit light , Can improve the contrast of the corresponding display device.
  • the second light-emitting control sub-circuit 124 can also be turned on in response to the second light-emitting control signal, so that the reset circuit can be combined with the reset circuit to perform a reset operation on the driving sub-circuit 122 and the light-emitting element 120.
  • the second light emission control signal EM2 can be the same as or different from the first light emission control signal EM1, for example, the two can be connected to the same or different signal output terminals.
  • the reset circuit 129 is connected to the reset voltage terminal Vinit and the first terminal 134 (fourth node N4) of the light emitting element 120, and is configured to apply a reset voltage to the first terminal 134 of the light emitting element 120 in response to a reset signal.
  • the reset signal may also be applied to the control terminal 131 of the driving sub-circuit, that is, the first node N1.
  • the reset signal is the second scan signal, and the reset signal may also be another signal synchronized with the second scan signal, which is not limited in the embodiment of the present disclosure. For example, as shown in FIG.
  • the reset circuit 129 is respectively connected to the first terminal 134 of the light-emitting element 120, the reset voltage terminal Vinit, and the reset control terminal Rst (reset control line).
  • the reset circuit 129 can be turned on in response to a reset signal, so that a reset voltage can be applied to the first end 134 and the first node N1 of the light-emitting element 120, so that the driving sub-circuit 122 and the compensation sub-circuit 128 can be And the light-emitting element 120 performs a reset operation to eliminate the influence of the previous light-emitting stage.
  • the light-emitting element 120 includes a first end 134 and a second end 135.
  • the first end 134 of the light-emitting element 120 is configured to be coupled to the second end 133 of the driving sub-circuit 122, and the second end 135 of the light-emitting element 120 is configured to be coupled to The second voltage terminal VSS is connected.
  • the first end 134 of the light-emitting element 120 may be connected to the third node N3 through the second light-emitting control sub-circuit 124.
  • the embodiments of the present disclosure include but are not limited to this situation.
  • the light-emitting element 120 can be various types of OLEDs, such as top-emission, bottom-emission, double-side emission, etc., which can emit red light, green light, blue light, or white light.
  • the first electrode and the second electrode of the OLED serve as The first end 134 and the second end 135 of the light-emitting element.
  • the embodiments of the present disclosure do not limit the specific structure of the light-emitting element.
  • the first node N1, the second node N2, the third node N3, and the fourth node N4 do not necessarily represent actual components, but represent related circuits in the circuit diagram.
  • the confluence point of the connection does not necessarily represent actual components, but represent related circuits in the circuit diagram.
  • the symbol Vd can represent both the data signal terminal and the level of the data signal.
  • the symbols Ga1 and Ga2 can represent both the first scan signal and the second scan signal.
  • the signal can also represent the first scan signal terminal and the second scan signal terminal.
  • Rst can represent both the reset control terminal and the reset signal.
  • the symbol Vinit can represent both the reset voltage terminal and the reset voltage.
  • the symbol VDD can both represent the first A voltage terminal can also represent the first power supply voltage
  • the symbol VSS can represent both the second voltage terminal and the second power supply voltage.
  • FIG. 1C is a circuit diagram of a specific implementation example of the pixel circuit shown in FIG. 1B.
  • the pixel circuit 900 includes: first to seventh transistors T1, T2, T3, T4, T5, T6, T7, and a storage capacitor Cst.
  • the first transistor T1 is used as a driving transistor, and the other second to seventh transistors are used as switching transistors.
  • the driving sub-circuit 122 may be implemented as a first transistor T1.
  • the gate of the first transistor T1 serves as the control terminal 131 of the driving sub-circuit 122 and is connected to the first node N1;
  • the first pole of the first transistor T1 serves as the first terminal 132 of the driving sub-circuit 122 and is connected to the second node N2;
  • the second pole of the first transistor T1 serves as the second terminal 133 of the driving sub-circuit 122 and is connected to the third node N3.
  • the data writing sub-circuit 126 may be implemented as a second transistor T2.
  • the gate of the second transistor T2 is connected to the first scan line (first scan signal terminal Ga1) to receive the first scan signal, and the first electrode of the second transistor T2 is connected to the data line (data signal terminal Vd) to receive the data signal ,
  • the second pole of the second transistor T2 is connected to the first terminal 132 (the second node N2) of the driving sub-circuit 122.
  • the second transistor T2 is a P-type transistor, for example, the active layer is a thin film transistor with low-temperature doped polysilicon.
  • the compensation sub-circuit 128 may be implemented as a third transistor T3.
  • the gate of the third transistor T3 is configured to be connected to the second scan line (the second scan signal terminal Ga2) to receive the second scan signal, the first pole of the third transistor T3 and the control terminal 131 (first The node N1) is connected, and the second electrode of the third transistor T3 is connected to the second end 133 (third node N3) of the driving sub-circuit 122.
  • the storage sub-circuit 127 may be implemented as a storage capacitor Cst.
  • the storage capacitor Cst includes a first electrode Ca and a second electrode Cb.
  • the first electrode Ca of the storage capacitor is coupled to the first voltage terminal VDD.
  • the second electrode Cb of the storage capacitor and the control terminal 131 of the driving sub-circuit 122 are coupled, such as electrical connection.
  • the first light emission control sub-circuit 123 may be implemented as a fourth transistor T4.
  • the gate of the fourth transistor T4 is connected to the first emission control line (first emission control terminal EM1) to receive the first emission control signal, and the first pole of the fourth transistor T4 is connected to the first voltage terminal VDD to receive the first power supply Voltage, the second pole of the fourth transistor T4 is connected to the first terminal 132 (the second node N2) of the driving sub-circuit 122.
  • the first end and the second end of the light-emitting element 120 may also be referred to as the first electrode and the second electrode of the light-emitting element, respectively.
  • the light-emitting element 120 may be embodied as a light-emitting diode, such as an OLED, and its first electrode 134 (for example, an anode) and the fourth node N4 are connected and configured to pass through the second light-emitting control sub-circuit 124 from the second driving sub-circuit 122.
  • the terminal 133 receives the driving current
  • the second electrode 135 (for example, the cathode) of the light emitting element 120 is configured to be connected to the second voltage terminal VSS to receive the second power supply voltage.
  • the second voltage terminal can be grounded, that is, VSS can be 0V.
  • the second light emission control sub-circuit 124 may be implemented as a fifth transistor T5.
  • the gate of the fifth transistor T5 is connected to the second emission control line (the second emission control terminal EM2) to receive the second emission control signal.
  • the first pole of the fifth transistor T5 and the second terminal 133 (the first The three nodes N3) are connected, and the second electrode of the fifth transistor T5 is connected to the first end 134 (fourth node N4) of the light-emitting element 120.
  • the reset circuit 129 may include a first reset circuit configured to apply a first reset voltage Vini1 to the first node N1 in response to a first reset signal Rst1 and a second reset circuit configured to The second reset voltage Vini2 is applied to the fourth node N4 in response to the second reset signal Rst2.
  • the first reset circuit is implemented as a sixth transistor T6, and the second reset circuit is implemented as a seventh transistor T7.
  • the gate of the sixth transistor T6 is configured to be connected to the first reset control terminal Rst1 to receive the first reset signal Rst1, and the first pole of the sixth transistor T6 is connected to the first reset voltage terminal Vinit1 to receive the first reset voltage Vinit1.
  • the second pole of the six transistor T6 is configured to be connected to the first node N1.
  • the gate of the seventh transistor T7 is configured to be connected to the second reset control terminal Rst2 to receive the second reset signal Rst2, and the first pole of the seventh transistor T7 is connected to the second reset voltage terminal Vinit2 to receive the second reset voltage Vinit2.
  • the second pole of the seven transistor T7 is configured to be connected to the fourth node N4.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • thin film transistors are used as examples for description.
  • the source and drain of the transistor used here can be symmetrical in structure, so the source and drain of the transistor can be structurally indistinguishable.
  • one pole is directly described as the first pole and the other pole is the second pole.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages) );
  • the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltage)
  • the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable Voltage).
  • FIG. 2A is a schematic diagram of a display substrate 20 provided by at least one embodiment of the present disclosure.
  • the pixel circuits of the plurality of sub-pixels 100 are arranged as a pixel circuit array, the column direction of the pixel circuit array is the first direction D1, the row direction is the second direction D2, and the first direction D1 and the second direction D2 intersect, for example, orthogonally.
  • the pixel circuit of each sub-pixel can have exactly the same structure except for the connection structure with the light-emitting element, that is, the pixel circuit is repeatedly arranged in the row and column directions, and the connection structure of the different sub-pixels with the light-emitting element is based on
  • the arrangement shape and position of the electrode of the light emitting structure of each sub-pixel may be different.
  • the general frame (for example, the shape and position of each signal line) of the pixel circuit of different color sub-pixels is basically the same, and the relative positional relationship of each transistor is also basically the same.
  • the width, The shape, or the channel size and shape of some transistors, or the connecting lines or via positions used to connect to the light-emitting elements of different sub-pixels can be different, and can be adjusted according to each layout structure and sub-pixel arrangement.
  • FIG. 2A exemplarily shows two adjacent sub-pixels 100 in the same row, and shows the semiconductor layer 102, the first conductive layer 201, the second conductive layer 202, the third conductive layer 203, and the fourth conductive layer. ⁇ 204.
  • Fig. 2C is an example of a cross-sectional view of Fig. 2A along the section line A1-A2.
  • the layers 204 are sequentially disposed on the base substrate 101, thereby forming the structure of the display substrate as shown in FIG. 2A.
  • the embodiment of the present disclosure is not limited to this layout.
  • FIG. 2B corresponds to FIG. 2A and illustrates the semiconductor layer 102 and the first conductive layer (gate layer) 201 of the transistors T1-T7 in the two sub-pixels 100, and shows the gate, first electrode, and second electrode of each transistor. Two poles.
  • a large dashed frame shows the area where each sub-pixel 100 is located, and a small dashed frame shows the gates T1g-T7g of the first to seventh transistors T1-T7 in one sub-pixel 100.
  • Tng, Tns, Tnd, and Tna are used to denote the gate, the first electrode, the second electrode, and the active layer of the n-th transistor Tn, respectively, where n is 1-7.
  • the “same layer arrangement” in the present disclosure refers to a structure formed by two (or more than two) structures formed by the same deposition process and patterned by the same patterning process. Their materials Can be the same or different.
  • the "integrated structure” in the present disclosure refers to two (or more than two) structures formed by the same deposition process and patterned by the same patterning process to form a structure connected to each other, and their materials may be the same or different .
  • the semiconductor layer 102 includes the active layers T1a-T7a of the first to seventh transistors T1-T7.
  • the active layers T1a-T7a of the first to seventh transistors T1-T7 are connected to each other as an integral structure.
  • the semiconductor layer 102 in each column of sub-pixels is an integrated structure connected to each other, and the semiconductor layers in two adjacent columns of sub-pixels are spaced apart from each other, so that signal crosstalk between adjacent pixels in the second direction can be avoided.
  • the first conductive layer 201 includes gates T1g-T7g of the first to seventh transistors T1-T7.
  • the third transistor T3 and the sixth transistor T6 adopt a double gate structure, which can improve the gate control capability of the transistor and reduce the leakage current.
  • the first conductive layer 104 further includes a plurality of scan lines 210, a plurality of reset control lines 220, and a plurality of light-emitting control lines 230 that are insulated from each other.
  • each row of sub-pixels is respectively connected to a scan line 210, a reset control line 220, and a light emission control line 230.
  • the scan line 210 is electrically connected to the gate of the second transistor T2 in the corresponding row of sub-pixels (or is an integrated structure) to provide the first scan signal Ga1, and the reset control line 220 is connected to the gate of the sixth transistor T6 in the corresponding row of sub-pixels.
  • the gate is electrically connected to provide the first reset signal Rst1
  • the emission control line 230 is electrically connected to the gate of the fourth transistor T4 in the corresponding row of sub-pixels to provide the first emission control signal EM1.
  • the scan line 210 is also electrically connected to the gate of the third transistor T3 (or in an integrated structure) to provide a second scan signal Ga2, that is, a first scan signal Ga1 and a second scan signal Ga2 It may be the same signal;
  • the emission control line 230 is also electrically connected to the gate of the fifth transistor T5 to provide the second emission control signal EM2, that is, the first emission control signal EM1 and the second emission control signal EM2 are the same signal.
  • the gate of the seventh transistor T7 of the pixel circuit of the current row and the pixel circuit of the next row (that is, according to the scanning order of the scan line, the pixel circuit row where the scan line is sequentially turned on after the scan line of the current row is located
  • the reset control line 220(n+1) corresponding to) is electrically connected to receive the second reset signal Rst2.
  • the gate line 11 dividing the pixel area in the column direction (first direction D1) can be the reset control line 220 or the light emission control line 230, and each pixel circuit area includes a reset control line 220. , Each part of a light-emitting control line 230 and a scan line 210.
  • the display substrate 20 adopts a self-aligned process, using the first conductive layer 201 as a mask to conduct a conductive treatment (for example, doping treatment) on the semiconductor layer 102, so that the semiconductor layer 102 is not
  • a conductive treatment for example, doping treatment
  • the portion covered by the first conductive layer 201 is conductive, so that the portions of the active layer of each transistor located on both sides of the channel region are conductive to form the first electrode and the second electrode of the transistor, respectively.
  • the second conductive layer 202 includes the first electrode Ca of the storage capacitor.
  • the first electrode Ca of the storage capacitor overlaps the gate T1g of the first transistor T1 in a direction perpendicular to the base substrate 101 to form a storage capacitor Cst, that is, the gate T1g of the first transistor T1 serves as the storage capacitor Cst.
  • the second electrode Cb the first electrode Ca of the storage capacitor includes a via 301 (an example of the fourth via in the present disclosure), and the via 301 exposes at least part of the gate T1g of the first transistor T1 to facilitate the gate
  • the pole T1g is electrically connected to other structures.
  • the first electrodes Ca of the storage capacitors of adjacent sub-pixels are electrically connected to each other. Since the first electrode Ca of the storage capacitor of each sub-pixel is electrically connected to the first power supply line 250 corresponding to the sub-pixel, and the first electrodes Ca of the plurality of storage capacitors are connected to each other in the first direction D1, a plurality of first power supplies can be connected to each other.
  • the wires 250 are connected in a mesh structure, which can reduce the resistance and voltage drop on the power wires, so that the first power voltage is uniformly delivered to each sub-pixel, and the uniformity of the display substrate is improved.
  • the second conductive layer 202 may further include a plurality of reset voltage lines 240, and the plurality of reset voltage lines 240 are connected to a plurality of rows of sub-pixels in a one-to-one correspondence.
  • the reset voltage line 240 is electrically connected to the first electrode of the sixth transistor T6 in the corresponding row of sub-pixels to provide the first reset voltage Vinit1.
  • the first pole of the seventh transistor T7 in the sub-pixels in the current row may be electrically connected to the reset voltage line 240 corresponding to the sub-pixels in the next row to receive the second reset voltage Vinit2.
  • the third conductive layer 203 includes a first power line 250 extending along the first direction D1, and the first power line 250 is connected to the first voltage terminal VDD and is configured to provide the first power voltage VDD for the plurality of sub-pixels 100 .
  • the third conductive layer 203 includes a plurality of first power lines 250 electrically connected to a plurality of columns of sub-pixels in a one-to-one correspondence.
  • the first power line 250 is electrically connected to the first electrode Ca of the storage capacitor in the corresponding column of sub-pixels through the via 302, and electrically connected to the first electrode of the fourth transistor T4 through the via 303.
  • the various embodiments of the present disclosure do not limit the number and arrangement of the first power lines (for example, the corresponding connection with the sub-pixels).
  • the third conductive layer 203 further includes the plurality of data lines 12.
  • the multiple data lines 12 are electrically connected to multiple columns of sub-pixels in a one-to-one correspondence to provide data signals.
  • the data line 12 is electrically connected to the first electrode T2s of the second transistor T2 in the corresponding column of sub-pixels through the via 305 to provide the data signal.
  • the third conductive layer 203 further includes a connection electrode 231 (an example of the second connection electrode of the present disclosure), and one end of the connection electrode 231 passes through a via hole in the first electrode Ca of the storage capacitor.
  • 301 and the via 401 in the insulating layer are electrically connected to the gate T1g of the first transistor T1, that is, the second electrode Cb of the storage capacitor, and the other end is electrically connected to the first electrode of the third transistor T3 through the via 402,
  • the second electrode Cb of the storage capacitor is electrically connected to the first electrode T3s of the third transistor T3.
  • the via hole 401 penetrates the second insulating layer 104 and the third insulating layer 105
  • the via hole 402 penetrates the first insulating layer 103, the second insulating layer 104 and the third insulating layer 105.
  • the third conductive layer 203 further includes a connecting electrode 232.
  • One end of the connecting electrode 232 is electrically connected to the reset voltage line 240 through a via 403, and the other end is electrically connected to the sixth transistor T6 through a via 404.
  • the via hole 403 penetrates the third insulating layer 105
  • the via hole 404 penetrates the first insulating layer 103, the second insulating layer 104 and the third insulating layer 105.
  • the third conductive layer 203 further includes a connection electrode 233 that passes through a via 405 (an example of the third via in the present disclosure) and the second transistor T5.
  • the electrode T5d is electrically connected to the second electrode T5d of the fifth transistor T5 and the first electrode 134 of the light-emitting element.
  • the via 405 penetrates the first insulating layer 103, the second insulating layer 104, and the third Insulation layer 105.
  • the connecting electrode 233 is the second electrode contact electrode of the fifth transistor T5.
  • the fourth conductive layer 204 (an example of the electrical connection layer of the present disclosure) includes a first portion 204a located in the display area DA. As shown in FIG. There are two connection electrodes 234 (an example of the first connection electrode of the present disclosure), and the pixel circuit of each sub-pixel is electrically connected to the light-emitting element 120 through the connection electrode 234.
  • the pixel circuit in the embodiment of the present disclosure refers to a circuit structure (such as each transistor structure) located on the side of the fourth conductive layer 204 close to the base substrate 101, so as to be connected to the fourth conductive layer 204
  • the electrode 234, the light emitting element 120 above the fourth conductive layer 204, etc. are distinguished.
  • the fourth insulating layer 106 is located between the fourth conductive layer 204 and the pixel circuit 900, and the connecting electrode 234 passes through the via hole 307 in the fourth insulating layer 106 (the first via hole in the present disclosure).
  • An example of is electrically connected to the connection electrode 233 in the third conductive layer 203, thereby electrically connecting to the pixel circuit 900 of the sub-pixel.
  • the connecting electrode 234 is also configured to be electrically connected to the first electrode 134 of the light-emitting element 120 through a via 308 (an example of a second via in the present disclosure), thereby connecting the light-emitting element and the pixel circuit 900 (for example, the first electrode of the fifth transistor).
  • the via 308 is located in the fifth insulating layer 107; the via 307 and the via 308 do not overlap in the direction perpendicular to the base substrate 101, that is, the via 307 and the via 308 are on the base substrate.
  • the orthographic projections on 101 do not overlap.
  • connection electrode 234 Connecting the light emitting element 120 and the pixel circuit 900 through the connection electrode 234 has various beneficial effects.
  • the resistance of the pixel electrode (the first electrode 134) can be reduced to increase the driving current.
  • the flatness of the first electrode 134 of the light-emitting element 120 affects the light-emitting uniformity of the light-emitting layer.
  • the influence of the lower-layer pixel circuit 900 on the flatness of the first electrode 134 can be reduced.
  • the distance between the via 405 and the first electrode 134 can be increased in the longitudinal direction by providing the connection electrode 234, thereby reducing the effect of the deeper via 405 on the first electrode. The effect of flatness.
  • the via 307 and the via 308 are designed so as not to overlap in the direction perpendicular to the base substrate 101, which can avoid the direction perpendicular to the base substrate, which helps to disperse the influence of multiple vias in the longitudinal direction.
  • the flatness of the first electrode 134 is further improved.
  • the via 405, the via 307, and the via 308 do not overlap in the direction perpendicular to the base substrate 101, that is, the vias 405, 307, and 308 are on the base substrate 101.
  • the projections do not overlap each other.
  • the portion (ie, the first portion) of the fourth conductive layer 204 in the display area DA does not overlap with any of the first power lines 250 in the direction perpendicular to the base substrate 101.
  • the fourth conductive layer is located in the first part of the display area DA (that is, the fourth conductive layer is located in the entire pattern of the display area) and does not overlap any of the first power lines 250 in the direction perpendicular to the base substrate 101. Effectively reduce the parasitic capacitance on the first power line and improve the display effect.
  • the fourth conductive layer 204 may also include a second portion located in the non-display area NDA, and the second portion of the fourth conductive layer 204 may be arranged in parallel with the conductive structure located in the non-display area NDA to reduce the resistance of the conductive structure.
  • the conductive structure is, for example, a signal line or an electrode of a device. The details will be introduced later.
  • the orthographic projection of the via 307 and the via 308 on the base substrate 101 are both located within the orthographic projection of the third connecting electrode 234 on the base substrate.
  • the via holes 307 and the via holes 308 are arranged side by side in the D1 direction, and their center lines along the first direction D1 are substantially coincident. In this way, the size of the connecting electrode 234 in the second direction D2 can be reduced, and the overlapping of the connecting electrode 234 and the first power line 250 can be avoided.
  • the display substrate 20 further includes a pixel defining layer 108 on the first electrode of the light-emitting element.
  • An opening is formed in the pixel defining layer 108 to define the opening area 600 of the display substrate.
  • the light-emitting layer 136 is formed at least in the opening (the light-emitting layer 136 may also cover part of the pixel defining layer), and the second electrode 135 is formed on the light-emitting layer 136 to form the light-emitting element 120.
  • the second electrode 135 is a common electrode, and the entire surface is arranged in the display substrate 20.
  • the first electrode is the anode of the light-emitting element
  • the second electrode is the cathode of the light-emitting element.
  • the opening area 600 does not overlap with the vias 307 and 308 in the direction perpendicular to the base substrate 101 to improve the flatness of the light-emitting layer.
  • the via 308 in a direction parallel to the surface of the base substrate 101, the via 308 is farther away from the opening region 600 of the sub-pixel than the via 307 (for example, the area of the first electrode 134 is larger than the corresponding opening region 600).
  • the opening area 600 is roughly located in the middle area of the first electrode 134), that is, the orthographic projection of the via 308 on the base substrate 101 is farther away from the orthographic projection of the via 307 on the base substrate 101 The orthographic projection of the opening area 600 on the base substrate.
  • the fifth insulating layer 107 (for example, the second flat layer) where the via 308 is located, is opposite to the fourth insulating layer 106 (for example, the first flat layer) where the via 307 is located.
  • the flat layer is closer to the opening area 600. Therefore, the via hole 308 has a greater influence on the flatness of the portion of the first electrode 134 exposed to the opening area (that is, the portion used for contact with the light-emitting layer). Setting it farther away from the opening area (on the surface parallel to the base substrate) can reduce the influence of the via on the flatness of the light-emitting layer 136 in the opening area, and improve the performance of the light-emitting element.
  • the via 307 may partially overlap the opening area 600, because the layer where the via 307 is located is at least separated from the layer where the first electrode 134 is located between the fourth conductive layer 204, and the second layer where the via 308 is located. Five insulating layers 107, so the influence of the via 307 on the flatness of the opening area is smaller than the influence of the via 308 on the flatness of the opening area.
  • the orthographic projection of the via 307 and the via 308 on the base substrate are respectively located on both sides of the orthographic projection of the light emission control line 230 of the sub-pixel 100 on the base substrate. This arrangement can prevent the signal on the light-emitting control line 230 from interfering with the signal on the pixel electrode.
  • connection electrode 234 since the connection electrode 234 needs to extend away from the via hole 307 to be electrically connected to the first electrode 134 through the via hole 308, in order to avoid poor contact at the via hole 308, the connection electrode 234 is usually in the lateral direction. The upper part extends a sufficient distance so as to make sufficient contact with the first electrode 134. Since the layout design is relatively compact, this arrangement will cause the connection electrode 234 and the connection electrode 231 to overlap in a direction perpendicular to the base substrate 101 and generate parasitic capacitance. Errors generally occur when the patterning process is performed on each material layer to form a pattern.
  • the process can be designed to ensure that the parasitic capacitance exists in each sub-pixel, thereby improving the uniformity of the display.
  • the overlap size d1 of the orthographic projection of the connection electrode 234 on the base substrate 101 and the orthographic projection of the connection electrode 231 on the base substrate 101 satisfies: d1 ⁇ ( (cdbias1) ⁇ 2+ ⁇ (cdbias2) ⁇ 2), where cdbias1 is the difference between the design value and the actual value of the third conductive layer 203 where the connecting electrode 231 is located, and cdbias2 is the fourth conductive layer where the connecting electrode 234 is located The difference between the design value of 204 and the actual value.
  • the specific values of cdbias1 and cdbias2 depend on the process capability.
  • cdbias1 and cdbias2 are both between 0.1 ⁇ m and 0.9 ⁇ m.
  • FIG. 3 is a schematic diagram of a display substrate provided by other embodiments of the present disclosure.
  • the first electrode Ca of the storage capacitor and the first electrode T1s of the first transistor T1 overlap in a direction perpendicular to the base substrate 101.
  • the first power line 250 is located between the data line 12 and the via 301 in the first electrode Ca of the storage capacitor, and is electrically connected to the first electrode Ca of the storage capacitor through the via 303, so The first electrode Ca of the storage capacitor needs to extend fully toward the data line 12 to ensure good contact with the first power line 250.
  • the first electrode T1s of the first transistor T1 has a first electrode side 601 near the data line 12 along the first direction D1
  • the first electrode Ca of the storage capacitor has a capacitance near the data line 12 along the first direction D1.
  • the electrode side 602. For example, in the first direction D2, the first electrode side 601 is the side closest to the data line 12 of the first electrode T1s of the first transistor T1, and the capacitor electrode side 602 is the second side of the storage capacitor.
  • An electrode Ca is closest to the side of the data line 12.
  • the capacitor electrode side 602 is closer to the data line 12 than the first electrode side 601, that is, the capacitor electrode side 602 extends beyond the first electrode side 601.
  • the process is designed to ensure that in each sub-pixel, the side edge 602 of the capacitor electrode exceeds the side edge 601 of the first electrode.
  • the distance d2 between the orthographic projection of the capacitor electrode side 602 on the base substrate 101 and the orthographic projection of the first pole side 601 on the base substrate 101 satisfies: d2 ⁇ ⁇ ((cdbias3) ⁇ 2+ ⁇ (cdbias4) ⁇ 2), where cdbias3 is the difference between the design value and the actual value of the semiconductor layer 201 where the first pole T1s of the first transistor T1 is located, and cdbias4 is the value of the storage capacitor The difference between the design value and the actual value of the second conductive layer 202 where the first electrode Ca is located.
  • the specific values of Cdbias3 and cdbias4 depend on the process capability.
  • cdbias3 and cdbias4 are both between 0.1 ⁇ m and 0.9 ⁇ m. With this arrangement, it can be ensured that in the case of process fluctuations, the capacitor electrode side 602 of each sub-pixel exceeds the first electrode side 601, thereby improving uniformity.
  • the portion of the connection electrode 234 exposed by the via hole 308 has an inclined surface with respect to the base substrate 101.
  • this arrangement can increase the contact area between the first electrode 134 of the light-emitting element 120 and the connecting electrode 234 in the same space, thereby reducing the contact resistance and improving the yield; on the other hand, when the display substrate 20 is a flexible display
  • the inclined surface arrangement can relieve the stability of the connection at the via hole 308 by the bending stress, and improve the bending resistance of the substrate.
  • the inclination direction of the connecting electrode 234 of the sub-pixel is consistent with the bending direction of the substrate area where the sub-pixel is located, thereby alleviating the bending stress.
  • the inclination angle of the inclined surface relative to the base substrate is between 20 degrees and 50 degrees.
  • FIG. 4B shows an enlarged schematic diagram of the via hole 308 in FIG. 4A.
  • ⁇ 1 is greater than or equal to 55 degrees and less than or equal to 70 degrees
  • ⁇ 2 is greater than or equal to 60 degrees and less than or equal to 80 degrees
  • ⁇ 1 is less than ⁇ 2
  • the inclined surface 500 of the connecting electrode 234 is provided, so that the connecting electrode 234 and the first electrode 134 of the light emitting element 120 have a better contact effect and electrical connection effect.
  • this arrangement also helps to improve the etching rate and etching effect of etching the third conductive layer 203 and the fourth conductive layer 204 to form the connecting electrode 233 and the connecting electrode 234, respectively.
  • FIG. 5 is a schematic diagram of a display substrate provided by still other embodiments of the present disclosure.
  • the active layer T1a of the first transistor T1 includes a bent structure. With this arrangement, the width-to-length ratio W/L of the channel region of the first transistor T1 can be reduced.
  • the first transistor T1 is a driving transistor of the pixel circuit, a larger size is generally designed to obtain a sufficiently large driving current.
  • the inventor found that excessive driving current will cause gray scale loss, for example, the inability to display low gray scale data causes picture distortion. This problem can be solved by reducing the aspect ratio of the first transistor T1, and the display effect can be improved.
  • the active layer T1a of the first transistor T1 has an ⁇ -shape or a "ji" shape, or is similar to the ⁇ -shape or a "ji" shape, that is, it includes a protruding structure.
  • the active layer T1a includes a first portion 701, a second portion 702, and a connecting portion 703.
  • the second part 702 is located on both sides of the first part 701, and the first part 701 is a protruding part.
  • the connecting part 703 connects the first part 701 and the second part 702.
  • first part 701 and the second part 702 are both straight and not on the same horizontal line, and the second part 702 is arc-shaped.
  • the average radius of curvature of the second portion 702 is greater than 1 ⁇ m.
  • the average width W3 of the connecting portion 703 is larger than the average width W1 of the first part 701 and the average width W2 of the second part 702. This is because the arc-shaped connecting portion 703 is easier to break during the formation process than the linear structure. By making the connecting portion 703 wider, the process yield can be improved.
  • the via 301 in the first electrode Ca of the storage capacitor and the active layer T1a of the first transistor T1 do not overlap in a direction perpendicular to the base substrate.
  • the active layer T1a and the via 301 do not overlap in the direction perpendicular to the base substrate.
  • This design can avoid the part of the gate T1g of the first transistor T1 exposed by the via 301, that is, the part in contact with the connecting electrode 231 that is uneven due to the active layer T1a of the first transistor T1, and the connecting electrode is improved.
  • the contact yield of 231 and the gate T1g is improved.
  • the gate drive circuit 13 of the display substrate 20 usually includes a plurality of shift register units.
  • the shift register unit generates a shift pulse signal under the action of the control signal of the external circuit, and the shift pulse signal serves as the scanning of the current row of pixels.
  • the signal is used as the start signal of the next line (the first line is triggered by the frame start signal STV) and the end signal of the previous line for control.
  • the control signal of the external circuit mainly includes a frame start signal (STV), a pair of CLK and CLKB signals with opposite phases, a transistor turn-off signal (such as VGL), and possible DC voltage signals VGH and VGL.
  • the plurality of shift register units are connected in a one-to-one correspondence with multiple rows of sub-pixels in the display area, and are configured to output the first scan signal Ga1 and the second scan signal Ga2 to the corresponding row of sub-pixels through output nodes.
  • FIG. 6A shows a schematic circuit diagram of a gate driving circuit provided by at least one embodiment of the present disclosure, and the figure shows a shift register unit in the gate driving circuit.
  • the shift register unit includes an input circuit 501, an output circuit 502, a storage circuit 503, and a reset circuit 504.
  • the input circuit 501 is configured to transmit the high potential VGH to the pull-up node PU, that is, the control end of the output circuit 502 and one end of the storage circuit 503 in response to the trigger signal STV.
  • the output circuit 502 is configured to output the CLK signal under the control of the pull-up node PU.
  • the reset circuit 504 is configured to reset the output node OUT in response to the CLKB signal.
  • the input circuit 501 includes an eighth transistor T8, the output circuit 502 includes a ninth transistor T9, the reset circuit 504 includes a tenth transistor T10, and the storage circuit 503 includes a first capacitor C1, which is connected to the output node OUT , And includes a first electrode C1a and a second electrode C1b.
  • the working process of the shift register unit will be exemplarily described below by taking a P-type transistor as an example, but the embodiments of the present disclosure are not limited thereto.
  • a working process of the shift register unit includes: when the trigger signal STV comes, the CLK signal is at a high potential, the eighth transistor T8 is turned on, and the low potential VGL is transmitted to the gate (pull-up node PU) of the ninth transistor T9, At the same time, it is stored to the first electrode of the first capacitor C1, and the ninth transistor T9 is turned on under the action of the low potential VGL, and outputs the low potential CLK signal to turn on the transistors of the sub-pixels in this row, and at the same time, it serves as the next stage shift register unit
  • the potential of the CLK signal changes from low to high
  • the tenth transistor T10 is turned on under the action of the low-level CLKB signal, and the first capacitor C1 is discharged to output a high potential, turning off the transistors of the sub-pixels in this row. In this way, the progressive scanning of the sub-pixels in the display area is realized.
  • FIG. 6B shows a schematic structural diagram of the shift register unit shown in FIG. 6A
  • FIG. 6C is a cross-sectional view along the cross-sectional line B1-B2 of FIG. 6B
  • FIG. 6D is a cross-sectional view along the cross-sectional line E1-E2 of FIG. 6B.
  • the structures under the first conductive layer 201 are omitted in FIGS. 6B and 6C.
  • the display substrate 20 includes a first power signal line VGH, a second power signal line VGL, a trigger signal line STV, a first clock signal line CLK, and a second clock signal line CLKB located in the non-display area NDA.
  • each signal line extends along the first direction.
  • the first power signal line VGH is electrically connected to the first pole of the eighth transistor T8 to provide the first power signal VGH
  • the second power signal line VGL is electrically connected to the first pole of the tenth transistor T8 to provide the second power signal VGL
  • the first clock signal line CLK is electrically connected to the first electrode of the ninth transistor to provide the first clock signal CLK
  • the second clock signal line CLKB is electrically connected to the gate of the tenth transistor T10 to provide the second clock signal CLKB.
  • the trigger signal line STV is electrically connected to the gate of the eighth transistor T8 to provide the trigger signal STV.
  • the gate driving circuit 13 can be formed at the same time as the sub-pixels in the display area.
  • the gates of the eighth to tenth transistors T8-T10 may be located in the first conductive layer 201, the active layer, the first electrode, and the second electrode may be located in the semiconductor layer 102, and the signal lines of the non-display area NDA It may be located in the third conductive layer 203.
  • the second electrode of the eighth transistor T8 is electrically connected to the gate T9g of the ninth transistor T9 and the first electrode C1a of the first capacitor C1 through the connecting electrode 650, and the second electrode of the first capacitor C1
  • C1b is insulated from the connecting electrode 650 in the same layer.
  • the connecting electrode 650 and the second electrode C1b of the first capacitor C1 may be located in the third conductive layer 203.
  • each signal line is connected to the gate driving circuit 13 through the wiring pattern in the first conductive layer 201, and the gate driving circuit 13 is connected to the display through the wiring pattern in the third conductive layer 203.
  • Pixel circuit in area DA Pixel circuit in area DA.
  • the second portion 204b of the fourth conductive layer 204 in the non-display area includes an auxiliary capacitor electrode C1c, and the auxiliary capacitor electrode C1c can be connected in parallel with the first electrode C1a or the second electrode C1b of the first capacitor C1 to increase the first electrode C1a or the second electrode C1b.
  • the auxiliary capacitor electrode C1c is electrically connected to the connection electrode 650 through a via hole penetrating the third insulating layer, thereby being electrically connected to the first electrode C1a of the first capacitor C1, and is perpendicular to the base substrate 101. It overlaps with the second electrode C1b of the first capacitor C1 in the direction.
  • the first electrode C1a and the auxiliary capacitor electrode C1c respectively at least partially overlap the second electrode C1b to form a parallel capacitor structure, which increases the capacitance value of the first capacitor C1 and improves the bootstrap of the first capacitor C1 Ability to improve the stability of the output signal.
  • the second portion 204b of the fourth conductive layer 204 in the non-display area further includes auxiliary signal lines corresponding to the signal lines.
  • Each auxiliary signal line is connected in parallel with each signal line to reduce the resistance of the signal line. And the voltage drop on the signal line.
  • Each auxiliary signal line and its corresponding signal line overlap each other in a direction perpendicular to the base substrate 101, and are connected in parallel through via holes.
  • the auxiliary signal line of the trigger signal line STV will be exemplarily described below in conjunction with FIG. 6B and FIG. 6D.
  • the trigger signal line STV is electrically connected to the gate T8g of the eighth transistor T8 through a via.
  • the second portion 204b of the fourth conductive layer 204 in the non-display area further includes an auxiliary trigger signal line STV1, which is connected in parallel with the trigger signal line STV through a via hole penetrating the third insulating layer.
  • the second portion 204b of the fourth conductive layer 204 located in the non-display area further includes the binding electrode 80, that is, the binding electrode 80 is located in the fourth conductive layer 204.
  • Fig. 7A is an example of a cross-sectional view of Fig. 1A along the section line D1-D2.
  • the second portion 204b of the fourth conductive layer 204 located in the non-display area further includes a wiring 81 located in the non-display area.
  • One end of the wire 81 is connected to the binding electrode 80, for example, connected as an integral structure; the other end of the wire 81 extends to the display area.
  • the wiring 81 and the bonding electrode are located on the fourth insulating layer 106, and the fifth insulating layer 107 covers the wiring 81 and exposes the bonding electrode 80 to facilitate bonding with an external circuit.
  • FIG. 7A shows that covers the fourth insulating layer 106, and the fifth insulating layer 107 covers the wiring 81 and exposes the bonding electrode 80 to facilitate bonding with an external circuit.
  • a part of the wiring 81 is located in the bending area BA.
  • inorganic materials are brittle and easy to break under bending
  • the first insulating layer 103, the second insulating layer 104, and the third insulating layer 105 are, for example, inorganic insulating layers, such as silicon oxides such as silicon oxide, silicon nitride, and silicon oxynitride, silicon nitrides, or silicon nitrides. Oxides, or aluminum oxide, titanium nitride, etc. include metal oxynitride insulating materials.
  • the fourth insulating layer 106, the fifth insulating layer 107 and the pixel defining layer 108 are respectively organic insulating materials, such as polyimide (PI), acrylate, epoxy resin, polymethylmethacrylate (PMMA) And other organic insulating materials.
  • the fourth insulating layer 106 and the fifth insulating layer 107 are planarization layers.
  • the first insulating layer 103, the second insulating layer 104, and the third insulating layer 105 are all removed, and the fourth insulating layer 106 and the fifth insulating layer 107 remain
  • the portion of the fourth insulating layer 106 located in the bending area BA is filled between the wiring 81 and the base substrate 101, and is in direct contact with the base substrate 101, thereby The bending resistance of the wire 81 is improved, and the risk of wire breakage is reduced.
  • the fifth insulating layer 107 covers the wiring 81 to protect the wiring 81.
  • the fourth conductive layer is present in the display substrate provided by at least one embodiment of the present disclosure, the fourth insulating layer and the fifth insulating layer are both existing structures in the display substrate, and no additional process is required to form .
  • FIG. 7B is another example of the cross-sectional view of FIG. 1A along the section line D1-D2.
  • the difference between the embodiment shown in FIG. 7B and the embodiment shown in FIG. 7A is that the display substrate 20 shown in FIG. The side close to the base substrate 101 is connected in parallel with the bonding electrode 80 to reduce resistance.
  • the bonding electrode 80 and the auxiliary bonding electrode 82 are directly contacted and electrically connected (lapped), that is, the fourth insulating layer between the auxiliary bonding electrode 82 and the bonding electrode 80 106 removed.
  • the binding electrode 80 covers at least one side of the auxiliary binding electrode 82, so that the contact resistance can be reduced.
  • the auxiliary bonding electrode 82 may be provided in the same layer as any conductive layer located below the fourth conductive layer in the display area DA.
  • the auxiliary bonding electrode 82 is located in the third conductive layer 203, that is, is provided in the same layer as the first power line 250.
  • the base substrate 101 may be a rigid substrate, such as a glass substrate, a silicon substrate, etc., or may be formed of a flexible material with excellent heat resistance and durability, such as polyimide (PI ), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyarylate, polyetherimide, polyethersulfone, polyethylene glycol Phthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethylmethacrylate (PMMA), cellulose triacetate (TAC), cycloolefin polymer ( COP) and cyclic olefin copolymer (COC), etc.
  • PI polyimide
  • PC polycarbonate
  • PET polyethylene terephthalate
  • PET polyethylene
  • polyacrylate polyarylate
  • polyetherimide polyethersulfone
  • PET polyethylene glycol Phthalate
  • PE polyethylene
  • PP polypropylene
  • PSF polysulfone
  • the material of the semiconductor layer 102 includes, but is not limited to, silicon-based materials (a-Si, polysilicon, p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.), and organic materials (hexathiophene , Polythiophene, etc.).
  • the material of the first to fourth conductive layers may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W) and the above Alloy materials composed of metals; or conductive metal oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc aluminum oxide (AZO), etc.
  • the light-emitting element 120 has a top-emitting structure
  • the first electrode 134 has reflectivity
  • the second electrode 135 has transmissive or semi-transmissive properties.
  • the first electrode 134 is a high work function material to act as an anode, such as an ITO/Ag/ITO laminate structure
  • the second electrode 135 is a low work function material to act as a cathode, such as a semi-transmissive metal or metal alloy
  • the material is, for example, an Ag/Mg alloy material.
  • At least one embodiment of the present disclosure also provides a display panel including any of the above display substrates 20.
  • the above-mentioned display substrate 20 provided by at least one embodiment of the present disclosure may or may not include the light-emitting element 120, that is, the light-emitting element 120 may be formed in a panel factory after the display substrate 20 is completed.
  • the display panel provided by at least one embodiment of the present disclosure further includes the light-emitting element 120 in addition to the display substrate 20.
  • the display panel is an OLED display panel, and accordingly the display substrate 20 included therein is an OLED display substrate.
  • the display panel 30 further includes an encapsulation layer 801 and a cover plate 802 disposed on the display substrate 20.
  • the encapsulation layer 801 is configured to seal the light-emitting elements on the display substrate 20 to prevent external moisture. The penetration of gas and oxygen into the light-emitting element and the driving sub-circuit causes damage to the device.
  • the encapsulation layer 801 includes an organic thin film or a structure in which an organic thin film and an inorganic thin film are alternately stacked.
  • a water absorption layer (not shown) may be further provided between the encapsulation layer 801 and the display substrate 20, configured to absorb residual water vapor or sol in the preliminary manufacturing process of the light-emitting element.
  • the cover plate 802 is, for example, a glass cover plate.
  • the cover plate 802 and the encapsulation layer 801 may be an integral structure.
  • At least one embodiment of the present disclosure further provides a display device 40.
  • the display device 40 includes any of the above-mentioned display substrate 20 or display panel 30.
  • the display device in this embodiment may be: a display, an OLED Panels, OLED TVs, electronic paper, mobile phones, tablet computers, notebook computers, digital photo frames, navigators and other products or components with display functions.
  • At least one embodiment of the present disclosure also provides a method for manufacturing the above-mentioned display substrate 20.
  • the structure and manufacturing method of the display substrate provided by at least one embodiment of the present disclosure will be exemplified below in conjunction with FIGS. 2A-2C, FIGS. 6B-6D, and FIGS. 7A-7B.
  • at least one embodiment of the present disclosure is not limited thereto. .
  • the manufacturing method includes the following steps S61-S70.
  • Step S61 A semiconductor material layer is formed on the base substrate, and a patterning process is performed on the semiconductor material layer to form a semiconductor layer 102.
  • the semiconductor layer 102 includes the active elements of the first to seventh transistors T1-T7 in each pixel area.
  • the layers T1a-T7a and the doped region patterns that is, the source regions and drain regions corresponding to the first to seventh transistors T1-T7) (as shown in FIG. 2B), and the active of each transistor in the same pixel region
  • the layer pattern and the doped region pattern are integrally arranged.
  • the semiconductor layer 102 also includes the active layer and doped region patterns of the eighth to tenth transistors T8-T10 in the non-display area NDA (that is, corresponding to the source and drain regions of the eighth to tenth transistors T8-T10). area).
  • the active layer may include an integrally formed low-temperature polysilicon layer, in which the source region and the drain region may be conductive through doping or the like to achieve electrical connection of each structure. That is, the active semiconductor layer of each transistor of each sub-pixel is an overall pattern formed of p-silicon, and each transistor in the same pixel region includes a doped region pattern (ie, a source region and a drain region) and an active layer Pattern, the active layers of different transistors are separated by doped structures.
  • Step S62 forming a first insulating layer 103 (for example, a transparent layer), such as a first gate insulating layer, on the semiconductor layer 102; and forming a plurality of first insulating layer via holes on the first insulating layer for connecting with The pattern connection of the third conductive layer 203 formed subsequently.
  • a first insulating layer 103 for example, a transparent layer
  • first gate insulating layer such as a first gate insulating layer
  • the drain region overlaps for the connection between the source region and the drain region and the data line 12 and the first power line 250 in the third conductive layer, such as the via 402 penetrating the first insulating layer. 405, via 303, via 305 and so on.
  • Step S63 A first conductive material layer is formed on the first insulating layer 103, and a patterning process is performed on the first conductive material layer to form a first conductive layer 201.
  • the conductive layer 201 includes, for example, insulating layers located in the display area DA. And the scan line 210, the reset control line 220, and the light emission control line 230 extending in the second direction. For example, for a row of pixel circuits, the correspondingly connected reset control lines 220, scan lines 210, and light emission control lines 230 are sequentially arranged in the first direction D1.
  • the first conductive layer 201 further includes the gates and wirings of the eighth to tenth transistors T8-T10 in the non-display area NDA.
  • the first conductive layer 201 further includes the gates T1g-T7g of the first to seventh transistors T1-T7.
  • the gate T6g of the sixth transistor T6 and the reset control line 220 are integrated, that is, a part of the reset control line 220 serves as the gate T6g of the sixth transistor T6;
  • the gate T2g of the second transistor T2 and the scan line 210 are The integrated structure, that is, the part of the scan line 210 serves as the gate T2g of the second transistor T2;
  • the gate T4g of the fourth transistor T4 and the gate T5g of the fifth transistor T5 are both integrated with the light emission control line 230, that is, the light emission
  • a part of the control line 230 serves as the gate T4g of the fourth transistor T4 and the gate T5g of the fifth transistor T5;
  • the gate T7g of the seventh transistor T7 is integrated with the reset control line 220 corresponding to the pixel circuit of the next row.
  • the sixth transistor T6 and the third transistor T3 both have a double-gate structure
  • the two gates T6g of the sixth transistor T6 are both part of the reset control line 220
  • one gate of the third transistor T3 is a part of the scan line 210.
  • the other gate of the third transistor T3 is a part that is integrally connected to the scan line 210 and protrudes toward the sixth transistor T6.
  • the overlapping portion of the semiconductor layer 102 and the first conductive layer 201 in a direction perpendicular to the base substrate defines the active layers (channel regions) T1a-T7a of the first to seventh transistors T1-T7.
  • Step S64 As shown in FIG. 2B, a self-aligned process is used to conduct a conductive treatment (for example, doping treatment) on the semiconductor layer 102 using the first conductive layer 201 as a mask, so that the semiconductor layer 102 is not exposed to the semiconductor layer 102.
  • the portion covered by the first conductive layer 201 is conductive, so that the portions of the semiconductor layer 102 located on both sides of the active layer of each transistor are conductive to form the source regions and drains of the first to tenth transistors T1-T10, respectively.
  • the pole regions that is, the first pole (T1s-T10s) and the second pole (T1d-T10d) of the first to tenth transistors T1-T10.
  • Step S65 forming a second insulating layer 104 (for example, a transparent layer) on the first conductive layer 201, for example, a second gate insulating layer; and forming at least a via hole corresponding to the first insulating layer on the second insulating layer
  • the second insulating layer via For example, the via holes corresponding to at least the first insulating layer and the second insulating layer include at least via 402, via 405, via 303, via 305, and so on.
  • the via hole in the first insulating layer and the via hole in the second insulating layer can also be formed in one process, which is not limited in the embodiments of the present disclosure.
  • Step S66 forming a second conductive material layer on the second insulating layer 104 and on the second insulating layer, and performing a patterning process on the second conductive material layer to form a second conductive layer 202 as shown in FIG. 2A, that is, The first electrodes Ca of storage capacitors that are insulated from each other and the reset voltage line 240 extending in the first direction are formed.
  • the first electrode Ca of the storage capacitor and the gate T1g of the first transistor T1 at least partially overlap in a direction perpendicular to the base substrate 101.
  • the patterning process also forms a via 301 in the first electrode Ca of the storage capacitor, and the via 301 exposes at least part of the gate T1g of the first transistor T1.
  • Step S67 forming a third insulating layer 105 on the second conductive layer 202.
  • the third insulating layer may be, for example, an interlayer insulating layer.
  • a via hole is formed in the third insulating layer for connection with the third conductive layer formed later. At least part of the vias correspond to the positions of the first insulating layer vias and the second insulating layer vias, and pass through the first insulating layer, the second insulating layer and the third insulating layer at the same time, such as vias 402, vias 405, and vias 303. Via 305.
  • Step S68 forming a third conductive material layer on the third insulating layer 105, and performing a patterning process on the third conductive material layer to form a third conductive layer 203.
  • the third conductive layer 203 includes, for example, the data line 12, the first power line 250, the connection electrode 231, the connection electrode 232, and the connection electrode 233 that are insulated from each other.
  • the data line 12 and the first power line 250 extend along the first direction D1. As shown in FIGS.
  • the third conductive layer 203 may also include a connection electrode 650 located in the non-display area NDA, a second electrode C1b of the storage capacitor of the first capacitor C1, and various signal lines (STV, CLK, CLKB, VGL, VGH).
  • the data line 12 overlaps with the first electrode T2s of the second transistor T2 in a direction perpendicular to the base substrate 101 and is electrically connected to the first electrode T2s of the second transistor T2 through the via 305.
  • the via 305 penetrates the first insulating layer 103, the second insulating layer 104, and the third insulating layer 105, for example.
  • the first power line 250 is electrically connected to the first electrode Ca of the storage capacitor in the corresponding column of sub-pixels through the via 302, and is electrically connected to the first electrode Ca of the fourth transistor T4 through the via 303.
  • the via hole 302 penetrates the third insulating layer 105
  • the via hole 303 penetrates the first insulating layer 103, the second insulating layer 104 and the third insulating layer 105.
  • one end of the connecting electrode 231 passes through the via 301 in the first electrode Ca of the storage capacitor and the via 401 in the insulating layer and the gate T1g of the first transistor T1, that is, the storage capacitor
  • the second electrode Cb is electrically connected, and the other end is electrically connected to the first electrode of the third transistor T3 through the via 402, thereby electrically connecting the second electrode Cb of the storage capacitor to the first electrode T3s of the third transistor T3.
  • the via hole 401 penetrates the second insulating layer 104 and the third insulating layer 105
  • the via hole 402 penetrates the first insulating layer 103, the second insulating layer 104 and the third insulating layer 105.
  • one end of the connecting electrode 232 is electrically connected to the reset voltage line 240 through the via 403, and the other end is electrically connected to the sixth transistor T6 through the via 404, so that the first electrode of the sixth transistor T6 T6s may receive the first reset voltage Vinit1 from the reset voltage line 240.
  • the via hole 403 penetrates the third insulating layer 105
  • the via hole 404 penetrates the first insulating layer 103, the second insulating layer 104 and the third insulating layer 105.
  • the connecting electrode 233 is electrically connected to the second electrode T5d of the fifth transistor T5 through a via 405, and is used to connect the second electrode T5d of the fifth transistor T5 to the first electrode 134 of the light-emitting element.
  • the via 405 penetrates the first insulating layer 103, the second insulating layer 104, and the third insulating layer 105.
  • Step S69 forming a fourth insulating layer 106 on the third conductive layer 203. And forming a via hole in the third insulating layer for connecting with the fourth conductive layer to be formed later.
  • the fourth insulating layer 106 includes a first planar layer.
  • the fourth insulating layer 106 includes two layers of a passivation layer and a first flat layer, and the via hole formed in the fourth insulating layer needs to penetrate through the two layers of the passivation layer and the first flat layer.
  • the first flat layer is located on the side of the passivation layer away from the third conductive layer.
  • the first flat layer is an organic insulating material
  • the passivation layer is an inorganic insulating material.
  • Step S70 A fourth conductive material layer is formed on the fourth insulating layer 106, and a patterning process is performed on the fourth conductive material layer to form a fourth conductive layer 204.
  • the fourth conductive layer 204 includes a first portion 204a located in the display area DA And the second part 204b located in the non-display area NDA.
  • the first portion 204a includes a connecting electrode 234.
  • the second portion 204b includes auxiliary signal lines corresponding to each signal line, bonding electrodes 80, wiring 81, and the like.
  • the first portion 204a and the first power line 250 do not overlap in a direction perpendicular to the base substrate 101.
  • connection electrode 234 and the connection electrode 233 overlap in a direction perpendicular to the base substrate 101, and the connection electrode 234 is electrically connected to the connection electrode 233 through a via 307 penetrating the fourth insulating layer 106 .
  • the manufacturing method of the display substrate may further include forming a fifth insulating layer 107 on the fourth conductive layer 204, and forming a via hole in the fifth insulating layer 107 for connecting with the fifth conductive layer formed subsequently .
  • the fifth insulating layer 107 may be a second flat layer. 2C, the fifth insulating layer via hole is used to connect the first electrode 134 and the connecting electrode 234 of the light emitting element 120, for example, the fifth insulating layer via hole may overlap with the second electrode of the fifth transistor T5, or not overlap.
  • the manufacturing method of the display substrate may further include forming a fifth conductive material layer on the fifth insulating layer 107, and performing a patterning process on the fifth conductive material layer to form the fifth conductive layer 205, that is, forming a plurality of insulating layers.
  • the first electrode 134 is used to form a light-emitting element.
  • the manufacturing method of the display substrate may further include sequentially forming a pixel defining layer 108 on the fifth conductive layer 205, and corresponding to the main body of each first electrode 134 in the pixel defining layer 108
  • the portion 141 forms an opening area 600, and then at least a light emitting layer 136 is formed in the opening area 600, and a second electrode 135 is formed on the light emitting layer.
  • the material of the semiconductor material layer includes, but is not limited to, silicon-based materials (a-Si, polysilicon, p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.), and organic materials (hexathiophene , Polythiophene, etc.).
  • silicon-based materials a-Si, polysilicon, p-Si, etc.
  • metal oxide semiconductors IGZO, ZnO, AZO, IZTO, etc.
  • organic materials hexathiophene , Polythiophene, etc.
  • the materials of the first conductive material layer, the second conductive material layer, the third conductive material layer, the fourth conductive material layer, the fifth conductive material layer, and the second electrode may include gold (Au), silver (Ag), Copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and alloy materials combined with the above metals; or transparent metal oxide conductive materials, such as indium tin oxide (ITO), Indium zinc oxide (IZO), zinc oxide (ZnO), zinc aluminum oxide (AZO), etc.
  • ITO indium tin oxide
  • IZO Indium zinc oxide
  • ZnO zinc oxide
  • AZO zinc aluminum oxide
  • the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, and the fifth insulating layer 107 are, for example, inorganic insulating layers, such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the oxide, silicon nitride or silicon oxynitride, or aluminum oxide, titanium nitride, etc. include metal oxynitride insulating materials.
  • some of these insulating layers may also be organic materials, such as the first flat layer and the second flat layer, such as polyimide (PI), acrylate, epoxy, polymethylmethacrylate (PMMA), etc.
  • PI polyimide
  • PMMA polymethylmethacrylate
  • the fourth insulating layer 106 and the fifth insulating layer 107 may include flat layers, respectively.
  • the above-mentioned patterning process may use a conventional photolithography process, for example, including the steps of photoresist coating, exposure, development, drying, and etching.

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Abstract

一种显示基板(20)以及显示装置(40)。显示基板(20)包括衬底基板(101)、位于衬底基板(101)上的多个子像素(100)、第一电源线(250)以及电连接层(204)，每个子像素(100)包括像素电路(900)，多个像素电路(900)沿第一方向(D1)和第二方向(D2)分布为多行多列。像素电路(900)通过电连接层(240)与发光元件(120)电连接，电连接层(204)位于显示基板(20)的显示区(DA)的部分(204a)与第一电源线(250)在垂直于衬底基板(101)的方向上不重叠。显示基板(20)有助于提高显示效果。

Description

显示基板及显示装置
本申请要求于2020年3月30日递交的中国专利申请第202010234010.7号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开实施例涉及一种显示基板及显示装置。
背景技术
在OLED(Organic Light-Emitting Diode，有机发光二极管)显示领域，随着高分辨率产品的快速发展，对显示基板的结构设计，例如像素和信号线的排布等都提出了更高的要求。
发明内容
本公开至少一实施例提供一种显示基板，包括衬底基板、多个子像素、第一电源线和电连接层，所述衬底基板包括显示区和非显示区；所述多个子像素位于所述衬底基板的显示区，所述多个子像素每个包括像素电路，所述像素电路用于驱动发光元件发光；所述多个子像素的多个像素电路沿第一方向和第二方向分布为多行多列，所述像素电路包括驱动子电路、数据写入子电路、补偿子电路和存储子电路；所述驱动子电路包括控制端、第一端和第二端，且配置为与所述发光元件连接并且控制流经发光元件的驱动电流；所述数据写入子电路包括控制端、第一端和第二端，所述数据写入子电路的控制端配置为接收第一扫描信号，所述数据写入子电路的第一端配置为接收数据信号，所述数据写入子电路的第二端与所述驱动子电路电连接，所述数据写入子电路配置为响应于所述第一扫描信号将所述数据信号写入所述驱动子电路的第一端；所述补偿子电路包括控制端、第一端和第二端，所述补偿子电路的控制端配置为接收第二扫描信号，所述补偿子电路的第一端和第二端分别与所述驱动子电路的控制端和第二端电连接，所述补偿子电路配置为响应所述第二扫描信号对所述驱动子电路进行阈值补偿；所述存储子电路与所述驱动子电路的控制端和第一电压端电连接，且被配置为存储所述数据信号；所述存储子电路包括存储电容，所述存储电容包括第一电极和第二电极，所述存储电容的的第一电极和所述第一电压端电连接，存储电容的第二电极和所述驱动子电路的控制端电连接。所述第一电源线位于所述显示区，沿所述第一方向延伸，与所述第一电压端连接，并配置为为所述多个子像素提供第一电源电压。所述电连接层位于所述像素电路远离所述衬底基板的一侧，所述电连接层包括位于显示区的第一部分，所述第一部分包括多个第一连接电极，所述多个第一连接电极分别与所述多个子像素一一对应设置，每个子像素的像素电路通过第一过孔与所对应的第一连接电极电连接，每个子像素所对应的第一 连接电极配置为通过第二过孔与所述发光元件电连接，从而将所述子像素的像素电路与发光元件电连接；所述第一过孔与所述第二过孔在垂直于所述衬底基板的方向上不重叠；所述电连接层的第一部分与所述第一电源线在垂直于所述衬底基板的方向上不重叠。
在一些示例中，所述第一过孔和第二过孔沿所述第一方向排列。
在一些示例中，所述显示基板还包括位于所述非显示区的电源信号线和栅极驱动电路，所述栅极驱动电路配置为为所述子像素提供所述第一扫描信号和所述第二扫描信号，所述电源信号线配置为为所述子像素的栅极驱动电路提供电源信号；所述电连接层还包括位于所述非显示区的第二部分，所述第二部分包括辅助信号线，所述辅助信号线与所述电源信号线并联。
在一些示例中，所述栅极驱动电路包括多个移位寄存器单元，所述多个移位寄存器单元与所述多行子像素一一对应连接，并配置为通过输出节点向所对应的一行子像素输出所述第一扫描信号和所述第二扫描信号，每个移位寄存器单元包括与所述输出节点连接的第一电容，所述第一电容包括第一电极和第二电极，所述电连接层的第二部分还包括辅助电容电极，所述辅助电容电极与所述第一电容的第一电极或第二电极并联。
在一些示例中，所述子像素还包括第一发光控制子电路，第一发光控制子电路包括控制端、第一端和第二端，第一端与驱动子电路电连接，第二端配置为通过第三过孔与第一连接电极电连接，控制端配置为接收第一发光控制信号，所述第一发光控制子电路配置为响应于第一发光控制信号使得驱动电流可被施加至发光元件；所述第一过孔、所述第二过孔和所述第三过孔在垂直于所述衬底基板的方向上均不重叠。
在一些示例中，所述显示基板还包括第一发光控制线，所述第一发光控制线沿所述第二方向延伸，且与所述第一发光控制子电路的控制端连接以提供所述第一发光控制信号，所述第一过孔在所述衬底基板上的正投影和所述第二过孔在所述衬底基板上的正投影分别位于所述第一发光控制线在所述衬底基板上的正投影的两侧。
在一些示例中，对于至少一个子像素，所述第一连接电极被所述第二过孔暴露的部分具有相对于衬底基板的倾斜面。
在一些示例中，每个子像素还包括第二连接电极，所述第二连接电极位于所述存储电容的第一电极远离所述衬底基板的一侧，所述第二连接电极分别与所述存储电容的第二电极和所述补偿子电路的第二端连接。
在一些示例中，所述第二连接电极与所述第一连接电极在垂直于衬底基板的方向上重叠。
在一些示例中，所述驱动子电路包括第一晶体管，所述第一晶体管的栅极、第一极 和第二极分别作为所述驱动子电路的控制端、第一端和第二端。
在一些示例中，所述存储电容的第一电极包括第四过孔，所述第二连接电极通过所述第四过孔与所述存储电容的第二电极电连接。
在一些示例中，所述第四过孔与所述第一晶体管的有源层在垂直于所述衬底基板的方向上不重叠。
在一些示例中，所述第一晶体管的有源层包括弯折结构。
在一些示例中，所述第一晶体管的有源层类似于“Ω”形或“几”字形，包括第一部分、第二部分和连接部，所述有源层的第一部分和第二部分均为直线型，且不在同一水平线，所述有源层的连接部连接所述第一部分与第二部分，且为弧状。
在一些示例中，所述有源层的连接部的平均宽度大于所述第一部分或所述第二部分的平均宽度。
在一些示例中，所述显示基板还包括数据线，所述数据线沿所述第一方向延伸，并与所述数据写入子电路的第一端连接以提供所述数据信号；所述存储电容的第一电极与所述第一晶体管的第一极在垂直于衬底基板的方向重叠，所述第一晶体管的第一极具有靠近所述数据线的沿所述第一方向的第一极侧边，所述存储电容的第一电极具有靠近所述数据线的沿所述第一方向的电容电极侧边，在所述第二方向上，所述电容电极侧边较所述第一极侧边更靠近所述数据线。
在一些示例中，所述非显示区包括绑定区，所述电连接层还包括位于所述非显示区的第二部分，所述第二部分包括位于所述非显示区的绑定电极，所述显示基板还包括辅助绑定电极，所述辅助绑定电极与所述第一电源线同层设置且材料相同，并与所述绑定电极搭接。
在一些示例中，所述电连接层的第二部分还包括位于所述非显示区的走线，所述走线的一端与所述绑定电极连接，另一端延伸至所述显示区；所述非显示区还包括弯折区，所述走线的一部分位于所述弯折区。
在一些示例中，所述显示基板还包括有机绝缘层，所述有机绝缘层位于所述电连接层与所述像素电路之间，所述第一过孔位于所述有机绝缘层中，所述有机绝缘层包括位于弯折区的弯折部，所述弯折部位于所述走线靠近所述衬底基板的一侧。
在一些示例中，所述电连接层位于所述显示区的全部图案与所述第一电源线在垂直于所述衬底基板的方向上均不重叠。
本公开实施例还提供一种显示装置，包括上述显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，并非对本公开的限制。
图1A为本公开至少一实施例提供的显示基板的示意图之一；
图1B为本公开至少一实施例提供的显示基板中的像素电路图之一；
图1C为本公开至少一实施例提供的显示基板中的像素电路图之二；
图2A为本公开至少一实施例提供的显示基板的示意图之二；
图2B为本公开至少一实施例提供的显示基板的示意图之三；
图2C为图2A沿剖面线A1-A2的剖视图的一个示例；
图3为本公开至少一实施例提供的显示基板的示意图之四；
图4A为图2A沿剖面线A1-A2的剖视图的另一个示例；
图4B为图2A沿剖面线A1-A2的剖视图的又一示例；
图5为本公开至少一实施例提供的显示基板的示意图之五；
图6A为本公开至少一实施例提供的栅极驱动电路的示意图；
图6B为本公开至少一实施例提供的显示基板的示意图之六；
图6C为图6B沿剖面线B1-B2的剖视图；
图6D为图6B沿剖面线E1-E2的剖视图；
图7A为图1A沿剖面线D1-D2的剖视图的一个示例；
图7B为图1A沿剖面线D1-D2的剖视图的另一个示例；
图8为本公开至少一实施例提供的显示面板的示意图；以及
图9为本公开至少一实施例提供的显示装置的示意图。
具体实施方式
下面将结合附图，对本公开实施例中的技术方案进行清楚、完整地描述参考在附图中示出并在以下描述中详述的非限制性示例实施例，更加全面地说明本公开的示例实施例和它们的多种特征及有利细节。应注意的是，图中示出的特征不是必须按照比例绘制。本公开省略了已知材料、组件和工艺技术的描述，从而不使本公开的示例实施例模糊。所给出的示例仅旨在有利于理解本公开示例实施例的实施，以及进一步使本领域技术人员能够实施示例实施例。因而，这些示例不应被理解为对本公开的实施例的范围的限制。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在OLED(Organic Light-Emitting Diode，有机发光二极管)显示领域，随着高分辨率产品的快速发展，对显示基板的结构设计，例如像素和信号线的排布等都提出了更高的要求。例如，相对于分辨率为4K的OLED显示装置，大尺寸、分辨率为8K的OLED显示装置由于需要设置的子像素单元的个数成倍增加，像素密度相应地成倍增大，一方面信号线的线宽也相应变小，导致信号线的自身电阻变大；另一方面信号线之间的交叠情形变多，导致信号线的寄生电容变大，这些导致信号线的阻容负载变大。相应地，阻容负载引起的信号延迟(RC delay)以及电压降(IR drop)、电压升(IR rise)等现象也会变得严重。这些现象会严重影响显示产品的显示品质。例如，当版图设计更为紧凑，会影响像素电极的平整度，从而影响发光的均一性，降低了显示效果。
图1A是本公开至少一实施例提供的显示基板的示意图。如图1A所示，该显示基板20包括显示区DA和显示区DA外的非显示区NDA，显示区DA中设置有阵列分布的多个子像素100、多条栅线11和多条数据线12。每个子像素100包括发光元件和驱动该发光元件的像素电路。多条栅线11和多条数据线12彼此交叉在显示区中定义出阵列分布的多个像素区，每个像素区中设置一个子像素100的像素电路。该像素电路例如为常规的像素电路，例如为2T1C(即两个晶体管和一个电容)像素电路、4T2C、5T1C、7T1C等nTmC(n、m为正整数且n大于等于2)像素电路，并且在不同的实施例中，该像素电路还可以进一步包括补偿子电路，该补偿子电路包括内部补偿子电路或外部补偿子电路，补偿子电路可以包括晶体管、电容等。例如，根据需要，该像素电路还可以进一步包括复位电路、发光控制子电路、检测电路等。例如，该显示基板还可以包括位于非显示区NDA中的栅极驱动电路13和数据驱动电路(未示出)。该栅极驱动电路13通过栅线11与像素电路连接以提供各种扫描信号(如下文的第一扫描信号和第二扫描信号)，该数据驱动子电路通过数据线12与像素电路连接以提供数据信号。如图1A所示，该显示基板20包括两个栅极驱动电路13，两个栅极驱动电路13分别位于显示区DA的两侧，并分别与奇数行和偶数行的栅线连接，这种设置可以提高栅极驱动电路的响应速度。图1A中示出的栅极驱动电路13、栅线11和数据线12在显示基板中的位置关系只是示例，实际的排布位置可以根据需要进行设计。
例如，如图1A所示，该显示基板20的非显示区NDA还包括绑定区BP，该绑定区BP中设置有绑定电极(bonding pad)80，该绑定电极用于与外部元件(例如驱动芯片)进行绑定(Bonding)，以为显示区的像素阵列结构提供各种信号，例如电源电压信号、时序信号等。例如，在显示基板20制备完成时，该绑定电极80为裸露状态。图1A仅中示意性地示出了与栅极驱动电路13及数据线12连接的绑定电极80，然而本公开的各实施例并不限于此。显示区DA中的像素阵列结构通过走线81与绑定电极80相连以实现像素阵列结构和绑定电极之间信号的传输。
例如，显示基板20为柔性基板，该显示基板20的非显示区NDA还可以包括弯折区BA。如图1A所示，该弯折区BA位于显示区DA与绑定区BP之间，通过将弯折区BA进行弯折可以将绑定区BP弯折至显示基板20的背面从而实现窄边框显示。例如，弯折区BA位于显示区DA与绑定区BP之间。
例如，显示基板20还可以包括控制电路(未示出)。例如，该控制电路配置为控制数据驱动电路施加该数据信号，以及控制栅极驱动电路施加该扫描信号。该控制电路的一个示例为时序控制电路(T-con)。控制电路可以为各种形式，例如包括处理器和存储器，存储器包括可执行代码，处理器运行该可执行代码以执行上述检测方法。
例如，处理器可以是中央处理单元(CPU)或者具有数据处理能力和/或指令执行能力的其它形式的处理装置，例如可以包括微处理器、可编程逻辑控制器(PLC)等。
例如，存储装置可以包括一个或多个计算机程序产品，所述计算机程序产品可以包括各种形式的计算机可读存储介质，例如易失性存储器和/或非易失性存储器。易失性存储器例如可以包括随机存取存储器(RAM)和/或高速缓冲存储器(cache)等。非易失性存储器例如可以包括只读存储器(ROM)、硬盘、闪存等。在计算机可读存储介质上可以存储一个或多个计算机程序指令，处理器可以运行该程序指令期望的功能。在计算机可读存储介质中还可以存储各种应用程序和各种数据。
该像素电路可以包括驱动子电路、数据写入子电路、补偿子电路和存储子电路，根据需要还可以包括发光控制子电路、复位电路等。
图1B示出了一种像素电路的示意图。如图1B所示，该像素电路900包括驱动子电路122、数据写入子电路126、补偿子电路128、存储子电路127、第一发光控制子电路123、第二发光控制子电路124及复位电路129。
例如，驱动子电路122包括控制端131、第一端132和第二端133，其配置为控制流经发光元件120的驱动电流，且驱动子电路122的控制端131和第一节点N1连接，驱动子电路122的第一端132和第二节点N2连接，驱动子电路122的第二端133和第三节点N3连接。
例如，数据写入子电路126包括控制端、第一端和第二端，其控制端配置为接收第一扫描信号，第一端配置为接收数据信号，第二端与驱动子电路122的第一端132(第二节点N2)连接，且配置为响应于该第一扫描信号Ga1将该数据信号写入驱动子电路122的第一端132。例如，数据写入子电路126的第一端与数据线12连接以接收该数据信号，控制端与栅线11连接以接收该第一扫描信号Ga1。
例如，在数据写入阶段，数据写入子电路126可以响应于第一扫描信号Ga1而开启，从而可以将数据信号写入驱动子电路122的第一端132(第二节点N2)，并将数据信号存储在存储子电路127中，以在例如发光阶段时可以根据该数据信号生成驱动发光元件120发光的驱动电流。
例如，补偿子电路128包括控制端、第一端和第二端，其控制端配置为接收第二扫描信号Ga2，其第一端和第二端分别与驱动子电路122的控制端131和第二端133电连接，该补偿子电路配置为响应于该第二扫描信号对该驱动子电路120进行阈值补偿。
例如，存储子电路127与驱动子电路122的控制端131及第一电压端VDD电连接，配置为存储数据写入子电路126写入的数据信号。例如，在数据写入和补偿阶段，补偿子电路128可以响应于该第二扫描信号Ga2而开启，从而可以将数据写入子电路126写入的数据信号存储在该存储子电路127中。例如，同时在数据写入和补偿阶段，补偿子电路128可以将驱动子电路122的控制端131和第二端133电连接，从而可以使驱动子电路122的阈值电压的相关信息也相应地存储在该存储子电路中，从而例如在发光阶段可以利用存储的数据信号以及阈值电压对驱动子电路122进行控制，使得驱动子电路122的输出得到补偿。
例如，第一发光控制子电路123与驱动子电路122的第一端132(第二节点N2)以及第一电压端VDD连接，且配置为响应于第一发光控制信号将第一电压端VDD的第一电源电压施加至驱动子电路122的第一端132。例如，如图1B所示，第一发光控制子电路123和第一发光控制端EM1、第一电压端VDD以及第二节点N2连接。
例如，第二发光控制子电路124和第二发光控制端EM2、发光元件120的第一端134以及驱动子电路122的第二端133连接，且配置为响应于第二发光控制信号使得驱动电流可被施加至发光元件122。
例如，在发光阶段，第二发光控制子电路124响应于第二发光控制端EM2提供的第二发光控制信号而开启，从而驱动子电路122可以通过第二发光控制子电路124与发光元件120电连接，从而驱动发光元件120在驱动电流控制下发光；而在非发光阶段，第二发光控制子电路124响应于第二发光控制信号而截止，从而避免有电流流过发光元件120而使其发光，可以提高相应的显示装置的对比度。
又例如，在初始化阶段，第二发光控制子电路124也可以响应于第二发光控制信号而开启，从而可以结合复位电路以对驱动子电路122以及发光元件120进行复位操作。
例如，第二发光控制信号EM2可以与第一发光控制信号EM1相同或不同，例如二者可以连接到相同或不同的信号输出端。
例如，复位电路129与复位电压端Vinit以及发光元件120的第一端134(第四节点N4)连接，且配置为响应于复位信号将复位电压施加至发光元件120的第一端134。在另一些示例中，如图1B所示，该复位信号还可以施加至驱动子电路的控制端131，也即第一节点N1。例如，复位信号为该第二扫描信号，复位信号还可以是和第二扫描信号同步的其他信号，本公开的实施例对此不作限制。例如，如图1B所示，该复位电路129分别和发光元件120的第一端134、复位电压端Vinit以及复位控制端Rst(复位控制线)连接。例如，在初始化阶段，复位电路129可以响应于复位信号而开启，从而可以将复位电压施加至发光元件120的第一端134及第一节点N1，从而可以对驱动子电路122、补偿子电路128以及发光元件120进行复位操作，消除之前的发光阶段的影响。
例如，发光元件120包括第一端134和第二端135，发光元件120的第一端134配置为与驱动子电路122的第二端133耦接，发光元件120的第二端135配置为与第二电压端VSS连接。例如，在一个示例中，如图1B所示，发光元件120的第一端134可以通过第二发光控制子电路124连接至第三节点N3。本公开的实施例包括但不限于此情形。例如，发光元件120可以为各种类型的OLED，例如顶发射、底发射、双侧发射等，可以发红光、绿光、蓝光或白光等，该OLED的第一电极和第二电极分别作为该发光元件的第一端134和第二端135。本公开的实施例对发光元件的具体结构不作限制。
需要注意的是，在本公开至少一实施例的说明中，第一节点N1、第二节点N2、第三节点N3和第四节点N4并非一定表示实际存在的部件，而是表示电路图中相关电路连接的汇合点。
需要说明的是，在本公开的实施例的描述中，符号Vd既可以表示数据信号端又可以表示数据信号的电平，同样地，符号Ga1、Ga2既可以表示第一扫描信号、第二扫描信号，也可以表示第一扫描信号端和第二扫描信号端，Rst既可以表示复位控制端又可以表示复位信号，符号Vinit既可以表示复位电压端又可以表示复位电压，符号VDD既可以表示第一电压端又可以表示第一电源电压，符号VSS既可以表示第二电压端又可以表示第二电源电压。以下各实施例与此相同，不再赘述。
图1C为图1B所示的像素电路的一种具体实现示例的电路图。如图1C所示，该像素电路900包括：第一至第七晶体管T1、T2、T3、T4、T5、T6、T7以及包括存储电容Cst。例如，第一晶体管T1被用作驱动晶体管，其他的第二至第七晶体管被用作开关晶体管。
例如，如图1C所示，驱动子电路122可以实现为第一晶体管T1。第一晶体管T1的栅极作为驱动子电路122的控制端131，和第一节点N1连接；第一晶体管T1的第一极作为驱动子电路122的第一端132，和第二节点N2连接；第一晶体管T1的第二极作为驱动子电路122的第二端133，和第三节点N3连接。
例如，如图1C所示，数据写入子电路126可以实现为第二晶体管T2。第二晶体管T2的栅极和第一扫描线(第一扫描信号端Ga1)连接以接收第一扫描信号，第二晶体管T2的第一极和数据线(数据信号端Vd)连接以接收数据信号，第二晶体管T2的第二极和驱动子电路122的第一端132(第二节点N2)连接。例如，该第二晶体管T2为P型晶体管，例如有源层为低温掺杂多晶硅的薄膜晶体管。
例如，如图1C所示，补偿子电路128可以实现为第三晶体管T3。第三晶体管T3的栅极配置为和第二扫描线(第二扫描信号端Ga2)连接以接收第二扫描信号，第三晶体管T3的第一极和驱动子电路122的控制端131(第一节点N1)连接，第三晶体管T3的第二极和驱动子电路122的第二端133(第三节点N3)连接。
例如，如图1C所示，存储子电路127可以实现为存储电容Cst，该存储电容Cst包括第一电极Ca和第二电极Cb，该存储电容的第一电极Ca和第一电压端VDD耦接，例如电连接，该存储电容的第二电极Cb和驱动子电路122的控制端131耦接，例如电连接。
例如，如图1C所示，第一发光控制子电路123可以实现为第四晶体管T4。第四晶体管T4的栅极和第一发光控制线(第一发光控制端EM1)连接以接收第一发光控制信号，第四晶体管T4的第一极和第一电压端VDD连接以接收第一电源电压，第四晶体管T4的第二极和驱动子电路122的第一端132(第二节点N2)连接。
例如，发光元件120的第一端和第二端也可以分别称为该发光元件的第一电极和第二电极。例如，该发光元件120可以具体实现为发光二极管，例如OLED，其第一电极134(例如为阳极)和第四节点N4连接配置为通过第二发光控制子电路124从驱动子电路122的第二端133接收驱动电流，发光元件120的第二电极135(例如为阴极)配置为和第二电压端VSS连接以接收第二电源电压。例如第二电压端可以接地，即VSS可以为0V。
例如，第二发光控制子电路124可以实现为第五晶体管T5。第五晶体管T5的栅极和第二发光控制线(第二发光控制端EM2)连接以接收第二发光控制信号，第五晶体管T5的第一极和驱动子电路122的第二端133(第三节点N3)连接，第五晶体管T5的第二极和发光元件120的第一端134(第四节点N4)连接。
例如，复位电路129可以包括第一复位电路和第二复位电路，该第一复位电路配置 为响应于第一复位信号Rst1将第一复位电压Vini1施加到第一节点N1，该第二复位电路配置为响应于第二复位信号Rst2将第二复位电压Vini2施加到第四节点N4。例如，如图1C所示，该第一复位电路实现为第六晶体管T6，该第二复位电路实现为第七晶体管T7。第六晶体管T6的栅极配置为和第一复位控制端Rst1连接以接收第一复位信号Rst1，第六晶体管T6的第一极和第一复位电压端Vinit1连接以接收第一复位电压Vinit1，第六晶体管T6的第二极配置为和第一节点N1连接。第七晶体管T7的栅极配置为和第二复位控制端Rst2连接以接收第二复位信号Rst2，第七晶体管T7的第一极和第二复位电压端Vinit2连接以接收第二复位电压Vinit2，第七晶体管T7的第二极配置为和第四节点N4连接。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)，关闭电压为高电平电压(例如，5V、10V或其他合适的电压)；当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其他合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)。需要说明的是，本公开实施例均以P型晶体管为例进行说明，然而不作为对本公开的限制。
图2A为本公开至少一个实施例提供的显示基板20的示意图。多个子像素100的像素电路布置为像素电路阵列，该像素电路阵列的列方向为第一方向D1，行方向为第二方向D2，第一方向D1与第二方向D2交叉，例如正交。在一些实施例中，各子像素的像素电路除与发光元件的连接结构外，可以具有完全相同的结构，即像素电路在行和列方向重复排列，不同子像素的与发光元件的连接结构根据各个子像素的发光结构的电极的布置形状和位置可以不同。在一些实施例中，不同颜色子像素的像素电路的大致框架(例如各个信号线的形状和位置)基本相同，各个晶体管的相对位置关系也基本相同，但对于有些信号线或连接线的宽度、形状，或者某些晶体管的例如沟道尺寸、形状，或者用于与不同子像素的发光元件连接的连接线或者过孔位置等可以有不同，可以根据各个布局结构以及子像素排列进行调整。
图2A中示例性地示出了位于同一行的相邻的两个子像素100，并示出了半导体层102、第一导电层201、第二导电层202、第三导电层203、第四导电层204。图2C为图2A沿剖面线A1-A2的剖视图的一个示例。该半导体层102、第一绝缘层103、第一导电层201、第二绝缘层104、第二导电层202、第三绝缘层105、第三导电层203、第四绝缘 层106、第四导电层204依次设置于衬底基板101上，从而形成如图2A所示的显示基板的结构。然而，本公开的实施例不限于此布局。
图2B对应于图2A示意出了该两个子像素100中晶体管T1-T7的半导体层102和第一导电层(栅极层)201，并示出了各晶体管的栅极、第一极和第二极。图2B中用大虚线框示出了每个子像素100所在的区域，用小虚线框示出了一个子像素100中第一到第七晶体管T1-T7的栅极T1g-T7g。为了方便说明，在以下的描述中用Tng、Tns、Tnd、Tna分别表示第n晶体管Tn的栅极、第一极、第二极和有源层，其中n为1-7。
以下将结合图2A-图2C对本公开至少一实施例提供的显示基板的一个子像素的结构进行示例性说明，其它子像素的结构例如与此基本相同。
需要说明的是，本公开中所称的“同层设置”是指两种(或两种以上)结构通过同一道沉积工艺形成并通过同一道构图工艺得以图案化而形成的结构，它们的材料可以相同或不同。本公开中的“一体的结构”是指两种(或两种以上)结构通过同一道沉积工艺形成并通过同一道构图工艺得以图案化而形成的彼此连接的结构，它们的材料可以相同或不同。
例如，结合图2A和图2B所示，该半导体层102包括第一到第七晶体管T1-T7的有源层T1a-T7a。如图2B所示，该第一到第七晶体管T1-T7的有源层T1a-T7a彼此连接为一体的结构。例如，每一列子像素中的半导体层102为彼此连接的一体的结构，相邻两列子像素中的半导体层彼此间隔，这样可以避免第二方向上相邻像素之间的信号串扰。
例如，如图2B所示，该第一导电层201包括第一到第七晶体管T1-T7的栅极T1g-T7g。例如，第三晶体管T3和第六晶体管T6采用双栅结构，这样可以提高晶体管的栅控能力，降低漏电流。
例如，该第一导电层104还包括彼此绝缘的多条扫描线210、多条复位控制线220和多条发光控制线230。例如，每行子像素分别对应连接一条扫描线210、一条复位控制线220和一条发光控制线230。
扫描线210与对应一行子像素中的第二晶体管T2的栅极电连接(或为一体的结构)以提供第一扫描信号Ga1，复位控制线220与对应一行子像素中的第六晶体管T6的栅极电连接以提供第一复位信号Rst1，发光控制线230与对应一行子像素中的第四晶体管T4的的栅极电连接以提供第一发光控制信号EM1。
例如，如图2A所示，该扫描线210还与第三晶体管T3的栅极电连接(或为一体的结构)以提供第二扫描信号Ga2，即第一扫描信号Ga1和第二扫描信号Ga2可以为同一信号；该发光控制线230还与第五晶体管T5的栅极电连接以提供第二发光控制信号EM2，也即该第一发光控制信号EM1和第二发光控制信号EM2为同一信号。
例如，如图2A所示，本行像素电路的第七晶体管T7的栅极与下一行像素电路(即按照扫描线的扫描顺序，在本行扫描线之后顺序开启的扫描线所在的像素电路行)所对应的复位控制线220(n+1)电连接以接收第二复位信号Rst2。
例如，从图2A可知，在列方向(第一方向D1)划分像素区的栅线11可以是该复位控制线220或该发光控制线230，每个像素电路的区域都包含一条复位控制线220，一条发光控制线230和一条扫描线210的各一部分。
例如，如图2B所示，该显示基板20采用自对准工艺，利用第一导电层201作为掩膜对该半导体层102进行导体化处理(例如掺杂处理)，使得该半导体层102未被该第一导电层201覆盖的部分被导体化，从而各晶体管的有源层位于沟道区两侧的部分被导体化而形成分别该晶体管的第一极和第二极。
例如，如图2A所示，该第二导电层202包括存储电容的第一电极Ca。该存储电容的第一电极Ca在垂直于衬底基板101的方向上与第一晶体管T1的栅极T1g重叠从而形成存储电容Cst，也即该第一晶体管T1的栅极T1g充当该存储电容Cst的第二电极Cb。例如，该存储电容的第一电极Ca包括过孔301(本公开的第四过孔的一个示例)，该过孔301暴露出该第一晶体管T1的栅极T1g的至少部分，以便于该栅极T1g与其它结构电连接。
例如，如图2A所示，相邻的子像素的存储电容的第一电极Ca彼此电连接。由于每个子像素的存储电容的第一电极Ca与子像素对应的第一电源线250电连接，多个存储电容的第一电极Ca在第一方向D1上彼此连接，可以将多条第一电源线250连接成网状结构，这样可以降低电源线上的电阻和电压降，使得第一电源电压均匀地输送到每个子像素，提高了显示基板的均一性。
例如，如图2A所示，该第二导电层202还可以包括多条复位电压线240，该多条复位电压线240与多行子像素一一对应连接。该复位电压线240与对应一行子像素中的第六晶体管T6的第一极电连接以提供第一复位电压Vinit1。
例如，本行子像素中的第七晶体管T7的第一极可以与下一行子像素所对应的的复位电压线240电连接以接收第二复位电压Vinit2。
例如，该第三导电层203包括沿第一方向D1延伸的第一电源线250，该第一电源线250与第一电压端VDD连接，并配置为为多个子像素100提供第一电源电压VDD。例如，如图2A所示，该第三导电层203包括与多列子像素一一对应电连接的多条第一电源线250。该第一电源线250通过过孔302与所对应的一列子像素中的存储电容的第一电极Ca电连接，通过过孔303与第四晶体管T4的第一极电连接。然而，本公开各实施例对第一电源线的数目及设置方式(例如与子像素的对应连接方式)不作限制。
例如，该第三导电层203还包括该多条数据线12。该多条数据线12与多列子像素一一对应电连接以提供数据信号。例如，该数据线12与所对应的的一列子像素中的第二晶体管T2的第一极T2s通过过孔305电连接以提供该数据信号。
例如，如图2A所示，该第三导电层203还包括连接电极231(本公开的第二连接电极的一个示例)，该连接电极231的一端通过存储电容的第一电极Ca中的过孔301以及绝缘层中的过孔401与该第一晶体管T1的栅极T1g，即存储电容的第二电极Cb电连接，另一端通过过孔402与该第三晶体管T3的第一极电连接，从而将该存储电容的第二电极Cb与该第三晶体管T3的第一极T3s电连接。例如，如图2C所示，该过孔401贯穿第二绝缘层104和第三绝缘层105，该过孔402贯穿第一绝缘层103、第二绝缘层104和第三绝缘层105。
例如，如图2A所示，该第三导电层203还包括连接电极232，该连接电极232的一端通过过孔403与复位电压线240电连接，另一端通过过孔404与第六晶体管T6电连接，使得该第六晶体管T6的第一极T6s可以从该复位电压线240接收第一复位电压Vinit1。例如，该过孔403贯穿第三绝缘层105，该过孔404贯穿第一绝缘层103、第二绝缘层104和第三绝缘层105。
例如，如图2A和2C所示，该第三导电层203还包括连接电极233，该连接电极233通过过孔405(本公开的第三过孔的一个示例)与第五晶体管T5的第二极T5d电连接，并用于将该第五晶体管T5的第二极T5d与发光元件的第一电极134电连接，例如，该过孔405贯穿第一绝缘层103、第二绝缘层104和第三绝缘层105。例如，该连接电极233即为该第五晶体管T5的第二极接触电极。
该第四导电层204(本公开的电连接层的一个示例)包括位于显示区DA的第一部分204a，如图2A所示，该第一部分204a包括分别与多个子像素100一一对应设置的多个连接电极234(本公开第一连接电极的一个示例)，每个子像素的像素电路通过该连接电极234与发光元件120电连接。
需要说明的是，本公开实施例中的像素电路是指位于该第四导电层204靠近衬底基板101一侧的电路结构(例如各晶体管结构)，从而与该第四导电层204中的连接电极234、该第四导电层204上方的发光元件120等进行区分。
如图2A和2C所示，第四绝缘层106位于该第四导电层204与像素电路900之间，该连接电极234通过第四绝缘层106中的过孔307(本公开的第一过孔的一个示例)与第三导电层203中的连接电极233电连接，从而与子像素的像素电路900电连接。该连接电极234还配置为通过过孔308(本公开的第二过孔的一个示例)与发光元件120的第一电极134电连接，从而将发光元件与像素电路900(例如第五晶体管的第二极)电连接。如图2C所示，过孔308位于第五绝缘层107中；过孔307与过孔308在垂直于衬底基板 101的方向上不重叠，也即过孔307与过孔308在衬底基板101上的正投影不重叠。
通过连接电极234将发光元件120与像素电路900连接具有多方面的有益效果。一方面可以降低像素电极(第一电极134)的电阻从而增大驱动电流。另一方面，可以避免在垂直于衬底基板的方向上，过孔直接贯通导致导电材料的填充深度过深导致连接不良、断线或不平坦。再一方面，发光元件120的第一电极134的平整度影响着发光层的发光均匀性。通过设置第四导电层204将下层的像素电路900与上层的发光元件间隔，可以降低下层像素电路900对于第一电极134的平整度的影响。例如，如图2C所示，由于过孔405较深，通过设置连接电极234可以在纵向上拉大过孔405与第一电极134的距离，从而降低该较深的过孔405对于第一电极平整度的影响。
此外，将过孔307与过孔308设计为在垂直于衬底基板101的方向上不重叠，可以避免在垂直于衬底基板的方向上，有助于分散纵向上多个过孔的影响，进一步提高第一电极134的平整度。
例如，如图2C所示，过孔405、过孔307与过孔308在垂直于衬底基板101的方向上均不重叠，也即过孔405、307、308在衬底基板101上的正投影彼此不重叠。
如图2A所示，第四导电层204位于显示区DA的部分(也即第一部分)与任一第一电源线250在垂直于衬底基板101的方向上不重叠。
发明人发现，第一电源线250上的电阻、寄生电容引起的阻容负载对电源线上电源电压信号的均一稳定性起到重要影响，并进一步影响显示的均一性。发明人进一步发现，对于显示基板的显示区DA，相较于降低第一电源线250上的电阻，降低其寄生电容更有助于提高显示区的显示效果。将第四导电层位于显示区DA的第一部分(也即该第四导电层位于显示区的全部图案)设置与任一第一电源线250在垂直于衬底基板101的方向上不重叠，可以有效降低第一电源线上的寄生电容，提高显示效果。
例如，该第四导电层204还可以包括位于非显示区NDA的第二部分，该第四导电层204的第二部分可以与位于非显示区NDA的导电结构并联设置从而降低该导电结构的电阻，该导电结构例如为信号线或器件的电极等。具体将在后文介绍。
如图2A所示，过孔307和过孔308在衬底基板101的正投影均位于第三连接电极234在衬底基板的正投影内。例如，过孔307和过孔308在D1方向并列排布，且其沿第一方向D1的中心线大致重合。这样可以降低连接电极234在第二方向D2的尺寸，避免连接电极234与第一电源线250的重叠。
例如，如图2C所示，显示基板20还包括位于发光元件的第一电极上的像素界定层108。像素界定层108中形成开口从而界定显示基板的开口区600。发光层136至少形成于该开口内(发光层136还可以覆盖部分的像素界定层)，第二电极135形成于发光层 136上从而形成该发光元件120。例如，该第二电极135为公共电极，整面布置于该显示基板20中。例如第一电极为发光元件的阳极，第二电极为发光元件的阴极。
如图2C所示，该开口区600在垂直于衬底基板101的方向上与过孔307、308均不重叠以提高发光层的平整度。
在另一些示例中，在平行于衬底基板101板面的方向上，过孔308相较于过孔307更加远离子像素的开口区600(例如第一电极134的面积大于对应的开口区600的面积，开口区600大致位于第一电极134的中部区域)，也即该过孔308在衬底基板101上的正投影相较于过孔307在衬底基板101上的正投影更加远离该开口区600在衬底基板上的正投影。这是由于在垂直于衬底基板101的方向上，过孔308位于的第五绝缘层107(例如为第二平坦层)，相对于过孔307位于的第四绝缘层106(例如为第一平坦层)更靠近开口区600，因此该过孔308对于第一电极134暴露于开口区的部分(也即用于与发光层接触的部分)的平整度的影响较大，将该过孔308设置得离开口区更远(在平行于衬底基板的表面上)可以降低过孔对于开口区内的发光层136的平整度的影响，提高发光元件的性能。
在又一些示例中，过孔307可以与开口区600有部分交叠，因为过孔307所在的层与第一电极134所在的层中间至少间隔第四导电层204，以及过孔308所在的第五绝缘层107，所以过孔307对开口区的平坦性影响较过孔308对开口区的平坦性影响小。
例如，如图2A和图2C所示，过孔307和过孔308在衬底基板上的正投影分别位于该子像素100的发光控制线230在衬底基板上的正投影的两侧。这种设置可以避免该发光控制线230上的信号对于像素电极上的信号的干扰。
例如，如图2C所示，由于连接电极234需要向远离过孔307的方向延伸以与第一电极134通过过孔308电连接，为了避免过孔308处接触不良，该连接电极234通常在横向上延伸足够的距离从而与第一电极134充分接触。由于版图设计较为紧凑，这种设置会造成连接电极234与连接电极231在垂直于衬底基板101的方向上重叠而产生寄生电容。而在对各材料层进行图案化工艺形以形成图案时一般会出现误差。例如在光刻工艺中，曝光阶段容易出现对位误差；而在刻蚀工艺中，刻蚀所得到的图案的实际尺寸比设计值小，出现设计值与实际值的差值(即“CD bias”)。为了保证各子像素的均一性，可以对工艺进行设计从而保证在每个子像素中均存在该寄生电容，从而提高显示的均一性。
例如，如图2A和2C所示，在第一方向D1上，连接电极234在衬底基板101的正投影与连接电极231在衬底基板101的正投影的重叠尺寸d1满足：d1≥√((cdbias1)^2+〖(cdbias2)〗^2)，其中，cdbias1为连接电极231所在的第三导电层203的设计值与实际值的差值，cdbias2为连接电极234所在的第四导电层204的设计值与实际值的差值。 cdbias1和cdbias2的具体数值取决于工艺能力。例如，cdbias1和cdbias2均在0.1μm至0.9μm之间。通过这种设置，可以保证在存在工艺波动的情形下，各子像素的连接电极234与连接电极231在垂直于衬底基板101的方向上重叠，从而提高均一性。
图3为本公开另一些实施例提供的显示基板的示意图。如图3所示，存储电容的第一电极Ca与第一晶体管T1的第一极T1s在垂直于衬底基板101的方向上重叠。由于在第二方向D2上，第一电源线250位于数据线12与存储电容的第一电极Ca中的过孔301之间，并与存储电容的第一电极Ca通过过孔303电连接，因此该存储电容的第一电极Ca需要朝着数据线12的方向充分延伸，以保证与第一电源线250的良好接触。例如，第一晶体管T1的第一极T1s具有靠近数据线12的沿第一方向D1的第一极侧边601，存储电容的第一电极Ca具有靠近数据线12的沿第一方向D1的电容电极侧边602。例如，在第一方向D2上，该第一极侧边601为该第一晶体管T1的第一极T1s的最靠近该数据线12的侧边，该电容电极侧边602为该存储电容的第一电极Ca的最靠近该数据线12的侧边。
例如，在第二方向D2上，电容电极侧边602较第一极侧边601更靠近数据线12，也即该电容电极侧边602延伸出该第一极侧边601之外。
例如，为了防止工艺波动造成存储电容的第一电极Ca与第一晶体管T1的第一极T1s在垂直于衬底基板101的方向上的重叠面积不均一，从而引起寄生电容的不均一，可以对工艺进行设计从而保证在每个子像素中，该电容电极侧边602均超出该第一极侧边601之外。
例如，如图3所示，在第二方向D2上，电容电极侧边602在衬底基板101的正投影与第一极侧边601在衬底基板101的正投影的距离d2满足：d2≥√((cdbias3)^2+〖(cdbias4)〗^2)，其中，cdbias3为第一晶体管T1的第一极T1s所在的半导体层201的设计值与实际值的差值，cdbias4为存储电容的第一电极Ca所在的第二导电层202的设计值与实际值的差值。Cdbias3和cdbias4的具体数值取决于工艺能力。例如，cdbias3和cdbias4均在0.1μm至0.9μm之间。通过这种设置，可以保证在存在工艺波动的情形下，各子像素的电容电极侧边602均超出第一极侧边601之外，从而提高均一性。
在另一些示例中，如图4A所示，连接电极234被过孔308暴露的部分具有相对于衬底基板101的倾斜面。一方面，这种设置可以在相同空间下，提高发光元件120的第一电极134与连接电极234的接触面积，从而降低接触电阻，提高良率；另一方面，当该显示基板20为柔性显示基板时，该倾斜面设置可以缓解弯折应力对于过孔308处连接的稳定性，提高基板的耐弯折性。例如，该子像素的连接电极234的倾斜方向与该子像素所在基板区域的弯折方向一致，从而缓解该弯折应力。例如，该倾斜面相对于衬底基板的倾斜角在20度至50度之间。
图4B示出了图4A中过孔308处的放大示意图，例如，如图4B所示，连接电极233具有第一坡度角∠1，连接电极234在靠近过孔308的一端具有第二坡度角∠2，假定连接电极233形成于第三绝缘层105的平坦表面上，可以设置∠1大于等于55度小于等于70度，∠2大于等于60度小于等于80度，且∠1小于∠2，以对该连接电极234的倾斜面500进行设置，从而使得连接电极234与发光元件120的第一电极134之间具有较好的接触效果和电连接效果。此外，这种设置也有助于提高刻蚀第三导电层203和第四导电层204以分别形成该连接电极233和该连接电极234的刻蚀速率和刻蚀效果。
图5为本公开又一些实施例提供的显示基板的示意图。如图5所示，第一晶体管T1的有源层T1a包括弯折结构。通过这种设置可以降低该第一晶体管T1的沟道区的宽长比W/L。
由于第一晶体管T1为该像素电路的驱动晶体管，一般会设计较大的尺寸以获得足够大的驱动电流。然而，发明人发现，驱动电流过大会造成灰阶丢失，例如，无法对低灰阶数据进行显示而引起画面失真。通过降低第一晶体管T1的宽长比可以解决这个问题，提高显示效果。
例如，第一晶体管T1的有源层T1a为Ω形或“几”字形，或者类似于Ω形或“几”字形，也即包括突出结构。如图5所示，该有源层T1a包括第一部分701、第二部分702和连接部703。该第二部分702位于该第一部分701的两侧，该第一部分701为突出的部分。该连接部703连接该第一部分701和第二部分702。
例如，该第一部分701与第二部分702均为直线型，且不在同一水平线上，该第二部分702为弧状。例如，该第二部分702的平均曲率半径大于1μm。
如图5所示，连接部703的平均宽度W3比第一部分701的平均宽度W1和第二部分702的平均宽度W2均大。这是由于弧状的连接部703较直线型结构在形成过程中容易发生断裂，通过将连接部703做得更宽，可以提高工艺良率。
例如，如图5所示，存储电容的第一电极Ca中的过孔301与第一晶体管T1的有源层T1a在垂直于衬底基板的方向上不重叠。例如，通过在该有源层T1a中设置上述突出结构使得该有源层T1a与该过孔301在垂直于衬底基板的方向上不重叠。这种设计可以避免第一晶体管T1的栅极T1g被该过孔301暴露的部分，也即与该连接电极231接触的部分由于第一晶体管T1的有源层T1a而不平整，提高了连接电极231与该栅极T1g的接触良率。
显示基板20的栅极驱动电路13通常包括多个移位寄存器单元，该移位寄存器单元在外电路的控制信号的作用下，产生移位脉冲信号，该移位脉冲信号既作为当前行像素的扫描信号，又作为下一行的起始信号(第一行由帧起始信号STV触发)和上一行的结 束信号进行控制。例如，外电路的控制信号主要包括帧起始信号(STV)、相位相反的CLK和CLKB信号对、晶体管关闭信号(如VGL)以及可能的直流电压信号VGH、VGL。该多个移位寄存器单元与显示区的多行子像素一一对应连接，并配置为通过输出节点向所对应的一行子像素输出上述第一扫描信号Ga1和第二扫描信号Ga2。
图6A示出了本公开至少一实施例提供的一种栅极驱动电路的电路示意图，图中示出了该栅极驱动电路中的一个移位寄存器单元。如图6A所示，该移位寄存器单元包括输入电路501、输出电路502、存储电路503和复位电路504。输入电路501配置为响应于触发信号STV，将高电位VGH传输到上拉节点PU，也即输出电路502的控制端以及存储电路503的一端。输出电路502配置为在上拉节点PU的控制下将CLK信号输出。复位电路504配置为响应于CLKB信号将输出节点OUT复位。
例如，该输入电路501包括第八晶体管T8，输出电路502包括第九晶体管T9，复位电路504包括第十晶体管T10，存储电路503包括第一电容C1，该第一电容C1与该输出节点OUT连接，并包括第一电极C1a和第二电极C1b。以下将以P型晶体管为例对该移位寄存器单元的工作过程进行示例性说明，然而本公开实施例并不限于此。
该移位寄存器单元的一种工作过程包括：当触发信号STV来临，CLK信号为高电位，第八晶体管T8开启，将低电位VGL传输到第九晶体管T9的栅极(上拉节点PU)，同时存储到第一电容C1的第一电极，第九晶体管T9在低电位VGL的作用下开启，将低电位的CLK信号输出，开启本行子像素的晶体管，同时作为下一级移位寄存器单元的输入信号；随着CLK信号的电位由低变高，第十晶体管T10在低电位的CLKB信号作用下开启，第一电容C1放电，输出高电位，将本行子像素的晶体管关闭。如此，实现对显示区的子像素的逐行扫描。
图6B示出了图6A所示移位寄存器单元的结构示意图，图6C为图6B沿剖面线B1-B2的剖视图，图6D为图6B沿剖面线E1-E2的剖视图。需要说明的是，为了清楚起见，图6B和图6C中均省略了第一导电层201下方的结构(如第一绝缘层和半导体层)。
如图6B所示，该显示基板20包括位于非显示区NDA的第一电源信号线VGH、第二电源信号线VGL、触发信号线STV、第一时钟信号线CLK和第二时钟信号线CLKB。例如，各信号线均沿第一方向延伸。
第一电源信号线VGH与第八晶体管T8的第一极电连接以提供第一电源信号VGH，第二电源信号线VGL与第十晶体管T8的第一极电连接以提供第二电源信号VGL。第一时钟信号线CLK与第九晶体管的第一极电连接以提供第一时钟信号CLK，第二时钟信号线CLKB与第十晶体管T10的栅极电连接以提供第二时钟信号CLKB。触发信号线STV与第八晶体管T8的栅极电连接以提供触发信号STV。
该栅极驱动电路13可以与显示区的子像素同时形成。例如，该第八至第十晶体管T8-T10的栅极可以位于第一导电层201中，有源层、第一极及第二极可以位于半导体层102中，非显示区NDA的各信号线可以位于第三导电层203中。
如图6B和6C所示，第八晶体管T8的第二极通过连接电极650与第九晶体管T9的栅极T9g和第一电容C1的第一电极C1a电连接，第一电容C1的第二电极C1b例如与该连接电极650同层绝缘设置。例如，该连接电极650及该第一电容C1的第二电极C1b可以位于第三导电层203中。
例如，如图6B所示，各信号线通过第一导电层201中的走线图案连接到栅极驱动电路13，该栅极驱动电路13通过第三导电层203中的走线图案连接到显示区DA中的像素电路。
例如，第四导电层204位于非显示区的第二部分204b包括辅助电容电极C1c，该辅助电容电极C1c可以与该第一电容C1的第一电极C1a或第二电极C1b并联从而增大该第一电容C1的电容值。
如图6C所示，该辅助电容电极C1c通过贯穿第三绝缘层的过孔与连接电极650电连接，从而与第一电容C1的第一电极C1a电连接，并在垂直于衬底基板101的方向上与第一电容C1的第二电极C1b重叠。由此，该第一电极C1a与该辅助电容电极C1c分别与第二电极C1b至少部分重叠从而形成并联电容的结构，增大了第一电容C1的电容值，提高了第一电容C1的自举能力，从而提高了输出信号的稳定性。
例如，如图6B所示，第四导电层204位于非显示区的第二部分204b还包括与各信号线对应的辅助信号线，各辅助信号线与各信号线并联从而可以降低信号线的电阻以及该信号线上的电压降。各辅助信号线与其对应的信号线在垂直于衬底基板101的方向上彼此重叠，并通过过孔并联。
以下结合图6B和图6D对于触发信号线STV的辅助信号线进行示例性说明。
如图6B所示，触发信号线STV通过过孔与第八晶体管T8的栅极T8g电连接。例如，第四导电层204位于非显示区的第二部分204b还包括辅助触发信号线STV1，该辅助触发信号线STV1通过贯穿第三绝缘层的过孔与触发信号线STV并联。
例如，第四导电层204位于非显示区的第二部分204b还包括绑定电极80，也即绑定电极80位于该第四导电层204中。
图7A为图1A沿剖面线D1-D2的剖视图的一个示例。结合图1A和图7A所示，例如，该第四导电层204位于非显示区的第二部分204b还包括位于非显示区的走线81。该走线81的一端与绑定电极80连接，例如连接为一体的结构；该走线81的另一端延伸至显示区。如图7A所示，该走线81和绑定电极位于第四绝缘层106上，第五绝缘层107 覆盖走线81，并暴露出该绑定电极80以便于和外部电路进行绑定。如图7A所示，该走线81的一部分位于该弯折区BA。例如，由于无机材料较脆，在弯折下容易断裂，因此为了提高基板的耐弯折性，通常需要将弯折区BA内的无机绝缘材料去除(也即在该无机绝缘材料中形成开口)，并在该开口中填充韧性较好的无机材料。
例如，第一绝缘层103、第二绝缘层104、第三绝缘层105例如为无机绝缘层，例如氧化硅、氮化硅、氮氧化硅等硅的氧化物、硅的氮化物或硅的氮氧化物，或者氧化铝、氮化钛等包括金属氮氧化物绝缘材料。例如，第四绝缘层106、第五绝缘层107和像素界定层108分别为有机绝缘材料，例如为聚酰亚胺(PI)、丙烯酸酯、环氧树脂、聚甲基丙烯酸甲酯(PMMA)等有机绝缘材料。例如，第四绝缘层106和第五绝缘层107为平坦化层。
在这种情形，如图7A所示，弯折区BA内，第一绝缘层103、第二绝缘层104、第三绝缘层105均被去除，第四绝缘层106和第五绝缘层107保留，第四绝缘层106位于弯折区BA的部分(本公开的有机绝缘层的弯折部一个示例)填充在走线81与衬底基板101之间，并与衬底基板101直接接触，从而提高了走线81的耐弯折性能，降低了断线风险。第五绝缘层107覆盖在走线81上对走线81形成保护。
由于本公开上述至少一实施例提供的显示基板中存在该第四导电层，因此，该第四绝缘绝缘层和第五绝缘层均为该显示基板中的现有结构，而不需要额外工艺形成。
图7B为图1A沿剖面线D1-D2的剖视图的另一个示例。图7B所示实施例与图7A所示实施例的区别在于，图7B所示的显示基板20还包括位于非显示区NDA的辅助绑定电极82，该辅助绑定电极82位于绑定电极80靠近衬底基板101的一侧，与该绑定电极80并联以降低电阻。
例如，如图7B所示，该绑定电极80与该辅助绑定电极82直接接触电连接(搭接)，也即该辅助绑定电极82与该绑定电极80之间的第四绝缘层106去除。例如，该绑定电极80包覆该辅助绑定电极82的至少一个侧边，这样可以降低接触电阻。
例如，该辅助绑定电极82可以与显示区DA中位于第四导电层以下的任一导电层同层设置。例如，该辅助绑定电极82位于第三导电层203中，也即与第一电源线250同层设置。
例如，在不同的实施例中，衬底基板101可以为刚性基板，例如玻璃基板、硅基板等，也可以由具有优良的耐热性和耐久性的柔性材料形成，例如聚酰亚胺(PI)、聚碳酸酯(PC)、聚乙烯对苯二甲酸乙二醇酯(PET)、聚乙烯、聚丙烯酸酯、多芳基化合物、聚醚酰亚胺、聚醚砜、聚乙二醇对苯二甲酸酯(PET)、聚乙烯(PE)、聚丙烯(PP)、聚砜(PSF)、聚甲基丙烯酸甲酯(PMMA)、三醋酸纤维素(TAC)、环烯烃聚合物(COP)和环烯 烃共聚物(COC)等。
例如，该半导体层102的材料包括但不限于硅基材料(非晶硅a-Si，多晶硅p-Si等)、金属氧化物半导体(IGZO，ZnO，AZO，IZTO等)以及有机物材料(六噻吩，聚噻吩等)。
例如，该第一到第四导电层的材料可以包括金(Au)、银(Ag)、铜(Cu)、铝(Al)、钼(Mo)、镁(Mg)、钨(W)以及以上金属组合而成的合金材料；或者导电金属氧化物材料，例如氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化锌铝(AZO)等。
例如，该发光元件120为顶发射结构，第一电极具134有反射性而第二电极135具有透射性或半透射性。例如，第一电极134为高功函数的材料以充当阳极，例如为ITO/Ag/ITO叠层结构；第二电极135为低功函数的材料以充当阴极，例如为半透射的金属或金属合金材料，例如为Ag/Mg合金材料。
本公开至少一实施例还提供一种显示面板，包括以上任一显示基板20。需要说明的是，本公开至少一实施例提供的上述显示基板20可以包括发光元件120，也可以不包括发光元件120，也即该发光元件120可以在显示基板20完成后在面板厂形成。在该显示基板20本身不包括发光元件120的情形下，本公开至少一实施例提供的显示面板除了包括显示基板20之外，还进一步包括发光元件120。
例如，该显示面板为OLED显示面板，相应地其包括的显示基板20为OLED显示基板。如图8所示，例如，该显示面板30还包括设置于显示基板20上的封装层801和盖板802，该封装层801配置为对显示基板20上的发光元件进行密封以防止外界的湿气和氧向该发光元件及驱动子电路的渗透而造成对器件的损坏。例如，封装层801包括有机薄膜或者包括有机薄膜及无机薄膜交替层叠的结构。例如，该封装层801与显示基板20之间还可以设置吸水层(未示出)，配置为吸收发光元件在前期制作工艺中残余的水汽或者溶胶。盖板802例如为玻璃盖板。例如，盖板802和封装层801可以为一体的结构。
本公开的至少一实施例还提供一种显示装置40，如图9所示，该显示装置40包括上述任一显示基板20或显示面板30，本实施例中的显示装置可以为：显示器、OLED面板、OLED电视、电子纸、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开至少一实施例还提供上述显示基板20的制作方法。以下将结合图2A-2C、图6B-图6D和图7A-图7B对本公开至少一实施例提供的显示基板的结构和制作方法进行实例性说明，然而本公开至少一实施例并不限于此。
在一些示例中，该制作方法包括如下步骤S61-S70。
步骤S61：在衬底基板上形成半导体材料层，并对该半导体材料层进行构图工艺从而形成半导体层102，半导体层102包括在每个像素区内第一到第七晶体管T1-T7的有源层T1a-T7a和掺杂区图案(即对应第一到第七晶体管T1-T7的源极区域和漏极区域)(如图2B所示的)，且同一像素区中的各晶体管的有源层图案和掺杂区图案一体设置。例如，该半导体层102还包括非显示区NDA中第八到第十晶体管T8-T10的有源层和掺杂区图案(即对应第八到第十晶体管T8-T10的源极区域和漏极区域)。
需要说明的是，有源层可以包括一体形成的低温多晶硅层，其中的源极区域和漏极区域可以通过掺杂等进行导体化实现各结构的电连接。也就是每个子像素的各晶体管的有源半导体层为由p-硅形成的整体图案，且同一像素区中的各晶体管包括掺杂区图案(即源极区域和漏极区域)和有源层图案，不同晶体管的有源层之间由掺杂结构隔开。
步骤S62：在半导体层102层上形成第一绝缘层103(例如可以为透明层)，例如为第一栅绝缘层；并在第一绝缘层上形成多个第一绝缘层过孔用于与后续形成的第三导电层203的图案连接。例如对应半导体层中的源极区域和漏极区域的位置，分别在第一绝缘层中形成对应的第一绝缘层过孔，即第一绝缘层过孔分别与半导体层中的源极区域和漏极区域交叠，以用于源极区域和漏极区域与第三导电层中的数据线12、第一电源线250等结构进行连接，例如贯穿第一绝缘层的过孔402，过孔405，过孔303，过孔305等。
步骤S63：在第一绝缘层103上形成第一导电材料层，并对该第一导电材料层进行构图工艺从而形成第一导电层201，该导电层201例如包括位于显示区DA中的彼此绝缘且沿第二方向延伸的扫描线210、复位控制线220和发光控制线230。例如，对于一行像素电路，其对应连接的复位控制线220、扫描线210和发光控制线230在第一方向D1上依次排布。例如，如图6B所示，该第一导电层201还包括非显示区NDA中的第八到第十晶体管T8-T10的栅极以及走线等。
例如，该第一导电层201还包括第一到第七晶体管T1-T7的栅极T1g-T7g。例如，第六晶体管T6的栅极T6g和复位控制线220为一体的结构，即复位控制线220的一部分作为第六晶体管T6的栅极T6g；第二晶体管T2的栅极T2g和扫描线210为一体的结构，即扫描线210的部分作为第二晶体管T2的栅极T2g；第四晶体管T4的栅极T4g和第五晶体管T5的栅极T5g均与发光控制线230为一体的结构，即发光控制线230的一部分作为第四晶体管T4的栅极T4g和第五晶体管T5的栅极T5g；第七晶体管T7的栅极T7g与下一行像素电路所对应的复位控制线220为一体的结构。例如，第六晶体管T6和第三晶体管T3均为双栅结构，第六晶体管T6的两个栅极T6g均为复位控制线220的一部分，第三晶体管T3的一个栅极为扫描线210的一部分，第三晶体管T3的另一个栅极为 在扫描线210一体连接并朝向第六晶体管T6突出的一部分。
例如，该半导体层102与该第一导电层201在垂直于衬底基板的方向上重叠的部分定义出该第一到第七晶体管T1-T7的有源层(沟道区)T1a-T7a。
步骤S64：如图2B所示，采用自对准工艺，利用该第一导电层201作为掩膜对该半导体层102进行导体化处理(例如掺杂处理)，从而使得该半导体层102未被该第一导电层201覆盖的部分被导体化，从而使得该半导体层102位于各晶体管的有源层两侧的部分被导体化而分别形成第一到第十晶体管T1-T10的源极区域和漏极区域,也即第一到第十晶体管T1-T10的第一极(T1s-T10s)和第二极(T1d-T10d)。
步骤S65：在第一导电层201上形成第二绝缘层104(例如可以为透明层)，例如可以为第二栅绝缘层；并在第二绝缘层上至少形成与第一绝缘层过孔对应的第二绝缘层过孔。例如对应至少贯穿第一绝缘层和第二绝缘层的过孔至少包括过孔402，过孔405，过孔303，过孔305等。该第一绝缘层中的过孔与该第二绝缘层中的过孔也可以在一道工艺中形成，本公开各实施例对此不作限制。
步骤S66：在该第二绝缘层104并在该第二绝缘层上形成第二导电材料层，对该第二导电材料层进行构图工艺形成如图2A所示的第二导电层202，也即形成彼此绝缘的存储电容的第一电极Ca以及沿第一方向延伸的复位电压线240。
例如，该存储电容的第一电极Ca与该第一晶体管T1的栅极T1g在垂直于衬底基板101的方向上至少部分重叠。该构图工艺还在该存储电容的第一电极Ca中形成过孔301，该过孔301暴露出第一晶体管T1的栅极T1g的至少部分。
步骤S67：在该第二导电层202上形成第三绝缘层105。第三绝缘层例如可以为层间绝缘层。在第三绝缘层中形成用于连接与后续形成的第三导电层的连接的过孔。至少部分过孔与第一绝缘层过孔和第二绝缘层过孔位置对应，且同时贯穿第一绝缘层、第二绝缘层和第三绝缘层，例如过孔402、过孔405、过孔303、过孔305。
步骤S68：在该第三绝缘层105上形成第三导电材料层，对该第三导电材料层进行构图工艺形成第三导电层203。如图2A所示，该第三导电层203例如包括彼此绝缘的数据线12、第一电源线250、连接电极231、连接电极232和连接电极233。该数据线12和该第一电源线250沿第一方向D1延伸。如图6B-6C所示，该第三导电层203还可以包括位于非显示区NDA的连接电极650、第一电容C1的存储电容的第二电极C1b以及各信号线(STV、CLK、CLKB、VGL、VGH)。
例如，如图2A所示，该数据线12与第二晶体管T2的第一极T2s在垂直于衬底基板101的方向上重叠并通过过孔305与该第二晶体管T2的第一极T2s电连接，该过孔305例如贯穿第一绝缘103、第二绝缘层104和第三绝缘层105。
例如，如图2A所示，该第一电源线250通过过孔302与所对应的一列子像素中的存储电容的第一电极Ca电连接，并通过过孔303与第四晶体管T4的第一极T4s电连接。例如，该过孔302贯穿第三绝缘层105，该过孔303贯穿第一绝缘103、第二绝缘层104和第三绝缘层105。
例如，如图2A所示，该连接电极231的一端通过存储电容的第一电极Ca中的过孔301以及绝缘层中的过孔401与该第一晶体管T1的栅极T1g，即存储电容的第二电极Cb电连接，另一端通过过孔402与该第三晶体管T3的第一极电连接，从而将该存储电容的第二电极Cb与该第三晶体管T3的第一极T3s电连接。例如，该过孔401贯穿第二绝缘层104和第三绝缘层105，该过孔402贯穿第一绝缘层103、第二绝缘层104和第三绝缘层105。
例如，如图2A所示，该连接电极232的一端通过过孔403与复位电压线240电连接，另一端通过过孔404与第六晶体管T6电连接，使得该第六晶体管T6的第一极T6s可以从该复位电压线240接收第一复位电压Vinit1。例如，该过孔403贯穿第三绝缘层105，该过孔404贯穿第一绝缘层103、第二绝缘层104和第三绝缘层105。
例如，如图2A所示，该连接电极233通过过孔405与第五晶体管T5的第二极T5d电连接，并用于将该第五晶体管T5的第二极T5d与发光元件的第一电极134电连接，例如，该过孔405贯穿第一绝缘层103、第二绝缘层104和第三绝缘层105。
步骤S69：在第三导电层203上形成第四绝缘层106。并在第三绝缘层中形成用于与后续形成的第四导电层连接的过孔。在一些实施例中，例如第四绝缘层106包括第一平坦层。在另一些实施例中，例如第四绝缘层106包括钝化层和第一平坦层两层，则形成在第四绝缘层中的过孔需要贯穿钝化层和第一平坦层两层。例如，第一平坦层位于钝化层远离第三导电层的一侧。例如，该第一平坦层为有机绝缘材料，该钝化层为无机绝缘材料。
步骤S70：在该第四绝缘层106上形成第四导电材料层，对该第四导电材料层进行构图工艺形成第四导电层204，该第四导电层204包括位于显示区DA的第一部分204a和位于非显示区NDA的第二部分204b。如图2A所示，该第一部分204a包括连接电极234。如图6B所示，该第二部分204b包括与各信号线对应的辅助信号线以及绑定电极80、走线81等。该第一部分204a与第一电源线250在垂直于衬底基板101的方向上不重叠。
例如，如图2A所示，该连接电极234与连接电极233在垂直于衬底基板101的方向上重叠，并且该连接电极234通过贯穿第四绝缘层106的过孔307与连接电极233电连接。
例如，该显示基板的制作方法还可以包括在该第四导电层204上形成第五绝缘层107，并在第五绝缘层107中形成用于与后续形成的第五导电层进行连接的过孔。例如第五绝缘层107可以为第二平坦层。参考图2C，第五绝缘层过孔例如用于连接发光元件120的第一电极134和连接电极234，第五绝缘层过孔与第五晶体管T5的第二极可以有交叠，也可以没有交叠。
例如，该显示基板的制作方法还可以包括在该第五绝缘层107上形成第五导电材料层，对该第五导电材料层进行构图工艺形成第五导电层205，即形成彼此绝缘的多个用于形成发光元件的第一电极134。
例如，如图2C所示，该显示基板的制作方法还可以包括依次在该第五导电层205上形成像素界定层108，并在该像素界定层108中对应于每个第一电极134的主体部141形成开口区600，然后至少在该开口区600中形成发光层136，并在该发光层上形成第二电极135。
例如，该半导体材料层的材料包括但不限于硅基材料(非晶硅a-Si，多晶硅p-Si等)、金属氧化物半导体(IGZO，ZnO，AZO，IZTO等)以及有机物材料(六噻吩，聚噻吩等)。
例如，上述第一导电材料层、第二导电材料层、第三导电材料层、第四导电材料层、第五导电材料层及第二电极的材料可以包括金(Au)、银(Ag)、铜(Cu)、铝(Al)、钼(Mo)、镁(Mg)、钨(W)以及以上金属组合而成的合金材料；或者透明金属氧化物导电材料，例如氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化锌铝(AZO)等。
例如，第一绝缘层103、第二绝缘层104、第三绝缘层105、第四绝缘层106、第五绝缘层107例如为无机绝缘层，例如氧化硅、氮化硅、氮氧化硅等硅的氧化物、硅的氮化物或硅的氮氧化物，或者氧化铝、氮化钛等包括金属氮氧化物绝缘材料。例如，这些绝缘层部分层也可以是有机材料，例如第一平坦层和第二平坦层，例如聚酰亚胺(PI)、丙烯酸酯、环氧树脂、聚甲基丙烯酸甲酯(PMMA)等，本公开各实施例对此不作限制。例如，第四绝缘层106和第五绝缘层107可以分别包括平坦层。
例如，上述构图工艺可以采用常规的光刻工艺，例如包括光刻胶的涂布、曝光、显影、烘干、刻蚀等步骤。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (21)

  1. 一种显示基板，包括：
    衬底基板，包括显示区和非显示区；
    多个子像素，位于所述衬底基板的显示区，其中，所述多个子像素每个包括像素电路，所述像素电路用于驱动发光元件发光；所述多个子像素的多个像素电路沿第一方向和第二方向分布为多行多列，
    所述像素电路包括驱动子电路、数据写入子电路、补偿子电路和存储子电路；
    所述驱动子电路包括控制端、第一端和第二端，且配置为与所述发光元件连接并且控制流经发光元件的驱动电流；
    所述数据写入子电路包括控制端、第一端和第二端，所述数据写入子电路的控制端配置为接收第一扫描信号，所述数据写入子电路的第一端配置为接收数据信号，所述数据写入子电路的第二端与所述驱动子电路电连接，所述数据写入子电路配置为响应于所述第一扫描信号将所述数据信号写入所述驱动子电路的第一端；
    所述补偿子电路包括控制端、第一端和第二端，所述补偿子电路的控制端配置为接收第二扫描信号，所述补偿子电路的第一端和第二端分别与所述驱动子电路的控制端和第二端电连接，所述补偿子电路配置为响应所述第二扫描信号对所述驱动子电路进行阈值补偿；
    所述存储子电路与所述驱动子电路的控制端和第一电压端电连接，且被配置为存储所述数据信号；所述存储子电路包括存储电容，所述存储电容包括第一电极和第二电极，所述存储电容的第一电极和所述第一电压端电连接，所述存储电容的第二电极和所述驱动子电路的控制端电连接；
    第一电源线，其中，所述第一电源线位于所述显示区，沿所述第一方向延伸，与所述第一电压端连接，并配置为为所述多个子像素提供第一电源电压；
    电连接层，位于所述像素电路远离所述衬底基板的一侧，其中，所述电连接层包括位于所述显示区的第一部分，所述第一部分包括多个第一连接电极，所述多个第一连接电极分别与所述多个子像素一一对应设置，
    其中，每个子像素的像素电路通过第一过孔与所对应的第一连接电极电连接，每个子像素所对应的第一连接电极配置为通过第二过孔与所述发光元件电连接，从而将所述子像素的像素电路与发光元件电连接；所述第一过孔与所述第二过孔在垂直于所述衬底基板的方向上不重叠；
    所述电连接层的第一部分与所述第一电源线在垂直于所述衬底基板的方向上不重叠。
  2. 如权利要求1所述的显示基板，其中，所述第一过孔和第二过孔沿所述第一方向排列。
  3. 如权利要求1或2所述的显示基板，还包括位于所述非显示区的电源信号线和栅极驱动电路，
    其中，所述栅极驱动电路配置为为所述子像素提供所述第一扫描信号和所述第二扫描信号，所述电源信号线配置为为所述子像素的栅极驱动电路提供电源信号，
    所述电连接层还包括位于所述非显示区的第二部分，所述第二部分包括辅助信号线，所述辅助信号线与所述电源信号线并联。
  4. 如权利要求3所述的显示基板，其中，所述栅极驱动电路包括多个移位寄存器单元，所述多个移位寄存器单元与所述多行子像素一一对应连接，并配置为通过输出节点向所对应的一行子像素输出所述第一扫描信号和所述第二扫描信号，
    每个移位寄存器单元包括与所述输出节点连接的第一电容，所述第一电容包括第一电极和第二电极，
    所述电连接层的第二部分还包括辅助电容电极，所述辅助电容电极与所述第一电容的第一电极或第二电极并联。
  5. 如权利要求1-4任一所述的显示基板，其中，所述子像素还包括第一发光控制子电路，第一发光控制子电路包括控制端、第一端和第二端，第一端与驱动子电路电连接，第二端配置为通过第三过孔与第一连接电极电连接，控制端配置为接收第一发光控制信号，
    所述第一发光控制子电路配置为响应于第一发光控制信号使得驱动电流可被施加至发光元件；
    所述第一过孔、所述第二过孔和所述第三过孔在垂直于所述衬底基板的方向上均不重叠。
  6. 如权利要求5所述的显示基板，其中，所述显示基板还包括第一发光控制线，所述第一发光控制线沿所述第二方向延伸，且与所述第一发光控制子电路的控制端连接以提供所述第一发光控制信号，
    所述第一过孔在所述衬底基板上的正投影和所述第二过孔在所述衬底基板上的正投影分别位于所述第一发光控制线在所述衬底基板上的正投影的两侧。
  7. 如权利要求1-6任一所述的显示基板，其中，对于至少一个子像素，所述第一连接电极被所述第二过孔暴露的部分具有相对于衬底基板的倾斜面。
  8. 如权利要求1-7任一所述的显示基板，其中，每个子像素还包括第二连接电极，所述第二连接电极位于所述存储电容的第一电极远离所述衬底基板的一侧，
    所述第二连接电极分别与所述存储电容的第二电极和所述补偿子电路的第二端连接。
  9. 如权利要求8所述的显示基板，其中，所述第二连接电极与所述第一连接电极在垂直于衬底基板的方向上重叠。
  10. 如权利要求8或9所述的显示基板，其中，所述驱动子电路包括第一晶体管，所述第一晶体管的栅极、第一极和第二极分别作为所述驱动子电路的控制端、第一端和第二端。
  11. 如权利要求10所述的显示基板，其中，所述存储电容的第一电极包括第四过孔，所述第二连接电极通过所述第四过孔与所述存储电容的第二电极电连接。
  12. 如权利要求11所述的显示基板，其中，所述第四过孔与所述第一晶体管的有源层在垂直于所述衬底基板的方向上不重叠。
  13. 如权利要求10-12任一所述的显示基板，其中，所述第一晶体管的有源层包括弯折结构。
  14. 如权利要求13所述的显示基板，其中，所述第一晶体管的有源层类似于“Ω”形或“几”字形，包括第一部分、第二部分和连接部，
    所述有源层的第一部分和第二部分均为直线型，且不在同一水平线；所述有源层的连接部连接所述第一部分与第二部分，且为弧状。
  15. 如权利要求14所述的显示基板，其中，所述有源层的连接部的平均宽度大于所述第一部分或所述第二部分的平均宽度。
  16. 如权利要求10-15任一所述的显示基板，还包括数据线，其中，所述数据线沿所述第一方向延伸，并与所述数据写入子电路的第一端连接以提供所述数据信号；
    所述存储电容的第一电极与所述第一晶体管的第一极在垂直于衬底基板的方向重叠，
    所述第一晶体管的第一极具有靠近所述数据线的沿所述第一方向的第一极侧边，
    所述存储电容的第一电极具有靠近所述数据线的沿所述第一方向的电容电极侧边，
    在所述第二方向上，所述电容电极侧边较所述第一极侧边更靠近所述数据线。
  17. 如权利要求1-16任一所述的显示基板，其中，所述非显示区包括绑定区，所述电连接层还包括位于所述非显示区的第二部分，所述第二部分包括位于所述非显示区的绑定电极，
    所述显示基板还包括辅助绑定电极，所述辅助绑定电极与所述第一电源线同层设置且材料相同，并与所述绑定电极搭接。
  18. 如权利要求17所述的显示基板，其中，所述电连接层的第二部分还包括位于所述非显示区的走线，所述走线的一端与所述绑定电极连接，另一端延伸至所述显示区；
    所述非显示区还包括弯折区，所述走线的一部分位于所述弯折区。
  19. 如权利要求18所述的显示基板，还包括有机绝缘层，
    其中，所述有机绝缘层位于所述电连接层与所述像素电路之间，所述第一过孔位于所述有机绝缘层中，
    所述有机绝缘层包括位于所述弯折区的弯折部，所述弯折部位于所述走线靠近所述 衬底基板的一侧并与所述衬底基板直接接触。
  20. 如权利要求1-19任一所述的显示基板，其中，所述电连接层位于所述显示区的全部图案与所述第一电源线在垂直于所述衬底基板的方向上均不重叠。
  21. 一种显示装置，包括如权利要求1-20任一所述的显示基板。
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