WO2021128453A1 - 阵列基板及其制备方法、显示面板 - Google Patents

阵列基板及其制备方法、显示面板 Download PDF

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Publication number
WO2021128453A1
WO2021128453A1 PCT/CN2020/070407 CN2020070407W WO2021128453A1 WO 2021128453 A1 WO2021128453 A1 WO 2021128453A1 CN 2020070407 W CN2020070407 W CN 2020070407W WO 2021128453 A1 WO2021128453 A1 WO 2021128453A1
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Prior art keywords
area
layer
substrate
region
conductive
Prior art date
Application number
PCT/CN2020/070407
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English (en)
French (fr)
Inventor
朱清永
Original Assignee
Tcl华星光电技术有限公司
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Priority to US16/641,043 priority Critical patent/US20210405478A1/en
Publication of WO2021128453A1 publication Critical patent/WO2021128453A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133388—Constructional arrangements; Manufacturing methods with constructional differences between the display region and the peripheral region
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/28—Adhesive materials or arrangements

Definitions

  • This application relates to the field of display technology, and in particular to an array substrate, a preparation method thereof, and a display panel.
  • FIG. 1 is a schematic structural diagram of a gate driving circuit of an existing display panel.
  • the first metal layer 101 and the second metal layer 102 are connected to each other through the conductive layer 103.
  • the conductive layer 103 passes through The via hole on the gate insulating layer 104 and the via hole on the protective layer 105 realize the electrical connection between the first metal layer 101 and the second metal layer 102, and the first metal layer 101 and the second metal layer 101 are electrically connected to each other.
  • the embodiments of the present application provide an array substrate, a preparation method thereof, and a display panel, which can reduce the contact resistance of the gate drive circuit, improve the problem of gradation lines that are prone to appear in the display of the display panel, improve the display quality, and reduce the process of preparing the array substrate.
  • a substrate having a first area, a second area, and a third area, the second area being located between the first area and the third area;
  • a first metal layer including a first metal member provided in the first region of the substrate and a second metal member provided in the third region of the substrate;
  • a first insulating layer, the first insulating layer covering the first metal layer and the substrate, and the first insulating layer is provided with a through hole corresponding to the third region;
  • the conductive layer is located on the side of the first insulating layer away from the first metal layer, and the conductive layer includes a first conductive portion disposed in the first region and the second region, and a first conductive portion disposed in the first region. At least part of the second conductive portion in the three regions is connected to the second metal member through the through hole;
  • a second metal layer includes a third metal member provided in the first region of the substrate and a fourth metal member provided in the third region of the substrate, the The fourth metal member is connected to the second conductive portion.
  • the array substrate has a display area and a non-display area, the non-display area includes a gate drive circuit area, and the gate drive circuit area has a first wiring and a second wiring. line;
  • the first area and the second area of the substrate correspond to the display area of the array substrate
  • the third area of the substrate corresponds to the gate drive circuit area in the non-display area of the array substrate;
  • the first metal member is a gate electrode and a scan line.
  • the third metal member is a source electrode and a drain electrode.
  • the array substrate further includes a protective layer covering the conductive layer and the second metal layer.
  • the array substrate further includes a semiconductor layer provided corresponding to the first region of the substrate and between the first insulating layer and the conductive layer.
  • the embodiment of the present application also provides a method for manufacturing an array substrate, which includes the following steps:
  • S10 providing a substrate, the substrate having a first area, a second area, and a third area, the second area being located between the first area and the third area;
  • S20 Form a first metal layer on the entire surface of the substrate, and pattern the first metal layer to obtain a patterned first metal layer.
  • the patterned first metal layer includes A first metal member in the first region of the substrate and a second metal member provided in the third region of the substrate;
  • S50 sequentially forming a conductive layer covering the entire surface of the first insulating layer and the semiconductor layer and a second metal layer covering the entire surface;
  • S60 Provide a photomask, use the photomask to expose the conductive layer and the second metal layer, and go through a developer solution development and etching process, so that the conductive layer is in the first region And the second region form a first conductive part, the conductive layer forms a second conductive part in the third region; the second metal layer forms a third metal member in the first region, the second The metal layer forms a fourth metal member in the third area.
  • the photomask has a full display area, a half display area, and a reserved area.
  • the method further includes the following steps:
  • the photoresist layer After exposing the photoresist layer by using the photomask, the photoresist layer forms a first photoresist area corresponding to the full display area of the photomask, and the photoresist layer corresponds to the photomask The half display area forms a second photoresist area, and the photoresist layer forms a third photoresist area corresponding to the reserved area of the photomask;
  • S603 Remove the photoresist layer, the second metal layer, and the conductive layer in the first photoresist region, so that the semiconductor layer corresponding to the first region of the substrate is exposed; A portion of the first insulating layer corresponding to the second area and the third area of the substrate is exposed to form the patterned conductive layer;
  • S604 Remove the photoresist layer and the second metal layer of the second photoresist region, and expose the conductive layer corresponding to the first region and the second region of the substrate to form The first conductive part;
  • S605 Remove the photoresist layer of the third photoresist region, expose the second metal layer corresponding to the first region of the substrate to form the third metal member; The second metal layer in the third area of the substrate is exposed to form the fourth metal member.
  • the method further includes the following steps:
  • S70 preparing a protective layer covering the conductive layer and the second metal layer.
  • An embodiment of the present application also provides a display panel, the display panel includes the array substrate, and the array substrate includes:
  • a substrate having a first area, a second area, and a third area, the second area being located between the first area and the third area;
  • a first metal layer including a first metal member provided in the first region of the substrate and a second metal member provided in the third region of the substrate;
  • a first insulating layer, the first insulating layer covering the first metal layer and the substrate, and the first insulating layer is provided with a through hole corresponding to the third region;
  • the conductive layer is located on the side of the first insulating layer away from the first metal layer, and the conductive layer includes a first conductive portion disposed in the first region and the second region, and a first conductive portion disposed in the first region. At least part of the second conductive portion in the three regions is connected to the second metal member through the through hole;
  • a second metal layer includes a third metal member provided in the first region of the substrate and a fourth metal member provided in the third region of the substrate, the The fourth metal member is connected to the second conductive portion.
  • the array substrate has a display area and a non-display area, the non-display area includes a gate drive circuit area, and the gate drive circuit area has a first wiring and a second wiring. line;
  • the first area and the second area of the substrate correspond to the display area of the array substrate
  • the third area of the substrate corresponds to the gate drive circuit area in the non-display area of the array substrate;
  • the second metal member is the first wiring of the gate driving circuit area
  • the fourth metal member is the second wiring of the gate driving circuit area
  • the first metal member is a gate electrode and a scan line.
  • the third metal member is a source electrode and a drain electrode.
  • the array substrate further includes a protective layer covering the conductive layer and the second metal layer.
  • the conductive layer is made of indium tin oxide.
  • the display panel further includes a color filter substrate disposed opposite to the array substrate, and the array substrate is flush with the side of the color filter substrate to form a side binding area for The narrow frame design of the display panel is realized.
  • the side binding area includes:
  • a conductive film, one side of the conductive film is attached to the sides of the color filter substrate and the array substrate, and is electrically connected to the binding terminal on the array substrate;
  • a chip-on-chip film, the chip-on-chip film is attached to a side of the conductive film away from the color filter substrate and the array substrate;
  • the conductive adhesive is located between the chip on film and the conductive film, and is used to electrically connect the chip on film and the conductive film.
  • the conductive adhesive is anisotropic conductive adhesive.
  • the conductive film is made of silver.
  • the array substrate includes a substrate.
  • the substrate has a first region, a second region, and a third region.
  • the second area is located between the first area and the third area; a first metal layer, the first metal layer includes a first metal member provided in the first area of the substrate and a first metal member provided in the first area of the substrate.
  • the third region is provided with a through hole; a conductive layer is located on the side of the first insulating layer away from the first metal layer, and the conductive layer includes a conductive layer provided in the first region and the second region The first conductive portion and the second conductive portion provided in the third area, at least part of the second conductive portion is connected to the second metal member through the through hole; a second metal layer, the second metal
  • the layer includes a third metal member provided in the first region of the substrate and a fourth metal member provided in the third region of the substrate, the fourth metal member and the second conductive Part connection, reducing the overlapping length of the second conductive part when overlapping the second metal member and the fourth metal member, thereby reducing the first metal layer and the second metal layer The contact resistance between.
  • the halftone mask is used to realize the patterning process of the conductive layer and the patterning process of the second metal layer at the same time, which saves two masks and two exposure and development processes, and simplifies Manufacturing process of array substrate.
  • the display panel made of the array substrate provided by the embodiment of the present application can improve the problem that the display panel is prone to gradation lines, and improve the display quality of the display panel.
  • FIG. 1 is a schematic diagram of the structure of a gate driving circuit of a conventional display panel
  • FIG. 2A is a schematic structural diagram of an array substrate provided by an embodiment of the application.
  • FIG. 2B is a top view of the array substrate in FIG. 2A;
  • Figure 2C is a partial enlarged view of part I in Figure 2B;
  • 2D is a schematic structural diagram of a display area of an array substrate provided by an embodiment of the application.
  • FIG. 3 is a preparation flow chart of the array substrate provided by an embodiment of the application.
  • 4A to 4J are schematic diagrams of the process of preparing the array substrate shown in the flowchart shown in FIG. 3;
  • FIG. 5 is a schematic diagram of the structure of a display panel provided by an embodiment of the application.
  • FIG. 2A is a schematic structural diagram of an array substrate provided by an embodiment of the application; the array substrate includes:
  • a substrate 201 having a first area 201a, a second area 201b, and a third area 201c, and the second area 201b is located between the first area 201a and the third area 201c;
  • the first metal layer 202 includes a first metal member 2021 provided in the first region 201a of the substrate 201 and a first metal member 2021 provided in the third region 201c of the substrate 201 Second metal member 2022;
  • the conductive layer 204 is located on the side of the first insulating layer 203 away from the first metal layer 202.
  • the conductive layer 204 includes a first conductive portion disposed in the first region 201a and the second region 201b 2041 and the second conductive portion 2042 provided in the third region 201c, at least part of the second conductive portion 2042 is connected to the second metal member 2022 through the through hole 203a;
  • the second metal layer 205 includes a third metal member 2051 provided in the first region 201a of the substrate 201 and a third metal member 2051 provided in the third region 201c of the substrate 201
  • the fourth metal member 2052 is connected to the second conductive portion 2042 to reduce the contact resistance between the first metal layer 202 and the second metal layer 205.
  • the array substrate further includes a semiconductor layer 211 disposed corresponding to the first region 200a of the substrate 201 and between the first insulating layer 203 and the conductive layer 204, and the semiconductor layer includes an active layer 211a and ohmic contact layer 211b.
  • FIG. 2B is a top view of the array substrate in FIG. 2A.
  • the array substrate 200 has a display area 200a and a non-display area 200b.
  • the non-display area 200b includes a gate drive circuit area 206a.
  • the driving circuit area 206a has a first wiring 2061 and a second wiring 2062;
  • the first area 201a and the second area 201b of the substrate 201 correspond to the display area 200a of the array substrate 200;
  • the third area 201c of the substrate 201 corresponds to the gate driving circuit area 206a in the non-display area 200b of the array substrate 200;
  • the second metal member 2022 is the first trace 2061 of the gate driving circuit region 206a
  • the fourth metal member 2052 is the second trace 2062 of the gate driving circuit region 206a.
  • the first wiring 2061 is used for externally connecting the chip on film 2064 or printed circuit board, and transmits the signal to the gate driving circuit 2063 via the second wiring 2062 through the chip on film 2064 or the printed circuit board, so as to realize the connection Control of the grid.
  • FIG. 2C is a partial enlarged view of part I in FIG. 2B, and cut along A-A' in FIG. 2C to obtain a schematic structural diagram corresponding to the third region 201c as shown in FIG. 2A.
  • FIG. 2D is a schematic diagram of the structure of the display area of the array substrate provided by the embodiment of the application;
  • the array substrate has a plurality of data lines 207a, 207b and a plurality of scan lines 208a, 208b, two adjacent scans
  • a pixel area is formed between the lines 208a, 208b and the data lines 207a, 207b, and a thin film transistor and a pixel electrode 210 corresponding to the thin film transistor are respectively disposed above each pixel area.
  • each of the thin film transistors has a gate 209a, a source 209b, and a drain 209c.
  • the gate electrode 209a of the thin film transistor is electrically connected to the scan line 208a
  • the source electrode 209b of the thin film transistor is electrically connected to the data line 207a
  • the drain electrode 209c of the thin film transistor is electrically connected to the corresponding data line 207a.
  • the pixel electrode 210 is electrically connected.
  • the first metal member 2021 is the gate 209a and the scan line 208a
  • the third metal member 2051 is the source 209b and the drain 209c. Cut along B-B' in FIG. 2D to obtain a schematic diagram of the structure corresponding to the first area 200a and the second area 200b in FIG. 2A.
  • the array substrate 200 further includes a protective layer (not shown in the figure).
  • the protective layer covers the conductive layer 204 and the second metal layer 205 to protect the conductive layer 204 and the second metal layer 205.
  • the second metal layer 205 is protected from corrosion.
  • FIG. 3 is a preparation flow chart of the array substrate provided by the embodiment of the application; as shown in FIGS. 4A to 4J, which are schematic diagrams of the preparation process of the array substrate as shown in the flow chart in FIG.
  • a method for preparing an array substrate is provided, which includes the following steps:
  • S10 Provide a substrate 201.
  • the substrate 201 has a first area 201a, a second area 201b, and a third area 201c.
  • the second area 201b is located between the first area 201a and the third area 201c.
  • S20 forming a first metal layer on the entire surface of the substrate 201, and patterning the first metal layer to obtain a patterned first metal layer 202, the patterned first metal layer 202 It includes a first metal member 2021 provided in the first region 201a of the substrate 201 and a second metal member 2022 provided in the third region 201c of the substrate 201, as shown in FIG. 4B;
  • the semiconductor layer 211 includes an active layer 211a and an ohmic contact layer 211b;
  • S60 Provide a photomask, use the photomask to expose the conductive layer 204 and the second metal layer 205, and go through a developer solution development and etching process, so that the conductive layer 204 is in the
  • the first area 201b and the second area 201c form a first conductive portion 2041
  • the conductive layer 204 forms a second conductive portion 2042 in the third area 201c
  • the second metal layer 205 forms a second conductive portion 2042 in the first area.
  • 201a forms a third metal member 2051
  • the second metal layer 205 forms a fourth metal member 2052 in the third region 201c, as shown in FIG. 4J.
  • the photomask has a full display area, a half display area, and a reserved area.
  • step S60 it further includes the following steps:
  • the photoresist layer 213 After exposing the photoresist layer 213 by using the photomask, the photoresist layer 213 forms a first photoresist region 213a corresponding to the full display area of the photomask, and the photoresist layer 213 corresponds to The half-display area of the photomask forms a second photoresist area 213b, and the photoresist layer 213 forms a third photoresist area 213c corresponding to the reserved area of the photomask, as shown in FIG. 4G;
  • S603 Remove the photoresist layer 213, the second metal layer 205, and the conductive layer 204 of the first photoresist region 213a so as to correspond to all of the first region 201a of the substrate 201
  • the semiconductor layer 211 is exposed; the first insulating layer 203 corresponding to the second region 201b and the third region 201c of the substrate 201 is exposed to form the patterned conductive layer 204, as shown in FIG. Shown at 4H;
  • S605 Remove the photoresist layer of the third photoresist region 213c, and expose the second metal layer 205 corresponding to the first region 201a of the substrate 201 to form the third metal member 2051 The second metal layer 205 corresponding to the third region 201c of the substrate 201 is exposed to form the fourth metal member 2052, as shown in FIG. 4J.
  • the photomask is a halftone photomask; the conductive layer is made of indium tin oxide.
  • the photoresist layer 213 is removed by the ashing and drying process of the lighting resist, and a metal etching solution is used to remove the corresponding first photoresist region 213a and the second photoresist region 213a.
  • a metal etching solution is used to remove the conductive layer 204 corresponding to the first photoresist region 213a.
  • the method for preparing the array substrate uses a halftone photomask to expose the conductive layer 204 and the second metal layer 205, and the full display area of the photomask is used to form the first light.
  • the half-display region of the photomask is used to form a second photoresist region 213b, and the reserved region of the photomask is used to form a third photoresist region 213c.
  • the second photoresist region 213b, and the third photoresist region 213c are etched to form a gate electrode, a source electrode and a drain electrode in the first region 201a corresponding to the substrate 201;
  • the second region 201b of the substrate 201 forms a pixel electrode;
  • the first trace 2061 and the second trace 2062 are formed in the third region 201c corresponding to the substrate 201, saving two masks and two exposures
  • the development process simplifies the manufacturing process of the array substrate, and at the same time reduces the contact resistance between the first wiring 2061 and the second wiring 2062.
  • the method further includes the following steps:
  • S70 Prepare a protective layer covering the conductive layer 204 and the second metal layer 205 to protect the conductive layer 204 and the second metal layer 205 from corrosion.
  • FIG. 5 is a schematic structural diagram of a display panel provided by an embodiment of the present application; an embodiment of the present application also provides a display panel, and the display panel includes the array substrate 501.
  • the display panel also includes a color filter substrate 502 arranged opposite to the array substrate 501, and the array substrate 501 is provided with a polarizer 5011 and a backlight 5012 on a side away from the color filter substrate 502; the color filter The substrate 502 is provided with a polarizer 5021 on a side away from the array substrate 501; a sealant 503 and liquid crystal molecules 504 are provided between the array substrate 501 and the color filter substrate 502.
  • the side edges of the array substrate 501 and the color filter substrate 502 are flush to form a side binding area 505, and the side binding area 505 includes:
  • a conductive film 5051, one side of the conductive film 5051 is attached to the sides of the color filter substrate 502 and the array substrate 501, and is electrically connected to the binding terminal 5013 on the array substrate 501;
  • the chip on film 5052 is attached to a side of the conductive film 5051 away from the color filter substrate 502 and the array substrate 501.
  • the chip on film 5052 and the conductive film 5051 are electrically connected by conductive glue 5053, and the conductive glue 5053 is also in contact with the frame 5054 of the display panel to fix the color film substrate 502 and the array substrate 501;
  • the conductive adhesive 5053 is anisotropic conductive adhesive.
  • the conductive film 5051 is made of silver.
  • the display panel can avoid the problem of abnormal display caused by horizontal gradient lines when displaying images, and it is also conducive to the realization of a narrow frame design.
  • the array substrate 200 includes a substrate 201 having a first area 201a, a second area 201b, and a third area 201c.
  • the second area 201b is located between the first area 201a and the third area 201c;
  • the first metal layer 202 includes the first metal layer 202 disposed in the first area 201a of the substrate 201 A metal member 2021 and a second metal member 2022 disposed in the third region 201c of the substrate 201; a first insulating layer 203, the first insulating layer 203 covering the first metal layer and the second metal member 2022
  • the substrate 201, and the first insulating layer 203 is provided with a through hole 203a corresponding to the third region 201c;
  • the conductive layer 204 is located on the side of the first insulating layer 203 away from the first metal layer 202
  • the conductive layer 204 includes a first conductive portion 2041 disposed in the first region 201a and the
  • a halftone mask is used to realize the patterning process of the conductive layer 204 and the patterning process of the second metal layer 205 at the same time, saving two masks and two exposure and development processes.
  • the manufacturing process of the array substrate is simplified.
  • the display panel made of the array substrate provided by the embodiment of the present application can improve the problem that the display panel is prone to gradation lines, and improve the display quality of the display panel.

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Abstract

本申请公开一种阵列基板及制备方法、显示面板；所述阵列基板包括：衬底、第一金属层、第一绝缘层、导电层，以及第二金属层；第一金属层与第二金属层之间通过第一绝缘层上的通孔以及导电层的第二导电部实现电连接，以降低第一金属层与第二金属层之间的接触阻抗，改善显示面板易出现渐变线的问题，提高显示面板的显示品质。

Description

阵列基板及其制备方法、显示面板 技术领域
本申请涉及显示技术领域，特别涉及一种阵列基板及其制备方法、显示面板。
 背景技术
在显示面板的制备过程中，阵列基板的第二金属层、保护层、像素电极层总共需三张曝光掩膜板，通过三次曝光、显影等工艺做成，制作工艺复杂、成本高。此外，为实现窄边框设计，显示面板多采用栅极驱动电路（Gate on Array，GOA)制备于阵列基板上的结构，因此会在阵列基板上形成栅极驱动电路。请参阅图1，其为现有的显示面板的栅极驱动电路的结构示意图，第一金属层101与第二金属层102通过导电层103实现表面搭接，具体地，所述导电层103通过栅极绝缘层104上的过孔及保护层105上的过孔实现所述第一金属层101与所述第二金属层102的电连接，所述第一金属层101与所述第二金属层102之间会存在较大的转接接触阻抗，且所述导电层103在负电压下易发生腐蚀，造成所述第一金属层101与所述第二金属层102搭接不良，导致所述显示面板出现渐变线、画面显示异常的问题。
 技术问题
本申请实施例提供一种阵列基板及其制备方法、显示面板，可以降低栅极驱动电路的接触阻抗，改善显示面板显示时易出现渐变线的问题，提高显示品质，且减少阵列基板制备过程中所需的光罩数目。
 技术解决方案
本申请实施例提供一种阵列基板，所述阵列基板包括：
衬底，所述衬底具有第一区域、第二区域以及第三区域，所述第二区域位于所述第一区域和所述第三区域之间；
第一金属层，所述第一金属层包括设置于所述衬底的所述第一区域的第一金属构件和设置于所述衬底的所述第三区域的第二金属构件；
第一绝缘层，所述第一绝缘层覆盖所述第一金属层及所述衬底，且所述第一绝缘层在对应所述第三区域处设置有通孔；
导电层，位于所述第一绝缘层远离所述第一金属层的一侧，所述导电层包括设置于所述第一区域和所述第二区域的第一导电部和设置于所述第三区域的第二导电部，至少部分所述第二导电部通过所述通孔与所述第二金属构件连接；
第二金属层，所述第二金属层包括设置于所述衬底的所述第一区域的第三金属构件和设置于所述衬底的所述第三区域的第四金属构件，所述第四金属构件与所述第二导电部连接。
在所述的阵列基板中，所述阵列基板具有一显示区与非显示区，所述非显示区包括一栅极驱动电路区，所述栅极驱动电路区具有第一走线和第二走线；
所述衬底的所述第一区域与所述第二区域对应所述阵列基板的所述显示区；
所述衬底的所述第三区域对应所述阵列基板的所述非显示区内的所述栅极驱动电路区；
所述第二金属构件为所述栅极驱动电路区的所述第一走线，所述第四金属构件为所述栅极驱动电路区的所述第二走线。
在所述的阵列基板中，所述第一金属构件为栅极和扫描线。
在所述的阵列基板中，所述第三金属构件为源极与漏极。
在所述的阵列基板中，所述阵列基板还包括保护层，所述保护层覆盖所述导电层及所述第二金属层。
在所述的阵列基板中，所述阵列基板还包括对应所述衬底的所述第一区域设置且在所述第一绝缘层与所述导电层之间的半导体层。
本申请实施例还提供一种阵列基板的制备方法，包括如下步骤：
S10：提供一衬底，所述衬底具有第一区域、第二区域以及第三区域，所述第二区域位于所述第一区域和所述第三区域之间；
S20：于所述衬底表面形成整面的第一金属层，并对所述第一金属层进行图形化，得到图形化的第一金属层，所述图形化的第一金属层包括设置于所述衬底的所述第一区域的第一金属构件和设置于所述衬底的所述第三区域的第二金属构件；
S30：形成覆盖所述第一金属层及所述衬底的第一绝缘层，且所述第一绝缘层在对应所述第三区域制备有通孔；
S40：于所述第一区域的所述第一绝缘层远离所述衬底的表面形成半导体层；
S50：依次形成覆盖所述第一绝缘层和所述半导体层的整面的导电层和整面的第二金属层；
S60：提供一光罩，利用所述光罩对所述导电层及所述第二金属层进行曝光处理，并经过显影液显影和刻蚀工艺，以使所述导电层在所述第一区域和所述第二区域形成第一导电部，所述导电层在所述第三区域形成第二导电部；所述第二金属层在所述第一区域形成第三金属构件，所述第二金属层在所述第三区域形成第四金属构件。
在所述的阵列基板的制备方法中，所述光罩具有全显区、半显区及保留区，在步骤S60中，还包括如下步骤：
S601：在所述第二金属层表面制备光阻层；
S602：利用所述光罩对所述光阻层进行曝光后，所述光阻层对应所述光罩的所述全显区形成第一光阻区，所述光阻层对应所述光罩的所述半显区形成第二光阻区，所述光阻层对应所述光罩的所述保留区形成第三光阻区；
S603：去除所述第一光阻区的所述光阻层、所述第二金属层及所述导电层，以使对应所述衬底的所述第一区域的所述半导体层外露；使对应所述衬底的所述第二区域和所述第三区域的部分所述第一绝缘层外露，形成图形化的所述导电层；
S604：去除所述第二光阻区的所述光阻层及所述第二金属层，使对应所述衬底的所述第一区域和所述第二区域的所述导电层外露，形成所述第一导电部；
S605：去除所述第三光阻区的所述光阻层，使对应所述衬底的所述第一区域的所述第二金属层外露，形成所述第三金属构件；使对应所述衬底的所述第三区域的所述第二金属层外露，形成所述第四金属构件。
在所述的阵列基板的制备方法中，在所述步骤S60后，还包括如下步骤：
S70：制备覆盖所述导电层及所述第二金属层的保护层。
本申请实施例还提供一种显示面板，所述显示面板包括所述阵列基板，所述阵列基板包括：
衬底，所述衬底具有第一区域、第二区域以及第三区域，所述第二区域位于所述第一区域和所述第三区域之间；
第一金属层，所述第一金属层包括设置于所述衬底的所述第一区域的第一金属构件和设置于所述衬底的所述第三区域的第二金属构件；
第一绝缘层，所述第一绝缘层覆盖所述第一金属层及所述衬底，且所述第一绝缘层在对应所述第三区域处设置有通孔；
导电层，位于所述第一绝缘层远离所述第一金属层的一侧，所述导电层包括设置于所述第一区域和所述第二区域的第一导电部和设置于所述第三区域的第二导电部，至少部分所述第二导电部通过所述通孔与所述第二金属构件连接；
第二金属层，所述第二金属层包括设置于所述衬底的所述第一区域的第三金属构件和设置于所述衬底的所述第三区域的第四金属构件，所述第四金属构件与所述第二导电部连接。
在所述的显示面板中，所述阵列基板具有一显示区与非显示区，所述非显示区包括一栅极驱动电路区，所述栅极驱动电路区具有第一走线和第二走线；
所述衬底的所述第一区域与所述第二区域对应所述阵列基板的所述显示区；
所述衬底的所述第三区域对应所述阵列基板的所述非显示区内的所述栅极驱动电路区；
所述第二金属构件为所述栅极驱动电路区的所述第一走线，所述第四金属构件为所述栅极驱动电路区的所述第二走线。
在所述的显示面板中，所述第一金属构件为栅极和扫描线。
在所述的显示面板中，所述第三金属构件为源极与漏极。
在所述的显示面板中，所述阵列基板还包括保护层，所述保护层覆盖所述导电层及所述第二金属层。
在所述的显示面板中，所述阵列基板还包括对应所述衬底的所述第一区域设置且在所述第一绝缘层与所述导电层之间的半导体层。
在所述的显示面板中，所述导电层的制备材料为氧化铟锡。
在所述的显示面板中，所述显示面板还包括与所述阵列基板相对设置的彩膜基板，所述阵列基板与所述彩膜基板的侧边平齐构成侧面绑定区，以用于实现所述显示面板的窄边框设计。
在所述的显示面板中，所述侧面绑定区包括：
导电膜，所述导电膜一侧贴合在所述彩膜基板及所述阵列基板的侧边，并与所述阵列基板上的绑定端子电连接；
覆晶薄膜，所述覆晶薄膜贴合在所述导电膜远离所述彩膜基板及所述阵列基板的一侧；
导电胶，位于所述覆晶薄膜与所述导电膜之间，用于电连接所述覆晶薄膜与所述导电膜。
在所述的显示面板中，所述导电胶为异方性导电胶。
在所述的显示面板中，所述导电膜的制备材料为银。
 有益效果
相较于现有技术，本申请实施例提供的阵列基板及制备方法、显示面板，所述阵列基板包括：衬底，所述衬底具有第一区域、第二区域以及第三区域，所述第二区域位于所述第一区域和所述第三区域之间；第一金属层，所述第一金属层包括设置于所述衬底的所述第一区域的第一金属构件和设置于所述衬底的所述第三区域的第二金属构件；第一绝缘层，所述第一绝缘层覆盖所述第一金属层及所述衬底，且所述第一绝缘层在对应所述第三区域处设置有通孔；导电层，位于所述第一绝缘层远离所述第一金属层的一侧，所述导电层包括设置于所述第一区域和所述第二区域的第一导电部和设置于所述第三区域的第二导电部，至少部分所述第二导电部通过所述通孔与所述第二金属构件连接；第二金属层，所述第二金属层包括设置于所述衬底的所述第一区域的第三金属构件和设置于所述衬底的所述第三区域的第四金属构件，所述第四金属构件与所述第二导电部连接，减小了所述第二导电部在搭接所述第二金属构件与所述第四金属构件时的搭接长度，从而降低了所述第一金属层与所述第二金属层之间的接触阻抗。在阵列基板的制备过程中，利用半色调光罩同时实现所述导电层的图案化制程与所述第二金属层的图案化制程，节省了两道光罩及两道曝光显影的制程，简化了阵列基板的制作工艺。采用本申请实施例提供的阵列基板制成的显示面板，可改善所述显示面板易出现渐变线的问题，提高所述显示面板的显示品质。
 附图说明
图1为现有的显示面板的栅极驱动电路的结构示意图；
图2A为本申请实施例提供的阵列基板的结构示意图；
图2B为图2A中阵列基板的俯视图；
图2C为图2B中I部位的局部放大图；
图2D为本申请实施例提供的阵列基板的显示区的结构示意图；
图3为本申请实施例提供的阵列基板的制备流程图；
图4A~图4J为图3中所示流程图制备阵列基板的过程示意图；
图5为本申请实施例提供的显示面板结构示意图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
具体的，请参阅图2A，其为本申请实施例提供的阵列基板的结构示意图；所述阵列基板包括：
衬底201，所述衬底201具有第一区域201a、第二区域201b以及第三区域201c，所述第二区域201b位于所述第一区域201a和所述第三区域201c之间；
第一金属层202，所述第一金属层202包括设置于所述衬底201的所述第一区域201a的第一金属构件2021和设置于所述衬底201的所述第三区域201c的第二金属构件2022；
第一绝缘层203，所述第一绝缘层203覆盖所述第一金属层202及所述衬底201，且所述第一绝缘层203在对应所述第三区域201c处设置有通孔203a；
导电层204，位于所述第一绝缘层203远离所述第一金属层202的一侧，所述导电层204包括设置于所述第一区域201a和所述第二区域201b的第一导电部2041和设置于所述第三区域201c的第二导电部2042，至少部分所述第二导电部2042通过所述通孔203a与所述第二金属构件2022连接；
第二金属层205，所述第二金属层205包括设置于所述衬底201的所述第一区域201a的第三金属构件2051和设置于所述衬底201的所述第三区域201c的第四金属构件2052，所述第四金属构件2052与所述第二导电部2042连接，以降低所述第一金属层202与所述第二金属层205之间的接触阻抗。
所述阵列基板还包括对应所述衬底201的所述第一区域200a设置且在所述第一绝缘层203与所述导电层204之间的半导体层211，所述半导体层包括有源层211a和欧姆接触层211b。
请参阅图2B，其为图2A中阵列基板的俯视图，所述阵列基板200具有一显示区200a与非显示区200b，所述非显示区200b包括一栅极驱动电路区206a，所述栅极驱动电路区206a具有第一走线2061和第二走线2062；
请继续参阅图2A和图2B，所述衬底201的所述第一区域201a与所述第二区域201b对应所述阵列基板200的所述显示区200a；
所述衬底201的所述第三区域201c对应所述阵列基板200的所述非显示区200b内的所述栅极驱动电路区206a；
所述第二金属构件2022为所述栅极驱动电路区206a的所述第一走线2061，所述第四金属构件2052为所述栅极驱动电路区206a的所述第二走线2062。
所述第一走线2061用于外接覆晶薄膜2064或印刷电路板，并通过覆晶薄膜2064或印刷电路板将信号经所述第二走线2062传输至栅极驱动电路2063，以实现对栅极的控制。
请参阅图2C，其为图2B中I部位的局部放大图，沿图2C中的A-A’剖切，即可得到对应如图2A中所述第三区域201c的结构示意图。
请参阅图2D，其为本申请实施例提供的阵列基板的显示区的结构示意图；所述阵列基板具有多条数据线207a、207b及多条扫描线208a、208b，相邻的两所述扫描线208a、208b以及所述数据线207a、207b之间构成一个像素区域，而每一像素区域上方分别配置有一个薄膜晶体管以及一个对应于所述薄膜晶体管的像素电极210。以所述扫描线208a所控制的多个所述薄膜晶体管为例进行说明，每一个所述薄膜晶体管都具有一栅极209a、一源极209b以及一漏极209c。其中，所述薄膜晶体管的栅极209a与所述扫描线208a电性连接，所述薄膜晶体管的源极209b与所述数据线207a电性连接，所述薄膜晶体管的漏极209c与对应的所述像素电极210电性连接。所述第一金属构件2021为所述栅极209a和扫描线208a，所述第三金属构件2051为源极209b与漏极209c。沿图2D中的B-B’剖切，即可得到对应如图2A中的所述第一区域200a与所述第二区域200b的结构示意图。
在一些实施例中，所述阵列基板200还包括保护层（图中未示出），所述保护层覆盖所述导电层204及所述第二金属层205，以保护所述导电层204及所述第二金属层205免受腐蚀。
请参阅图3，其为本申请实施例提供的阵列基板的制备流程图；如图4A~图4J所示，其为图3中所示流程图制备阵列基板的过程示意图，本申请实施例还提供一种阵列基板的制备方法，包括如下步骤：
S10：提供一衬底201，所述衬底201具有第一区域201a、第二区域201b以及第三区域201c，所述第二区域201b位于所述第一区域201a和所述第三区域201c之间，如图4A所示；
S20：于所述衬底201表面形成整面的第一金属层，并对所述第一金属层进行图形化，得到图形化的第一金属层202，所述图形化的第一金属层202包括设置于所述衬底201的所述第一区域201a的第一金属构件2021和设置于所述衬底201的所述第三区域201c的第二金属构件2022，如图4B所示；
S30：形成覆盖所述第一金属层202及所述衬底201的第一绝缘层203，且所述第一绝缘层203在对应所述第三区域201c制备有通孔203a，如图4C所示；
S40：于所述第一区域201a的所述第一绝缘层203远离所述衬底201的表面形成半导体层211，如图4D所示，所述半导体层211包括有源层211a和欧姆接触层211b；
S50：依次形成覆盖所述第一绝缘层203和所述半导体层211的整面的导电层204和整面的第二金属层205，如图4E所示；
S60：提供一光罩，利用所述光罩对所述导电层204及所述第二金属层205进行曝光处理，并经过显影液显影和刻蚀工艺，以使所述导电层204在所述第一区域201b和所述第二区域201c形成第一导电部2041，所述导电层204在所述第三区域201c形成第二导电部2042；所述第二金属层205在所述第一区域201a形成第三金属构件2051，所述第二金属层205在所述第三区域201c形成第四金属构件2052，如图4J所示。
所述光罩具有全显区、半显区及保留区，在步骤S60中，还包括如下步骤：
S601：在所述第二金属层205表面制备光阻层213，如图4F所示；
S602：利用所述光罩对所述光阻层213进行曝光后，所述光阻层213对应所述光罩的所述全显区形成第一光阻区213a，所述光阻层213对应所述光罩的所述半显区形成第二光阻区213b，所述光阻层213对应所述光罩的所述保留区形成第三光阻区213c，如图4G所示；
S603：去除所述第一光阻区213a的所述光阻层213、所述第二金属层205及所述导电层204，以使对应所述衬底201的所述第一区域201a的所述半导体层211外露；使对应所述衬底201的所述第二区域201b和所述第三区域201c的部分所述第一绝缘层203外露，形成图形化的所述导电层204，如图4H所示；
S604：去除所述第二光阻区213b的所述光阻层213及所述第二金属层205，使对应所述衬底201的所述第一区域201a和所述第二区域201b的所述导电层204外露，形成所述第一导电部2041，如图4I所示；
S605：去除所述第三光阻区213c的所述光阻层，使对应所述衬底201的所述第一区域201a的所述第二金属层205外露，形成所述第三金属构件2051；使对应所述衬底201的所述第三区域201c的所述第二金属层205外露，形成所述第四金属构件2052，如图4J所示。
所述光罩为半色调光罩；所述导电层的制备材料为氧化铟锡。
在所述步骤S603、所述步骤S604及所述步骤S605中，采光阻灰化和干燥工艺去除所述光阻层213，采用金属蚀刻液去除对应所述第一光阻区213a及所述第二光阻区213b的所述第二金属层205，采用氧化铟锡蚀刻液去除对应所述第一光阻区213a的所述导电层204。
本申请实施例提供的阵列基板的制备方法通过使用半色调光罩对所述导电层204及所述第二金属层205进行曝光处理，利用所述光罩的所述全显区形成第一光阻区213a，利用所述光罩的所述半显区形成第二光阻区213b，利用所述光罩的所述保留区形成第三光阻区213c，分别对所述第一光阻区213a、所述第二光阻区213b、所述第三光阻区213c进行蚀刻，在对应所述衬底201的所述第一区域201a形成栅极、源极及漏极；在对应所述衬底201的所述第二区域201b形成像素电极；在对应所述衬底201的所述第三区域201c形成第一走线2061及第二走线2062，节省了两道光罩及两道曝光显影的制程，简化了阵列基板的制作工艺，同时也降低了所述第一走线2061及所述第二走线2062之间的接触阻抗。
在所述的阵列基板的制备方法中，在所述步骤S60后，还包括如下步骤：
S70：制备覆盖所述导电层204及所述第二金属层205的保护层，以保护所述导电层204及所述第二金属层205免受腐蚀。
请参阅图5，其为本申请实施例提供的显示面板结构示意图；本申请实施例还提供一种显示面板，所述显示面板包括所述阵列基板501。
所述显示面板还包括与所述阵列基板501相对设置的彩膜基板502，所述阵列基板501在远离所述彩膜基板502的一侧设置有偏光片5011及背光源5012；所述彩膜基板502在远离所述阵列基板501的一侧设置有偏光片5021；所述阵列基板501与所述彩膜基板502之间设置有框胶503及液晶分子504。
所述阵列基板501与所述彩膜基板502的侧边平齐构成侧面绑定区505，所述侧面绑定区505包括：
导电膜5051，所述导电膜5051一侧贴合在所述彩膜基板502及所述阵列基板501的侧边，并与所述阵列基板501上的绑定端子5013电连接；
覆晶薄膜5052，所述覆晶薄膜5052贴合在所述导电膜5051远离所述彩膜基板502及所述阵列基板501的一侧。
所述覆晶薄膜5052与所述导电膜5051通过导电胶5053实现电连接，所述导电胶5053还与所述显示面板的边框5054相接触，以固定所述彩膜基板502及所述阵列基板501；所述导电胶5053为异方性导电胶。
所述导电膜5051的制备材料为银。
由于所述阵列基板501中所述第一金属层及所述第二金属层在所述非显示区直接通过所述导电层实现电连接，减小接触阻抗的同时也增大了侧面绑定区的接触面积，故所述显示面板可避免显示画面时出现水平渐变线导致显示异常的问题，也有利于实现窄边框设计。
本申请实施例提供的阵列基板及制备方法、显示面板，所述阵列基板200包括：衬底201，所述衬底201具有第一区域201a、第二区域201b以及第三区域201c，所述第二区域201b位于所述第一区域201a和所述第三区域201c之间；第一金属层202，所述第一金属层202包括设置于所述衬底201的所述第一区域201a的第一金属构件2021和设置于所述衬底201的所述第三区域201c的第二金属构件2022；第一绝缘层203，所述第一绝缘层203覆盖所述第一金属层及202所述衬底201，且所述第一绝缘层203在对应所述第三区域201c处设置有通孔203a；导电层204，位于所述第一绝缘层203远离所述第一金属层202的一侧，所述导电层204包括设置于所述第一区域201a和所述第二区域201b的第一导电部2041和设置于所述第三区域201c的第二导电部2042，至少部分所述第二导电部2042通过所述通孔203a与所述第二金属构件2022连接；第二金属层205，所述第二金属层205包括设置于所述衬底201的所述第一区域201a的第三金属构件2051和设置于所述衬底201的所述第三区域201c的第四金属构件2052，所述第四金属构件2052与所述第二导电部2042连接，减小了所述第二导电部2042在搭接所述第二金属构件2022与所述第四金属构件2052时的搭接长度，从而降低了所述第一金属层202与所述第二金属层205之间的接触阻抗。在阵列基板的制备过程中，利用半色调光罩同时实现所述导电层204的图案化制程与所述第二金属层205的图案化制程，节省了两道光罩及两道曝光显影的制程，简化了阵列基板的制作工艺。采用本申请实施例提供的阵列基板制成的显示面板，可改善所述显示面板易出现渐变线的问题，提高所述显示面板的显示品质。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的阵列基板及制备方法、显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种阵列基板，其中，所述阵列基板包括：
    衬底，所述衬底具有第一区域、第二区域以及第三区域，所述第二区域位于所述第一区域和所述第三区域之间；
    第一金属层，所述第一金属层包括设置于所述衬底的所述第一区域的第一金属构件和设置于所述衬底的所述第三区域的第二金属构件；
    第一绝缘层，所述第一绝缘层覆盖所述第一金属层及所述衬底，且所述第一绝缘层在对应所述第三区域处设置有通孔；
    导电层，位于所述第一绝缘层远离所述第一金属层的一侧，所述导电层包括设置于所述第一区域和所述第二区域的第一导电部和设置于所述第三区域的第二导电部，至少部分所述第二导电部通过所述通孔与所述第二金属构件连接；
    第二金属层，所述第二金属层包括设置于所述衬底的所述第一区域的第三金属构件和设置于所述衬底的所述第三区域的第四金属构件，所述第四金属构件与所述第二导电部连接。
  2. 根据权利要求1所述的阵列基板，其中，所述阵列基板具有一显示区与非显示区，所述非显示区包括一栅极驱动电路区，所述栅极驱动电路区具有第一走线和第二走线；
    所述衬底的所述第一区域与所述第二区域对应所述阵列基板的所述显示区；
    所述衬底的所述第三区域对应所述阵列基板的所述非显示区内的所述栅极驱动电路区；
    所述第二金属构件为所述栅极驱动电路区的所述第一走线，所述第四金属构件为所述栅极驱动电路区的所述第二走线。
  3. 根据权利要求1所述的阵列基板，其中，所述第一金属构件为栅极和扫描线。
  4. 根据权利要求1所述的阵列基板，其中，所述第三金属构件为源极与漏极。
  5. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括保护层，所述保护层覆盖所述导电层及所述第二金属层。
  6. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括对应所述衬底的所述第一区域设置且在所述第一绝缘层与所述导电层之间的半导体层。
  7. 一种阵列基板的制备方法，其中，包括如下步骤：
    S10：提供一衬底，所述衬底具有第一区域、第二区域以及第三区域，所述第二区域位于所述第一区域和所述第三区域之间；
    S20：于所述衬底表面形成整面的第一金属层，并对所述第一金属层进行图形化，得到图形化的第一金属层，所述图形化的第一金属层包括设置于所述衬底的所述第一区域的第一金属构件和设置于所述衬底的所述第三区域的第二金属构件；
    S30：形成覆盖所述第一金属层及所述衬底的第一绝缘层，且所述第一绝缘层在对应所述第三区域制备有通孔；
    S40：于所述第一区域的所述第一绝缘层远离所述衬底的表面形成半导体层；
    S50：依次形成覆盖所述第一绝缘层和所述半导体层的整面的导电层和整面的第二金属层；
    S60：提供一光罩，利用所述光罩对所述导电层及所述第二金属层进行曝光处理，并经过显影液显影和刻蚀工艺，以使所述导电层在所述第一区域和所述第二区域形成第一导电部，所述导电层在所述第三区域形成第二导电部；所述第二金属层在所述第一区域形成第三金属构件，所述第二金属层在所述第三区域形成第四金属构件。
  8. 根据权利要求7所述的制备方法，其中，所述光罩具有全显区、半显区及保留区，在步骤S60中，还包括如下步骤：
    S601：在所述第二金属层表面制备光阻层；
    S602：利用所述光罩对所述光阻层进行曝光后，所述光阻层对应所述光罩的所述全显区形成第一光阻区，所述光阻层对应所述光罩的所述半显区形成第二光阻区，所述光阻层对应所述光罩的所述保留区形成第三光阻区；
    S603：去除所述第一光阻区的所述光阻层、所述第二金属层及所述导电层，以使对应所述衬底的所述第一区域的所述半导体层外露；使对应所述衬底的所述第二区域和所述第三区域的部分所述第一绝缘层外露，形成图形化的所述导电层；
    S604：去除所述第二光阻区的所述光阻层及所述第二金属层，使对应所述衬底的所述第一区域和所述第二区域的所述导电层外露，形成所述第一导电部；
    S605：去除所述第三光阻区的所述光阻层，使对应所述衬底的所述第一区域的所述第二金属层外露，形成所述第三金属构件；使对应所述衬底的所述第三区域的所述第二金属层外露，形成所述第四金属构件。
  9. 根据权利要求7所述的制备方法，其中，在所述步骤S60后，还包括如下步骤：
    S70：制备覆盖所述导电层及所述第二金属层的保护层。
  10. 一种显示面板，其中，包括如权利要求1所述的阵列基板，所述阵列基板包括：
    衬底，所述衬底具有第一区域、第二区域以及第三区域，所述第二区域位于所述第一区域和所述第三区域之间；
    第一金属层，所述第一金属层包括设置于所述衬底的所述第一区域的第一金属构件和设置于所述衬底的所述第三区域的第二金属构件；
    第一绝缘层，所述第一绝缘层覆盖所述第一金属层及所述衬底，且所述第一绝缘层在对应所述第三区域处设置有通孔；
    导电层，位于所述第一绝缘层远离所述第一金属层的一侧，所述导电层包括设置于所述第一区域和所述第二区域的第一导电部和设置于所述第三区域的第二导电部，至少部分所述第二导电部通过所述通孔与所述第二金属构件连接；
    第二金属层，所述第二金属层包括设置于所述衬底的所述第一区域的第三金属构件和设置于所述衬底的所述第三区域的第四金属构件，所述第四金属构件与所述第二导电部连接。
  11. 根据权利要求10所述的显示面板，其中，所述阵列基板具有一显示区与非显示区，所述非显示区包括一栅极驱动电路区，所述栅极驱动电路区具有第一走线和第二走线；
    所述衬底的所述第一区域与所述第二区域对应所述阵列基板的所述显示区；
    所述衬底的所述第三区域对应所述阵列基板的所述非显示区内的所述栅极驱动电路区；
    所述第二金属构件为所述栅极驱动电路区的所述第一走线，所述第四金属构件为所述栅极驱动电路区的所述第二走线。
  12. 根据权利要求10所述的显示面板，其中，所述第一金属构件为栅极和扫描线。
  13. 根据权利要求10所述的显示面板，其中，所述第三金属构件为源极与漏极。
  14. 根据权利要求10所述的显示面板，其中，所述阵列基板还包括保护层，所述保护层覆盖所述导电层及所述第二金属层。
  15. 根据权利要求10所述的显示面板，其中，所述阵列基板还包括对应所述衬底的所述第一区域设置且在所述第一绝缘层与所述导电层之间的半导体层。
  16. 根据权利要求10所述的显示面板，其中，所述导电层的制备材料为氧化铟锡。
  17. 根据权利要求10所述的显示面板，其中，所述显示面板还包括与所述阵列基板相对设置的彩膜基板，所述阵列基板与所述彩膜基板的侧边平齐构成侧面绑定区，以用于实现所述显示面板的窄边框设计。
  18. 根据权利要求17所述的显示面板，其中，所述侧面绑定区包括：
    导电膜，所述导电膜一侧贴合在所述彩膜基板及所述阵列基板的侧边，并与所述阵列基板上的绑定端子电连接；
    覆晶薄膜，所述覆晶薄膜贴合在所述导电膜远离所述彩膜基板及所述阵列基板的一侧；
    导电胶，位于所述覆晶薄膜与所述导电膜之间，用于电连接所述覆晶薄膜与所述导电膜。
  19. 根据权利要求18所述的显示面板，其中，所述导电胶为异方性导电胶。
  20. 根据权利要求18所述的显示面板，其中，所述导电膜的制备材料为银。
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