WO2020143099A1 - 显示面板走线结构及其制作方法 - Google Patents

显示面板走线结构及其制作方法 Download PDF

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Publication number
WO2020143099A1
WO2020143099A1 PCT/CN2019/075510 CN2019075510W WO2020143099A1 WO 2020143099 A1 WO2020143099 A1 WO 2020143099A1 CN 2019075510 W CN2019075510 W CN 2019075510W WO 2020143099 A1 WO2020143099 A1 WO 2020143099A1
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WIPO (PCT)
Prior art keywords
fan
signal line
out signal
area
display
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PCT/CN2019/075510
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English (en)
French (fr)
Inventor
郝思坤
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020143099A1 publication Critical patent/WO2020143099A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present invention relates to the field of display technology, and in particular to a wiring structure of a display panel and a manufacturing method thereof.
  • LCD Liquid crystal display
  • PDAs personal digital assistants
  • digital cameras computer screens or notebook computer screens, etc.
  • the working principle of the LCD display device is to use the optical rotation and birefringence of the liquid crystal to control the rotation of the liquid crystal by voltage, so that the linearly polarized light passing through the lower polarizer rotates accordingly, from the upper polarizer (the polarization direction of the upper polarizer) Vertical), so that the upper and lower polarizers plus the liquid crystal cell function as an optical switch. Therefore, a polarizer must be attached to the upper and lower sides of the LCD panel.
  • the liquid crystal display panel has a display area and a fan-out area. Multiple pixels are arranged in the display area to form a pixel array, and fan-out traces are provided in the fan-out area. Each pixel includes a thin film transistor and a pixel electrode connected to the thin film transistor, and the thin film transistor of each pixel is electrically connected to a scanning line and a data line. Generally, these scan lines and data lines are collectively referred to as display signal lines. Each display signal line extends from the display area to the fan-out area, and passes through the fan-out wiring and the driver chip (driver) IC) electrically connected to receive drive signals for screen display.
  • driver driver
  • the line width of the display signal line formed in the display area after the photolithography process is narrower than the line width of the fan-out signal line formed in the fan-out area, between each other
  • the difference can reach 2-3um.
  • the main reason for this kind of bad is that: from the layout point of view, the display signal lines of the display area are relatively sparse, and the fan-out signal lines of the fan-out area are relatively dense.
  • the photoresist between the signal lines is exposed, and the photoresist on the signal line is not exposed. Taking a positive photoresist as an example, the exposed photoresist is denatured Developed off.
  • the photoresist between the signal lines is more difficult to be developed due to the very dense wiring of the fan-out signal lines in the fan-out area, making the width of the fan-out signal lines relatively large, and from the perspective of light intensity distribution .
  • the fan-out signal line is very dense, so that the overall light intensity received by the fan-out area during exposure is small, and accordingly, the light intensity received by the photoresist between the fan-out signal lines in the fan-out area is relatively weak.
  • the photoresist developed by exposure is relatively small, making the width of the signal line in the fan-out area relatively large.
  • An object of the present invention is to provide a wiring structure for a display panel, which can improve the difference in line width between the fan-out signal line and the display signal line, and improve the display quality of the display panel.
  • the object of the present invention is also to provide a manufacturing method of a display panel wiring structure, which can improve the line width difference between the fan-out signal line and the display signal line, and improve the display quality of the display panel.
  • the present invention provides a display panel wiring structure, including a substrate, the substrate includes a fan-out area, and the fan-out area is provided with a plurality of fan-out signal lines arranged in sequence at intervals;
  • a hollow area is formed inside each fan-out signal line or a plurality of serrated grooves arranged in sequence are formed on both edges of each fan-out signal line.
  • the substrate also includes a display area connected to the fan-out area.
  • the display area is provided with a plurality of display signal lines arranged in sequence at intervals. Each display signal line is electrically connected to a fan-out signal line; adjacent The spacing between the two display signal lines is greater than the spacing between the two adjacent fan-out signal lines.
  • a hollow area is formed inside each fan-out signal line, and the hollow area in each fan-out signal line extends from one edge of the fan-out signal line to the other end edge of the fan-out signal line.
  • the material of the fan-out signal line is one or a combination of molybdenum, titanium, copper and aluminum.
  • Each fan-out signal line is electrically connected to the driving chip.
  • the invention provides a method for manufacturing a display panel wiring structure, which includes the following steps:
  • Step S1 Provide a substrate, the substrate includes a fan-out area;
  • Step S2 forming a conductive film and a photoresist film on the fan-out area in sequence
  • Step S3 providing a photomask, the photomask includes a light-transmitting area and a non-transparent area;
  • the light-transmitting area corresponds to the interval between multiple fan-out signal lines to be formed and the hollow area inside each fan-out signal line is set or corresponds to the interval between multiple fan-out signal lines to be formed and each fan Set the position of the sawtooth groove on both sides of the signal line;
  • the non-transparent area is provided with a non-transparent area corresponding to the position of the fan-out signal line to be formed;
  • Step S4 Expose and develop the photoresist film through the photomask to obtain a photoresist pattern
  • Step S5. Etching the conductive film with the photoresist pattern as a shield. After the etching is completed, the photoresist pattern is removed to obtain a plurality of fan-out signal lines arranged in sequence in the fan-out area, and each one The fan-out signal lines are all formed with hollowed-out areas or a plurality of sequentially arranged serrated grooves are formed on both edges of each fan-out signal line.
  • the substrate further includes a display area adjacent to the fan-out area;
  • the conductive film and the photoresist film are also formed on the display area;
  • the light-transmitting area is also set corresponding to the interval between the multiple display signal lines to be formed, and the non-light-transmitting area is also set corresponding to the position where the multiple display signal lines are to be formed;
  • step S5 a plurality of display signal lines arranged at intervals in the display area are also obtained, and each display signal line is electrically connected to a fan-out signal line correspondingly;
  • the spacing between two adjacent display signal lines is greater than the spacing between the two adjacent fan-out signal lines.
  • the hollow area in each fan-out signal line extends from one edge of the fan-out signal line to the other end edge of the fan-out signal line.
  • the material of the fan-out signal line is one or a combination of molybdenum, titanium, copper and aluminum.
  • the manufacturing method of the display panel wiring structure further includes step S6, providing a driving chip, and electrically connecting each fan-out signal line to the driving chip.
  • the present invention provides a display panel wiring structure including a substrate, the substrate includes a fan-out area, and the fan-out area is provided with a plurality of fan-out signal lines arranged in sequence at intervals, and each Hollow areas are formed inside the fan-out signal lines, or multiple serration grooves are formed in sequence on both sides of each fan-out signal line.
  • a display panel wiring structure including a substrate, the substrate includes a fan-out area, and the fan-out area is provided with a plurality of fan-out signal lines arranged in sequence at intervals, and each Hollow areas are formed inside the fan-out signal lines, or multiple serration grooves are formed in sequence on both sides of each fan-out signal line.
  • a plurality of sequentially arranged serrated grooves are formed on both edges of a fan-out signal line, which can improve the line width difference between the fan-out signal line and the display signal line, and improve the display quality of the display panel.
  • the invention also provides a manufacturing method of the display panel wiring structure, which can improve the line width difference
  • FIGS 1 and 2 are schematic diagrams of steps S1 to S2 of the first embodiment of the method for manufacturing the display panel wiring structure of the present invention
  • step S3 is a schematic diagram of step S3 of the first embodiment of the method for manufacturing the display panel wiring structure of the present invention.
  • FIG. 4 is a schematic diagram of steps S4 to S5 of the first embodiment of the manufacturing method of the display panel wiring structure of the present invention and a schematic diagram of the first embodiment of the display panel wiring structure of the present invention;
  • FIGS 5 and 6 are schematic diagrams of steps S1 to S2 of the second embodiment of the method for manufacturing the display panel wiring structure of the present invention.
  • FIG. 8 is a schematic diagram of steps S4 to S5 of the second embodiment of the method for manufacturing the display panel wiring structure of the present invention and a schematic diagram of the second embodiment of the display panel wiring structure of the present invention.
  • the present invention provides a wiring structure for a display panel.
  • By adding an additional light-transmitting structure to an existing fan-out signal line the development rate of the corresponding photoresist of the fan-out signal line during the manufacturing process is increased, and The line width of the fan-out signal line and the display signal line tend to be consistent.
  • the present invention provides a display panel wiring structure, including a substrate 1 , The substrate 1 Including fan-out area 11 , The fan-out area 11 There are multiple fan-out signal lines arranged in sequence at intervals 12 , Each fan-out signal line 12 Hollowed out areas 121 .
  • the substrate 1 also includes the fan-out area 11 Connected display area twenty one , The display area twenty one There are multiple display signal lines arranged in sequence at intervals twenty two , Each display signal line twenty two Corresponding to the electrical connection of a fan-out signal line 12 ; Two adjacent display signal lines twenty two The distance between them is greater than the two adjacent fan-out signal lines 12 The spacing between.
  • the fan-out signal line 12 And display signal line twenty two The material is a combination of one or more of molybdenum, titanium, copper and aluminum.
  • the substrate 1 It is a glass substrate.
  • each fan-out signal line 12 It is also electrically connected to the driving chip (not shown).
  • the present invention also provides a method for manufacturing a display panel wiring structure, including the following steps:
  • step S1 Provide a substrate 1 , The substrate 1 Including fan-out area 11 .
  • the steps S1 In the substrate 1 also includes the fan-out area 11 Adjacent display area twenty one .
  • the substrate 1 It is a glass substrate.
  • step S2 In the fan-out area 11 Form a conductive film on top 100 And photoresist film 200 .
  • the conductive film 100 Is made of one or more of molybdenum, titanium, copper and aluminum, the photoresist film 200 It is a positive photoresist.
  • step S3 Provide a mask 300 ,
  • the photomask includes multiple fan-out signal lines to be formed 12 Interval position between each fan-out signal line 12 Hollow area inside 121 Set light transmission area 301 And corresponding to the fan-out signal line to be formed 12 Non-light-transmissive area 302 .
  • the steps S3 In the light-transmitting area 301 also corresponds to the formation of multiple display signal lines twenty two
  • the spacing between the settings, the non-light-transmitting area 302 also corresponds to the formation of multiple display signal lines twenty two Location settings.
  • step S4 Through the mask 300 For the photoresist film 200 Exposure and development are performed to obtain a photoresist pattern.
  • exposed photoresist film 200 Photoresist film that can be removed by development without being exposed 200 Will not be removed during development, the photoresist film that has not been removed 200 Composition photoresist pattern.
  • step S5 Use the photoresist pattern as a shield to the conductive film 100 Etching is performed, and the photoresist pattern is removed after the etching is completed to obtain the fan-out area 11 Multiple fan-out signal lines arranged in sequence 12 , And each fan-out signal line 12 Hollowed out areas 121 .
  • each fan-out signal line 12 Hollow area 121 All signal lines from the fan 12 One edge extends to the fan-out signal line 12 The other end of the edge.
  • the present invention uses a fan-out signal line 12 Hollow area is set inside to increase the fan-out signal line 12 Fan-out zone 11 Transmittance in medium, increase fan-out signal line 12 Between the development rate of the photoresist, thereby compensating for the fan-out signal line 12 The development rate of the photoresist is reduced due to the denser wiring, which also makes the fan-out signal line 12 With display signal line twenty two The width is the same.
  • a wiring structure for a display panel including a substrate 1 , The substrate 1 Including fan-out area 11 , The fan-out area 11 There are multiple fan-out signal lines arranged in sequence at intervals 12 , Each fan-out signal line 12 A plurality of serrated grooves arranged in sequence are formed on the edges on both sides 121 ’.
  • the substrate 1 also includes the fan-out area 11 Connected display area twenty one , The display area twenty one There are multiple display signal lines arranged in sequence at intervals twenty two , Each display signal line twenty two Corresponding to the electrical connection of a fan-out signal line 12 ; Two adjacent display signal lines twenty two The distance between them is greater than the two adjacent fan-out signal lines 12 The spacing between.
  • the fan-out signal line 12 And display signal line twenty two The material is a combination of one or more of molybdenum, titanium, copper and aluminum.
  • the substrate 1 It is a glass substrate.
  • each fan-out signal line 12 It is also electrically connected to the driving chip (not shown).
  • the present invention also provides a method for manufacturing a display panel wiring structure, including the following steps:
  • step S1 Provide a substrate 1 , The substrate 1 Including fan-out area 11 ;
  • the steps S1 In the substrate 1 also includes the fan-out area 11 Adjacent display area twenty one ;
  • the substrate 1 It is a glass substrate.
  • step S2 In the fan-out area 11 Form a conductive film on top 100 And photoresist film 200 ;
  • the conductive film 100 Is made of one or more of molybdenum, titanium, copper and aluminum, the photoresist film 200 It is a positive photoresist.
  • step S3 Provide a mask 300 ,
  • the photomask includes multiple fan-out signal lines to be formed 12 Interval position between each fan-out signal line 12 Serrated grooves on both sides of the 121 ’Translucent area 301 And corresponding to the fan-out signal line to be formed 12 Non-light-transmissive area 302 .
  • the steps S3 In the light-transmitting area 301 also corresponds to the formation of multiple display signal lines twenty two
  • the spacing between the settings, the non-light-transmitting area 302 also corresponds to the formation of multiple display signal lines twenty two Location settings.
  • step S4 Through the mask 300 For the photoresist film 200 Exposure and development are performed to obtain a photoresist pattern.
  • exposed photoresist film 200 Photoresist film that can be removed by development without being exposed 200 Will not be removed during development, the photoresist film that has not been removed 200 Composition photoresist pattern.
  • step S5 Use the photoresist pattern as a shield to the conductive film 100 Etching is performed, and the photoresist pattern is removed after the etching is completed to obtain the fan-out area 11
  • Multiple fan-out signal lines arranged in sequence 12 And each fan-out signal line 12 A plurality of serrated grooves arranged in sequence are formed on the edges on both sides 121 ’.
  • the present invention uses a fan-out signal line 12 Add serrated grooves on both edges 121 ’To increase the fan-out signal line 12 Fan-out zone 11 Transmittance in medium, increase fan-out signal line 12 Between the development rate of the photoresist, thereby compensating for the fan-out signal line 12 The development rate of the photoresist is reduced due to the denser wiring, which also makes the fan-out signal line 12 With display signal line twenty two The width is the same. ,
  • the present invention provides a wiring structure for a display panel, which includes a substrate, the substrate includes a fan-out area, and the fan-out area is provided with a plurality of fan-out signal lines arranged in sequence at intervals, and each fan Hollow areas are formed inside the signal output lines or a plurality of serrated grooves are formed in sequence on both sides of each fan-out signal line.
  • a hollow area inside each fan-out signal line or in each A plurality of sequentially arranged serrated grooves are formed on both edges of the fan-out signal line, which can improve the line width difference between the fan-out signal line and the display signal line, and improve the display quality of the display panel.
  • the invention also provides a manufacturing method of the display panel wiring structure, which can improve the line width difference between the fan-out signal line and the display signal line, and improve the display quality of the display panel.

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Abstract

本发明提供一种显示面板走线结构及其制作方法。所述显示面板走线结构包括基板，所述基板包括扇出区，所述扇出区内设有多条依次间隔排列的扇出信号线，且每一条扇出信号线的内部均形成有镂空区或每一条扇出信号线的两侧边缘均形成有多个依次排列的锯齿槽，通过在每一条扇出信号线的内部均形成镂空区或在每一条扇出信号线的两侧边缘均形成多个依次排列的锯齿槽，能够改善扇出信号线与显示信号线之间的线宽差异，提升显示面板的显示品质。

Description

显示面板走线结构及其制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种显示面板走线结构及其制作方法。
 背景技术
液晶显示装置(Liquid Crystal Display，LCD)具有机身薄、省电等众多优点，得 到了广泛的应用。如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔 记本电脑屏幕等，在平板显示领域中占主导地位。
现有市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶面板及背光模 组(Backlight Module)。LCD显示器件的工作原理是利用液晶的旋光性和双折射，通过电压 控制液晶的转动，使经过下偏光片后的线偏振光随之发生旋转，从上偏光片(与上偏光片的偏振方向垂直)射出，从而上、下偏光片加上液晶盒起到光开关的作用。因此，液晶显示面板上下两侧还必须各贴附一片偏光片。
液晶显示面板具有显示区以及扇出区。显示区内配置有多个像素以形成像素阵列，扇出区则设有扇出走线。每个像素都包括薄膜晶体管以及与该薄膜晶体管连接的像素电极，且每个像素的薄膜晶体管均电性连接一条扫描线以及一条数据线。通常这些扫描线以及数据线统称为显示信号线，每一条显示信号线均会由显示区延伸至扇出区，并通过扇出走线与驱动芯片(driver IC)电性连接，以接收驱动信号进行画面显示。
在液晶显示面板的制作过程中，对于同样的图案，光刻工艺后形成在显示区的显示信号线的线宽，比形成在扇出区的扇出信号线的线宽要窄，彼此之间的差异能达到2-3um。导致这种不良的原因主要是：从布局上看，显示区的显示信号线走线比较稀疏，而扇出区的扇出信号线走线比较稠密。在形成信号线时，是对信号线之间的光刻胶进行曝光，而对信号线上的光刻胶不进行曝光，以正性光刻胶为例，受到曝光的光刻胶变性而被显影掉。这样在显影时，由于扇出区的扇出信号线走线十分稠密所以信号线之间的光刻胶较难被显影掉，使得扇出信号线的宽度比较大，且从光强分布来看，扇出信号线走线十分稠密，使得扇出区在曝光时接收到的整体光强较小，相应地，扇出区的扇出信号线之间的光阻接受到的光强也比较弱，受到曝光被显影掉的光阻也比较少，使得扇出区信号线的宽度比较大。
 技术问题
本发明的目的在于提供一种显示面板走线结构，能够改善扇出信号线与显示信号线之间的线宽差异，提升显示面板的显示品质。
本发明的目的还在于提供一种显示面板走线结构的的制作方法，能够改善扇出信号线与显示信号线之间的线宽差异，提升显示面板的显示品质。
 技术解决方案
为实现上述目的，本发明提供一种显示面板走线结构，包括基板，所述基板包括扇出区，所述扇出区内设有多条依次间隔排列的扇出信号线；
每一条扇出信号线的内部均形成有镂空区或每一条扇出信号线两侧边缘均形成有多个依次排列的锯齿槽。
所述基板还包括与所述扇出区相连的显示区，所述显示区内设有多条依次间隔排列的显示信号线，每一条显示信号线对应电性连接一条扇出信号线；相邻的两条显示信号线之间的间距大于所述相邻的两条扇出信号线之间的间距。
每一条扇出信号线的内部均形成有镂空区，每一条扇出信号线中的镂空区均从该条扇出信号线一端边缘延伸至该条扇出信号线的另一端边缘。
所述扇出信号线的材料为钼、钛、铜及铝中的一种或多种的组合。
每一条扇出信号线均电性连接至驱动芯片。
本发明提供一种显示面板走线结构的制作方法，包括如下步骤：
步骤S1、提供一基板，所述基板包括扇出区；
步骤S2、在所述扇出区上依次形成导电薄膜及光阻薄膜；
步骤S3、提供一光罩，所述光罩包括透光区及非透明区；
所述透光区对应待形成多条扇出信号线之间的间隔位置及每一条扇出信号线内部的镂空区设置或对应待形成多条扇出信号线之间的间隔位置及每一条扇出信号线的两侧边缘的锯齿槽位置设置；
所述非透明区对应所述待形成扇出信号线的位置设置非透光区；
步骤S4、通过所述光罩对所述光阻薄膜进行曝光及显影，得到光阻图案；
步骤S5、以所述光阻图案为遮挡对所述导电薄膜进行蚀刻，蚀刻完成后去除光阻图案，得到位于所述扇出区内的多条依次间隔排列的扇出信号线，且每一条扇出信号线的内部均形成有镂空区或每一条扇出信号线两侧边缘均形成有多个依次排列的锯齿槽。
所述步骤S1中，所述基板还包括与所述扇出区相邻的显示区；
所述步骤S2中，所述导电薄膜及光阻薄膜还形成于所述显示区上；
所述步骤S3中，所述透光区还对应待形成多条显示信号线之间的间隔位置设置，所述非透光区还对应待形成多条显示信号线的位置设置；
所述步骤S5中，还得到位于所述显示区内的多条依次间隔排列的显示信号线，且每一条显示信号线对应电性连接一条扇出信号线；
相邻的两条显示信号线之间的间距大于所述相邻的两条扇出信号线之间的间距。
每一条扇出信号线中的镂空区均从该条扇出信号线一端边缘延伸至该条扇出信号线的另一端边缘。
所述扇出信号线的材料为钼、钛、铜及铝中的一种或多种的组合。
所述显示面板走线结构的制作方法还包括步骤S6、提供一驱动芯片，将每一条扇出信号线均电性连接至驱动芯片。
 有益效果
本发明的有益效果：本发明提供一种显示面板走线结构，包括基板，所述基板包括扇出区，所述扇出区内设有多条依次间隔排列的扇出信号线，且每一条扇出信号线的内部均形成有镂空区或每一条扇出信号线的两侧边缘均形成有多个依次排列的锯齿槽，通过在每一条扇出信号线的内部均形成镂空区或在每一条扇出信号线的两侧边缘均形成多个依次排列的锯齿槽，能够改善扇出信号线与显示信号线之间的线宽差异，提升显示面板的显示品质。本发明还提供一种显示面板走线结构的的制作方法，能够改善扇出信号线与显示信号线之间的线宽差异，提升显示面板的显示品质。
 附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1和图2为本发明的显示面板走线结构的制作方法的第一实施例的步骤S1至步骤S2的示意图；
图3为本发明的显示面板走线结构的制作方法的第一实施例的步骤S3的示意图；
图4为本发明的显示面板走线结构的制作方法的第一实施例的步骤S4至步骤S5的示意图暨本发明的显示面板走线结构的第一实施例的示意图；
图5和图6为本发明的显示面板走线结构的制作方法的第二实施例的步骤S1至步骤S2的示意图；
图7为本发明的显示面板走线结构的制作方法的第二实施例的步骤S3的示意图；
图8为本发明的显示面板走线结构的制作方法的第二实施例的步骤S4至步骤S5的示意图暨本发明的显示面板走线结构的第二实施例的示意图。
 本发明的实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
本发明提供一种显示面板走线结构，其通过在现有的扇出信号线上增加额外的透光结构，使得扇出信号线在制作过程中的其对应的光阻的显影率增加，并使得扇出信号线与显示信号线的线宽趋于一致。
基于上述构思，请参阅图 4 ，在本发明的第一实施例中，本发明提供一种显示面板走线结构，包括基板 1 ，所述基板 1 包括扇出区 11 ，所述扇出区 11 内设有多条依次间隔排列的扇出信号线 12 ，每一条扇出信号线 12 的内部均形成有镂空区 121 。
进一步地，如图 4 所示，所述基板 1 还包括与所述扇出区 11 相连的显示区 21 ，所述显示区 21 内设有多条依次间隔排列的显示信号线 22 ，每一条显示信号线 22 对应电性连接一条扇出信号线 12 ；相邻的两条显示信号线 22 之间的间距大于所述相邻的两条扇出信号线 12 之间的间距。
详细地，每一条扇出信号线 12 中的镂空区 121 均从该条扇出信号线 12 一端边缘延伸至该条扇出信号线 12 的另一端边缘。
可选地，所述扇出信号线 12 和显示信号线 22 的材料为钼、钛、铜及铝中的一种或多种的组合。
可选地，所述基板 1 为玻璃基板。
具体地，每一条扇出信号线 12 还与驱动芯片（未图示）电性连接。
请参阅图 1 至图 4 ，基于图 4 所示的显示面板走线结构，本发明还提供一种显示面板走线结构的制作方法，包括如下步骤：
步骤 S1 、提供一基板 1 ，所述基板 1 包括扇出区 11 。
具体地，所述步骤 S1 中，所述基板 1 还包括与所述扇出区 11 相邻的显示区 21 。
优选地，所述基板 1 为玻璃基板。
步骤 S2 、在所述扇出区 11 上依次形成导电薄膜 100 及光阻薄膜 200 。
具体地，所述步骤 S2 中，所述导电薄膜 100 及光阻薄膜 200 还形成于所述显示区 2 上。
具体地，所述导电薄膜 100 的材料为钼、钛、铜及铝中的一种或多种的组合，所述光阻薄膜 200 为正性光阻。
步骤 S3 、提供一光罩 300 ，所述光罩包括对应待形成多条扇出信号线 12 之间的间隔位置及每一条扇出信号线 12 内部的镂空区 121 设置的透光区 301 及对应所述待形成扇出信号线 12 的位置设置非透光区 302 。
具体地，所述步骤 S3 中，所述透光区 301 还对应待形成多条显示信号线 22 之间的间隔位置设置，所述非透光区 302 还对应待形成多条显示信号线 22 的位置设置。
步骤 S4 、通过所述光罩 300 对所述光阻薄膜 200 进行曝光及显影，得到光阻图案。
具体地，通过透光区 301 对所述光阻薄膜 200 曝光，被曝光后的光阻薄膜 200 能够通过显影去除，而未被曝光的光阻薄膜 200 则不会在显影时被去除，未被去除的光阻薄膜 200 组成光阻图案。
步骤 S5 、以所述光阻图案为遮挡对所述导电薄膜 100 进行蚀刻，蚀刻完成后去除光阻图案，得到位于所述扇出区 11 内的多条依次间隔排列的扇出信号线 12 ，且每一条扇出信号线 12 的内部均形成有镂空区 121 。
具体地，所述步骤 S5 中，还得到位于所述显示区 21 内的多条依次间隔排列的显示信号线 22 ，且每一条显示信号线 22 对应电性连接一条扇出信号线 12 ；
相邻的两条显示信号线 22 之间的间距大于所述相邻的两条扇出信号线 12 之间的间距。
具体地，每一条扇出信号线 12 中的镂空区 121 均从该条扇出信号线 12 一端边缘延伸至该条扇出信号线 12 的另一端边缘。
需要说明的是，本发明通过在扇出信号线 12 内部设置镂空区，以增加用于形成扇出信号线 12 的光罩的在扇出区 11 中的透过率，增加扇出信号线 12 之间的光阻的显影率，从而补偿因为扇出信号线 12 走线比较稠密引起的光阻的显影率下降，也使得扇出信号线 12 与显示信号线 22 的宽度一致。
请参阅图 8 ，在本发明第二实施例中，还提供一种显示面板走线结构，包括基板 1 ，所述基板 1 包括扇出区 11 ，所述扇出区 11 内设有多条依次间隔排列的扇出信号线 12 ，每一条扇出信号线 12 两侧边缘均形成有多个依次排列的锯齿槽 121 ’。
具体地，所述基板 1 还包括与所述扇出区 11 相连的显示区 21 ，所述显示区 21 内设有多条依次间隔排列的显示信号线 22 ，每一条显示信号线 22 对应电性连接一条扇出信号线 12 ；相邻的两条显示信号线 22 之间的间距大于所述相邻的两条扇出信号线 12 之间的间距。
可选地，所述扇出信号线 12 和显示信号线 22 的材料为钼、钛、铜及铝中的一种或多种的组合。
可选地，所述基板 1 为玻璃基板。
具体地，每一条扇出信号线 12 还与驱动芯片（未图示）电性连接。
请参阅图 5 至图 8 ，基于图 4 所示的显示面板走线结构，本发明还提供一种显示面板走线结构的制作方法，包括如下步骤：
步骤 S1 、提供一基板 1 ，所述基板 1 包括扇出区 11 ；
具体地，所述步骤 S1 中，所述基板 1 还包括与所述扇出区 11 相邻的显示区 21 ；
优选地，所述基板 1 为玻璃基板。
步骤 S2 、在所述扇出区 11 上依次形成导电薄膜 100 及光阻薄膜 200 ；
具体地，所所述步骤 S2 中，所述导电薄膜 100 及光阻薄膜 200 还形成于所述显示区 2 上。
具体地，所述导电薄膜 100 的材料为钼、钛、铜及铝中的一种或多种的组合，所述光阻薄膜 200 为正性光阻。
步骤 S3 、提供一光罩 300 ，所述光罩包括对应待形成多条扇出信号线 12 之间的间隔位置及每一条扇出信号线 12 的两侧边缘的锯齿槽 121 ’位置设置的透光区 301 及对应所述待形成扇出信号线 12 的位置设置非透光区 302 。
具体地，所所述步骤 S3 中，所述透光区 301 还对应待形成多条显示信号线 22 之间的间隔位置设置，所述非透光区 302 还对应待形成多条显示信号线 22 的位置设置。
步骤 S4 、通过所述光罩 300 对所述光阻薄膜 200 进行曝光及显影，得到光阻图案。
具体地，通过透光区 301 对所述光阻薄膜 200 曝光，被曝光后的光阻薄膜 200 能够通过显影去除，而未被曝光的光阻薄膜 200 则不会在显影时被去除，未被去除的光阻薄膜 200 组成光阻图案。
步骤 S5 、以所述光阻图案为遮挡对所述导电薄膜 100 进行蚀刻，蚀刻完成后去除光阻图案，得到位于所述扇出区 11 内的多条依次间隔排列的扇出信号线 12 ，且每一条扇出信号线 12 两侧边缘均形成有多个依次排列的锯齿槽 121 ’。
具体地，所所述步骤 S5 中，还得到位于所述显示区 21 内的多条依次间隔排列的显示信号线 22 ，且每一条显示信号线 22 对应电性连接一条扇出信号线 12 ；所相邻的两条显示信号线 22 之间的间距大于所述相邻的两条扇出信号线 12 之间的间距。
需要说明的是，本发明通过在扇出信号线 12 两侧边缘增设锯齿槽 121 ’，以增加用于形成扇出信号线 12 的光罩的在扇出区 11 中的透过率，增加扇出信号线 12 之间的光阻的显影率，从而补偿因为扇出信号线 12 走线比较稠密引起的光阻的显影率下降，也使得扇出信号线 12 与显示信号线 22 的宽度一致。、
综上所述，本发明提供一种显示面板走线结构，包括基板，所述基板包括扇出区，所述扇出区内设有多条依次间隔排列的扇出信号线，且每一条扇出信号线的内部均形成有镂空区或每一条扇出信号线的两侧边缘均形成有多个依次排列的锯齿槽，通过在每一条扇出信号线的内部均形成镂空区或在每一条扇出信号线的两侧边缘均形成多个依次排列的锯齿槽，能够改善扇出信号线与显示信号线之间的线宽差异，提升显示面板的显示品质。本发明还提供一种显示面板走线结构的的制作方法，能够改善扇出信号线与显示信号线之间的线宽差异，提升显示面板的显示品质。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

  1. 一种显示面板走线结构，包括基板，所述基板包括扇出区，所述扇出区内设有多条依次间隔排列的扇出信号线；
    每一条扇出信号线的内部均形成有镂空区或每一条扇出信号线两侧边缘均形成有多个依次排列的锯齿槽。
  2. 如权利要求1所述的显示面板走线结构，其中，所述基板还包括与所述扇出区相连的显示区，所述显示区内设有多条依次间隔排列的显示信号线，每一条显示信号线对应电性连接一条扇出信号线；相邻的两条显示信号线之间的间距大于所述相邻的两条扇出信号线之间的间距。
  3. 如权利要求1所述的显示面板走线结构，其中，每一条扇出信号线的内部均形成有镂空区，每一条扇出信号线中的镂空区均从该条扇出信号线一端边缘延伸至该条扇出信号线的另一端边缘。
  4. 如权利要求1所述的显示面板走线结构，其中，所述扇出信号线的材料为钼、钛、铜及铝中的一种或多种的组合。
  5. 如权利要求1所述的显示面板走线结构，其中，每一条扇出信号线均电性连接至一驱动芯片。
  6. 一种显示面板走线结构的制作方法，包括如下步骤：
    步骤S1、提供一基板，所述基板包括扇出区；
    步骤S2、在所述扇出区上依次形成导电薄膜及光阻薄膜；
    步骤S3、提供一光罩，所述光罩包括透光区及非透明区；
    所述透光区对应待形成多条扇出信号线之间的间隔位置及每一条扇出信号线内部的镂空区设置或对应待形成多条扇出信号线之间的间隔位置及每一条扇出信号线的两侧边缘的锯齿槽位置设置；
    所述非透明区对应所述待形成扇出信号线的位置设置非透光区；
    步骤S4、通过所述光罩对所述光阻薄膜进行曝光及显影，得到光阻图案；
    步骤S5、以所述光阻图案为遮挡对所述导电薄膜进行蚀刻，蚀刻完成后去除光阻图案，得到位于所述扇出区内的多条依次间隔排列的扇出信号线，且每一条扇出信号线的内部均形成有镂空区或每一条扇出信号线两侧边缘均形成有多个依次排列的锯齿槽。
  7. 如权利要求6所述的显示面板走线结构的制作方法，其中，所述步骤S1中，所述基板还包括与所述扇出区相邻的显示区；
    所述步骤S2中，所述导电薄膜及光阻薄膜还形成于所述显示区上；
    所述步骤S3中，所述透光区还对应待形成多条显示信号线之间的间隔位置设置，所述非透光区还对应待形成多条显示信号线的位置设置；
    所述步骤S5中，还得到位于所述显示区内的多条依次间隔排列的显示信号线，且每一条显示信号线对应电性连接一条扇出信号线；
    相邻的两条显示信号线之间的间距大于所述相邻的两条扇出信号线之间的间距。
  8. 如权利要求6所述的显示面板走线结构的制作方法，其中，每一条扇出信号线中的镂空区均从该条扇出信号线一端边缘延伸至该条扇出信号线的另一端边缘。
  9. 如权利要求6所述的显示面板走线结构的制作方法，其中，所述扇出信号线的材料为钼、钛、铜及铝中的一种或多种的组合。
  10. 如权利要求6所述的显示面板走线结构的制作方法，还包括步骤S6、提供一驱动芯片，将每一条扇出信号线均电性连接至驱动芯片。
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