JP6902110B2 - アレイ基板構造及びアレイ基板の製造方法 - Google Patents
アレイ基板構造及びアレイ基板の製造方法 Download PDFInfo
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Description
基板を提供し、前記基板上に第1金属層を製造し、1枚目のフォトマスクにより前記第1金属層をパターニングして、ゲート電極を製造するステップ1と、
前記基板上にゲート絶縁層を製造し、2枚目のフォトマスクにより活性層を製造するステップ2と、
3枚目のフォトマスクにより、前記ゲート絶縁層において前記第1金属層に対応しる第1ビアホールを形成するステップ3と、
前記ゲート絶縁層上に第2金属層を製造し、4枚目のフォトマスクにより前記第2金属層をパターニングして、ソース/ドレイン電極を製造し、前記活性層に対応する第2ビアホールを形成し、前記第1金属層と前記第2金属層とが前記第1ビアホールで接続されるステップ4と、
5枚目のフォトマスクにより画素電極を製造し、前記画素電極と前記ソース/ドレイン電極とが前記第2ビアホールで直接接続され、前記第2金属層が前記画素電極で覆われて保護されるステップ5と、を含む、アレイ基板の製造方法を提供する。
層別に製造された基板と、第1金属層と、ゲート電極と、ゲート絶縁層と、活性層と、第2金属層と、ソース/ドレイン電極と、画素電極とを含み、
前記ゲート絶縁層上において前記第1金属層に対応する位置に第1ビアホールが設けられ、前記活性層に対応する前記ソース/ドレイン電極に第2ビアホールが設けられ、前記第1ビアホールで前記第1金属層と前記第2金属層とが接続され、前記第2ビアホールで前記画素電極と前記ソース/ドレイン電極とが直接接続され、前記第2金属層が前記画素電極で覆われて保護されている、アレイ基板構造を提供する。
基板を提供し、前記基板上に第1金属層を製造し、1枚目のフォトマスクにより前記第1金属層をパターニングして、ゲート電極を製造するステップ1と、
前記基板上にゲート絶縁層を製造し、2枚目のフォトマスクにより活性層を製造するステップ2と、
3枚目のフォトマスクにより、前記ゲート絶縁層において第1金属層に対応する第1ビアホールを形成するステップ3と、
前記ゲート絶縁層上に第2金属層を製造し、4枚目のフォトマスクにより前記第2金属層をパターニングして、ソース/ドレイン電極を製造し、前記活性層に対応する第2ビアホールを形成し、前記第1金属層と前記第2金属層とが前記第1ビアホールで接続されるステップ4と、
5枚目のフォトマスクにより画素電極を製造し、前記画素電極と前記ソース/ドレイン電極とが前記第2ビアホールで直接接続され、前記第2金属層が前記画素電極で覆われて保護されるステップ5と、を含み、
前記ステップ1では、前記第1金属層のパターニング後に、走査線及び共通電極配線をさらに形成し、
ステップ4では、前記第2金属層のパターニング後にデータ線をさらに形成する、アレイ基板の製造方法を提供する。
基板を提供し、前記基板上に第1金属層を製造し、1枚目のフォトマスクにより前記第1金属層をパターニングして、ゲート電極を製造するステップ1と、
前記基板上にゲート絶縁層を製造し、2枚目のフォトマスクにより活性層を製造するステップ2と、
3枚目のフォトマスクにより、前記ゲート絶縁層において前記第1金属層に対応しる第1ビアホールを形成するステップ3と、
前記ゲート絶縁層上に第2金属層を製造し、4枚目のフォトマスクにより前記第2金属層をパターニングして、ソース/ドレイン電極を製造し、前記活性層に対応する第2ビアホールを形成し、前記第1金属層と前記第2金属層とが前記第1ビアホールで接続されるステップ4と、
5枚目のフォトマスクにより画素電極を製造し、前記画素電極と前記ソース/ドレイン電極とが前記第2ビアホールで直接接続され、前記第2金属層が前記画素電極で覆われて保護されるステップ5と、を含む。
本発明に係るアレイ基板の製造方法により、本発明は、対応するアレイ基板構造を提供する。アレイ基板構造は、図3に示すように、層別に製造された基板30と、第1金属層31と、ゲート電極32と、ゲート絶縁層33と、活性層34と、第2金属層35と、ソース/ドレイン電極36と、画素電極37とを含み、ゲート絶縁層33上において第1金属層31に対応して第1ビアホール38が設けられ、活性層34に対応するソース/ドレイン電極36の位置に第2ビアホール39を形成し、第1ビアホール38で第1金属層31と第2金属層35とが接続され、第2ビアホール39で画素電極37とソース/ドレイン電極36とが直接接続され、第2金属層35が画素電極37で覆われて保護される。
1.画素内ソース/ドレイン電極と画素電極とがビアホールを介して直接接続され、高精細な液晶表示装置において、該ビアホールが液晶表示装置の開口率を向上させ、さらに液晶表示装置の液晶効率を向上させる。
2.液晶表示装置の周辺駆動回路では、第1金属層と第2金属層との接続にITOブリッジを用いる必要がなく、本発明のブリッジ構造は額縁の幅を低減させ、特にGOA回路の面積を低減させ、また、当該ブリッジ方法はブリッジのインピーダンスを低減させ、パネルの電気的特性を改善する。
Claims (9)
- 基板を提供し、前記基板上に第1金属層を製造し、1枚目のフォトマスクにより前記第1金属層をパターニングして、ゲート電極と、周辺駆動回路部とを製造するステップ1と、
前記基板上にゲート絶縁層を製造し、2枚目のフォトマスクにより活性層を製造するステップ2と、
3枚目のフォトマスクにより、前記ゲート絶縁層において前記周辺駆動回路部に対応する第1ビアホールを形成するステップ3と、
前記ゲート絶縁層上に第2金属層を製造し、4枚目のフォトマスクにより前記第2金属層をパターニングして、ソース/ドレイン電極と、データ線とを製造し、前記活性層に対応する第2ビアホールを形成し、前記周辺駆動回路部と前記データ線とが前記第1ビアホールで接続されるステップ4と、
5枚目のフォトマスクにより画素電極を製造し、前記画素電極と前記ソース/ドレイン電極とが前記第2ビアホールで直接接続され、前記データ線が前記画素電極で覆われて保護されるステップ5と、を含む、アレイ基板の製造方法。 - 前記アレイ基板が、VA型液晶表示装置のアレイ基板である、請求項1に記載のアレイ基板の製造方法。
- 前記画素電極の材料が、酸化インジウムスズである、請求項1に記載のアレイ基板の製造方法。
- 前記周辺駆動回路部は、走査線及び共通電極配線を含む、請求項1に記載のアレイ基板の製造方法。
- 層別に製造された基板と、周辺駆動回路部と、ゲート電極と、ゲート絶縁層と、活性層と、データ線と、ソース/ドレイン電極と、画素電極とを含み、
前記ゲート絶縁層上において前記周辺駆動回路部に対応する位置に第1ビアホールが設けられ、前記活性層に対応する前記ソース/ドレイン電極に第2ビアホールが設けられ、前記第1ビアホールで前記周辺駆動回路部と前記データ線とが接続され、前記第2ビアホールで前記画素電極と前記ソース/ドレイン電極とが直接接続され、前記データ線が前記画素電極で覆われて保護されている、VA型液晶表示装置のアレイ基板のアレイ基板構造。 - 前記画素電極の材料が、酸化インジウムスズである、請求項5に記載のアレイ基板構造。
- 基板を提供し、前記基板上に第1金属層を製造し、1枚目のフォトマスクにより前記第1金属層をパターニングして、ゲート電極と、周辺駆動回路部とを製造するステップ1と、
前記基板上にゲート絶縁層を製造し、2枚目のフォトマスクにより活性層を製造するステップ2と、
3枚目のフォトマスクにより、前記ゲート絶縁層において前記周辺駆動回路部に対応する第1ビアホールを形成するステップ3と、
前記ゲート絶縁層上に第2金属層を製造し、4枚目のフォトマスクにより前記第2金属層をパターニングして、ソース/ドレイン電極と、データ線とを製造し、前記活性層に対応する第2ビアホールを形成し、前記周辺駆動回路部と前記データ線とが前記第1ビアホールで接続されるステップ4と、
5枚目のフォトマスクにより画素電極を製造し、前記画素電極と前記ソース/ドレイン電極とが前記第2ビアホールで直接接続され、前記データ線が前記画素電極で覆われて保護されるステップ5と、を含み、
前記周辺駆動回路部は、走査線及び共通電極配線を含む、
アレイ基板の製造方法。 - 前記アレイ基板が、VA型液晶表示装置のアレイ基板である、請求項7に記載のアレイ基板の製造方法。
- 前記画素電極の材料が、酸化インジウムスズである請求項7に記載のアレイ基板の製造方法。
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