WO2018192052A1 - 阵列基板结构及阵列基板的制备方法 - Google Patents

阵列基板结构及阵列基板的制备方法 Download PDF

Info

Publication number
WO2018192052A1
WO2018192052A1 PCT/CN2017/084975 CN2017084975W WO2018192052A1 WO 2018192052 A1 WO2018192052 A1 WO 2018192052A1 CN 2017084975 W CN2017084975 W CN 2017084975W WO 2018192052 A1 WO2018192052 A1 WO 2018192052A1
Authority
WO
WIPO (PCT)
Prior art keywords
metal layer
array substrate
layer
preparing
pixel electrode
Prior art date
Application number
PCT/CN2017/084975
Other languages
English (en)
French (fr)
Inventor
郝思坤
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US15/570,374 priority Critical patent/US10192909B2/en
Priority to EP17906674.1A priority patent/EP3614201A4/en
Priority to KR1020197033812A priority patent/KR102228827B1/ko
Priority to JP2019556356A priority patent/JP6902110B2/ja
Publication of WO2018192052A1 publication Critical patent/WO2018192052A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13625—Patterning using multi-mask exposure
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • the present invention relates to the field of liquid crystal displays, and in particular, to an array substrate structure and a method for preparing the array substrate.
  • Liquid crystal display is one of the most widely used flat panel displays, and has gradually become a widely used electronic device such as mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or laptop screens with high-resolution color screens. monitor.
  • PDAs personal digital assistants
  • Currently used liquid crystal displays usually have an upper and lower substrate and an intermediate liquid crystal layer, and the substrate is composed of glass and electrodes. If the upper and lower substrates have electrodes, a vertical electric field mode display such as a twisted nematic (TN, Twist Nematic) mode, a vertical alignment (VA) mode, and a multi-domain vertical alignment developed to solve the narrow viewing angle can be formed. (MVA, Multi-domain Vertical Alignment) mode.
  • TN twisted nematic
  • VA vertical alignment
  • MVA Multi-domain Vertical Alignment
  • the electrodes are located only on one side of the substrate to form a display of a transverse electric field mode, such as an IPS (In-plane switching) mode, a Fringe Field Switching (FFS) mode, and the like.
  • IPS In-plane switching
  • FFS Fringe Field Switching
  • Thin-film transistor displays are used for large-size panels such as LCD TVs with high opening, high resolution, wide viewing angle, etc., but in high-resolution panels, the pixel aperture ratio is low, and the frame width of the array is low.
  • the drive (GOA) circuit is wide.
  • FIG. 1 it is a schematic diagram of a 5-mask process of a conventional array substrate.
  • the existing five-mask process mainly includes: providing a substrate 10, preparing a first metal layer 11 on the substrate 10, patterning the first metal layer 11 through the first mask, and preparing a gate electrode 12, except for the gate electrode
  • the first metal layer 11 outside the 12 may form a structure such as a scan line and a common electrode line; a gate insulating layer (GI) 13 is prepared on the substrate 10, and the active layer 14 is prepared through the second mask; a second metal layer 15 is prepared.
  • GI gate insulating layer
  • the source/drain electrode 16 is prepared by patterning the second metal layer 15 through the third mask, and the second metal layer 15 except the source/drain electrode 16 can form a structure such as a data line; and the protective layer 17 is prepared. Forming via holes on the protective layer 17 by the fourth mask preparation, the via positions respectively corresponding to the source/drain electrodes 16, the first metal layer 11 and the second metal layer 15 of the liquid crystal display peripheral driving circuit portion;
  • the photomask 18 is prepared by a photomask, and the pixel electrode material may be indium tin oxide (ITO).
  • FIG. 2 is a schematic diagram of a pixel structure based on the existing five-mask process, and the figure shows a VA pixel structure, which may be a pixel structure such as IPS in addition to the VA pixel.
  • the active layer and its adjacent gate, source and drain form a thin film that drives the pixel electrode
  • the film transistor, the pixel electrode and the source/drain electrodes are connected to each other via a via (VIA).
  • the liquid crystal display peripheral driving circuit mainly includes a gate line, a data line, and a common line.
  • the source/drain electrode of the pixel needs to be connected to the pixel electrode.
  • the via reduces the aperture ratio of the liquid crystal display, thereby affecting the liquid crystal efficiency of the liquid crystal display.
  • the first layer metal and the second layer metal connection need to use ITO bridging
  • the bridging structure adds a frame, especially affecting the area of the GOA circuit, and the ITO bridging structure increases the impedance of the bridge. Affect the electrical characteristics of the panel.
  • an object of the present invention is to provide a method for preparing an array substrate, which improves the transmittance of a high-resolution liquid crystal display and reduces the width of the frame.
  • Another object of the present invention is to provide an array substrate structure that improves the transmittance of a high-resolution liquid crystal display and reduces the width of the bezel.
  • the present invention provides a method for preparing an array substrate, comprising:
  • Step 1 providing a substrate, preparing a first metal layer on the substrate, and patterning the first metal layer through the first mask to prepare a gate electrode;
  • Step 2 preparing a gate insulating layer on the substrate, and preparing an active layer through the second photomask;
  • Step 3 forming a first via hole corresponding to the first metal layer on the gate insulating layer by using the third photomask;
  • Step 4 preparing a second metal layer on the gate insulating layer, patterning the second metal layer through the fourth mask, preparing a source/drain electrode, and forming a second via hole corresponding to the active layer, the first metal layer and The second metal layer is connected at the first via;
  • Step 5 Prepare a pixel electrode by using a fifth mask, the pixel electrode and the source/drain electrode are directly connected at the second via, and the second metal layer is covered by the pixel electrode for protection.
  • the array substrate is an array substrate of a VA type liquid crystal display.
  • the array substrate is an array substrate of an IPS type liquid crystal display.
  • the pixel electrode material is indium tin oxide.
  • the first metal layer is patterned to form a scan line and a common electrode line.
  • step 4 the second metal layer is patterned to form a data line.
  • the present invention also provides an array substrate structure including a substrate prepared layer by layer, a first metal layer and a gate electrode, a gate insulating layer, an active layer, a second metal layer, and source/drain electrodes, And a pixel electrode; a first via hole is disposed on the gate insulating layer corresponding to the first metal layer, and the source/drain electrode forms a second via hole corresponding to the position of the active layer, and the first metal layer and the second metal layer are The first via is connected, the pixel electrode is directly connected to the source/drain electrode at the second via, and the second metal layer is covered by the pixel electrode.
  • the array substrate is an array substrate of a VA type liquid crystal display.
  • the array substrate is an array substrate of an IPS type liquid crystal display.
  • the pixel electrode material is indium tin oxide.
  • the invention also provides a method for preparing an array substrate, comprising:
  • Step 1 providing a substrate, preparing a first metal layer on the substrate, and patterning the first metal layer through the first mask to prepare a gate electrode;
  • Step 2 preparing a gate insulating layer on the substrate, and preparing an active layer through the second photomask;
  • Step 3 forming a first via hole corresponding to the first metal layer on the gate insulating layer by using the third photomask;
  • Step 4 preparing a second metal layer on the gate insulating layer, patterning the second metal layer through the fourth mask, preparing a source/drain electrode, and forming a second via hole corresponding to the active layer, the first metal layer and The second metal layer is connected at the first via;
  • Step 5 preparing a pixel electrode by using a fifth reticle, the pixel electrode and the source/drain electrode are directly connected at the second via hole, and the second metal layer is covered and protected by the pixel electrode;
  • step 1 the first metal layer is patterned to form a scan line and a common electrode line;
  • step 4 the second metal layer is patterned to form a data line.
  • the array substrate structure and the method for fabricating the array substrate of the present invention can improve the pixel aperture ratio and the display effect and quality of the liquid crystal display at a high resolution, and improve the electrical characteristics of the panel.
  • FIG. 1 is a schematic view showing a process of a 5-mask of a conventional array substrate
  • FIG. 2 is a schematic diagram of a pixel structure based on an existing five-mask process
  • FIG. 3 is a schematic view showing a process of a method for preparing an array substrate according to the present invention.
  • FIG. 4 is a schematic diagram of a pixel structure of an array substrate according to the present invention.
  • FIG. 5 is a schematic diagram showing a layered structure of a pixel substrate of the array substrate of the present invention.
  • FIG. 6 is a flow chart of a method of preparing an array substrate of the present invention.
  • FIG. 6 is a flow chart of a method for preparing an array substrate of the present invention.
  • the method mainly includes:
  • Step 1 providing a substrate, preparing a first metal layer on the substrate, and patterning the first metal layer through the first mask to prepare a gate electrode;
  • Step 2 preparing a gate insulating layer on the substrate, and preparing an active layer through the second photomask;
  • Step 3 forming a first via hole corresponding to the first metal layer on the gate insulating layer by using the third photomask;
  • Step 4 preparing a second metal layer on the gate insulating layer, patterning the second metal layer through the fourth mask, preparing a source/drain electrode, and forming a second via hole corresponding to the active layer, the first metal layer and The second metal layer is connected at the first via;
  • Step 5 Prepare a pixel electrode by using a fifth mask, the pixel electrode and the source/drain electrode are directly connected at the second via, and the second metal layer is covered by the pixel electrode for protection.
  • the invention provides a new manufacturing process of a liquid crystal display array substrate, wherein the first metal layer and the second metal layer are directly connected through via holes, and the second metal layer is protected by ITO, and the liquid crystal is prepared based on the process.
  • the display has the advantages of high pixel aperture ratio and narrow bezel.
  • FIG. 3 it is a schematic diagram of a process for preparing a method for preparing an array substrate according to the present invention for further explaining a method for preparing an array substrate of the present invention.
  • a gate insulating layer 33 is prepared on the substrate 30, and an active layer 34 is prepared through the second mask;
  • first via 38 is corresponding to the first metal layer 31 of the liquid crystal display peripheral driving circuit portion
  • a second metal layer 35 is formed on the gate insulating layer 33, the second metal layer 35 is patterned by a fourth mask, the source/drain electrodes 36 are prepared, and a second via hole 39 is formed corresponding to the position of the active layer 34,
  • the first metal layer 31 and the second metal layer 35 are connected at the first via 38, and the second metal layer 35 except the source/drain electrodes 36 may form a structure such as a data line;
  • the pixel electrode 37 is prepared by a fifth mask, the pixel electrode 37 and the source/drain electrode 36 are directly connected at the second via 39, and the second metal layer 35 is covered and protected by the pixel electrode 37.
  • the material of the pixel electrode 37 may be indium tin oxide. (ITO).
  • the first metal layer 31 and the second metal layer 35 are directly connected by the first via 38, and the second metal layer 35 is covered with ITO.
  • the present invention provides a corresponding array substrate structure, As shown in FIG. 3, the substrate 30, the first metal layer 31 and the gate electrode 32, the gate insulating layer 33, the active layer 34, the second metal layer 35, the source/drain electrodes 36, and the pixels are prepared.
  • the electrode 37 is provided with a first via 38 corresponding to the first metal layer 31 on the gate insulating layer 33, and the source/drain electrode 36 forms a second via 39 corresponding to the position of the active layer 34, the first metal layer 31
  • the first metal via 35 is connected to the first via 38, the pixel electrode 37 is directly connected to the source/drain electrode 36 at the second via 39, and the second metal layer 35 is covered by the pixel electrode 37 for protection.
  • FIG. 4 it is a schematic diagram of a pixel structure of an array substrate according to the present invention.
  • the figure shows a VA pixel structure, which may be a pixel structure such as IPS in addition to the VA pixel.
  • An active layer and a gate thereof in the vicinity thereof, the source and the drain constitute a thin film transistor that drives a pixel electrode, and the pixel electrode and the source/drain electrode are directly connected at a via of the active layer.
  • the liquid crystal display peripheral driving circuit mainly includes a gate line, a data line, and a common line.
  • the pixel internal source/drain electrode and the pixel electrode are directly connected through the via hole.
  • the via hole enhances the aperture ratio of the liquid crystal display, thereby improving the liquid crystal efficiency of the liquid crystal display.
  • the first metal layer and the second metal layer are connected without using ITO bridge.
  • the bridging method of the invention reduces the width of the frame, especially the area of the GOA circuit, and the bridging mode is reduced.
  • the impedance of the bridge improves the electrical characteristics of the panel.
  • FIG. 5 it is a schematic diagram of a pixel structure of the array substrate of the present invention.
  • the structure of the pixel in FIG. 4 is illustrated in layers, which can correspond to a five-mask process.
  • a first mask process forming a gate electrode, and remaining first metal layer patterns, which may include scan lines and common electrode lines, etc.
  • a second mask process forming an active layer corresponding to a position of the gate electrode
  • a third mask The process forms a via corresponding to the remaining first metal layer pattern
  • the fourth mask process forms a source/drain electrode
  • the fifth mask process forms a pixel electrode, and the second metal layer is covered with indium tin oxide.
  • the array substrate structure and the method for fabricating the array substrate of the present invention can improve the pixel aperture ratio and the display effect and quality of the liquid crystal display at a high resolution, and improve the electrical characteristics of the panel.

Abstract

一种阵列基板结构及阵列基板的制备方法。该阵列基板的制备方法包括：步骤1、在基板(30)上制备第一金属层(31)，图案化第一金属层(31)，制备栅电极(32)；步骤2、在基板(30)上制备栅极绝缘层(33)，制备有源层(34)；步骤3、在栅极绝缘层(33)上对应于第一金属层(31)形成第一过孔(38)；步骤4、在栅极绝缘层(33)上制备第二金属层(35)，图案化第二金属层(35)，制备源/漏电极(36)，并且对应于有源层(34)形成第二过孔(39)，第一金属层(31)与第二金属层(35)在第一过孔(38)处连接；步骤5、制备像素电极(37)，像素电极(37)与源/漏电极(36)在第二过孔(39)处直接连接，第二金属层(35)由像素电极(37)覆盖保护。还提供了相应的阵列基板结构。该方案能够提升高分辨率下像素开口率和液晶显示器的显示效果和品质，改善了面板的电学特性。

Description

阵列基板结构及阵列基板的制备方法 技术领域
本发明涉及液晶显示器领域，尤其涉及一种阵列基板结构及阵列基板的制备方法。
背景技术
液晶显示器是目前使用最广泛的一种平板显示器，已经逐渐成为各种电子设备如移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕所广泛应用具有高分辨率彩色屏幕的显示器。目前普遍采用的液晶显示器，通常有上下衬底和中间液晶层组成，衬底有玻璃和电极等组成。如果上下衬底都有电极，可以形成纵向电场模式的显示器，如扭曲向列(TN，Twist Nematic)模式，垂直配向(VA，Vertical Alignment)模式，以及为了解决视角过窄开发的多畴垂直配向(MVA，Multi-domain Vertical Alignment)模式。另外一类与上述显示器不同，电极只位于衬底的一侧，形成横向电场模式的显示器，如平面转换(IPS，In-plane switching)模式、边缘场开关(FFS，Fringe Field Switching)模式等。
薄膜晶体管显示器，以其高开口、高分辨率、广视角等特点为液晶电视等大尺寸面板采用，但高分辨率面板中，使用传统制程方法设计的像素开口率低，边框宽度的阵列基板行驱动(GOA)电路宽。
参见图1，其为现有的阵列基板5道光罩制程示意图。现有的5道光罩制程主要包括：提供基板10，在基板10上制备第一金属层11，通过第一道光罩图案化第一金属层11，制备栅(Gate)电极12，除栅电极12外的第一金属层11可形成扫描线和公共电极线等结构；在基板10上制备栅极绝缘层(GI)13，通过第二道光罩制备有源层14；制备第二金属层15，通过第三道光罩图案化第二金属层15，制备源/漏(Source/Drain)电极16，除源/漏电极16外的第二金属层15可形成数据线等结构；制备保护层17，通过第四道光罩制备在保护层17上形成过孔，过孔位置分别对应于源/漏电极16，液晶显示外围驱动电路部分的第一金属层11和第二金属层15；通过第五道光罩制备像素电极18，像素电极材料可以为氧化铟锡(ITO)。
图2所示为基于现有5道光罩制程的像素结构示意图，图中所示为VA像素结构，除VA像素外还可以是IPS等像素结构。有源层(Active layer)及其附近的栅极，源极和漏极构成了驱动像素电极(Pixel electrode)的薄 膜晶体管，像素电极与源/漏电极经由过孔(VIA)相互连接。液晶显示外围驱动电路主要包括扫描线(Gate line)，数据线(Data line)，公共电极线(Com line)。
基于以上技术制造的高分辨率液晶显示器，有以下缺点：
1.像素内源/漏(Source/Drain)电极与像素电极连接需要过孔，在高分辨率液晶显示器中，该过孔降低了液晶显示器的开口率，进而影响液晶显示器的液晶效率。
2.在液晶显示外围驱动电路，第一层金属和第二层金属连接需要使用ITO桥接，该种桥接结构增加了边框，尤其是影响GOA电路的面积，另外ITO桥接结构增加了桥接的阻抗，影响面板的电学特性。
发明内容
因此，本发明的目的在于提供一种阵列基板的制备方法，提升高分辨液晶显示器的穿透率，降低边框宽度。
本发明的另一目的在于提供一种阵列基板结构，提升高分辨液晶显示器的穿透率，降低边框宽度。
为实现上述目的，本发明提供了一种阵列基板的制备方法，包括：
步骤1、提供基板，在基板上制备第一金属层，通过第一道光罩图案化第一金属层，制备栅电极；
步骤2、在基板上制备栅极绝缘层，通过第二道光罩制备有源层；
步骤3、通过第三道光罩在栅极绝缘层上对应于第一金属层形成第一过孔；
步骤4、在栅极绝缘层上制备第二金属层，通过第四道光罩图案化第二金属层，制备源/漏电极，并且对应于有源层形成第二过孔，第一金属层与第二金属层在第一过孔处连接；
步骤5、通过第五道光罩制备像素电极，像素电极与源/漏电极在第二过孔处直接连接，第二金属层由像素电极覆盖保护。
其中，所述阵列基板为VA型液晶显示器的阵列基板。
其中，所述阵列基板为IPS型液晶显示器的阵列基板。
其中，所述像素电极材料为氧化铟锡。
其中，步骤1中，该第一金属层图案化后还形成扫描线和公共电极线。
其中，步骤4中，该第二金属层图案化后还形成数据线。
本发明还相应提供了一种阵列基板结构，其包括逐层制备得到的基板，第一金属层和栅电极，栅极绝缘层，有源层，第二金属层和源/漏电极，以 及像素电极；在栅极绝缘层上对应于第一金属层设有第一过孔，源/漏电极对应于有源层的位置形成第二过孔，第一金属层与第二金属层在第一过孔处连接，像素电极与源/漏电极在第二过孔处直接连接，第二金属层由像素电极覆盖保护。
其中，所述阵列基板为VA型液晶显示器的阵列基板。
其中，所述阵列基板为IPS型液晶显示器的阵列基板。
其中，所述像素电极材料为氧化铟锡。
本发明还提供一种阵列基板的制备方法，包括：
步骤1、提供基板，在基板上制备第一金属层，通过第一道光罩图案化第一金属层，制备栅电极；
步骤2、在基板上制备栅极绝缘层，通过第二道光罩制备有源层；
步骤3、通过第三道光罩在栅极绝缘层上对应于第一金属层形成第一过孔；
步骤4、在栅极绝缘层上制备第二金属层，通过第四道光罩图案化第二金属层，制备源/漏电极，并且对应于有源层形成第二过孔，第一金属层与第二金属层在第一过孔处连接；
步骤5、通过第五道光罩制备像素电极，像素电极与源/漏电极在第二过孔处直接连接，第二金属层由像素电极覆盖保护；
其中，步骤1中，该第一金属层图案化后还形成扫描线和公共电极线；
其中，步骤4中，该第二金属层图案化后还形成数据线。
综上，本发明的阵列基板结构及阵列基板的制备方法能够提升高分辨率下像素开口率和液晶显示器的显示效果和品质，改善了面板的电学特性。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其他有益效果显而易见。
附图中，
图1为现有的阵列基板5道光罩制程示意图；
图2为基于现有5道光罩制程的像素结构示意图；
图3为本发明阵列基板的制备方法的制程示意图；
图4为本发明阵列基板的像素结构示意图；
图5为本发明阵列基板的像素结构分层示意图；
图6为本发明阵列基板的制备方法的流程图。
具体实施方式
参见图6，其为本发明阵列基板的制备方法的流程图。该方法主要包括：
步骤1、提供基板，在基板上制备第一金属层，通过第一道光罩图案化第一金属层，制备栅电极；
步骤2、在基板上制备栅极绝缘层，通过第二道光罩制备有源层；
步骤3、通过第三道光罩在栅极绝缘层上对应于第一金属层形成第一过孔；
步骤4、在栅极绝缘层上制备第二金属层，通过第四道光罩图案化第二金属层，制备源/漏电极，并且对应于有源层形成第二过孔，第一金属层与第二金属层在第一过孔处连接；
步骤5、通过第五道光罩制备像素电极，像素电极与源/漏电极在第二过孔处直接连接，第二金属层由像素电极覆盖保护。
本发明提供了一种新的液晶显示器阵列基板的制作工艺，该工艺中第一金属层和第二金属层通过过孔直接相连，第二金属层使用ITO覆盖保护，基于该种制程制作的液晶显示器，具有高像素开口率和窄边框等优点。
参见图3，其为本发明阵列基板的制备方法的制程示意图，用于进一步说明本发明阵列基板的制备方法。
提供基板30，在基板30上制备第一金属层31，通过第一道光罩图案化第一金属层31，制备栅电极32，除栅电极32外的第一金属层31可形成扫描线和公共电极线等结构；
然后在基板30上制备栅极绝缘层33，通过第二道光罩制备有源层34；
通过第三道光罩在栅极绝缘层33上对应于第一金属层31形成第一过孔38，第一过孔38位置对应于液晶显示外围驱动电路部分的第一金属层31；
在栅极绝缘层33上制备第二金属层35，通过第四道光罩图案化第二金属层35，制备源/漏电极36，并且对应于有源层34的位置形成第二过孔39，第一金属层31与第二金属层35在第一过孔38处连接，除源/漏电极36外的第二金属层35可形成数据线等结构；
通过第五道光罩制备像素电极37，像素电极37与源/漏电极36在第二过孔39处直接连接，第二金属层35由像素电极37覆盖保护，像素电极37材料可以为氧化铟锡(ITO)。
本发明的工艺中第一金属层31和第二金属层35通过第一过孔38直接相连，第二金属层35使用ITO覆盖保护。
根据本发明阵列基板的制备方法，本发明提供了相应的阵列基板结构， 如图3所示，包括逐层制备得到的基板30，第一金属层31和栅电极32，栅极绝缘层33，有源层34，第二金属层35和源/漏电极36，以及像素电极37；在栅极绝缘层33上对应于第一金属层31设有第一过孔38，源/漏电极36对应于有源层34的位置形成第二过孔39，第一金属层31与第二金属层35在第一过孔38处连接，像素电极37与源/漏电极36在第二过孔39处直接连接，第二金属层35由像素电极37覆盖保护。
参见图4，其为本发明阵列基板的像素结构示意图。图中所示为VA像素结构，除VA像素外还可以是IPS等像素结构。有源层(Active layer)及其附近的栅极，源极和漏极构成了驱动像素电极(Pixel electrode)的薄膜晶体管，像素电极与源/漏电极在有源层位置的过孔处直接连接。液晶显示外围驱动电路主要包括扫描线(Gate line)，数据线(Data line)，公共电极线(Com line)。
基于以上技术制造的高分辨率液晶显示器，有以下优点：
1.像素内源/漏电极与像素电极通过过孔直接连接，在高分辨率液晶显示器中，该过孔提升了液晶显示器的开口率，进而提升液晶显示器的液晶效率。
2.在液晶显示器外围驱动电路，第一金属层和第二金属层连接不需要使用ITO桥接，本发明的桥接方式降低了边框宽度，尤其是降低GOA电路的面积，另外该种桥接方式降低了桥接的阻抗，改善了面板的电学特性。
参见图5，其为本发明阵列基板的像素结构分层示意图，分层别说明了图4中像素的结构，可对应五道光罩制程。第一道光罩制程，形成栅电极，以及其余第一金属层图案，可包括扫描线和公共电极线等；第二道光罩制程，对应于栅电极的位置形成有源层；第三道光罩制程，对应于其余第一金属层图案形成过孔；第四道光罩制程，形成源/漏电极；第五道光罩制程，形成像素电极，第二金属层利用氧化铟锡覆盖保护。
综上，本发明的阵列基板结构及阵列基板的制备方法能够提升高分辨率下像素开口率和液晶显示器的显示效果和品质，改善了面板的电学特性。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (14)

  1. 一种阵列基板的制备方法，包括：
    步骤1、提供基板，在基板上制备第一金属层，通过第一道光罩图案化第一金属层，制备栅电极；
    步骤2、在基板上制备栅极绝缘层，通过第二道光罩制备有源层；
    步骤3、通过第三道光罩在栅极绝缘层上对应于第一金属层形成第一过孔；
    步骤4、在栅极绝缘层上制备第二金属层，通过第四道光罩图案化第二金属层，制备源/漏电极，并且对应于有源层形成第二过孔，第一金属层与第二金属层在第一过孔处连接；
    步骤5、通过第五道光罩制备像素电极，像素电极与源/漏电极在第二过孔处直接连接，第二金属层由像素电极覆盖保护。
  2. 如权利要求1所述的阵列基板的制备方法，其中，所述阵列基板为VA型液晶显示器的阵列基板。
  3. 如权利要求1所述的阵列基板的制备方法，其中，所述阵列基板为IPS型液晶显示器的阵列基板。
  4. 如权利要求1所述的阵列基板的制备方法，其中，所述像素电极材料为氧化铟锡。
  5. 如权利要求1所述的阵列基板的制备方法，其中，步骤1中，该第一金属层图案化后还形成扫描线和公共电极线。
  6. 如权利要求1所述的阵列基板的制备方法，其中，步骤4中，该第二金属层图案化后还形成数据线。
  7. 一种阵列基板结构，包括逐层制备得到的基板，第一金属层和栅电极，栅极绝缘层，有源层，第二金属层和源/漏电极，以及像素电极；在栅极绝缘层上对应于第一金属层设有第一过孔，源/漏电极对应于有源层的位置形成第二过孔，第一金属层与第二金属层在第一过孔处连接，像素电极与源/漏电极在第二过孔处直接连接，第二金属层由像素电极覆盖保护。
  8. 如权利要求7所述的阵列基板结构，其中，所述阵列基板为VA型液晶显示器的阵列基板。
  9. 如权利要求7所述的阵列基板结构，其中，所述阵列基板为IPS型液晶显示器的阵列基板。
  10. 如权利要求7所述的阵列基板结构，其中，所述像素电极材料为 氧化铟锡。
  11. 一种阵列基板的制备方法，包括：
    步骤1、提供基板，在基板上制备第一金属层，通过第一道光罩图案化第一金属层，制备栅电极；
    步骤2、在基板上制备栅极绝缘层，通过第二道光罩制备有源层；
    步骤3、通过第三道光罩在栅极绝缘层上对应于第一金属层形成第一过孔；
    步骤4、在栅极绝缘层上制备第二金属层，通过第四道光罩图案化第二金属层，制备源/漏电极，并且对应于有源层形成第二过孔，第一金属层与第二金属层在第一过孔处连接；
    步骤5、通过第五道光罩制备像素电极，像素电极与源/漏电极在第二过孔处直接连接，第二金属层由像素电极覆盖保护；
    其中，步骤1中，该第一金属层图案化后还形成扫描线和公共电极线；
    其中，步骤4中，该第二金属层图案化后还形成数据线。
  12. 如权利要求11所述的阵列基板的制备方法，其中，所述阵列基板为VA型液晶显示器的阵列基板。
  13. 如权利要求11所述的阵列基板的制备方法，其中，所述阵列基板为IPS型液晶显示器的阵列基板。
  14. 如权利要求11所述的阵列基板的制备方法，其中，所述像素电极材料为氧化铟锡。
PCT/CN2017/084975 2017-04-17 2017-05-18 阵列基板结构及阵列基板的制备方法 WO2018192052A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US15/570,374 US10192909B2 (en) 2017-04-17 2017-05-18 Array substrate structure and manufacturing method of array substrate
EP17906674.1A EP3614201A4 (en) 2017-04-17 2017-05-18 MATRIX SUBSTRATE STRUCTURE, AND METHOD FOR MANUFACTURING A MATRIX SUBSTRATE
KR1020197033812A KR102228827B1 (ko) 2017-04-17 2017-05-18 어레이 기판 구조체 및 어레이 기판의 제조방법
JP2019556356A JP6902110B2 (ja) 2017-04-17 2017-05-18 アレイ基板構造及びアレイ基板の製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710249966.2A CN106932986B (zh) 2017-04-17 2017-04-17 阵列基板结构及阵列基板的制备方法
CN201710249966.2 2017-04-17

Publications (1)

Publication Number Publication Date
WO2018192052A1 true WO2018192052A1 (zh) 2018-10-25

Family

ID=59438272

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/084975 WO2018192052A1 (zh) 2017-04-17 2017-05-18 阵列基板结构及阵列基板的制备方法

Country Status (5)

Country Link
EP (1) EP3614201A4 (zh)
JP (1) JP6902110B2 (zh)
KR (1) KR102228827B1 (zh)
CN (1) CN106932986B (zh)
WO (1) WO2018192052A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112543997A (zh) * 2019-07-22 2021-03-23 京东方科技集团股份有限公司 阵列基板及其制造方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108828862A (zh) * 2018-08-22 2018-11-16 惠科股份有限公司 阵列基板及其制作方法
CN109887883B (zh) * 2019-02-14 2020-11-06 南京中电熊猫平板显示科技有限公司 一种阵列基板及其制造方法
CN109739056A (zh) * 2019-02-25 2019-05-10 深圳市华星光电半导体显示技术有限公司 液晶显示器的像素电极及制造方法
CN110600425B (zh) * 2019-08-20 2023-07-04 武汉华星光电技术有限公司 阵列基板的制备方法及阵列基板

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060290865A1 (en) * 2005-06-24 2006-12-28 Choi Seung C Fabrication method of fringe field switching mode liquid crystal display device
CN101000896A (zh) * 2006-01-13 2007-07-18 中华映管股份有限公司 像素结构及其制造方法
CN101957529A (zh) * 2009-07-16 2011-01-26 北京京东方光电科技有限公司 Ffs型tft-lcd阵列基板及其制造方法
CN102033343A (zh) * 2009-09-25 2011-04-27 北京京东方光电科技有限公司 阵列基板及其制造方法
CN102299104A (zh) * 2011-09-20 2011-12-28 深圳市华星光电技术有限公司 Tft阵列基板的制作方法及tft阵列基板
CN103227148A (zh) * 2013-04-02 2013-07-31 京东方科技集团股份有限公司 一种阵列基板制备方法及阵列基板和显示装置
CN103928469A (zh) * 2013-04-23 2014-07-16 上海天马微电子有限公司 一种tft阵列基板及其制造方法、显示面板

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4493744B2 (ja) * 1998-12-28 2010-06-30 シャープ株式会社 液晶表示装置用基板及びその製造方法
KR101480007B1 (ko) * 2008-06-13 2015-01-08 삼성디스플레이 주식회사 박막 트랜지스터 기판 및 그 제조 방법
KR101287478B1 (ko) * 2009-06-02 2013-07-19 엘지디스플레이 주식회사 산화물 박막트랜지스터를 구비한 표시소자 및 그 제조방법

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060290865A1 (en) * 2005-06-24 2006-12-28 Choi Seung C Fabrication method of fringe field switching mode liquid crystal display device
CN101000896A (zh) * 2006-01-13 2007-07-18 中华映管股份有限公司 像素结构及其制造方法
CN101957529A (zh) * 2009-07-16 2011-01-26 北京京东方光电科技有限公司 Ffs型tft-lcd阵列基板及其制造方法
CN102033343A (zh) * 2009-09-25 2011-04-27 北京京东方光电科技有限公司 阵列基板及其制造方法
CN102299104A (zh) * 2011-09-20 2011-12-28 深圳市华星光电技术有限公司 Tft阵列基板的制作方法及tft阵列基板
CN103227148A (zh) * 2013-04-02 2013-07-31 京东方科技集团股份有限公司 一种阵列基板制备方法及阵列基板和显示装置
CN103928469A (zh) * 2013-04-23 2014-07-16 上海天马微电子有限公司 一种tft阵列基板及其制造方法、显示面板

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3614201A4 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112543997A (zh) * 2019-07-22 2021-03-23 京东方科技集团股份有限公司 阵列基板及其制造方法
CN112543997B (zh) * 2019-07-22 2024-03-19 京东方科技集团股份有限公司 阵列基板及其制造方法

Also Published As

Publication number Publication date
KR102228827B1 (ko) 2021-03-17
JP6902110B2 (ja) 2021-07-14
EP3614201A4 (en) 2020-12-02
EP3614201A1 (en) 2020-02-26
JP2020516956A (ja) 2020-06-11
CN106932986A (zh) 2017-07-07
KR20190139283A (ko) 2019-12-17
CN106932986B (zh) 2019-04-02

Similar Documents

Publication Publication Date Title
US20230408876A1 (en) Liquid crystal display panel
US9176339B2 (en) Liquid crystal display device
US8964153B2 (en) In-plane switching mode liquid crystal display device and fabricating method thereof
JP4953416B2 (ja) 液晶表示装置
WO2018192052A1 (zh) 阵列基板结构及阵列基板的制备方法
US9030637B2 (en) In-plane switching mode liquid crystal display and method for fabricating the same
KR101212067B1 (ko) 액정표시장치 및 이의 제조방법
US7751009B2 (en) Array substrate for in-plane switching mode liquid crystal display
JP2005301226A (ja) 液晶表示装置及びこれに使用する表示板
US9857620B2 (en) Display device
WO2016141705A1 (zh) 阵列基板及其制造方法和显示装置
KR101802935B1 (ko) 횡전계 방식 액정표시장치 및 그 제조방법
KR101960363B1 (ko) 액정 표시 장치 및 이의 제조 방법
US10192909B2 (en) Array substrate structure and manufacturing method of array substrate
KR101890735B1 (ko) 프린지 필드형 액정표시장치 및 그 제조방법
US9810960B2 (en) Liquid crystal display panel and array substrate thereof
KR20070049882A (ko) 박막 트랜지스터 기판과 이를 포함하는 액정 표시 장치
KR20070002779A (ko) 액정 표시패널 및 그 제조방법
KR20070025528A (ko) 액정 표시 장치, 박막 트랜지스터 기판 및 그 제조 방법
KR20080003085A (ko) 횡전계모드 액정표시소자 및 그 제조방법
US20180217460A1 (en) Liquid Crystal Display Panel, Array Substrate And Methods For Manufacturing The Same
KR101894552B1 (ko) 폭이 다른 화소전극이 형성된 액정표시소자
KR20120037847A (ko) 액정표시장치 및 그의 제조방법
KR20060000287A (ko) 박막트랜지스터 어레이 기판 및 그 제조 방법
JP2003107525A (ja) アクティブマトリクス基板

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15570374

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17906674

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2019556356

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 20197033812

Country of ref document: KR

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 2017906674

Country of ref document: EP

Effective date: 20191118