WO2012068747A1 - 像素单元、液晶显示面板及其制造方法 - Google Patents

像素单元、液晶显示面板及其制造方法 Download PDF

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WO2012068747A1
WO2012068747A1 PCT/CN2010/079540 CN2010079540W WO2012068747A1 WO 2012068747 A1 WO2012068747 A1 WO 2012068747A1 CN 2010079540 W CN2010079540 W CN 2010079540W WO 2012068747 A1 WO2012068747 A1 WO 2012068747A1
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light
pixel electrode
shielding line
line
shielding
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PCT/CN2010/079540
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English (en)
French (fr)
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林沛
贺成明
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深圳市华星光电技术有限公司
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Priority to US13/000,376 priority Critical patent/US8400602B2/en
Publication of WO2012068747A1 publication Critical patent/WO2012068747A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/122—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode having a particular pattern

Definitions

  • the present invention relates to a pixel unit, a liquid crystal display panel, and a method of fabricating the same, and more particularly to a pixel unit or a liquid crystal display panel that improves brightness unevenness due to an error in pattern matching accuracy between a gate layer and a source/drain layer. And its manufacturing method.
  • LCD monitors have become widely used in a wide range of electronic devices such as mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or notebook computer screens. Rate display with color screen.
  • the liquid crystal production process is divided into four masks and five mask processes. Among them, the four mask processes have gradually become the main mode of production due to their short production cycle and high capacity utilization. However, the four mask process control is relatively more complicated than the five mask processes, and the current production yield is also difficult to reach a high level.
  • a liquid crystal panel manufactured by a four-mask process is a gate (GE) layer on which a metal layer is exposed and etched using a first mask on a glass substrate to form a switching unit. An insulating layer and an active layer are then formed over the gate layer. Another metal layer is then deposited over the insulating layer and the active layer, and the metal layer is exposed and etched with a second mask to form the source/drain (SD) layer and data lines of the switching cells.
  • the current industry mainly uses exposure machine mixed exposure (Mix & The Match) method, that is, when forming the gate (GE) layer and the source/drain (SD) layer, respectively, exposes the metal layer using different exposure machines. Graphical coincidence accuracy between the GE layer and the SD layer exposed by different exposure machines due to different process flow (G/D Overlay) is prone to errors, resulting in an increase in the probability of a local shift.
  • FIG. 1 and FIG. 2 respectively show a schematic diagram of the offset of the formed data line with respect to the pixel electrode position
  • FIG. 3 is an equivalent circuit diagram of FIG. 1 and FIG.
  • the coupling capacitance Cpd2 corresponding to the data line 12b and the pixel electrode 14b in FIG. 3 is larger than the coupling capacitance Cpd1 between the data line 12a and the pixel electrode 14a.
  • the charging voltage of the pixel electrodes 14b is actually smaller than the charging voltage of the pixel electrodes 14a, thereby causing the liquid crystals to be deflected between the liquid crystal capacitors Clc1 and Clc2.
  • the gray level seen by the pixel electrode 14b is brighter than the gray level seen by the pixel electrode 14a.
  • the distance of the data line 12d with respect to the pixel electrode 14d is smaller than the distance of the data line 12c with respect to the pixel electrode 14c.
  • the coupling capacitance Cpd4 corresponding to the data line 12d and the pixel electrode 14d in FIG. 3 is smaller than the coupling capacitance Cpd3 between the data line 12c and the pixel electrode 14c.
  • the charging voltage of the pixel electrodes 14d is actually larger than the charging voltage of the pixel electrodes 14c, thereby causing the liquid crystals to be deflected between the liquid crystal capacitors Clc3 and Clc4.
  • the gray scale seen by the pixel electrode 14d is darker than the gray scale seen by the pixel electrode 14c.
  • the graphics overlay accuracy of the GE layer and the SD layer (G/D) Overlay A slight error will cause the LCD panel to display uneven brightness.
  • Each pixel capacitor Cpix needs to consider the following capacitors: a liquid crystal capacitor Clc, a storage capacitor Cs between the pixel electrode and the common voltage line 16, a parasitic capacitance Cgs between the gate and the source of the switching unit as a switching unit, and A coupling capacitance Cpd between the data line and the pixel electrode 14. As described above, the error in the coincidence accuracy of the pattern causes the coupling capacitance Cpd between the data line and the pixel electrode to change.
  • each pixel capacitance Cpix Clc+Cs+Cgs+Cpd
  • the ratio of the coupling capacitance Cpd between the data line and the pixel electrode to the pixel capacitance Cpix is larger, and the pattern coincidence precision (G/D) Overlay) causes the LCD panel to display uneven brightness. So how to improve the accuracy due to graphics coincidence (G/D The overlay error causes the coupling capacitance Cpd to change, causing uneven brightness, which is the goal of the industry.
  • An object of the present invention is to provide a method for fabricating a liquid crystal display panel and a pixel unit to solve the problem of uneven brightness of the conventional liquid crystal display panel.
  • the invention discloses a pixel unit electrically connected to a switching unit.
  • the pixel unit includes a pixel electrode, a common voltage line, a first light-shielding line, and a second light-shielding line.
  • the common voltage line is below the pixel electrode for providing a common voltage.
  • the first light-shielding line and the second light-shielding line are located under the pixel electrode and connected to the common voltage line, and at least one side of the first and second light-shielding lines are curved and connected to the common voltage line Produced for the same metal layer.
  • a liquid crystal display panel includes a switch unit, a pixel electrode electrically connected to the switch unit, a common voltage line, a first light-shielding line, and a second light-shielding line.
  • the common voltage line is below the pixel electrode for providing a common voltage.
  • the first light-shielding line and the second light-shielding line are both under the pixel electrode and connected to the common voltage line, and at least one side of the first and second light-shielding lines are curved and the common voltage Lines are produced for the same metal layer.
  • a method of fabricating a liquid crystal display panel includes the steps of: providing a glass substrate; etching a first metal layer formed on the glass substrate to form a gate of a thin film transistor a first common voltage line, a first light-shielding line and a second light-shielding line, wherein the first and second light-shielding lines are curved; sequentially depositing an insulating layer, an active layer, an ohmic contact layer and a first a second metal layer on the glass substrate and the first metal layer; simultaneously etching the active layer, the ohmic contact layer and the second metal layer to form above the gate until the active An opening of the layer and a source and a drain of the thin film transistor; depositing a passivation layer on the second metal layer and the insulating layer; etching the passivation layer to form a top over the drain a contact window; depositing a transparent conductive layer on the passivation layer and the contact window; etching the transparent conductive layer on the passivation layer
  • a side of the first light-shielding line and the second light-shielding line portion that do not overlap the pixel electrode is curved.
  • the first light-shielding line and the second light-shielding line are undulated or triangular wave-shaped or square-wave-shaped on a side not overlapping the pixel electrode.
  • a side of the first light-shielding line and the second light-shielding line overlapping the pixel electrode is asymmetric with a side not overlapping the pixel electrode.
  • the gate of the switching unit When the liquid crystal display panel of the present invention etches the first metal layer, the gate of the switching unit, the common voltage line, the first light-shielding line, and the second light-shielding line are formed.
  • the common voltage line is electrically connected to the first and second light shielding lines such that the first and second light shielding lines and the common voltage line simultaneously serve as a lower plate of the storage capacitor.
  • the curved first and second shading lines connected to the common voltage line increase the area of the lower plate, that is, the storage capacitance also increases.
  • Figure 3 is an equivalent circuit diagram in conjunction with Figures 1 and 2.
  • 5 to 8 are schematic views showing respective mask processes of the liquid crystal display panel of the present invention.
  • Fig. 9 is a view showing a pixel unit of the second embodiment.
  • Fig. 10 is a view showing a pixel unit of the third embodiment.
  • FIG. 4 is a schematic diagram of a pixel unit of a first embodiment of a liquid crystal display panel of the present invention.
  • the liquid crystal display panel includes a plurality of pixel units 50, each of which includes a switching unit 13 and a pixel electrode 15.
  • the switching unit 13 can be a thin film transistor or other unit having a switching function.
  • the liquid crystal molecules control the direction of rotation according to the voltage difference of the data voltage transmitted to the pixel electrode 15, thereby determining the degree of penetration of the light.
  • the first light-shielding line 41 and the second light-shielding line 42 are connected to the common voltage line 43, and are generated from the same metal layer as the common voltage line 43. The flow of forming the pixel unit 50 will be described below.
  • FIG. 5 to FIG. 8 are schematic diagrams showing the mask processes of the liquid crystal display panel 100 of the present invention.
  • Each of the figures represents a mask process, that is, the completion of the liquid crystal display panel 100 has to go through four mask processes.
  • a first metal layer (not shown) is deposited on the glass substrate 101 and a development process is performed using the first mask.
  • the developing process is to apply a photoresist (not shown) on the first metal layer, expose the photoresist by an exposure machine according to the first mask having a specific pattern, and then expose the exposed developer.
  • the photoresist is washed away.
  • the first metal layer is then etched.
  • the etching process is to remove the first metal layer without photoresist and remove the strong metal, and the first metal layer covered by the photoresist (Apparently in this particular pattern) will generate the gate 131 and the lower plate 141 of the switching unit, and then wash away the remaining photoresist.
  • the lower plate 141 includes a common electrode line 43, a first light-shielding line 41, and a second light-shielding line 42 (see FIG. 4). Since the process forms the gate 131, the cells formed by the first metal layer in the same mask belong to the gate (Gate). Electrode, GE) layer.
  • the insulating layer is first deposited (isolation). Layer)16, then depositing an active layer 17, and then depositing an ohmic contact layer (n+ Layer 18, finally depositing a second metal layer (not shown), then performing a development process using a second mask, and etching the active layer 17, the ohmic contact layer 18, and the second metal layer.
  • the ohmic contact layer 18 and the second metal layer corresponding to the upper portion of the gate electrode 131 are removed, and an opening 21 and a drain electrode 132 and a source electrode 133 of the switching unit are formed.
  • the cells formed by the second metal layer in the same mask belong to the source/drain (Source/Drain). Electrode, SD) layer. Please note that exposure to the GE and SD layers can utilize the same exposure machine or a different exposure machine.
  • the passivation layer is first deposited. Layer 19, and then using a third mask for the development process, and etching the passivation layer 19 to create a via 20 over the source 133.
  • a transparent conductive layer is first deposited, then a fourth mask is used for the development process, and the transparent conductive layer is etched to produce the pixel electrode 15.
  • FIG. 8 is also a cross-sectional view of FIG. 4 taken along line A-B-C.
  • the gate 131 of the switching unit 13 is composed of a first metal layer (GE). Layer) is formed, and source 132 and drain 133 are second metal layers (SD) Layer) formed.
  • the lower plate 141 is also formed by the first metal layer between the two points B and C.
  • a storage capacitor Cs is formed between the pixel electrode 15 and the lower plate 141.

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Description

像素单元、液晶显示面板及其制造方法 技术领域
本发明涉及一种像素单元、液晶显示面板及其制造方法，尤指一种改善因栅极层和源/漏极层之间图形重合精度的误差导致亮度不均问题的像素单元、液晶显示面板及其制造方法。
 背景技术
功能先进的显示器渐成为现今消费电子产品的重要特色，其中液晶显示器已经逐渐成为各种电子设备如移动电话、个人数字助理(PDA)、数码相机、计算机屏幕或笔记本计算机屏幕所广泛应用具有高分辨率彩色屏幕的显示器。
随着液晶面板尺寸越来越大，出现面板发生亮度不均匀造成显示痕迹(Mura)现象的几率也逐渐升高。目前液晶生产工艺流程，业内主要分为四道掩膜以及五道掩膜工艺两种。其中四道掩膜工艺由于其生产周期短，产能利用率高已逐渐成为生产的主要方式。但是四道掩膜工艺控制相对较五道掩膜工艺复杂，目前生产良率也较难达到高水平。
目前利用四道掩膜工艺制造的液晶面板，是在玻璃基板上利用第一道掩膜对金属层曝光再蚀刻以形成开关单元的栅极(GE)层。接着在栅极层之上形成绝缘层和主动层。随后在绝缘层和主动层之上再沉积另一金属层，并以第二道掩膜对该金属层曝光并蚀刻以形成开关单元的源极/漏极(SD)层和数据线。为了提高产能利用率，目前业界主要采用曝光机混合曝光（Mix & Match）方式，也就是说，在形成栅极(GE)层和源极/漏极(SD)层时，是使用不同的曝光机分别对金属层曝光。由于工艺流程不同，利用不同曝光机曝光的GE层和SD层间的图形重合精度（G/D Overlay）容易有误差，导致图案偏移(Local shift)发生几率也升高。
请一并参阅图1、图2和图3，图1和图2分别显示形成的数据线相对于像素电极位置发生偏移的示意图，图3是结合图1和图2的等效电路图。如图1所示，对位于同一行扫描线11上的像素电极14a、14b而言，数据线12b相对于像素电极14b的距离相较于数据线12a相对于像素电极14a的距离向左偏移，所以对应于图3中的数据线12b和与像素电极14b间的耦合电容Cpd2会大于数据线12a和与像素电极14a间的耦合电容Cpd1。即使数据线12a和数据线12b馈入像素电极14a、14b的数据电压一致，实际上像素电极14b的充电电压会小于像素电极14a的充电电压，从而使得液晶电容Clc1和Clc2间的液晶偏转极性不一致，所以像素电极14b看到的灰阶会较像素电极14a看到的灰阶亮。相对地，如图2所示，对位于同一行扫描线11上的像素电极14c、14d而言，数据线12d相对于像素电极14d的距离相较于数据线12c相对于像素电极14c的距离向右偏移，所以对应于图3中的数据线12d和与像素电极14d间的耦合电容Cpd4会小于数据线12c和与像素电极14c间的耦合电容Cpd3。即使数据线12c和数据线12d馈入像素电极14c、14d的数据电压一致，实际上像素电极14d的充电电压会大于像素电极14c的充电电压，从而使得液晶电容Clc3和Clc4间的液晶偏转极性不一致，所以像素电极14d看到的灰阶会较像素电极14c看到的灰阶暗。也就是说，GE层和SD层的图形重合精度（G/D Overlay）稍有误差便会导致液晶显示面板显示亮度不均的问题。
每一像素电容Cpix需考虑以下几个电容：液晶电容Clc、像素电极与公共电压线16之间的存储电容Cs、作为开关单元的开关单元的栅极和源极之间的寄生电容Cgs、以及数据线和像素电极14间的耦合电容Cpd。如前所述，图形重合精度的误差会导致数据线和像素电极间的耦合电容Cpd发生变化。又因为每一像素电容Cpix=Clc+Cs+Cgs+Cpd，所以数据线和像素电极间的耦合电容Cpd占像素电容Cpix的比例Q越大，则图形重合精度（G/D Overlay）导致液晶显示面板显示亮度不均越严重。因此如何改善因图形重合精度（G/D Overlay）误差导致耦合电容Cpd改变而造成亮度不均的问题，是业界努力的目标。
技术问题
本发明的目的在于提供一种液晶显示面板的制造方法以及一种像素单元，以解决现有液晶显示面板亮度不均匀的问题。
 技术解决方案
根据本发明的实施例，本发明揭露一种像素单元，电性连接一开关单元。所述像素单元包含像素电极、公共电压线、第一遮光线和第二遮光线。所述公共电压线位于所述像素电极之下，用来提供一公共电压。所述第一遮光线和第二遮光线位于所述像素电极之下且连接于所述公共电压线，所述第一和第二遮光线的至少一侧呈弯曲状且与所述公共电压线为同一金属层产生。
根据本发明的实施例，本发明另揭露一种液晶显示面板，其包含开关单元、电性连接所述开关单元的像素电极、一公共电压线、一第一遮光线和一第二遮光线。所述公共电压线位于所述像素电极之下，用来提供一公共电压。所述第一遮光线和第二遮光线皆位于所述像素电极之下且连接于所述公共电压线，所述第一和第二遮光线的至少一侧呈弯曲状且与所述公共电压线为同一金属层产生。
根据本发明的实施例，本发明又揭露一种液晶显示面板的制造方法，其步骤包含：提供一玻璃基板；蚀刻形成于所述玻璃基板上的第一金属层，以形成一薄膜晶体管的栅极、一公共电压线、一第一遮光线和一第二遮光线，所述第一和第二遮光线呈弯曲状；依序沉积一绝缘层、一主动层、一欧姆接触层和一第二金属层于所述玻璃基板以及所述第一金属层上；同时蚀刻所述主动层、所述欧姆接触层和所述第二金属层，以于所述栅极的上方形成直至所述主动层的开孔以及所述薄膜晶体管的源极和漏极；沉积一钝化层于所述第二金属层和所述绝缘层上；蚀刻所述钝化层以于所述漏极上方形成一接触窗；沉积一透明导电层于所述钝化层和所述接触窗上；蚀刻所述透明导电层以形成一连接所述漏极的像素电极。
根据本发明的实施例，所述第一遮光线和所述第二遮光线部分未重叠所述像素电极的一侧呈弯曲状。
根据本发明的实施例，所述第一遮光线和所述第二遮光线未重叠于所述像素电极的一侧呈波浪状或三角波状或方波状。
根据本发明的实施例，所述第一遮光线和所述第二遮光线重叠于所述像素电极的一侧与未重叠于所述像素电极的一侧呈非对称。
 有益效果
本发明的液晶显示面板在蚀刻第一金属层时，会形成所述开关单元的栅极、公共电压线、第一遮光线和第二遮光线。公共电压线电性连接于所述第一和第二遮光线，使得所述第一、第二遮光线和公共电压线同时作为存储电容的下极板。连接于公共电压线的弯曲状的第一、第二遮光线会扩大下极板的面积，也就是说存储电容也会同时增加。
附图说明
图1和图2分别显示形成的数据线相对于像素电极位置发生偏移的示意图。
图3是结合图1和图2的等效电路图。
图4显示第一实施例的像素单元的示意图。
图5至图8是本发明液晶显示面板的各掩膜制程的示意图。
图9显示第二实施例的像素单元的示意图。
图10显示第三实施例的像素单元的示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施之特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「顶」、「底」、「水平」、「垂直」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
请参阅图4，图4是本发明液晶显示面板的第一实施例的像素单元的示意图。液晶显示面板包含数个像素单元50，每一像素单元50包括开关单元13和像素电极15。开关单元13可以是薄膜晶体管或是其它具有开关功能的单元。当开关单元13接收来自扫描线32的扫描电压时，会将数据线30传来的数据电压经过开关单元13传输到像素电极15。液晶分子会依据传送至像素电极15的数据电压的电压差来控制其转动方向，据以决定光线的穿透程度。第一遮光线41和第二遮光线42连接于公共电压线43，而且与公共电压线43都是由同一金属层产生。以下先说明形成像素单元50的流程。
请参阅图5至图8，图5至图8是本发明液晶显示面板100的各掩膜制程的示意图。每一个图均代表一道掩膜制程，也就是说，完成液晶显示面板100必须经过四道掩膜制程。
请参阅图5，在此道制程中，会先于玻璃基板101上沉积第一金属层(未图示)并利用第一道掩膜进行显影制程。显影制程是在第一金属层上涂布光阻(未图示)后，依据具有特定图案的第一道掩膜利用一曝光机对光阻进行曝光再用显影剂(developer)将已曝光的光阻洗除。之后对第一金属层进行蚀刻制程。蚀刻制程是将没有光阻覆盖的第一金属层以强酸移除，而有光阻覆盖的第一金属层 (大致呈该特定图案)会产生开关单元的栅极131和下极板141，接着再洗除剩余的光阻。下极板141包括公共电极线43、第一遮光线41和第二遮光线42(请见图4)。由于此制程会形成栅极131，因此利用第一金属层于同一道掩膜形成的单元皆属于栅极(Gate electrode，GE)层。
请继续参阅图6，在此道制程中，首先会先沉积绝缘层(isolation layer)16，接着沉积主动层(active layer)17，再沉积欧姆接触层(n+ layer)18，最后再沉积第二金属层(未图示)，之后利用第二道掩膜进行显影制程，并且对主动层17、欧姆接触层18与该第二金属层进行蚀刻制程。在此掩膜制程中，对应于栅极131上方的欧姆接触层18与第二金属层会移除，而产生一开孔21以及开关单元的漏极132与源极133。由于此制程会形成漏极132与源极133，因此利用第二金属层于同一道掩膜形成的单元皆属于源/漏极(Source/Drain electrode，SD)层。请注意，对GE层和SD层的曝光可以利用同一曝光机或是不同的曝光机。
请继续参阅图7，在此道制程中，首先会先沉积钝化层(passivation layer)19，之后再利用第三道掩膜进行显影制程，并且对钝化层19进行蚀刻制程，以于源极133之上产生一接触窗(via)20。
最后请参阅图8，在此道制程中，首先会先沉积透明导电层，接着用第四道掩膜进行显影制程，并且对透明导电层进行蚀刻制程以产生像素电极15。
请继续参阅图4和图8，图8也是图4沿A-B-C切线的剖面图。如图8所示，在A、B两点间，开关单元13的栅极131是由第一金属层(GE layer)形成，而源极132与漏极133则是以第二金属层(SD layer)所形成。而于B、C两点间，下极板141也是由第一金属层形成。像素电极15与下极板141之间形成一存储电容Cs。第一遮光线41和第二遮光线42连接于公共电压线43，因此第一遮光线41、第二遮光线42和公共电压线43都会处于相同电平。同一电平的第一遮光线41、第二遮光线42和公共电压线43可视为下极板141。此外，第一遮光线41的一侧边411和第二遮光线42的一侧边421分别靠近数据线30、31，侧边411和侧边421呈弯曲型。优选地，侧边411和侧边421呈三角波形，而且侧边411和侧边421相互非对称。下极板141包括公共电压线43和侧边411和侧边421呈弯曲型的遮光线41、42，下极板141总面积会比只有直线状遮光线和公共电压线(如图1、图2所示)的总面积还要大。因为存储电容Cs是由像素电极15与下极板141重叠之处产生，因此当下极板141的面积越大，存储电容Cs的电容值也越大。
请参阅图9和图10，图9是本发明液晶显示面板的第二实施例的像素单元的示意图，图10是本发明液晶显示面板的第三实施例的像素单元的示意图。弯曲型的侧边411和侧边421不限定于三角波型，图9所示的第一遮光线41的侧边411和第二遮光线42的侧边421呈方波形，而图10所示的第一遮光线41的侧边411和第二遮光线42的侧边421呈波浪形。
本发明的液晶显示面板和其制作方法在蚀刻第一金属层时，会形成所述开关单元13的栅极131、公共电压线43、第一遮光线41和第二遮光线42。公共电压线43电性连接于第一遮光线41和第二遮光线42，使得第一遮光线41、第二遮光线42和公共电压线43同时作为存储电容Cs的下极板。一側具有弯曲型侧边411和侧边421的遮光线41、42连接于像素电极15会增加存储电容Cs下极板141的面积，因此存储电容Cs也会同时增加。综合以上，因为存储电容Cs增大，所以耦合电容Cpd占每一像素电容Cpix=Clc+Cs+Cgs+Cpd的比例Q减少。换言之，即使图形重合精度仍有误差，但是利用第一和第二遮光线41、42电性连接于公共电压线43的设计，可增大存储电容Cs，因此每一像素单元50的Q值仍然减少。这表示每一像素单元50受图形重合精度误差的影响大为降低，因此即使制造过程中液晶显示面板仍有图形重合精度的误差，液晶显示面板显示亮度不均的影响也会改善。
综上所述，虽然本发明已以较佳实施例揭露如上，但该较佳实施例并非用以限制本发明，该领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
 本发明的实施方式
工业实用性
序列表自由内容

Claims (18)

  1. 一种液晶显示面板的制造方法，其特征在于：
    提供一玻璃基板；
    蚀刻形成于所述玻璃基板上的第一金属层，以形成一薄膜晶体管的栅极、一公共电压线、一第一遮光线和一第二遮光线，所述第一和第二遮光线的至少一侧呈弯曲状；
    依序沉积一绝缘层、一主动层、一欧姆接触层和一第二金属层于所述玻璃基板以及所述第一金属层上；
    同时蚀刻所述主动层、所述欧姆接触层和所述第二金属层，以于所述栅极的上方形成直至所述主动层的开孔以及所述薄膜晶体管的源极和漏极；
    沉积一钝化层于所述第二金属层和所述绝缘层上；
    蚀刻所述钝化层以于所述漏极上方形成一接触窗；
    沉积一透明导电层于所述钝化层和所述接触窗上；以及
    蚀刻所述透明导电层以形成一连接所述漏极的像素电极。
  2. 根据权利要求1所述的制造方法，其特征在于：所述第一和第二遮光线未重叠于所述像素电极的一侧呈弯曲状。
  3. 根据权利要求2所述的制造方法，其特征在于：所述第一遮光线和所述第二遮光线未重疊于所述像素电极的一侧呈三角波状。
  4. 根据权利要求2所述的制造方法，其特征在于：所述第一遮光线和所述第二遮光线未重疊于所述像素电极的一侧呈方波状。
  5. 根据权利要求2所述的制造方法，其特征在于：所述第一遮光线和所述第二遮光线未重疊于所述像素电极的一侧呈波浪状。
  6. 根据权利要求1所述的制造方法，其特征在于：所述第一遮光线和所述第二遮光线重叠于所述像素电极的一侧与未重叠于所述像素电极的一侧呈非对称。
  7. 一种像素单元，电性连接一开关单元，其特征在于，所述像素单元包含：
    一像素电极；
    一公共电压线，位于所述像素电极之下，用来提供一公共电压；以及
    一第一遮光线和一第二遮光线，位于所述像素电极之下且连接于所述公共电压线，所述第一和第二遮光线的至少一侧呈弯曲状且与所述公共电压线为同一金属层产生。
  8. 根据权利要求7所述的像素单元，其特征在于：所述第一和第二遮光线未重叠于所述像素电极的一侧呈弯曲状。
  9. 根据权利要求8所述的像素单元，其特征在于：所述第一遮光线和所述第二遮光线未重叠于所述像素电极的一侧呈三角波状。
  10. 根据权利要求8所述的像素单元，其特征在于：所述第一遮光线和所述第二遮光线未重叠于所述像素电极的一侧呈方波状。
  11. 根据权利要求8所述的像素单元，其特征在于：所述第一遮光线和所述第二遮光线未重叠于所述像素电极的一侧呈波浪状。
  12. 根据权利要求7所述的像素单元，其特征在于：所述第一遮光线和所述第二遮光线重叠于所述像素电极的一侧与未重叠于所述像素电极的一侧呈非对称。
  13. 一种液晶显示面板，其包含开关单元和电性连接所述开关单元的像素电极，其特征在于：所述液晶显示面板还包含：
    一公共电压线，位于所述像素电极之下，用来提供一公共电压；以及
    一第一遮光线和一第二遮光线，位于所述像素电极之下且连接于所述公共电压线，所述第一和第二遮光线的至少一侧呈弯曲状且与所述公共电压线为同一金属层产生。
  14. 根据权利要求13所述的液晶显示面板，其特征在于：所述第一和第二遮光线未重叠于所述像素电极的一侧呈弯曲状。
  15. 根据权利要求14所述的液晶显示面板，其特征在于：所述第一遮光线和所述第二遮光线未重叠于所述像素电极的一侧呈三角波状。
  16. 根据权利要求14所述的液晶显示面板，其特征在于：所述第一遮光线和所述第二遮光线未重叠于所述像素电极的一侧呈方波状。
  17. 根据权利要求14所述的液晶显示面板，其特征在于：所述第一遮光线和所述第二遮光线未重叠于所述像素电极的一侧呈波浪状。
  18. 根据权利要求13所述的液晶显示面板，其特征在于：所述第一遮光线和所述第二遮光线重叠于所述像素电极的一侧与未重叠于所述像素电极的一侧呈非对称。
PCT/CN2010/079540 2010-11-24 2010-12-07 像素单元、液晶显示面板及其制造方法 WO2012068747A1 (zh)

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