WO2020077798A1 - 测试电路及显示装置 - Google Patents

测试电路及显示装置 Download PDF

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Publication number
WO2020077798A1
WO2020077798A1 PCT/CN2018/122004 CN2018122004W WO2020077798A1 WO 2020077798 A1 WO2020077798 A1 WO 2020077798A1 CN 2018122004 W CN2018122004 W CN 2018122004W WO 2020077798 A1 WO2020077798 A1 WO 2020077798A1
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WO
WIPO (PCT)
Prior art keywords
circuit
test
data lines
display panel
output
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/122004
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English (en)
French (fr)
Inventor
林佩欣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
Original Assignee
HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by HKC Co Ltd, Chongqing HKC Optoelectronics Technology Co Ltd filed Critical HKC Co Ltd
Priority to US17/042,315 priority Critical patent/US11145231B2/en
Publication of WO2020077798A1 publication Critical patent/WO2020077798A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1306—Details
    • G02F1/1309—Repairing; Testing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/14—Detecting light within display terminals, e.g. using a single or a plurality of photosensors
    • G09G2360/145—Detecting light within display terminals, e.g. using a single or a plurality of photosensors the light originating from the display screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • This application relates to the technical field of liquid crystal panels, in particular to a test circuit and a display device.
  • GOA circuit refers to the scanning line drive circuit directly prepared on the array substrate.
  • the GOA circuit includes multiple stages of sequentially connected shift registers, each shift register drives one Scanning line, and provide the start signal for the next stage shift register, so that the GOA circuit can achieve the purpose of enabling the scan line line by line.
  • the GOA technology not only saves costs, but also can save the bonding process in the gate direction, which is extremely beneficial to increase the production capacity and improve the integration of the display panel.
  • bilateral GOA circuits are generally used for driving, that is, GOA circuits are provided on both sides of the array substrate to drive each row of scanning lines on the panel together.
  • GOA circuits are provided on both sides of the array substrate to drive each row of scanning lines on the panel together.
  • array defects caused by broken scanning lines or data lines display defects caused by defects in the gate drive circuit or source drive circuit
  • all pixels on the panel need to be charged uniformly, that is, array synthesis Detection (Array Test AT)
  • Array Test AT array synthesis Detection
  • the exemplary array detection is provided with multiple test pads outside the panel to be tested, and the data signals are written bilaterally, and then the sensor is used to sense the panel. Pixel intensity, which detects poor electrical properties of pixels, thereby improving production yield.
  • the detection signal is written to the display panel at both ends at the same time, if there is a problem with the writing of the data signal on one side, it may not be possible to know whether there is a problem with the upper data line or a problem with the lower data line, so a false judgment may occur.
  • the main purpose of the present application is to provide a test circuit, which aims to solve the problem of not knowing whether the upper end data line is abnormal or the lower end data line is abnormal when there is a problem in writing the data signal.
  • a test circuit proposed by the present application is configured to test a display panel, the display panel having N first data lines and N second data lines, and the test circuit includes:
  • N first test pads configured to connect to the corresponding N first data lines
  • N second test pads configured to connect corresponding N second data lines
  • a first test circuit configured to output a plurality of data signals for testing the display panel to N first test pads and N second test pads;
  • Switching circuit including N first switching circuits and N second switching circuits, N first switching circuits are arranged one-to-one on N first data lines; N second switching circuits One to one set on the N second data lines; and
  • a control circuit configured to control the N first switch circuits to be individually turned on or control the N second switch circuits to be individually turned on, so that a plurality of the data signals are output to the data lines corresponding to the display panel for display Panel test, and determine whether the N first data lines or the N second data lines are working normally according to the lighting state of the display panel.
  • the first data line or the second data line is a data line connecting the test pad and the pixels on the display panel.
  • the test circuit further includes a pixel detection circuit, the pixel detection circuit is disposed on the display panel, and the pixel detection circuit is configured to detect that the N first switch circuits are individually turned on or N When the second switch circuit is individually turned on, the electric field intensity or pixel brightness of the pixels on the display panel, and outputs a feedback signal to the control circuit for the control circuit to determine the N first data lines or N Whether the second data line is working normally.
  • control circuit is specifically configured to: when the first test circuit outputs a data signal, output a first enable signal to the N first switch circuits to turn on and output a second Enable signals to N second switching circuits to turn them off, and receive the feedback signal output from the pixel detection circuit and compare the preset electric field strength to or the preset pixel brightness value, and the feedback signal is less than the When the electric field strength is set to or a preset pixel brightness value, it is judged that the N first data lines are abnormal; and the first enable signal is output to the N second switch circuits to turn on and output the second enable Signal to the N first switch circuits to turn them off, and receive the feedback signal output from the pixel detection circuit and compare the preset electric field strength to or the preset pixel brightness value, when the feedback signal is less than the preset electric field When the intensity reaches or presets the pixel brightness value, it is judged that the N second data lines are abnormal.
  • it further includes a third test pad and a fourth test pad, the controlled ends of the N first switch circuits are interconnected with the signal output ends of the third test pad, and the N test pads The controlled terminal of the second switch circuit is interconnected with the signal output terminal of the fourth test pad.
  • N of the first test pads, N of the second test pads, the third test pads and the fourth test pads are arranged side by side and parallel to the display panel .
  • both the first switch circuit and the second switch circuit are MOS transistors.
  • the first switch circuit and the second switch circuit are NMOS transistors.
  • control circuit and the first test circuit are integrated on a circuit board.
  • control circuit includes a level output circuit and a first control circuit.
  • the first signal output terminal of the level output circuit is connected to the controlled terminals of the N first switch circuits.
  • the second signal output terminal of the level output circuit is connected to N controlled terminals of the second switching circuit, the controlled terminal of the level output circuit is connected to the control terminal of the first control circuit, and the first The signal input terminal of a control circuit is connected to the signal output terminal of the pixel detection circuit.
  • the present invention also provides a test circuit configured to test a display panel having N first data lines and N second data lines.
  • the test circuit includes:
  • N first test pads configured to connect to the corresponding N first data lines
  • N second test pads configured to connect corresponding N second data lines
  • a first test circuit configured to output a plurality of data signals for testing the display panel to N first test pads and N second test pads;
  • Switching circuit including N first switching circuits and N second switching circuits, N first switching circuits are arranged one-to-one on N first data lines; N second switching circuits One-to-one set on the N second data lines;
  • a control circuit configured to control the N first switch circuits to be individually turned on or to control the N second switch circuits to be individually turned on;
  • a third test pad configured for the control circuit to output a first control signal to the N first switch circuits to control the N first switch circuits to be turned on or off;
  • a fourth test pad configured to allow the control circuit to output a second control signal to the N first switch circuits to control the N second switch circuits to be turned on or off;
  • the pixel detection circuit is configured to detect the electric field intensity or pixel brightness of the pixels on the display panel when N first switch circuits are individually turned on or N second switch circuits are individually turned on, and output a feedback signal to the A control circuit for the control circuit to determine whether the N first data lines or the N second data lines are working normally.
  • the invention also proposes a display device, the display panel testing device includes a display panel;
  • the driving circuit includes the test circuit.
  • the test circuit is configured to test a display panel.
  • the display panel has N first data lines and N second data lines.
  • the test circuit includes:
  • N first test pads configured to connect to the corresponding N first data lines
  • N second test pads configured to connect corresponding N second data lines
  • a first test circuit configured to output a plurality of data signals for testing the display panel to N first test pads and N second test pads;
  • Switching circuit including N first switching circuits and N second switching circuits, N first switching circuits are arranged one-to-one on N first data lines; N second switching circuits One to one set on the N second data lines; and
  • a control circuit configured to control the N first switch circuits to be individually turned on or to control the N second switch circuits to be individually turned on, so that a plurality of the data signals are output to data lines corresponding to the display panel Perform a display panel test and determine whether the N first data lines or the N second data lines are working normally according to the lighting state of the display panel.
  • the first data line or the second data line is a data line connecting the test pad and the pixels on the display panel.
  • the test circuit further includes a pixel detection circuit, the pixel detection circuit is disposed on the display panel, and the pixel detection circuit is configured to detect that the N first switch circuits are individually turned on or N When the second switch circuit is individually turned on, the electric field intensity or pixel brightness of the pixels on the display panel, and outputs a feedback signal to the control circuit for the control circuit to determine the N first data lines or N Whether the second data line is working normally.
  • control circuit is specifically configured as:
  • the first test circuit When the first test circuit outputs a data signal, it outputs a first enable signal to the N first switch circuits to make it conductive and outputs a second enable signal to the N second switch circuits to make It is turned off, and receives the feedback signal output by the pixel detection circuit and compares the preset electric field strength to or the preset pixel brightness value, and judges N when the feedback signal is less than the preset electric field strength to or the preset pixel brightness value
  • the first data line is abnormal;
  • it further includes a third test pad and a fourth test pad, the controlled ends of the N first switch circuits are interconnected with the signal output ends of the third test pad, and the N test pads The controlled terminal of the second switch circuit is interconnected with the signal output terminal of the fourth test pad.
  • N of the first test pads, N of the second test pads, the third test pads and the fourth test pads are arranged side by side and parallel to the display panel .
  • both the first switch circuit and the second switch circuit are MOS transistors.
  • control circuit and the first test circuit are integrated on a circuit board.
  • control circuit includes a level output circuit and a first control circuit.
  • the first signal output terminal of the level output circuit is connected to the controlled terminals of the N first switch circuits.
  • the second signal output terminal of the level output circuit is connected to N controlled terminals of the second switching circuit, the controlled terminal of the level output circuit is connected to the control terminal of the first control circuit, and the first The signal input terminal of a control circuit is connected to the signal output terminal of the pixel detection circuit.
  • the technical solution of the present application forms a test circuit by using N first test pads, N second test pads, first test circuits, switch circuits, and control circuits, and the first test circuit outputs data through N first test pads
  • the signals are output to the N first data lines of the display panel and output data signals to the N second data lines of the display panel through the N second test pads to charge the pixels of the display panel.
  • the switch circuit includes N first switch circuits corresponding to N first data lines and N second switch circuits provided on N second data lines, and the control circuit outputs
  • the control signal to the switch circuit enables N first switch circuits to be simultaneously turned on simultaneously or controls N second switch circuits to be turned on simultaneously at the same time, thereby realizing unilateral testing of the display panel and judging the N first data lines according to the brightness of the display panel Or the working state of N second data lines, thereby solving the problem of not being able to know whether the upper data line is abnormal or the lower data line is abnormal when writing data signals, and when judging the first data line and the second After the working state of the data line, it can be repaired accordingly, thereby improving the yield rate of the display panel.
  • 1 is a schematic diagram of functional modules of an embodiment of the test circuit of the application.
  • FIG. 2 is a schematic diagram of functional modules of another embodiment of the test circuit of the present application.
  • FIG. 3 is a schematic diagram of functional modules of an embodiment of a display device of the present application.
  • a test circuit proposed by the present application is configured to test a display panel 200, the display panel 200 having N first data lines L1 and N second data lines L2.
  • FIG. 1 is a schematic diagram of functional modules of an embodiment of a test circuit of the present application.
  • the test circuit includes:
  • N first test pads P1 set to connect to the corresponding N first data lines L1;
  • the first test circuit 10 is configured to output a plurality of data signals of the test display panel 200 to N first test pads P1 and N second test pads P2;
  • a switch circuit (not shown in the figure) includes N first switch circuits 21 and N second switch circuits 22, and the N first switch circuits 21 are provided one-to-one on the N first data lines L1 N; the second switch circuit 22 is provided one to one on the N second data line L2;
  • the control circuit 30 is configured to control the N first switch circuits 21 to be individually turned on or control the N second switch circuits 22 to be individually turned on, so that a plurality of the data signals are output to data corresponding to the display panel 200 Perform a display panel test online, and determine whether the N first data lines L1 or the N second data lines L2 are working normally according to the 200 pixel lighting state of the display panel.
  • the array comprehensive detection can realize the detection of conductive lines such as signal lines.
  • Exemplary array detection is provided with multiple test pads outside the panel to be detected, and the data signals are written bilaterally.
  • N The first data line L1 and the N second data lines L2 respectively receive data signals from the first test circuit 10 to charge all pixels.
  • the first data line L1 or the second data line L2 is a test pad to the outer edge of the display panel 200
  • the total length of the data line and the data line inside the display panel 200, a plurality of switch circuits in the switch circuit are provided on the data line between the test pad and the display panel 200, the test pad is provided outside the size of the display panel 200, And cut after the panel test is completed.
  • the first test pad P1 and the second test pad P2 may be distributed around the display panel 200, in a pin-shaped or on one side of the display panel 200, and may be specifically designed according to actual conditions.
  • the first test circuit 10 is configured to input data signals to charge the pixels on the display panel 200 when the display panel 200 performs an array test.
  • the first test circuit 10 passes through the probe and the first test pad P1 and the second test pad P2
  • the control circuit 30 may be integrated with the first test circuit 10 on the same circuit board.
  • the first switch circuit 21 and the second switch circuit The state of 22 must be kept the opposite, so that the first data line L1 and the second data line L2 are tested separately.
  • Both the first switching circuit 21 and the second switching circuit 22 in the switching circuit can use switching components with shut-off capability Or the switch circuit can be designed according to the actual situation.
  • the gate drive circuits are all in a normal working state, that is, the GOA circuit receives the drive signal normally, the control circuit 30 controls the N first switch circuits 21 to turn on and controls the N second switch circuits 22 to turn off, the A test circuit 10 inputs data signals into the N first data lines L1 through the N first test pads P1, and charges pixels connected to the N first data lines L1, because the second data line L2 is turned off The pixels connected to the second data line L2 do not work. Therefore, when the display panel 200 is not lit or the brightness is dim, it means that the N first data lines L1 are abnormal. If the display panel 200 is normally lit , It means that the N first data lines L1 are normal;
  • the control circuit 30 controls the N second switch circuits 22 to turn on and controls the N first switch circuits 21 to turn off, and the first test circuit 10 inputs the data signal to the N second test pads through the N second test pads P2 In the data line L2, the pixels connected to the N second data lines L2 are charged. Since the first data line L1 is turned off, the pixels connected to the first data line L1 do not work. Therefore, when the display panel is found If 200 is not lit or the brightness is dark, it means that the N second data lines L2 are abnormal. If the display panel 200 is normally lit, it means that the N second data lines L2 are normal. According to the N first switch circuits 21 and the N second switch circuits 22 are individually turned off or turned on, the working states of the N first data lines L1 and the N second data lines L2 can be judged, that is, possible There are four situations:
  • N first data lines L1 and N second data lines L2 are in a normal state; (2) N first data lines L1 are in a normal state, and N second data lines L2 are in an abnormal state; (3 ) N second data lines L2 are in a normal state, and N first data lines L1 are in an abnormal state; (4) N first data lines L1 and N second data lines L2 are in an abnormal state.
  • the array defect repair can be performed correspondingly, usually by laser processing, thereby improving the yield rate of the display panel 200 .
  • the technical solution of the present application forms a test circuit by using N first test pads P1, N second test pads P2, a first test circuit 10, a switch circuit, and a control circuit 30, and the first test circuit 10 passes the N first test pads
  • the test pad P1 outputs a data signal to the N first data lines L1 of the display panel 200 and outputs the data signal to the N second data lines L2 of the display panel 200 through the N second test pads P2, to the display panel 200 pixels for charging.
  • the switch circuit includes N first switch circuits 21 corresponding to N first data lines L1 and N second switch circuits 22 provided on N second data lines L2,
  • the control circuit 30 outputs the control signal to the switch circuit to enable the N first switch circuits 21 to be simultaneously turned on simultaneously or to control the N second switch circuits 22 to be simultaneously turned on separately, thereby realizing the unilateral test of the display panel 200 and according to the display panel 200 brightness to determine the working status of N first data lines L1 or N second data lines L2, thus solving the problem of not knowing whether the upper data line is abnormal or the lower data line is abnormal when there is a problem in writing the data signal, Moreover, after determining the operating states of the first data line L1 and the second data line L2, corresponding repairs can be performed to improve the yield of the display panel 200.
  • the test circuit further includes a pixel detection circuit 40, the pixel detection circuit 40 is disposed on the display panel 200, and the pixel detection circuit 40 is configured to detect the N first switches When the circuit 21 is individually turned on or the N second switching circuits 22 are individually turned on, the electric field intensity or pixel brightness of the pixels on the display panel 200 and outputs a feedback signal to the control circuit 30 for the control circuit 30 Determine whether the N first data lines or the N second data lines are working normally.
  • the pixel detection circuit 40 is placed on the display panel 200.
  • the pixel detection circuit 40 may use a sensor to sense the surface electric field intensity of the pixels of the display panel 200, or use a lighting box or other equipment to collect the surface brightness of the display panel 200, which can be flexibly selected according to actual conditions No specific restrictions are made here.
  • the gate drive circuits are all in a normal working state, that is, the GOA circuit normally receives the drive signal, the control circuit 30 controls the N first switch circuits 21 to be turned on, and controls the N second switch circuits 22 to be turned off.
  • a test circuit 10 inputs data signals into the N first data lines L1 through the N first test pads P1, and charges pixels connected to the N first data lines L1, and the pixel detection circuit 40 detects pixels Since the second data line L2 is turned off, the pixels connected to the second data line L2 do not work. Therefore, when the feedback signal output by the pixel detection circuit 40 is less than the preset value, it means N The first data line L1 is abnormal. If the feedback signal is greater than the preset value, it means that the N first data lines L1 are normal;
  • the control circuit 30 controls the N second switch circuits 22 to turn on and controls the N first switch circuits 21 to turn off, and the first test circuit 10 inputs the data signal to the N second test pads through the N second test pads P2 In the data line L2, the pixels connected to the N second data lines L2 are charged.
  • the pixel detection circuit 40 detects the electric field intensity or brightness of the pixels. Since the first data line L1 is turned off, it is connected to the first data line. None of the pixels connected to L1 work. Therefore, when the feedback signal output by the pixel detection circuit 40 is less than the preset value, it means that the N second data lines L2 are abnormal. If the feedback signal is greater than the preset value, it means N The second data line L2 is normal.
  • control circuit 30 is specifically configured as:
  • the first test circuit 10 When the first test circuit 10 outputs a data signal, it outputs a first enable signal to the N first switch circuits 21 to turn it on and outputs a second enable signal to the N second switch circuits 22 to turn it off, and receive the feedback signal output from the pixel detection circuit 40 and compare with the preset electric field strength to or preset pixel brightness value, when the feedback signal is less than the preset electric field strength to or preset pixel brightness value , It is judged that the N first data lines L1 are abnormal; and,
  • the feedback signal output by the circuit 40 is compared with a preset electric field strength to or a preset pixel brightness value, and when the feedback signal is less than a preset electric field strength to or a preset pixel brightness value, it is determined that the N second data lines L2 are abnormal .
  • control circuit 30 usually conducts the N first switch circuits 21 and the N second switch circuits 22 in two steps, and separately tests the connected data lines.
  • the first switch circuit 21 may be It is set at the upper end or the lower end of the display panel 200.
  • the second switch circuit 22 can be set at the lower end or the upper end of the display panel 200.
  • the first enable signal can be high level or low level
  • the second enable signal can be Low level or high level
  • the control circuit 30 outputs a first enable signal to control the N first switch circuits 21 to turn on and output a second enable signal Control the N second switch circuits 22 to be turned off, assuming that the first enable signal is at a high level and the second enable signal is at a low level
  • the first test circuit 10 inputs data through the N first test pads P1 The signal goes into the N first data lines L1 and charges the pixels connected to the N first data lines L1.
  • the pixel detection circuit 40 detects the electric field intensity or brightness of the pixels, because the second data line L2 is turned off , With the second data line L2 None of the connected pixels work. Therefore, if the feedback signal output by the pixel detection circuit 40 is less than the preset electric field strength or the preset pixel brightness value, it means that the N first data lines L1 are abnormal. If the feedback signal is greater than or When it is equal to the preset electric field strength or the preset pixel brightness value, it means that the N first data lines L1 are normal;
  • the control circuit 30 After the N first test lines are determined, the control circuit 30 outputs a second enable signal to control the N first switch circuits 21 to turn off and outputs a first enable signal to control the N second switch circuits 22 to turn on.
  • a test circuit 10 inputs data signals into the N second data lines L2 through the N second test pads P2, and charges pixels connected to the N second data lines L2, and the pixel detection circuit 40 detects pixels Since the first data line L1 is turned off, the pixels connected to the first data line L1 do not work. Therefore, if the feedback signal output by the pixel detection circuit 40 at this time is less than the preset value, it means The N second data lines L2 are abnormal. If the feedback signal is greater than or equal to the preset electric field strength or the preset pixel brightness value, it means that the N second data lines L2 are normal.
  • it further includes a third test pad P3 and a fourth test pad P4, N controlled terminals of the first switch circuit 21 and signal output terminals of the third test pad P3
  • the controlled terminals of the N second switch circuits 22 are interconnected with the signal output terminal of the fourth test pad P4.
  • the control circuit 30 outputs a control signal to the corresponding first switch circuit 21 and the third test pad P3 and the fourth test pad P4, respectively.
  • Two switch circuits 22, and the controlled ends of the N first switch circuits 21 are connected in parallel with the third test pad P3, and the controlled ends of the N second switch circuits 22 are connected in parallel with the fourth test pad P4 Interconnect to achieve the purpose of simplifying the circuit structure and reducing the design cost.
  • N first test pads P1, N second test pads P2, third test pads P3, and fourth test pads P4 are side by side with and The display panels 200 are arranged in parallel.
  • the plurality of test pads are arranged in a row, and the size of the display panel 200 is outside and parallel to the display panel 200. Therefore, the control circuit 30 and the third test pad P3 and the fourth test pad The connecting line between P4 can be designed to be shorter, so as to simplify the circuit structure and reduce the design cost.
  • both the first switch circuit 21 and the second switch circuit 22 are MOS transistors.
  • each MOS tube is correspondingly connected to the third test pad P3 and the fourth test pad P4 respectively.
  • the test pad outputs high and low levels to control the MOS tube to turn on or off.
  • the drain or source is set to receive the data signal, and output from the source or drain of each MOS tube to each pixel of the display panel 200, and then separately charge each pixel of the display panel 200 on the same side.
  • Type of MOS tube You can choose NMOS tube or PMOS tube, you can choose according to the specific situation.
  • the switch circuit is an NMOS transistor.
  • each NMOS tube is respectively connected to the third test pad P3 and the fourth test pad P4.
  • the test pad outputs a high level to control the conduction of the NMOS tube, and a low level to control the NMOS tube
  • the drain or source of each NMOS tube is set to receive the data signal, and output the data signal from the source of each NMOS tube to each pixel of the display panel 200, and then separate each pixel of the display panel 200 on the same side
  • each NMOS tube is turned on or off on one side according to the different control signals received, thereby achieving independent detection of the data line.
  • FIG. 2 is a schematic diagram of functional modules of another embodiment of the test circuit of the present application.
  • the control circuit 30 includes a level output circuit 31 and a first control circuit 32.
  • the first signal output terminal of the level output circuit 31 is connected to the controlled terminals of the N first switch circuits 21, and the second signal output terminal of the level output circuit 31 is connected to the N second switch circuits 22
  • the controlled end of the level output circuit 31 is connected to the control end of the first control circuit 32, the signal input end of the first control circuit 32 is connected to the signal of the pixel detection circuit 40 The output is connected.
  • the level output circuit 31 is controlled by the control signal output by the first control circuit 32.
  • the level output circuit 31 includes a first level output terminal and a second level output terminal.
  • the first level output terminal passes The third test pad P3 is connected to the controlled ends of the N first switch circuits 21, the second level output terminal is connected to the controlled ends of the N second switch circuits 22 through the fourth test pad P4, and the first control
  • the circuit 32 is configured to receive the feedback signal output by the pixel detection circuit 40 and compare it with the preset electric field strength or preset brightness value.
  • the first control circuit 32 outputs different high and low levels through the control level output circuit 31 to control the first switch
  • the circuit 21 or the second switch circuit 22 is individually turned on or off, and then the working states of the first data line L1 and the second data line L2 are judged.
  • the level output circuit 31 may use a signal generator, a level shifter or
  • the first control circuit 32 may use a microprocessor, a programmable controller, or the like.
  • control circuit 30 can also be integrated with the first test circuit 10 on the same circuit board, or integrated into the same chip, thereby further simplifying the structure of the test circuit.
  • control circuit 30 is also connected to a terminal device, and the control circuit 30 feeds back the working state of the first data line L1 and the working state of the second data line L2 to the Terminal Equipment.
  • the control circuit 30 drives the pixel corresponding to the first data line L1 and the pixel corresponding to the second data line L2
  • the first data line L1 and the second data line are determined according to the feedback signal output by the pixel detection circuit 40
  • the control circuit 30 indicates the working states of the first data line L1 and the second data line L2 as 1 and 0 or in text.
  • control circuit 30 can output 1 and 1, 1 and 0, 0 and 1, 0 and 0, the tester can determine which end of the data line is abnormal according to the value, and then perform corresponding repairs, thereby improving the yield of the display panel 200.
  • the present invention also provides a test circuit configured to test a display panel 200 having N first data lines L1 and N second data lines L2.
  • the test circuit includes:
  • test circuit configured to test a display panel 200 having N first data lines L1 and N second data lines L2, wherein the test circuit includes:
  • N first test pads P1 set to connect to the corresponding N first data lines L1;
  • the first test circuit 10 is configured to output a plurality of data signals of the test display panel 200 to N first test pads P1 and N second test pads P2;
  • a switch circuit includes N first switch circuits 21 and N second switch circuits 22, and the N first switch circuits 21 are arranged one-to-one on the N first data lines L1;
  • the second switch circuit 22 is disposed one-to-one on the N second data lines L2;
  • the control circuit 30 is configured to control N first switch circuits 21 to be individually turned on or to control N second switch circuits 22 to be individually turned on;
  • the third test pad P3 is provided for the control circuit 30 to output a first control signal to the N first switch circuits 21 to control the N first switch circuits 21 to be turned on or off;
  • the fourth test pad P4 is provided for the control circuit 30 to output a second control signal to the N first switch circuits 21 to control the N second switch circuits 22 to be turned on or off;
  • the pixel detection circuit 40 is configured to detect the electric field intensity or pixel brightness of the pixels on the display panel 200 when the N first switch circuits 21 are individually turned on or the N second switch circuits 22 are individually turned on, and output feedback A signal is sent to the control circuit 30 for the control circuit 30 to determine whether the N first data lines L1 or the N second data lines L2 work normally.
  • FIG. 3 is a schematic diagram of functional modules of an embodiment of a display device of the present application.
  • the present application also proposes a display device 1000.
  • the display device 1000 includes a display panel 200 and a driving circuit 300, wherein the driving circuit 300 includes the test circuit as described above.
  • the specific structure of the test circuit refers to the above-mentioned embodiments. Since the driving circuit 300 adopts all the technical solutions of all the above-mentioned embodiments, it has at least all of the technical solutions of the above-mentioned embodiments. The technical effects will not be repeated here.
  • the driving circuit 300 outputs a driving signal to the display panel 200 to drive the panel, and can detect the N first data lines L1 and the N second data lines L2 of the display panel 200 to determine the first data After the working states of the line L1 and the second data line L2, corresponding repairs can be performed to improve the yield of the display panel 200.

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Abstract

一种测试电路及显示装置，测试电路包括N个第一测试衬垫（P1）、N个第二测试衬垫（P2）、第一测试电路（10）、开关电路以及控制电路（30），第一测试电路（10）设置为输出多个测试信号至测试衬垫（P1、P2），控制电路（30）通过输出控制信号至开关电路使N个第一开关电路（21）单独同时导通或者控制N个第二开关电路（22）单独同时导通，从而实现对显示面板（200）单边测试，并根据显示面板（200）亮度判断N个第一数据线（L1）或者N个第二数据线（L2）的工作状态。

Description

测试电路及显示装置
相关申请
本申请要求2018年10月17日申请的，申请号为201811212054.9，名称为“测试电路及显示装置”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及液晶面板技术领域，特别涉及一种测试电路及显示装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。显示屏的工艺架构，以门极驱动设计来分，可以分为SOC(System on chip)和GOA(Gate driver on array) 两种，GOA电路在面板设计上是一项重要技术，GOA电路是指直接制备在阵列基板上的扫描线驱动电路，GOA电路包括多级依次连接的移位寄存器，每个移位寄存器驱动一条扫描线，并为下一级移位寄存器提供开启信号，从而GOA电路整体上可实现使扫描线逐行开启的目的。GOA技术相比示例性工艺，不仅节省了成本，同时由于可以省去栅极方向上的绑定工艺，对提升产能极为有利，并提高了显示面板的集成度。
对于大尺寸面板，一般采用双边GOA电路驱动，即在阵列基板两侧均设有GOA电路，一起驱动面板上的各行扫描线。当GOA电路的某个位置存在短接、断开等故障时，会将导致故障位置之后的各级移位寄存器不能正常工作，进而导致显示异常。在阵列基板生产过程中，当阵列基板上的功能模块存在缺陷时，显示过程中会出现各种与阵列基板有关的不良。例如，扫描线或数据线断线引起的显示不良，栅极驱动电路或源极驱动电路缺陷引起的显示不良，因此，阵列基板制成后需要对面板上的所有像素统一充电，即进行阵列综合检测（Array Test AT），阵列综合检测可实现对信号线等导电线路进行检测，示例性的阵列检测在待检测面板外设置多个测试衬垫，同时双边进行数据信号的写入，然后通过传感器感知面板上的像素强度，检测出像素的电学性不良，从而提高生产良率。
但是，因为检测信号是同时双端写入显示面板的，如果因为一边的数据信号写入有问题，可能无法得知是上端数据线出问题或是下端数据线有问题，因此可能出现误判。
发明内容
本申请的主要目的是提供一种测试电路，旨在解决在数据信号写入有问题时，无法得知是上端数据线异常还是下端数据线异常的问题。
为实现上述目的，本申请提出的一种测试电路，设置为测试显示面板，所述显示面板具有N个第一数据线及和N个第二数据线，所述测试电路包括：
N个第一测试衬垫，设置为连接对应的N个所述第一数据线；
N个第二测试衬垫，设置为连接对应的N个所述第二数据线；
第一测试电路，设置为输出测试显示面板的多个数据信号至N个所述第一测试衬垫和N个所述第二测试衬垫；
开关电路，包括N个第一开关电路和N个第二开关电路，N个所述第一开关电路一对一的设置于N个所述第一数据线上；N个所述第二开关电路一对一的设置于N个所述第二数据线上；以及
控制电路，设置为控制N个所述第一开关电路单独导通或者控制N个所述第二开关电路单独导通，以使多个所述数据信号输出至显示面板对应的数据线上进行显示面板测试，并根据所述显示面板点亮状态判断N个所述第一数据线或者N个所述第二数据线是否正常工作。
在一实施例中，所述第一数据线或者第二数据线为连接测试衬垫和所述显示面板上的像素之间的数据线。
在一实施例中，所述测试电路还包括像素检测电路，所述像素检测电路设置在所述显示面板上，所述像素检测电路设置为检测N个所述第一开关电路单独导通或者N个所述第二开关电路单独导通时显示面板上的像素的电场强度或者像素亮度，并输出反馈信号至所述控制电路，以供所述控制电路判断N个所述第一数据线或者N个所述第二数据线是否正常工作。
在一实施例中，所述控制电路具体设置为：在所述第一测试电路输出数据信号时，输出第一使能信号至N个所述第一开关电路以使其导通以及输出第二使能信号至N个所述第二开关电路以使其关断，并接收所述像素检测电路输出的反馈信号与预设电场强度至或者预设像素亮度值比较，在所述反馈信号小于预设电场强度至或者预设像素亮度值时，判断N个所述第一数据线异常；以及输出第一使能信号至N个所述第二开关电路以使其导通以及输出第二使能信号至N个所述第一开关电路以使其关断，并接收所述像素检测电路输出的反馈信号与预设电场强度至或者预设像素亮度值比较，在所述反馈信号小于预设电场强度至或者预设像素亮度值时，判断N个所述第二数据线异常。
在一实施例中，还包括第三测试衬垫和第四测试衬垫，N个所述第一开关电路的受控端与所述第三测试衬垫的信号输出端互连，N个所述第二开关电路的受控端与所述第四测试衬垫的信号输出端互连。
在一实施例中，N个所述第一测试衬垫、N个所述第二测试衬垫、所述第三测试衬垫及所述第四测试衬垫并排且与所述显示面板平行设置。
在一实施例中，所述第一开关电路及所述第二开关电路均为MOS管。
在一实施例中，所述第一开关电路及所述第二开关电路为NMOS管。
在一实施例中，所述控制电路与所述第一测试电路集成在电路板上。
在一实施例中，所述控制电路包括电平输出电路及第一控制电路，所述电平输出电路的第一信号输出端与N个所述第一开关电路的受控端连接，所述电平输出电路的第二信号输出端与N个所述第二开关电路的受控端连接，所述电平输出电路的受控端与所述第一控制电路的控制端连接，所述第一控制电路的信号输入端与所述像素检测电路的信号输出端连接。
本发明还提出一种测试电路，设置为测试显示面板，所述显示面板具有N个第一数据线及和N个第二数据线，所述测试电路包括：
N个第一测试衬垫，设置为连接对应的N个所述第一数据线；
N个第二测试衬垫，设置为连接对应的N个所述第二数据线；
第一测试电路，设置为输出测试显示面板的多个数据信号至N个所述第一测试衬垫和N个所述第二测试衬垫；
开关电路，包括N个第一开关电路和N个第二开关电路，N个所述第一开关电路一对一的设置于N个所述第一数据线上；N个所述第二开关电路一对一的设置于N个所述第二数据线上；
控制电路，设置为控制N个所述第一开关电路单独导通或者控制N个所述第二开关电路单独导通；
第三测试衬垫，设置为供所述控制电路输出第一控制信号至N个所述第一开关电路以控制N个所述第一开关电路导通或者关断；
第四测试衬垫，设置为供所述控制电路输出第二控制信号至N个所述第一开关电路以控制N个所述第二开关电路导通或者关断；以及
像素检测电路，设置为检测N个所述第一开关电路单独导通或者N个所述第二开关电路单独导通时显示面板上的像素的电场强度或者像素亮度，并输出反馈信号至所述控制电路，以供所述控制电路判断N个所述第一数据线或者N个所述第二数据线是否正常工作。
本发明还提出一种显示装置，该显示面板测试装置包括显示面板；
驱动电路；
其中，所述驱动电路包括所述测试电路，所述测试电路设置为测试显示面板，所述显示面板具有N个第一数据线及和N个第二数据线，所述测试电路包括：
N个第一测试衬垫，设置为连接对应的N个所述第一数据线；
N个第二测试衬垫，设置为连接对应的N个所述第二数据线；
第一测试电路，设置为输出测试显示面板的多个数据信号至N个所述第一测试衬垫和N个所述第二测试衬垫；
开关电路，包括N个第一开关电路和N个第二开关电路，N个所述第一开关电路一对一的设置于N个所述第一数据线上；N个所述第二开关电路一对一的设置于N个所述第二数据线上；以及
控制电路，设置为控制N个所述第一开关电路单独导通或者控制N个所述第二开关电路单独导通，以使多个所述数据信号输出至所述显示面板对应的数据线上进行显示面板测试，并根据所述显示面板点亮状态判断N个所述第一数据线或者N个所述第二数据线是否正常工作。
在一实施例中，所述第一数据线或者第二数据线为连接测试衬垫和所述显示面板上的像素之间的数据线。
在一实施例中，所述测试电路还包括像素检测电路，所述像素检测电路设置在所述显示面板上，所述像素检测电路设置为检测N个所述第一开关电路单独导通或者N个所述第二开关电路单独导通时显示面板上的像素的电场强度或者像素亮度，并输出反馈信号至所述控制电路，以供所述控制电路判断N个所述第一数据线或者N个所述第二数据线是否正常工作。
在一实施例中，所述控制电路具体设置为：
在所述第一测试电路输出数据信号时，输出第一使能信号至N个所述第一开关电路以使其导通以及输出第二使能信号至N个所述第二开关电路以使其关断，并接收所述像素检测电路输出的反馈信号与预设电场强度至或者预设像素亮度值比较，在所述反馈信号小于预设电场强度至或者预设像素亮度值时，判断N个所述第一数据线异常；以及
输出第一使能信号至N个所述第二开关电路以使其导通以及输出第二使能信号至N个所述第一开关电路以使其关断，并接收所述像素检测电路输出的反馈信号与预设电场强度至或者预设像素亮度值比较，在所述反馈信号小于预设电场强度至或者预设像素亮度值时，判断N个所述第二数据线异常。
在一实施例中，还包括第三测试衬垫和第四测试衬垫，N个所述第一开关电路的受控端与所述第三测试衬垫的信号输出端互连，N个所述第二开关电路的受控端与所述第四测试衬垫的信号输出端互连。
在一实施例中，N个所述第一测试衬垫、N个所述第二测试衬垫、所述第三测试衬垫及所述第四测试衬垫并排且与所述显示面板平行设置。
在一实施例中，所述第一开关电路及所述第二开关电路均为MOS管。
在一实施例中，所述控制电路与所述第一测试电路集成在电路板上。
在一实施例中，所述控制电路包括电平输出电路及第一控制电路，所述电平输出电路的第一信号输出端与N个所述第一开关电路的受控端连接，所述电平输出电路的第二信号输出端与N个所述第二开关电路的受控端连接，所述电平输出电路的受控端与所述第一控制电路的控制端连接，所述第一控制电路的信号输入端与所述像素检测电路的信号输出端连接。
本申请技术方案通过采用N个第一测试衬垫、N个第二测试衬垫、第一测试电路、开关电路以及控制电路组成测试电路，第一测试电路通过N个第一测试衬垫输出数据信号至显示面板的N个第一数据线上以及通过N个第二测试衬垫输出数据信号至显示面板的N个第二数据线，以对显示面板像素进行充电。
开关电路包括对应设置于N个所述第一数据线上的N个所述第一开关电路以及设置于N个所述第二数据线上的N个所述第二开关电路，控制电路通过输出控制信号至开关电路使N个第一开关电路单独同时导通或者控制N个第二开关电路单独同时导通，从而实现对显示面板单边测试，并根据显示面板亮度判断N个第一数据线或者N个第二数据线的工作状态，从而解决了在数据信号写入有问题时，无法得知是上端数据线异常还是下端数据线异常的问题，并且在判断出第一数据线以及第二数据线的工作状态后，可对应进行修补，从而提高显示面板的良品率。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为本申请测试电路一实施例的功能模块示意图；
图2为本申请测试电路另一实施例的功能模块示意图；
图3为本申请显示装置一实施例的功能模块示意图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明，在本申请中涉及“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，全文中出现的“和/或”的含义为：包括三个并列的方案，以“A/B”为例，包括A方案，或B方案，或A和B同时满足的方案，另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
本申请提出的一种测试电路，设置为测试显示面板200，所述显示面板200具有N个第一数据线L1及和N个第二数据线L2。
如图1所示，图1为本申请测试电路一实施例的功能模块示意图，所述测试电路包括：
N个第一测试衬垫P1，设置为连接对应的N个所述第一数据线L1；
N个第二测试衬垫P2，设置为连接对应的N个所述第二数据线L2；
第一测试电路10，设置为输出测试显示面板200的多个数据信号至N个所述第一测试衬垫P1和N个所述第二测试衬垫P2；
开关电路(图未示出)，包括N个第一开关电路21和N个第二开关电路22，N个所述第一开关电路21一对一的设置于N个所述第一数据线L1上；N个所述第二开关电路22一对一的设置于N个所述第二数据线L2上；
控制电路30，设置为控制N个所述第一开关电路21单独导通或者控制N个所述第二开关电路22单独导通，以使多个所述数据信号输出至显示面板200对应的数据线上进行显示面板测试，并根据所述显示面板200像素点亮状态判断N个所述第一数据线L1或者N个所述第二数据线L2是否正常工作。
阵列基板制成后需要对显示面板200上的所有像素统一充电，即进行阵列综合检测（Array Test AT），阵列综合检测可实现对信号线等导电线路进行检测，示例性的阵列检测在待检测面板外设置多个测试衬垫，同时双边进行数据信号的写入，本实施例中，N个第一数据线L1及N个第二数据线L2分别从第一测试电路10接收数据信号对所有像素进行充电，第一数据线L1或者第二数据线L2为测试衬垫至显示面板200外边缘的数据线以及显示面板200内部的数据线总长，开关电路中的多个开关电路设置在测试衬垫以及显示面板200之间的数据线上，测试衬垫设置在显示面板200的尺寸之外，并在进行面板测试完毕后进行切割。
根据面板驱动架构的不同，第一测试衬垫P1及第二测试衬垫P2可以分布在显示面板200的四周、呈品子型或者分布在显示面板200的一边，具体可根据实际情况进行设计。
第一测试电路10设置为在显示面板200进行阵列测试时输入数据信号对显示面板200上的像素进行充电，第一测试电路10通过探针与第一测试衬垫P1以及第二测试衬垫P2进行连接，需要说明的是，显示面板200在进行阵列综合检测时，为了减少测试板的体积，控制电路30可以与第一测试电路10集成在同一电路板上。
需要说明的是，开关电路中的N个第一开关电路21接收控制电路30输出的控制信号闭合时，N个第二开关电路22则需要保持断开，第一开关电路21与第二开关电路22的状态必须保持相反，从而对第一数据线L1及第二数据线L2进行单独测试，开关电路中的第一开关电路21及第二开关电路22均可采用具有关断能力的开关元器件或者开关电路，具体可根据实际情况进行设计。
测试电路工作时，栅极驱动电路即均处于正常工作状态，即GOA电路正常接收驱动信号，控制电路30控制N个第一开关电路21导通以及控制N个第二开关电路22断开，第一测试电路10通过N个第一测试衬垫P1输入数据信号至N个第一数据线L1内，并对与N个第一数据线L1连接的像素进行充电，由于第二数据线L2被关断，与第二数据线L2连接的像素均不工作，因此，当发现显示面板200没有点亮或者亮度较暗，则表示N个第一数据线L1出现异常，如果显示面板200正常点亮时，则表示N个第一数据线L1正常；
同理，控制电路30控制N个第二开关电路22导通以及控制N个第一开关电路21断开，第一测试电路10通过N个第二测试衬垫P2输入数据信号至N个第二数据线L2内，并对与N个第二数据线L2连接的像素进行充电，由于第一数据线L1被关断，与第一数据线L1连接的像素均不工作，因此，当发现显示面板200没有点亮或者亮度较暗，则表示N个第二数据线L2出现异常，如果显示面板200正常点亮时，则表示N个第二数据线L2正常。根据对N个第一开关电路21以及N个第二开关电路22单独关断或者导通，从而可对N个第一数据线L1以及N个第二数据线L2的工作状态进行判断，即可能存在的四种情况为：
（1）N个第一数据线L1与N个第二数据线L2均处于正常状态；（2）N个第一数据线L1处于正常状态，N个第二数据线L2处于异常状态；（3）N个第二数据线L2处于正常状态，N个第一数据线L1处于异常状态；（4）N个第一数据线L1与N个第二数据线L2均处于异常状态。
在判断出显示面板200的N个第一数据线L1以及N个第二数据线L2的工作状态后，即可对应进行阵列不良修复，通常采用激光加工的方式，从而提高显示面板200的良品率。
本申请技术方案通过采用N个第一测试衬垫P1、N个第二测试衬垫P2、第一测试电路10、开关电路以及控制电路30组成测试电路，第一测试电路10通过N个第一测试衬垫P1输出数据信号至显示面板200的N个第一数据线L1上以及通过N个第二测试衬垫P2输出数据信号至显示面板200的N个第二数据线L2，以对显示面板200像素进行充电。
开关电路包括对应设置于N个所述第一数据线L1上的N个所述第一开关电路21以及设置于N个所述第二数据线L2上的N个所述第二开关电路22，控制电路30通过输出控制信号至开关电路使N个第一开关电路21单独同时导通或者控制N个第二开关电路22单独同时导通，从而实现对显示面板200单边测试，并根据显示面板200亮度判断N个第一数据线L1或者N个第二数据线L2的工作状态，从而解决了在数据信号写入有问题时，无法得知是上端数据线异常还是下端数据线异常的问题，并且在判断出第一数据线L1以及第二数据线L2的工作状态后，可对应进行修补，从而提高显示面板200的良品率。
在一可选实施例中，所述测试电路还包括像素检测电路40，所述像素检测电路40设置在所述显示面板200上，所述像素检测电路40设置为检测N个所述第一开关电路21单独导通或者N个所述第二开关电路22单独导通时显示面板200上的像素的电场强度或者像素亮度，并输出反馈信号至所述控制电路30，以供所述控制电路30判断N个所述第一数据线或者N个所述第二数据线是否正常工作。
像素检测电路40放置在显示面板200上，像素检测电路40可采用传感器感知显示面板200的像素的表面电场强度，或者采用采光盒等设备采集显示面板200表面亮度，可根据实际情况进行灵活选择，在此不做具体限制。
测试电路工作时，栅极驱动电路即均处于正常工作状态，即GOA电路正常接收驱动信号，控制电路30控制N个第一开关电路21导通以及控制N个第二开关电路22断开，第一测试电路10通过N个第一测试衬垫P1输入数据信号至N个第一数据线L1内，并对与N个第一数据线L1连接的像素进行充电，此时像素检测电路40检测像素的电场强度或者亮度，由于第二数据线L2被关断，与第二数据线L2连接的像素均不工作，因此，当像素检测电路40输出的反馈信号小于预设值时，则表示N个第一数据线L1出现异常，如果反馈信号大于预设值时，则表示N个第一数据线L1正常；
同理，控制电路30控制N个第二开关电路22导通以及控制N个第一开关电路21断开，第一测试电路10通过N个第二测试衬垫P2输入数据信号至N个第二数据线L2内，并对与N个第二数据线L2连接的像素进行充电，此时像素检测电路40检测像素的电场强度或者亮度，由于第一数据线L1被关断，与第一数据线L1连接的像素均不工作，因此，当像素检测电路40输出的反馈信号小于预设值时，则表示N个第二数据线L2出现异常，如果反馈信号大于预设值时，则表示N个第二数据线L2正常。
在一可选实施例中，所述控制电路30具体设置为：
在所述第一测试电路10输出数据信号时，输出第一使能信号至N个所述第一开关电路21以使其导通以及输出第二使能信号至N个所述第二开关电路22以使其关断，并接收所述像素检测电路40输出的反馈信号与预设电场强度至或者预设像素亮度值比较，在所述反馈信号小于预设电场强度至或者预设像素亮度值时，判断N个所述第一数据线L1异常；以及，
输出第一使能信号至N个所述第二开关电路22以使其导通以及输出第二使能信号至N个所述第一开关电路21以使其关断，并接收所述像素检测电路40输出的反馈信号与预设电场强度至或者预设像素亮度值比较，在所述反馈信号小于预设电场强度至或者预设像素亮度值时，判断N个所述第二数据线L2异常。
本实施例中，控制电路30通常分两个步骤对N个第一开关电路21及N个第二开关电路22进行分别导通，并对连接的数据线进行分别测试，第一开关电路21可设置在显示面板200的上端或者下端，同理，第二开关电路22可设置在显示面板200的下端或者上端，第一使能信号可为高电平或者低电平，第二使能信号可为低电平或者高电平，测试电路工作时，栅极驱动电路均处于正常工作状态，控制电路30输出第一使能信号控制N个第一开关电路21导通以及输出第二使能信号控制N个第二开关电路22断开，假设此时第一使能信号为高电平，第二使能信号为低电平，第一测试电路10通过N个第一测试衬垫P1输入数据信号至N个第一数据线L1内，并对与N个第一数据线L1连接的像素进行充电，此时像素检测电路40检测像素的电场强度或者亮度，由于第二数据线L2被关断，与第二数据线L2连接的像素均不工作，因此，如果此时像素检测电路40输出的反馈信号小于预设电场强度或者预设像素亮度值时，则表示N个第一数据线L1出现异常，如果反馈信号大于或者等于预设电场强度或者预设像素亮度值时，则表示N个第一数据线L1正常；
在对N个第一测试线判定完毕后，控制电路30输出第二使能信号控制N个第一开关电路21关断以及输出第一使能信号控制N个第二开关电路22导通，第一测试电路10通过N个第二测试衬垫P2输入数据信号至N个第二数据线L2内，并对与N个第二数据线L2连接的像素进行充电，此时像素检测电路40检测像素的电场强度或者亮度，由于第一数据线L1被关断，与第一数据线L1连接的像素均不工作，因此，如果此时像素检测电路40输出的反馈信号小于预设值时，则表示N个第二数据线L2出现异常，如果反馈信号大于或者等于预设电场强度或者预设像素亮度值时，则表示N个第二数据线L2正常。
在一可选实施例中，还包括第三测试衬垫P3和第四测试衬垫P4，N个所述第一开关电路21的受控端与所述第三测试衬垫P3的信号输出端互连，N个所述第二开关电路22的受控端与所述第四测试衬垫P4的信号输出端互连。
本实施例中，为了减少控制电路30的输出端口以及避免线路杂乱，在控制电路30分别通过第三测试衬垫P3以及第四测试衬垫P4输出控制信号至对应的第一开关电路21以及第二开关电路22，并且，N个第一开关电路21的受控端并联后与第三测试衬垫P3互连，N个第二开关电路22的受控端并联后与第四测试衬垫P4互连，从而达到简化线路结构以及降低设计成本的目的。
在一可选实施例中，N个所述第一测试衬垫P1、N个所述第二测试衬垫P2、所述第三测试衬垫P3及所述第四测试衬垫P4并排且与所述显示面板200平行设置。
本实施例中，多个测试衬垫均呈一排设置，并且设置在显示面板200的尺寸在外且平行与显示面板200，因此，控制电路30与第三测试衬垫P3及第四测试衬垫P4之间的连接线可设计为更简短，从而达到简化线路结构以及降低设计成本的目的。
在一可选实施例中，所述第一开关电路21及所述第二开关电路22均为MOS管。
本实施例中，各MOS管的栅极分别对应与第三测试衬垫P3及第四测试衬垫P4连接，测试衬垫输出高低电平以控制MOS管导通或者关断，各MOS管的漏极或者源极设置为接收数据信号，并从各MOS管的源极或者漏极输出至显示面板200的各个像素中，进而为显示面板200的各像素进行同侧单独充电，MOS管的类型可以选择NMOS管或者PMOS管，可根据具体情况进行选择。
在一可选实施例中，所述开关电路为NMOS管。
本实施例中，各NMOS管的栅极分别对应与第三测试衬垫P3及第四测试衬垫P4连接，测试衬垫输出高电平以控制NMOS管导通，输出低电平控制NMOS管关断，各NMOS管的漏极或者源极设置为接收数据信号，并从各NMOS管的源极输出数据信号至显示面板200的各个像素中，进而为显示面板200的各像素进行同侧单独充电，各NMOS管根据接收到的不同控制信号分别进行单侧导通或者关断，进而实现对数据线的单独检测。
如图2所示，图2为本申请测试电路另一实施例的功能模块示意图，在一可选实施例中，所述控制电路30包括电平输出电路31及第一控制电路32，所述电平输出电路31的第一信号输出端与N个所述第一开关电路21的受控端连接，所述电平输出电路31的第二信号输出端与N个所述第二开关电路22的受控端连接，所述电平输出电路31的受控端与所述第一控制电路32的控制端连接，所述第一控制电路32的信号输入端与所述像素检测电路40的信号输出端连接。
本实施例中，电平输出电路31受控于第一控制电路32输出的控制信号，电平输出电路31包括第一电平输出端及第二电平输出端，第一电平输出端通过第三测试衬垫P3与N个第一开关电路21的受控端连接，第二电平输出端通过第四测试衬垫P4与N个第二开关电路22的受控端连接，第一控制电路32设置为接收像素检测电路40输出的反馈信号并与预设电场强度或者预设亮度值进行比较，第一控制电路32通过控制电平输出电路31输出不同的高低电平以控制第一开关电路21或者第二开关电路22单独导通或者关断，进而对第一数据线L1及第二数据线L2的工作状态进行判断，电平输出电路31可采用信号发生器、电平转换器或者其他电路或者元器件，第一控制电路32可采用微处理器、可编程控制器等。
进一步地，控制电路30还可与第一测试电路10集成在同一电路板上，或者集成在同一芯片内，从而可进一步简化测试电路的结构。
在一可选实施例中，所述控制电路30还与终端设备连接，所述控制电路30将所述第一数据线L1的工作状态以及所述第二数据线L2的工作状态反馈至所述终端设备。
本实施例中，在控制电路30通过分别驱动第一数据线L1对应的像素以及第二数据线L2对应的像素后，根据像素检测电路40输出的反馈信号判断出第一数据线L1以及第二数据线L2的工作状态后，控制电路30将第一数据线L1以及第二数据线L2的工作状态以1和0表示或以文字表示，例如当使用1和0表示时，1表示数据线正常，0表示数据线异常，并可输出对应的表格至终端设备，以使终端设备通过显示器显示，第一数据线L1与第二数据线L2根据不同状态控制电路30可输出1和1，1和0，0和1，0和0，测试人员根据数值即可判断哪一端的数据线出现异常，进而进行对应的修补，从而提高显示面板200的良品率。
本发明还提出一种测试电路，设置为测试显示面板200，所述显示面板200具有N个第一数据线L1及和N个第二数据线L2，所述测试电路包括：
一种测试电路，设置为测试显示面板200，所述显示面板200具有N个第一数据线L1及和N个第二数据线L2，其中，所述测试电路包括：
N个第一测试衬垫P1，设置为连接对应的N个所述第一数据线L1；
N个第二测试衬垫P2，设置为连接对应的N个所述第二数据线L2；
第一测试电路10，设置为输出测试显示面板200的多个数据信号至N个所述第一测试衬垫P1和N个所述第二测试衬垫P2；
开关电路，包括N个第一开关电路21和N个第二开关电路22，N个所述第一开关电路21一对一的设置于N个所述第一数据线L1上；N个所述第二开关电路22一对一的设置于N个所述第二数据线L2上；
控制电路30，设置为控制N个所述第一开关电路21单独导通或者控制N个所述第二开关电路22单独导通；
第三测试衬垫P3，设置为供所述控制电路30输出第一控制信号至N个所述第一开关电路21以控制N个所述第一开关电路21导通或者关断；
第四测试衬垫P4，设置为供所述控制电路30输出第二控制信号至N个所述第一开关电路21以控制N个所述第二开关电路22导通或者关断；
像素检测电路40，设置为检测N个所述第一开关电路21单独导通或者N个所述第二开关电路22单独导通时显示面板200上的像素的电场强度或者像素亮度，并输出反馈信号至所述控制电路30，以供所述控制电路30判断N个所述第一数据线L1或者N个所述第二数据线L2是否正常工作。
如图3所示，图3为本申请显示装置一实施例的功能模块示意图，本申请还提出一种显示装置1000，该显示装置1000包括显示面板200和驱动电路300，其中，所述驱动电路300包括如上所述的测试电路，该测试电路的具体结构参照上述实施例，由于本驱动电路300采用了上述所有实施例的全部技术方案，因此至少具有上述实施例的技术方案所带来的所有技术效果，在此不再一一赘述。
驱动电路300输出驱动信号至显示面板200以对面板进行驱动，并可实现对显示面板200的N个第一数据线L1及和N个第二数据线L2进行检测，从而在判断出第一数据线L1以及第二数据线L2的工作状态后，可对应进行修补，从而提高显示面板200的良品率。
以上所述仅为本申请的优选实施例，并非因此限制本申请的专利范围，凡是在本申请的申请构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。

Claims (20)

  1. 一种测试电路，设置为测试显示面板，所述显示面板具有N个第一数据线及和N个第二数据线，其中，所述测试电路包括：
    N个第一测试衬垫，设置为连接对应的N个所述第一数据线；
    N个第二测试衬垫，设置为连接对应的N个所述第二数据线；
    第一测试电路，设置为输出测试显示面板的多个数据信号至N个所述第一测试衬垫和N个所述第二测试衬垫；
    开关电路，包括N个第一开关电路和N个第二开关电路，N个所述第一开关电路一对一的设置于N个所述第一数据线上；N个所述第二开关电路一对一的设置于N个所述第二数据线上；以及
    控制电路，设置为控制N个所述第一开关电路单独导通或者控制N个所述第二开关电路单独导通，以使多个所述数据信号输出至所述显示面板对应的数据线上进行显示面板测试，并根据所述显示面板点亮状态判断N个所述第一数据线或者N个所述第二数据线是否正常工作。
  2. 如权利要求1所述的测试电路，其中，所述第一数据线或者第二数据线为连接所述测试衬垫和所述显示面板上的像素之间的数据线。
  3. 如权利要求1所述的测试电路，其中，所述测试电路还包括像素检测电路，所述像素检测电路设置在所述显示面板上，所述像素检测电路设置为检测N个所述第一开关电路单独导通或者N个所述第二开关电路单独导通时显示面板上的像素的电场强度或者像素亮度，并输出反馈信号至所述控制电路，以供所述控制电路判断N个所述第一数据线或者N个所述第二数据线是否正常工作。
  4. 如权利要求3所述的测试电路，其中，所述控制电路具体设置为：
    在所述第一测试电路输出数据信号时，输出第一使能信号至N个所述第一开关电路以使其导通以及输出第二使能信号至N个所述第二开关电路以使其关断，并接收所述像素检测电路输出的反馈信号与预设电场强度至或者预设像素亮度值比较，在所述反馈信号小于预设电场强度至或者预设像素亮度值时，判断N个所述第一数据线异常；以及
    输出第一使能信号至N个所述第二开关电路以使其导通以及输出第二使能信号至N个所述第一开关电路以使其关断，并接收所述像素检测电路输出的反馈信号与预设电场强度至或者预设像素亮度值比较，在所述反馈信号小于预设电场强度至或者预设像素亮度值时，判断N个所述第二数据线异常。
  5. 如权利要求1所述的测试电路，其中，还包括第三测试衬垫和第四测试衬垫，N个所述第一开关电路的受控端与所述第三测试衬垫的信号输出端互连，N个所述第二开关电路的受控端与所述第四测试衬垫的信号输出端互连。
  6. 如权利要求5所述的测试电路，其中，N个所述第一测试衬垫、N个所述第二测试衬垫、所述第三测试衬垫及所述第四测试衬垫并排且与所述显示面板平行设置。
  7. 如权利要求1所述的测试电路，其中，所述第一开关电路及所述第二开关电路均为MOS管。
  8. 如权利要7所述的测试电路，其中，所述第一开关电路及所述第二开关电路为NMOS管。
  9. 如权利要求1所述的测试电路，其中，所述控制电路与所述第一测试电路集成在电路板上。
  10. 如权利要求4所述的测试电路，其中，所述控制电路包括电平输出电路及第一第一控制电路，所述电平输出电路的第一信号输出端与N个所述第一开关电路的受控端连接，所述电平输出电路的第二信号输出端与N个所述第二开关电路的受控端连接，所述电平输出电路的受控端与所述第一第一控制电路的控制端连接，所述第一第一控制电路的信号输入端与所述像素检测电路的信号输出端连接。
  11. 一种测试电路，设置为测试显示面板，所述显示面板具有N个第一数据线及和N个第二数据线，其中，所述测试电路包括：
    N个第一测试衬垫，设置为连接对应的N个所述第一数据线；
    N个第二测试衬垫，设置为连接对应的N个所述第二数据线；
    第一测试电路，设置为输出测试显示面板的多个数据信号至N个所述第一测试衬垫和N个所述第二测试衬垫；
    开关电路，包括N个第一开关电路和N个第二开关电路，N个所述第一开关电路一对一的设置于N个所述第一数据线上；N个所述第二开关电路一对一的设置于N个所述第二数据线上；
    控制电路，设置为控制N个所述第一开关电路单独导通或者控制N个所述第二开关电路单独导通；
    第三测试衬垫，设置为供所述控制电路输出第一控制信号至N个所述第一开关电路以控制N个所述第一开关电路导通或者关断；
    第四测试衬垫，设置为供所述控制电路输出第二控制信号至N个所述第一开关电路以控制N个所述第二开关电路导通或者关断；以及
    像素检测电路，设置为检测N个所述第一开关电路单独导通或者N个所述第二开关电路单独导通时显示面板上的像素的电场强度或者像素亮度，并输出反馈信号至所述控制电路，以供所述控制电路判断N个所述第一数据线或者N个所述第二数据线是否正常工作。
  12. 一种显示装置，其中，包括:
    显示面板；
    驱动电路；
    其中，所述驱动电路包括所述测试电路，所述测试电路设置为测试显示面板，所述显示面板具有N个第一数据线及和N个第二数据线，所述测试电路包括：
    N个第一测试衬垫，设置为连接对应的N个所述第一数据线；
    N个第二测试衬垫，设置为连接对应的N个所述第二数据线；
    第一测试电路，设置为输出测试显示面板的多个数据信号至N个所述第一测试衬垫和N个所述第二测试衬垫；
    开关电路，包括N个第一开关电路和N个第二开关电路，N个所述第一开关电路一对一的设置于N个所述第一数据线上；N个所述第二开关电路一对一的设置于N个所述第二数据线上；以及
    控制电路，设置为控制N个所述第一开关电路单独导通或者控制N个所述第二开关电路单独导通，以使多个所述数据信号输出至所述显示面板对应的数据线上进行显示面板测试，并根据所述显示面板点亮状态判断N个所述第一数据线或者N个所述第二数据线是否正常工作。
  13. 如权利要求12所述的显示装置，其中，所述第一数据线或者第二数据线为连接所述测试衬垫和所述显示面板上的像素之间的数据线。
  14. 如权利要求12所述的显示装置，其中，所述测试电路还包括像素检测电路，所述像素检测电路设置在所述显示面板上，所述像素检测电路设置为检测N个所述第一开关电路单独导通或者N个所述第二开关电路单独导通时显示面板上的像素的电场强度或者像素亮度，并输出反馈信号至所述控制电路，以供所述控制电路判断N个所述第一数据线或者N个所述第二数据线是否正常工作。
  15. 如权利要求14所述的显示装置，其中，所述控制电路具体设置为：
    在所述第一测试电路输出数据信号时，输出第一使能信号至N个所述第一开关电路以使其导通以及输出第二使能信号至N个所述第二开关电路以使其关断，并接收所述像素检测电路输出的反馈信号与预设电场强度至或者预设像素亮度值比较，在所述反馈信号小于预设电场强度至或者预设像素亮度值时，判断N个所述第一数据线异常；以及
    输出第一使能信号至N个所述第二开关电路以使其导通以及输出第二使能信号至N个所述第一开关电路以使其关断，并接收所述像素检测电路输出的反馈信号与预设电场强度至或者预设像素亮度值比较，在所述反馈信号小于预设电场强度至或者预设像素亮度值时，判断N个所述第二数据线异常。
  16. 如权利要求12所述的显示装置，其中，还包括第三测试衬垫和第四测试衬垫，N个所述第一开关电路的受控端与所述第三测试衬垫的信号输出端互连，N个所述第二开关电路的受控端与所述第四测试衬垫的信号输出端互连。
  17. 如权利要求16所述的显示装置，其中，N个所述第一测试衬垫、N个所述第二测试衬垫、所述第三测试衬垫及所述第四测试衬垫并排且与所述显示面板平行设置。
  18. 如权利要求12所述的显示装置，其中，所述第一开关电路及所述第二开关电路均为MOS管。
  19. 如权利要求12所述的显示装置，其中，所述控制电路与所述第一测试电路集成在电路板上。
  20. 如权利要求15所述的显示装置，其中，所述控制电路包括电平输出电路及第一控制电路，所述电平输出电路的第一信号输出端与N个所述第一开关电路的受控端连接，所述电平输出电路的第二信号输出端与N个所述第二开关电路的受控端连接，所述电平输出电路的受控端与所述第一控制电路的控制端连接，所述第一控制电路的信号输入端与所述像素检测电路的信号输出端连接。
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