WO2019239984A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2019239984A1
WO2019239984A1 PCT/JP2019/022356 JP2019022356W WO2019239984A1 WO 2019239984 A1 WO2019239984 A1 WO 2019239984A1 JP 2019022356 W JP2019022356 W JP 2019022356W WO 2019239984 A1 WO2019239984 A1 WO 2019239984A1
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WO
WIPO (PCT)
Prior art keywords
clock signal
filter
circuit
delay
majority
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2019/022356
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English (en)
French (fr)
Japanese (ja)
Inventor
貴則 成田
大介 松浦
石井　茂
大輔 小林
和之 廣瀬
治 川崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Heavy Industries Ltd
Original Assignee
Mitsubishi Heavy Industries Ltd
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Filing date
Publication date
Application filed by Mitsubishi Heavy Industries Ltd filed Critical Mitsubishi Heavy Industries Ltd
Priority to US16/970,750 priority Critical patent/US11115035B2/en
Priority to EP19818654.6A priority patent/EP3748855A4/en
Publication of WO2019239984A1 publication Critical patent/WO2019239984A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/26—Time-delay networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
    • H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers

Definitions

  • the present invention relates to a semiconductor device, and more particularly, to a semiconductor device suitably used for generating a clock signal.
  • Clock signals are widely used to establish circuit synchronization in integrated circuits.
  • the clock signal is most typically generated using a PLL (phase locked loop) circuit and distributed to the circuits to be operated synchronously.
  • PLL phase locked loop
  • Improvement of the reliability of the circuit that generates the clock signal is useful for improving the reliability of the operation of the entire semiconductor integrated circuit. This problem is particularly important in an environment where radiation is strong, for example, in an integrated circuit used in outer space. In an environment where radiation is strong, the PLL circuit may malfunction. If the PLL circuit that generates the clock signal malfunctions, the semiconductor integrated circuit may malfunction.
  • Japanese Unexamined Patent Application Publication No. 2003-163583 discloses an asynchronous noise filter circuit that can remove noise even when the noise level exceeds the threshold value of the input logic circuit.
  • an object of the present invention is to provide a technique for improving the reliability of a circuit that generates a clock signal.
  • the semiconductor device is configured to operate in synchronization with a common reference clock signal and output first to Nth clock signals (N is an odd number of 3 or more), respectively.
  • N is an odd number of 3 or more
  • a first to NPLL circuit a majority circuit that performs a majority operation on the first to Nth clock signals to generate a majority clock signal; and the majority clock signal is input and operates as a low-pass filter to generate an output clock signal And a filter circuit for outputting.
  • the filter circuit includes a first RS flip-flop to which a majority clock signal or an inverted signal thereof is input to a reset terminal, and a first delay signal generated by delaying the majority clock signal to a set terminal of the first RS flip-flop. And a first delay circuit that supplies the first delay circuit.
  • An output clock signal is generated according to a signal output from the data output of the first RS flip-flop.
  • the filter circuit may further include a first inverter to which a majority clock signal is input.
  • the output signal of the first inverter is input to the reset terminal of the first RS flip-flop.
  • the first delay circuit is preferably configured such that the delay time is variable.
  • a delay setting circuit that sets the delay time of the first delay circuit based on PLL setting data that specifies the oscillation frequency of the first to NPLL circuits may be further provided.
  • the filter circuit includes a first filter to which a majority clock signal is input, a second inverter to which an output signal of the first filter is input, and a second filter to which an output signal of the second inverter is input. It has.
  • the first filter is configured to output a clock signal having a duty ratio different from that of the majority clock signal.
  • the first filter and the second filter have the same configuration.
  • the filter circuit includes a first filter to which a majority clock signal is input, a second inverter to which an output signal of the first filter is input, and a second filter to which an output signal of the second inverter is input.
  • the first filter includes a third inverter to which a majority clock signal is input, a first RS flip-flop, and a first delay signal generated by delaying the majority clock signal to a set terminal of the first RS flip-flop.
  • the second filter includes a fourth inverter to which the output signal of the second inverter is input, a second RS flip-flop, and a second delay signal generated by delaying the output signal of the second inverter. And a second delay circuit for supplying to the first delay circuit.
  • the first delay circuit and the second delay circuit have the same delay time and are configured to be variable in delay time.
  • a delay setting circuit for setting the delay times of the first delay circuit and the second delay circuit based on PLL setting data for specifying the oscillation frequency of the first to NPLL circuits may be provided.
  • the reliability of the circuit that generates the clock signal can be improved.
  • FIG. 1 is a block diagram illustrating a configuration of a semiconductor device 100 according to an embodiment.
  • the semiconductor device 100 is configured to generate the output clock signal CK OUT with high reliability even in an environment where radiation is strong by multiplexing the PLL circuit.
  • the PLL circuit 1 1 to 1 3 A majority circuit 2 and a filter circuit 3 are provided.
  • the PLL circuit 1 1 to 1 3 and the reference clock signal CK REF is commonly input, the PLL circuit 1 1 to 1 3, a clock signal CK1 ⁇ CK3 synchronized with the reference clock signal CK REF is generated.
  • PLL circuits 1 1 to 1 3 are connected to the PLL setting register 4, and generates a clock signal CK1 ⁇ CK3 at the frequency specified by the PLL setting data set in the PLL setting register 4.
  • the setting data may include a frequency division ratio of the frequency divider included in the PLL circuits 1 1 to 1 3 .
  • FIG. 2 is a block diagram showing an example of the configuration of the PLL circuits 1 1 to 1 3 .
  • the PLL circuits 1 1 to 1 3 have the same configuration, and each of them includes a frequency divider 11, 12, a phase comparator 13, a charge pump 14, a loop filter 15, And a voltage controlled oscillator (VCO) 16.
  • the output signal of the PLL circuit 1 1 to 1 3 of the voltage controlled oscillator 16, respectively, are input to the majority circuit 2 as the clock signal CK1 ⁇ CK3.
  • the frequency divider 11 divides the reference clock signal CK REF
  • the frequency divider 12 divides the output signal of the voltage controlled oscillator 16.
  • Dividing ratio of the frequency divider 11 is R
  • the frequency of the output signal of the frequency divider 11 is 1 / R of the frequency of the reference clock signal CK REF.
  • the frequency division ratio of the frequency divider 12 is N
  • the frequency of the output signal of the frequency divider 12 is 1 / N of the output signal of the voltage controlled oscillator 16.
  • the phase comparator 13 compares the phases of the output signals of the frequency dividers 11 and 12, and outputs an output signal corresponding to the phase difference between these output signals.
  • the charge pump 14 supplies a voltage signal having a signal level corresponding to the phase difference between the output signals of the frequency dividers 11 and 12 via the loop filter 15 to the voltage controlled oscillator 16.
  • the loop filter 15 is configured as a low pass filter.
  • the frequency division ratios R and N of the frequency dividers 11 and 12 are specified by PLL setting data stored in the PLL setting register 4. Oscillation frequency of the PLL circuit 1 1 to 1 3, the division ratio of the frequency divider 11, 12 R, by setting appropriately the N by the PLL setting data is set to a desired frequency.
  • the majority circuit 2 generates the majority clock signal CK MJR by performing majority operation with respect to the clock signal CK1 ⁇ CK3 received from the PLL circuit 1 1 to 1 3.
  • a majority operation is an operation that obtains an output having a state that occupies a majority of all inputs.
  • the majority circuit 2 includes NAND gates 21 to 24.
  • NAND gate 21 has a first input clock signal CK1 from the PLL circuit 1 1 is input, a second input clock signal CK2 from the PLL circuit 1 2 is input, the clock signal CK1, An output signal having a negative logical product value of CK2 is output.
  • NAND gate 22 has a first input clock signal CK2 from the PLL circuit 1 2 is input and a second input clock signal CK3 from the PLL circuit 1 3 is input, a clock signal CK2, An output signal having a negative logical product value of CK3 is output.
  • NAND gate 23 has a first input for receiving a clock signal CK3 from the PLL circuit 1 3 and a second input for receiving a clock signal CK1 from the PLL circuit 1 1, the clock signal CK3, CK1 negative logic of An output signal having a product value is output.
  • the NAND gate 24 has first to third inputs to which the output signals of the NAND gates 21 to 23 are input, respectively, and outputs an output signal having a negative logical product value of the output signals of the NAND gates 21 to 23. Output.
  • the output signal of the NAND gate 24 is the majority clock signal CK MJR .
  • Majority clock signal CK MJR output from the majority circuit 2, since the obtained by performing a majority operation with respect to the clock signal CK1 ⁇ CK3, one is for example radiation effects of one of the PLL circuits 1 1 to 1 3 Even if a malfunction occurs, an appropriate majority clock signal CK MJR can be generated.
  • the PLL circuit 1 1 to 1 since each has a separate feedback loop, a phase difference may occur between the clock signals CK1 ⁇ CK3 output from the PLL circuit 1 1 to 1 3.
  • the phase difference between the clock signals CK1 to CK3 can cause noise in the majority clock signal CK MJR .
  • FIG. 3 shows an example of the phase difference between the clock signals CK1 to CK3 that generates noise in the majority clock signal CK MJR .
  • the clock signals CK1 to CK3 have the same period T.
  • the clock signal CK2 is delayed from the clock signal CK1 by a delay time d2.
  • the clock signal CK3 is inverted from the clock signal CK1 (that is, delayed by T / 2) and further delayed by the delay time d3.
  • FIG. 4 shows the waveform of the majority clock signal CK MJR when the frequency of the clock signals CK1 to CK3 is 200 MHz, the delay time d2 of the clock signal CK2 is 300 ps, and the delay time d3 of the clock signal CK3 is 60 to 240 ps.
  • the simulation results are shown.
  • significant noise is generated in the vicinity of the rising and falling edges of the pulses of the majority clock signal CK MJR when the delay time d3 is 80 ⁇ 200 ps, the majority clock signal CK MJR Waveform is distorted. Such waveform disturbance is not preferable.
  • the majority clock signal CK MJR is input to the filter circuit 3 that operates as a low-pass filter, and the output clock signal CK OUT is output from the filter circuit 3.
  • the filter circuit 3 includes a front-stage filter 31, an inverter 32, a rear-stage filter 33, and an inverter 34.
  • the pre-stage filter 31 includes an inverter 35, a variable delay circuit 36, and an RS flip-flop 37.
  • the inverter 35 receives the majority clock signal CK MJR at its input, and supplies an inverted signal obtained by inverting the majority clock signal CK MJR to the reset terminal of the RS flip-flop 37.
  • the variable delay circuit 36 supplies a delay signal obtained by delaying the majority clock signal CK MJR to the set terminal of the RS flip-flop 37.
  • the variable delay circuit 36 is configured such that the delay time is variable. Delay time d1 of the variable delay circuit 36 is set in accordance with the oscillation frequency of the PLL circuit 1 1 to 1 3. In the present embodiment, the delay time d 1 of the variable delay circuit 36 is specified by the delay setting data stored in the delay setting register 5.
  • the inverter 32 inverts the output signal of the front-stage filter 31 and supplies it to the rear-stage filter 33.
  • the post-stage filter 33 has the same configuration as the pre-stage filter 31, and includes an inverter 38, a variable delay circuit 39, and an RS flip-flop 40.
  • the inverter 38 receives the output signal of the inverter 32 at its input, and supplies an inverted signal obtained by inverting the output signal of the inverter 32 to the reset terminal of the RS flip-flop 40.
  • the variable delay circuit 39 supplies a delay signal obtained by delaying the output signal of the inverter 32 to the set terminal of the RS flip-flop 37.
  • the variable delay circuit 39 is configured such that the delay time is variable.
  • the variable delay circuit 39 is set by the delay setting data stored in the delay setting register 5 so as to have the same delay time d1 as the variable delay circuit 36 of the pre-stage filter 31.
  • the inverter 34 generates an inverted signal of the output signal of the post-stage filter 33 and outputs it as the output clock signal CK OUT .
  • Front filter 31 a delay time d1 of the variable delay circuits 36 and 39 in the subsequent stage filter 33, by setting in accordance with the oscillation frequency of the PLL circuit 1 1 to 1 3, front filter 31, the subsequent stage filter 33, as a low-pass filter Function.
  • the pre-stage filter 31 alone operates as a low-pass filter and has a function of removing noise. However, since the pre-stage filter 31 performs an operation of widening the pulse width ( longening the time that is maintained at the high level) by the delay time d1 of the variable delay circuit 36, the duty ratio of the majority clock signal CK MJR is 50%. Even if it exists, the duty ratio of the output signal of the pre-stage filter 31 does not become 50%.
  • the inverter 32 and the post-stage filter 33 are used to obtain an output clock signal CK OUT having a duty ratio of 50%.
  • the post-stage filter 33 has the same configuration as that of the pre-stage filter 31 and performs an operation of expanding the pulse width by the delay time d1 of the variable delay circuit 39 with respect to the inverted signal of the output signal of the pre-stage filter 31.
  • the duty ratio of the output signal output from the post-stage filter 33 is 50%.
  • FIG. 5 is a timing chart showing an example of the operation of the pre-stage filter 31 and the post-stage filter 33. Symbols “A” to “H” indicate signal waveforms at nodes A to H of the filter circuit 3, respectively.
  • the pre-filter 31 operates as follows.
  • the majority clock signal CK MJR is input to the node A, and the duty ratio of the signal waveform of the node A is 50%.
  • an inverted signal of the majority clock signal CK MJR is generated in the node B.
  • a delayed signal obtained by delaying the majority clock signal CK MJR by the delay time d1 is generated at the node C.
  • the majority clock signal is supplied to the node D connected to the data output of the RS flip-flop 37.
  • a signal in which the pulse width of CK MJR is expanded by the delay time d1 is generated.
  • the post-stage filter 33 performs the same operation as the pre-stage filter 31 on the inverted signal of the output signal output from the pre-stage filter 31.
  • node E an inverted signal of the output signal of inverter 32 is generated.
  • a delayed signal obtained by delaying the output signal of the inverter 32 by the delay time d1 is generated at the node C. Since the node E is connected to the reset terminal of the RS flip-flop 40 and the node F is connected to the set terminal of the RS flip-flop 40, the node G connected to the data output of the RS flip-flop 40 is connected to the inverter 32.
  • a signal in which the pulse width of the output signal (that is, the inverted signal of the output signal of the pre-filter 31) is expanded by the delay time d1 is generated.
  • the duty ratio of the output signal of the post-stage filter 33 and the output clock signal CK OUT is 50%.
  • the inverter 35 and the variable delay circuit 36 of the pre-filter 31 have a function of supplying the majority clock signal CK MJR with an appropriate phase difference to the reset terminal and the set terminal of the RS flip-flop 37, as a whole. If the delay time d1 of the variable delay circuit 36 is appropriately set, the inverter 35 is not always necessary. For the same reason, the inverter 38 of the post-filter 33 is not always necessary.
  • FIG. 6 shows the filter circuit 3 having a configuration in which the inverters 35 and 38 are not provided.
  • the majority clock signal CK MJR is input to the reset terminal of the RS flip-flop 37, and the output signal of the inverter 32 is input to the reset terminal of the RS flip-flop 40.
  • the configuration of the filter circuit 3 can be variously changed.
  • another filter that operates as a low-pass filter for example, an RC filter may be used.
  • variable delay circuits 36 and 39 to facilitate the setting in accordance with the oscillation frequency of the PLL circuit 1 1 to 1 3, as illustrated in Figure 7, the PLL setting register 4
  • a delay setting circuit 6 for calculating the delay time d1 from the stored PLL setting data and generating delay setting data for designating the delay time d1.
  • the variable delay circuits 36 and 39 are set so as to have the delay time d1 specified in the delay setting data generated by the delay setting circuit 6.
  • the majority circuit 2 and the filter circuit 3 are not multiplexed, the incidence of radiation on the circuit elements constituting the majority circuit 2 and the filter circuit 3 may cause a malfunction.
  • the circuit scales of the majority circuit 2 and the filter circuit 3 can be reduced, malfunctions are unlikely to occur even in an environment where radiation is strong.
  • a plurality of MOS transistors to which the same signal is supplied to the gate are connected in series May be.
  • the inverter 50 may include PMOS transistors MP1 and MP2 and NMOS transistors MN1 and MN2.
  • the gates of the PMOS transistors MP1 and MP2 are commonly connected to the input terminal 51, and are connected in series between the output terminal 52 and the power supply line 53 where the power supply voltage VDD is generated.
  • the gates of the NMOS transistors MN1 and MN2 are commonly connected to the input terminal 51, and are connected in series between the output terminal and the ground line 54 having the ground potential VSS.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)
  • Logic Circuits (AREA)
PCT/JP2019/022356 2018-06-15 2019-06-05 半導体装置 Ceased WO2019239984A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US16/970,750 US11115035B2 (en) 2018-06-15 2019-06-05 Semiconductor devices
EP19818654.6A EP3748855A4 (en) 2018-06-15 2019-06-05 SEMICONDUCTOR DEVICE

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018-114846 2018-06-15
JP2018114846A JP7255790B2 (ja) 2018-06-15 2018-06-15 半導体装置

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WO2019239984A1 true WO2019239984A1 (ja) 2019-12-19

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US (1) US11115035B2 (enExample)
EP (1) EP3748855A4 (enExample)
JP (1) JP7255790B2 (enExample)
WO (1) WO2019239984A1 (enExample)

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Publication number Priority date Publication date Assignee Title
TWI750021B (zh) * 2021-02-01 2021-12-11 瑞昱半導體股份有限公司 可靠度偵測裝置與可靠度偵測方法
JPWO2023161758A1 (enExample) * 2022-02-25 2023-08-31

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5934013B2 (ja) * 1979-04-06 1984-08-20 株式会社京三製作所 多数決判定方式
JPH06303135A (ja) * 1993-04-13 1994-10-28 Hitachi Ltd クロック発生回路
JPH07193495A (ja) * 1993-12-27 1995-07-28 Mitsubishi Electric Corp 冗長クロック回路
JP2003163583A (ja) 2001-11-22 2003-06-06 Toshiba Corp 非同期型ノイズフィルタ回路
US6728327B1 (en) * 2000-01-05 2004-04-27 Lsi Logic Corporation Lower-jitter phase-locked loop
JP2018114846A (ja) 2017-01-18 2018-07-26 住友ゴム工業株式会社 タイヤ

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5934013A (ja) 1982-08-19 1984-02-24 Matsushita Electric Ind Co Ltd 流れ方向制御装置
EP0570158B1 (en) 1992-05-08 2000-01-19 National Semiconductor Corporation Frequency multiplication circuit and method for generating a stable clock signal
JP3724398B2 (ja) * 2001-02-20 2005-12-07 ティアック株式会社 信号処理回路及び信号処理方法
EP1386441B1 (en) 2001-03-27 2004-08-18 Acuid Corporation (Guernsey) Limited Receiver with recovery circuit using oversampling and majority decision
JP5793460B2 (ja) 2012-03-30 2015-10-14 富士通株式会社 可変遅延回路
JP5934013B2 (ja) 2012-04-05 2016-06-15 ヒロセ株式会社 補強土壁の足場構造及びその設置治具

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5934013B2 (ja) * 1979-04-06 1984-08-20 株式会社京三製作所 多数決判定方式
JPH06303135A (ja) * 1993-04-13 1994-10-28 Hitachi Ltd クロック発生回路
JPH07193495A (ja) * 1993-12-27 1995-07-28 Mitsubishi Electric Corp 冗長クロック回路
US6728327B1 (en) * 2000-01-05 2004-04-27 Lsi Logic Corporation Lower-jitter phase-locked loop
JP2003163583A (ja) 2001-11-22 2003-06-06 Toshiba Corp 非同期型ノイズフィルタ回路
JP2018114846A (ja) 2017-01-18 2018-07-26 住友ゴム工業株式会社 タイヤ

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3748855A4

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Publication number Publication date
EP3748855A4 (en) 2021-01-20
JP7255790B2 (ja) 2023-04-11
EP3748855A1 (en) 2020-12-09
US20210099180A1 (en) 2021-04-01
JP2019220763A (ja) 2019-12-26
US11115035B2 (en) 2021-09-07

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