EP3748855A4 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
EP3748855A4
EP3748855A4 EP19818654.6A EP19818654A EP3748855A4 EP 3748855 A4 EP3748855 A4 EP 3748855A4 EP 19818654 A EP19818654 A EP 19818654A EP 3748855 A4 EP3748855 A4 EP 3748855A4
Authority
EP
European Patent Office
Prior art keywords
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP19818654.6A
Other languages
German (de)
French (fr)
Other versions
EP3748855A1 (en
Inventor
Takanori Narita
Daisuke Matsuura
Shigeru Ishii
Daisuke Kobayashi
Kazuyuki Hirose
Osamu Kawasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Heavy Industries Ltd
Original Assignee
Mitsubishi Heavy Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Heavy Industries Ltd filed Critical Mitsubishi Heavy Industries Ltd
Publication of EP3748855A1 publication Critical patent/EP3748855A1/en
Publication of EP3748855A4 publication Critical patent/EP3748855A4/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00Networks using active elements
    • H03H11/02Multiple-port networks
    • H03H11/26Time-delay networks
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003Modifications for increasing the reliability for protection
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125Discriminating pulses
    • H03K5/1252Suppression or limitation of noise or interference
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131Digitally controlled
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
    • H03L7/23Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
EP19818654.6A 2018-06-15 2019-06-05 Semiconductor device Pending EP3748855A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018114846A JP7255790B2 (en) 2018-06-15 2018-06-15 semiconductor equipment
PCT/JP2019/022356 WO2019239984A1 (en) 2018-06-15 2019-06-05 Semiconductor device

Publications (2)

Publication Number Publication Date
EP3748855A1 EP3748855A1 (en) 2020-12-09
EP3748855A4 true EP3748855A4 (en) 2021-01-20

Family

ID=68842215

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19818654.6A Pending EP3748855A4 (en) 2018-06-15 2019-06-05 Semiconductor device

Country Status (4)

Country Link
US (1) US11115035B2 (en)
EP (1) EP3748855A4 (en)
JP (1) JP7255790B2 (en)
WO (1) WO2019239984A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI750021B (en) * 2021-02-01 2021-12-11 瑞昱半導體股份有限公司 Reliability detection device and reliability detection method
WO2023161758A1 (en) * 2022-02-25 2023-08-31 株式会社半導体エネルギー研究所 Semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0570158A2 (en) * 1992-05-08 1993-11-18 Cyrix Corporation A stable clock generator circuit with clock multiplication
JPH06303135A (en) * 1993-04-13 1994-10-28 Hitachi Ltd Clock generating circuit
WO2002078228A2 (en) * 2001-03-27 2002-10-03 Igor Anatolievich Abrosimov Receiver with recovery circuit using oversampling and majority decision
EP2645568A2 (en) * 2012-03-30 2013-10-02 Fujitsu Limited Variable delay circuit

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5934013B2 (en) * 1979-04-06 1984-08-20 株式会社京三製作所 Majority decision method
JPS5934013A (en) 1982-08-19 1984-02-24 Matsushita Electric Ind Co Ltd Flow direction control unit
JP3181457B2 (en) * 1993-12-27 2001-07-03 三菱電機株式会社 Redundant clock circuit
US6728327B1 (en) * 2000-01-05 2004-04-27 Lsi Logic Corporation Lower-jitter phase-locked loop
JP3724398B2 (en) * 2001-02-20 2005-12-07 ティアック株式会社 Signal processing circuit and signal processing method
JP2003163583A (en) 2001-11-22 2003-06-06 Toshiba Corp Asynchronous noise filter circuit
JP5934013B2 (en) 2012-04-05 2016-06-15 ヒロセ株式会社 Scaffolding structure of reinforced earth wall and its installation jig
WO2014203468A1 (en) 2013-06-18 2014-12-24 パナソニックIpマネジメント株式会社 Induction heating cooker
US9372752B2 (en) 2013-12-27 2016-06-21 Intel Corporation Assisted coherent shared memory
JP6852408B2 (en) 2017-01-18 2021-03-31 住友ゴム工業株式会社 tire
JP7193495B2 (en) 2020-03-31 2022-12-20 トヨタ自動車株式会社 Thermal management system for vehicles

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0570158A2 (en) * 1992-05-08 1993-11-18 Cyrix Corporation A stable clock generator circuit with clock multiplication
JPH06303135A (en) * 1993-04-13 1994-10-28 Hitachi Ltd Clock generating circuit
WO2002078228A2 (en) * 2001-03-27 2002-10-03 Igor Anatolievich Abrosimov Receiver with recovery circuit using oversampling and majority decision
EP2645568A2 (en) * 2012-03-30 2013-10-02 Fujitsu Limited Variable delay circuit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2019239984A1 *

Also Published As

Publication number Publication date
WO2019239984A1 (en) 2019-12-19
EP3748855A1 (en) 2020-12-09
US11115035B2 (en) 2021-09-07
JP2019220763A (en) 2019-12-26
JP7255790B2 (en) 2023-04-11
US20210099180A1 (en) 2021-04-01

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