EP3748855A4 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- EP3748855A4 EP3748855A4 EP19818654.6A EP19818654A EP3748855A4 EP 3748855 A4 EP3748855 A4 EP 3748855A4 EP 19818654 A EP19818654 A EP 19818654A EP 3748855 A4 EP3748855 A4 EP 3748855A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- semiconductor device
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/26—Time-delay networks
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
- H03K5/1252—Suppression or limitation of noise or interference
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/131—Digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
- H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018114846A JP7255790B2 (en) | 2018-06-15 | 2018-06-15 | semiconductor equipment |
PCT/JP2019/022356 WO2019239984A1 (en) | 2018-06-15 | 2019-06-05 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
EP3748855A1 EP3748855A1 (en) | 2020-12-09 |
EP3748855A4 true EP3748855A4 (en) | 2021-01-20 |
Family
ID=68842215
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP19818654.6A Pending EP3748855A4 (en) | 2018-06-15 | 2019-06-05 | Semiconductor device |
Country Status (4)
Country | Link |
---|---|
US (1) | US11115035B2 (en) |
EP (1) | EP3748855A4 (en) |
JP (1) | JP7255790B2 (en) |
WO (1) | WO2019239984A1 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI750021B (en) * | 2021-02-01 | 2021-12-11 | 瑞昱半導體股份有限公司 | Reliability detection device and reliability detection method |
WO2023161758A1 (en) * | 2022-02-25 | 2023-08-31 | 株式会社半導体エネルギー研究所 | Semiconductor device |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0570158A2 (en) * | 1992-05-08 | 1993-11-18 | Cyrix Corporation | A stable clock generator circuit with clock multiplication |
JPH06303135A (en) * | 1993-04-13 | 1994-10-28 | Hitachi Ltd | Clock generating circuit |
WO2002078228A2 (en) * | 2001-03-27 | 2002-10-03 | Igor Anatolievich Abrosimov | Receiver with recovery circuit using oversampling and majority decision |
EP2645568A2 (en) * | 2012-03-30 | 2013-10-02 | Fujitsu Limited | Variable delay circuit |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5934013B2 (en) * | 1979-04-06 | 1984-08-20 | 株式会社京三製作所 | Majority decision method |
JPS5934013A (en) | 1982-08-19 | 1984-02-24 | Matsushita Electric Ind Co Ltd | Flow direction control unit |
JP3181457B2 (en) * | 1993-12-27 | 2001-07-03 | 三菱電機株式会社 | Redundant clock circuit |
US6728327B1 (en) * | 2000-01-05 | 2004-04-27 | Lsi Logic Corporation | Lower-jitter phase-locked loop |
JP3724398B2 (en) * | 2001-02-20 | 2005-12-07 | ティアック株式会社 | Signal processing circuit and signal processing method |
JP2003163583A (en) | 2001-11-22 | 2003-06-06 | Toshiba Corp | Asynchronous noise filter circuit |
JP5934013B2 (en) | 2012-04-05 | 2016-06-15 | ヒロセ株式会社 | Scaffolding structure of reinforced earth wall and its installation jig |
WO2014203468A1 (en) | 2013-06-18 | 2014-12-24 | パナソニックIpマネジメント株式会社 | Induction heating cooker |
US9372752B2 (en) | 2013-12-27 | 2016-06-21 | Intel Corporation | Assisted coherent shared memory |
JP6852408B2 (en) | 2017-01-18 | 2021-03-31 | 住友ゴム工業株式会社 | tire |
JP7193495B2 (en) | 2020-03-31 | 2022-12-20 | トヨタ自動車株式会社 | Thermal management system for vehicles |
-
2018
- 2018-06-15 JP JP2018114846A patent/JP7255790B2/en active Active
-
2019
- 2019-06-05 WO PCT/JP2019/022356 patent/WO2019239984A1/en unknown
- 2019-06-05 US US16/970,750 patent/US11115035B2/en active Active
- 2019-06-05 EP EP19818654.6A patent/EP3748855A4/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0570158A2 (en) * | 1992-05-08 | 1993-11-18 | Cyrix Corporation | A stable clock generator circuit with clock multiplication |
JPH06303135A (en) * | 1993-04-13 | 1994-10-28 | Hitachi Ltd | Clock generating circuit |
WO2002078228A2 (en) * | 2001-03-27 | 2002-10-03 | Igor Anatolievich Abrosimov | Receiver with recovery circuit using oversampling and majority decision |
EP2645568A2 (en) * | 2012-03-30 | 2013-10-02 | Fujitsu Limited | Variable delay circuit |
Non-Patent Citations (1)
Title |
---|
See also references of WO2019239984A1 * |
Also Published As
Publication number | Publication date |
---|---|
WO2019239984A1 (en) | 2019-12-19 |
EP3748855A1 (en) | 2020-12-09 |
US11115035B2 (en) | 2021-09-07 |
JP2019220763A (en) | 2019-12-26 |
JP7255790B2 (en) | 2023-04-11 |
US20210099180A1 (en) | 2021-04-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE |
|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE |
|
17P | Request for examination filed |
Effective date: 20200820 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
AX | Request for extension of the european patent |
Extension state: BA ME |
|
A4 | Supplementary search report drawn up and despatched |
Effective date: 20201217 |
|
RIC1 | Information provided on ipc code assigned before grant |
Ipc: H03K 5/00 20060101ALI20201211BHEP Ipc: H03K 19/003 20060101AFI20201211BHEP Ipc: H03K 5/131 20140101ALI20201211BHEP Ipc: G06F 1/04 20060101ALI20201211BHEP Ipc: H03K 3/023 20060101ALI20201211BHEP |
|
DAV | Request for validation of the european patent (deleted) | ||
DAX | Request for extension of the european patent (deleted) | ||
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: EXAMINATION IS IN PROGRESS |
|
17Q | First examination report despatched |
Effective date: 20230724 |