JP7255790B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP7255790B2
JP7255790B2 JP2018114846A JP2018114846A JP7255790B2 JP 7255790 B2 JP7255790 B2 JP 7255790B2 JP 2018114846 A JP2018114846 A JP 2018114846A JP 2018114846 A JP2018114846 A JP 2018114846A JP 7255790 B2 JP7255790 B2 JP 7255790B2
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Japan
Prior art keywords
filter
circuit
delay
output
signal
Prior art date
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Application number
JP2018114846A
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English (en)
Japanese (ja)
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JP2019220763A5 (enExample
JP2019220763A (ja
Inventor
貴則 成田
大介 松浦
茂 石井
大輔 小林
和之 廣瀬
治 川崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Heavy Industries Ltd
Japan Aerospace Exploration Agency JAXA
Original Assignee
Mitsubishi Heavy Industries Ltd
Japan Aerospace Exploration Agency JAXA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Heavy Industries Ltd, Japan Aerospace Exploration Agency JAXA filed Critical Mitsubishi Heavy Industries Ltd
Priority to JP2018114846A priority Critical patent/JP7255790B2/ja
Priority to PCT/JP2019/022356 priority patent/WO2019239984A1/ja
Priority to US16/970,750 priority patent/US11115035B2/en
Priority to EP19818654.6A priority patent/EP3748855A4/en
Publication of JP2019220763A publication Critical patent/JP2019220763A/ja
Publication of JP2019220763A5 publication Critical patent/JP2019220763A5/ja
Application granted granted Critical
Publication of JP7255790B2 publication Critical patent/JP7255790B2/ja
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/26—Time-delay networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
    • H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)
  • Logic Circuits (AREA)
JP2018114846A 2018-06-15 2018-06-15 半導体装置 Active JP7255790B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2018114846A JP7255790B2 (ja) 2018-06-15 2018-06-15 半導体装置
PCT/JP2019/022356 WO2019239984A1 (ja) 2018-06-15 2019-06-05 半導体装置
US16/970,750 US11115035B2 (en) 2018-06-15 2019-06-05 Semiconductor devices
EP19818654.6A EP3748855A4 (en) 2018-06-15 2019-06-05 SEMICONDUCTOR DEVICE

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2018114846A JP7255790B2 (ja) 2018-06-15 2018-06-15 半導体装置

Publications (3)

Publication Number Publication Date
JP2019220763A JP2019220763A (ja) 2019-12-26
JP2019220763A5 JP2019220763A5 (enExample) 2021-04-01
JP7255790B2 true JP7255790B2 (ja) 2023-04-11

Family

ID=68842215

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018114846A Active JP7255790B2 (ja) 2018-06-15 2018-06-15 半導体装置

Country Status (4)

Country Link
US (1) US11115035B2 (enExample)
EP (1) EP3748855A4 (enExample)
JP (1) JP7255790B2 (enExample)
WO (1) WO2019239984A1 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI750021B (zh) * 2021-02-01 2021-12-11 瑞昱半導體股份有限公司 可靠度偵測裝置與可靠度偵測方法
JPWO2023161758A1 (enExample) * 2022-02-25 2023-08-31

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6728327B1 (en) 2000-01-05 2004-04-27 Lsi Logic Corporation Lower-jitter phase-locked loop
JP5934013B2 (ja) 2012-04-05 2016-06-15 ヒロセ株式会社 補強土壁の足場構造及びその設置治具

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5934013B2 (ja) * 1979-04-06 1984-08-20 株式会社京三製作所 多数決判定方式
JPS5934013A (ja) 1982-08-19 1984-02-24 Matsushita Electric Ind Co Ltd 流れ方向制御装置
EP0570158B1 (en) 1992-05-08 2000-01-19 National Semiconductor Corporation Frequency multiplication circuit and method for generating a stable clock signal
JPH06303135A (ja) * 1993-04-13 1994-10-28 Hitachi Ltd クロック発生回路
JP3181457B2 (ja) * 1993-12-27 2001-07-03 三菱電機株式会社 冗長クロック回路
JP3724398B2 (ja) * 2001-02-20 2005-12-07 ティアック株式会社 信号処理回路及び信号処理方法
EP1386441B1 (en) 2001-03-27 2004-08-18 Acuid Corporation (Guernsey) Limited Receiver with recovery circuit using oversampling and majority decision
JP2003163583A (ja) 2001-11-22 2003-06-06 Toshiba Corp 非同期型ノイズフィルタ回路
JP5793460B2 (ja) 2012-03-30 2015-10-14 富士通株式会社 可変遅延回路
JP6852408B2 (ja) 2017-01-18 2021-03-31 住友ゴム工業株式会社 タイヤ

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6728327B1 (en) 2000-01-05 2004-04-27 Lsi Logic Corporation Lower-jitter phase-locked loop
JP5934013B2 (ja) 2012-04-05 2016-06-15 ヒロセ株式会社 補強土壁の足場構造及びその設置治具

Also Published As

Publication number Publication date
EP3748855A4 (en) 2021-01-20
WO2019239984A1 (ja) 2019-12-19
EP3748855A1 (en) 2020-12-09
US20210099180A1 (en) 2021-04-01
JP2019220763A (ja) 2019-12-26
US11115035B2 (en) 2021-09-07

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