WO2019007344A1 - 半导体器件的栅极结构及其制造方法 - Google Patents

半导体器件的栅极结构及其制造方法 Download PDF

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Publication number
WO2019007344A1
WO2019007344A1 PCT/CN2018/094359 CN2018094359W WO2019007344A1 WO 2019007344 A1 WO2019007344 A1 WO 2019007344A1 CN 2018094359 W CN2018094359 W CN 2018094359W WO 2019007344 A1 WO2019007344 A1 WO 2019007344A1
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Prior art keywords
trench
silicon oxide
gate
conductivity type
sidewall
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PCT/CN2018/094359
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English (en)
French (fr)
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祁树坤
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无锡华润上华科技有限公司
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Priority to US16/483,396 priority Critical patent/US11088253B2/en
Priority to JP2019540366A priority patent/JP6846527B2/ja
Publication of WO2019007344A1 publication Critical patent/WO2019007344A1/zh

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Definitions

  • the present application relates to the field of semiconductor manufacturing, and in particular to a semiconductor device gate structure, and to a method of fabricating a semiconductor device gate structure.
  • a semiconductor device gate structure and a method of fabricating the same are provided.
  • a semiconductor device gate structure includes a trench gate and a planar gate, the planar gate includes a plurality of mutually separated polysilicon structures, and the semiconductor device gate structure further includes: a well region, which is a second conductivity type, The trench gate is adjacent to and disposed under the planar gate; the first conductive type doped region is disposed in the well region and includes a plurality of mutually separated regions, each region being disposed adjacent to the polysilicon Under the structure, each of the regions is electrically connected to the planar gate; the first conductivity type and the second conductivity type are opposite conductivity types; and the source is a first conductivity type and is disposed in the well region;
  • the trench gate includes: a silicon oxide fill comprising a sidewall silicon oxide on a sidewall of the trench of the trench gate and a bottom silicon oxide at a bottom of the trench gate, the sidewall silicon oxide The thickness of the lower gate is thicker; the control gate is made of polysilicon, is located at the upper portion of the trench gate, and the side surface is
  • a method for fabricating a gate structure of a semiconductor device comprising: step A, forming a trench on a surface of the wafer; and step B, filling the trench with silicon oxide by deposition; and step C, removing the trench by etching a portion of the surface of the silicon oxide in the trench; step D, forming a silicon oxide corner structure at a corner of the top of the trench by thermal oxidation, the silicon oxide corner structure being gradually changed from a corner to a silicon oxide located inside the trench a thick structure; step E, depositing a nitrogen-containing compound on the surface of the wafer to cover the surface of the silicon oxide in the trench and the surface of the silicon oxide corner structure; and step F, dry etching the nitrogen-containing compound, Removing a nitrogen-containing compound on the surface of the silicon oxide in the trench, the surface of the silicon oxide corner structure forming a sidewall of the nitrogen-containing compound extending in the trench; and step G, using the sidewall residue of the nitrogen-containing compound as a mask, Removing a portion of
  • FIG. 1 is a flow chart showing a method of fabricating a gate structure of a semiconductor device in an embodiment
  • FIG. 2 to FIG. 12 are cross-sectional views showing a device manufactured by a manufacturing method using a gate structure of a semiconductor device in a manufacturing process
  • Figure 13 is a schematic illustration of the potential of a planar gate, a control gate, and a doped region of a first conductivity type joined together in an embodiment.
  • the vocabulary of the semiconductor field used herein is a technical vocabulary commonly used by those skilled in the art, for example, for P-type and N-type impurities, to distinguish the doping concentration, the simple P+ type represents a heavily doped concentration of the P-type, and the P-type represents P type with doping concentration, P-type represents P type with light doping concentration, N+ type represents N type with heavy doping concentration, N type represents N type with medium doping concentration, and N type represents light doping concentration N type.
  • FIG. 1 is a flow chart showing a method of fabricating a gate structure of a semiconductor device in an embodiment, including the following steps:
  • a deep trench suitable for the trench gate can be etched on the surface of the wafer (in this embodiment, a silicon wafer) by a process known in the art, and the specific depth can be selected according to the design parameters of the device with reference to the prior art.
  • the etched trench can be etched by using silicon nitride as a hard mask, that is, the silicon nitride film layer on the surface of the wafer is patterned before etching the trench, and the exposed nitride is exposed.
  • a trench is etched at the window of the silicon layer, and a silicon nitride layer is formed around the top of the trench after the etching is completed.
  • the etching of the trenches is performed by a reactive ion etching (RIE) process, and in other embodiments, etching can be performed by other trench etching processes known in the art.
  • RIE reactive ion etching
  • a low doping concentration epitaxial layer 102 is epitaxially deposited on a highly doped concentration substrate by an epitaxial process, and the etched trench is formed in the epitaxial layer 102.
  • step S120 is a deposition of silicon oxide by a high density plasma chemical vapor deposition (HDPCVD) process to obtain a better morphology.
  • a silicon oxide layer may also be deposited by other deposition processes known in the art according to actual needs.
  • the excess silicon oxide layer can be removed by chemical mechanical polishing (CMP), that is, the silicon oxide layer exposed outside the trench is removed.
  • CMP is to polish the silicon oxide layer to the silicon nitride layer.
  • step S130 is performed by a high density plasma etching process.
  • a special corner morphology is formed by oxidation after etching, that is, the surface of the silicon oxide in the trench is similar to a hemispherical shape. Concave. From the corner, the silicon oxide inside the trench gradually thickens to form a rounded corner, as shown in FIG. In Fig. 2, a trench is formed on the surface of the silicon wafer, the trench is filled with silicon oxide 202, and a silicon nitride layer 302 is formed around the top of the trench.
  • the silicon oxide corner structure is obtained by low temperature oxidation of 800 to 950 degrees Celsius.
  • Low temperature oxidation is used because the inventors have found that if a higher temperature (for example, sacrificial oxidation of 1000 degrees Celsius) is used, the doping ions in the high concentration substrate of the wafer are easily de-amplified into the low concentration epitaxial layer 102, the device Performance has a negative impact.
  • a higher temperature for example, sacrificial oxidation of 1000 degrees Celsius
  • a thin layer of nitrogen-containing compound is formed by chemical vapor deposition, which is subsequently used as a hard mask for etching.
  • the nitrogen-containing compound may be silicon nitride, silicon oxynitride, boron nitride, titanium nitride or the like, and silicon nitride which is commonly used in the art may be employed in view of universality.
  • the nitrogen-containing compound on the surface of the silicon oxide 202 in the trench is removed by the anisotropy of the dry etching, and the sidewall of the nitrogen-containing compound extending in the trench is formed on the surface of the silicon oxide corner structure.
  • the nitrogen-containing compound sidewall residue 304 serves as a sidewall structure of the trench together with a portion of the silicon oxide 202 in the trench.
  • the silicon oxide 202 is etched to a deeper depth due to etching, while the silicon oxide 202 at the sidewall portion of the trench is also retained by the barrier of the nitrogen-containing compound sidewall residue 304, and the remaining silicon oxide remains. 202 gradually thickens from the bottom of the nitrogen-containing compound sidewall residue 304.
  • the use of the nitrogen-containing compound sidewall residue 304 as a hard mask etch can eliminate the need for a lithographic plate and saves cost.
  • the step S170 may be dry etching, and in this embodiment, high-density plasma etching is employed.
  • step S170 If the etching of step S170 is too deep, the morphology of the silicon oxide 202 of the sidewall cannot be ensured. Therefore, the steps of S150 to S170 above are repeated, and the etching is performed multiple times until the desired thickness of the bottom silicon oxide is obtained.
  • the specific depth of each etch requires experimentation to collect data.
  • the silicon oxide in the trench includes bottom silicon oxide and sidewall silicon oxide, and the thickness of the sidewall silicon oxide is gradually thickened from the top of the trench to the bottom of the trench. It can be understood that if the depth of the groove is shallow, only steps S150 to S170 need to be performed once.
  • wet etching may be employed, for example, etching with concentrated phosphoric acid as an etchant.
  • etching with concentrated phosphoric acid as an etchant.
  • the silicon nitride layer 302 and the nitrogen-containing compound sidewall residue 304 are removed together by concentrated phosphoric acid.
  • Polysilicon is filled into the trench according to the thickness required for the shield gate, as shown in FIG.
  • excess polysilicon can be deposited into the trenches, then CMP and etched back to the desired shield gate thickness to simplify the process.
  • an isolated silicon oxide 204 is formed.
  • the isolating silicon oxide 204 can be prepared by a process such as growing a high temperature oxide film (HTO) or a high density plasma chemical vapor deposition silicon oxide.
  • the shield gate 404 adopts a single-segment structure; in other embodiments, the shield gate 404 may also adopt a multi-segment structure, that is, the shield gate is a plurality of layers, and each layer is separated by a layer of isolation silicon oxide. Specifically, one or more segments can be flexibly selected according to the depth of the trench (determined by the withstand voltage of the device).
  • the formed shield gate 404 is used as a step field plate along the drift region of the trench sidewall, which helps to enhance the carrier concentration of the channel multi-sub-region 502 during operation (refer to the channel multi-sub-region 502 for specific reference) The following examples) reduce the on-resistance.
  • steps S220 and S230 are repeatedly performed n times in sequence.
  • the polysilicon is continuously filled into the trenches and the isolation silicon oxide 204 to form a control gate 402, see FIG.
  • the polysilicon filled in step S240 is in-situ polysilicon.
  • control gate 402 may be planarized by chemical mechanical polishing.
  • the step of forming the longitudinal channel multi-sub-region 502 on both sides of the trench by ion implantation is further included between steps S230 and S240, see FIG.
  • the semiconductor device is of the N type
  • the channel multi-sub-region 502 is an N-type ring (formed by implanting N-type ions).
  • the appropriate implantation energy can also be selected according to the depth of the shielding gate 404 (distance from the surface of the silicon wafer), and multiple N-type rings and P are formed by sequentially injecting N-type ions and P-type ions multiple times.
  • a longitudinal channel multi-sub-region composed of a ring.
  • the carrier concentration of the channel multi-sub-region 502 during operation is affected by the thickness of the control gate 402 and the isolation silicon oxide 204, contributing to the formation of the trench sidewall top to the sidewall spacer of the channel multi-sub-region 502, reducing On resistance.
  • the well region 503 is formed over the channel multi-sub-region 502 on one side of the trench, and the well can be pushed after ion implantation.
  • a plurality of polysilicon structures 406 are formed by photolithography and etching.
  • a portion of the polysilicon structure 406 is formed on the well region 503 and partially formed on the trench.
  • the method for fabricating the gate structure of the above semiconductor device uses the nitrogen-containing compound sidewall residue 304 as a hard mask etching, which can eliminate the need for a lithographic plate and can save cost.
  • the formation of silicon oxide in the trench by deposition + etching reduces the oxidation time and improves the production efficiency relative to the thermal oxidation.
  • the step of performing sidewall oxidation on the trench before the step S120 is further included.
  • the sidewall oxidation may serve to repair the defects of the trench etched in the inner wall of the trench and the silicon surface at the bottom of the trench in step S110, for example, defects caused by high-energy particle collision by reactive ion etching, eliminating the defect to generate gate oxide The negative impact.
  • the resulting silicon oxide may also be stripped after oxidation of the sidewalls.
  • step S262 is further included: a plurality of mutually separated first conductive type doped regions 504 are formed under the adjacent polysilicon structure 406 by ion implantation.
  • a cross-sectional view of the device after completion of step S262 is shown in FIG.
  • the photoresist photolithographically in step S260 remains as a mask.
  • step S270 it is also necessary in step S270 to connect the first conductivity type doping region 504 to the planar gate as shown in FIG.
  • the first conductivity type doping region 504 can enhance carrier mobility in the channel below the planar gate when the device is turned on, and reduce the on-resistance of the lateral channel.
  • one of the first conductive type doped regions 504 injected in step S262 serves as a source, and is not connected to a planar gate but is a bulk or ground.
  • the present application also provides a gate structure of a semiconductor device which can be fabricated by the aforementioned manufacturing method.
  • the gate structure includes a trench gate, a planar gate, a well region 503, a first conductivity type doping region 504, and a source electrode 504a.
  • the planar gate includes a plurality of polysilicon structures 406 that are separated from each other.
  • the well region 503 is of a second conductivity type adjacent to the trench gate and disposed under the planar gate.
  • the first conductive type doped region 504 is disposed in the well region 503 and includes a plurality of mutually separated regions, each region being disposed under two adjacent polysilicon structures 406, and each region is electrically connected to the planar gate.
  • the semiconductor device is an N-type device
  • the first conductivity type is N-type
  • the second conductivity type is P-type.
  • the trench gate includes a silicon oxide fill 202, a control gate 402, a shield gate 404, and an isolation silicon oxide 204.
  • the silicon oxide fill 202 includes sidewall silicon oxide on the trench sidewalls of the trench gate and bottom silicon oxide at the bottom of the trench gate, the thicker the sidewall silicon oxide is, the thicker it is.
  • the control gate 402 is made of polysilicon, located on the upper portion of the trench gate, and the sides are surrounded by the sidewall silicon oxide. The control gate 402 is electrically connected to the planar gate.
  • the shield grid 404 is made of polysilicon material, and has a single-stage structure in the embodiment shown in FIG.
  • the shield gate 404 may also be a longitudinally arranged multi-segment structure, and each adjacent shield gate 404 is separated by an isolation silicon oxide 204. Whether the shielding gate 404 adopts a single segment or a multi-segment structure can be flexibly selected according to the depth of the trench.
  • the isolation silicon oxide 204 is filled between the longitudinally adjacent control gates 402 and the shield gates 404.
  • the isolation silicon oxide 204 is also filled between adjacent shielded gates 404.
  • the gate structure of the above semiconductor device adopts a structure of a planar gate + a vertical trench gate, and the trench gate includes a vertical control gate and a shield gate.
  • the split type first conductivity type doping region can improve the carrier mobility in the channel under the planar gate and reduce the on-resistance of the lateral channel when the device is turned on.
  • the gate structure further includes a channel multi-sub-region 502 disposed on both sides of the trench gate, and the well region 503 is located above the trench multi-sub-region 502 on one side of the trench gate.
  • the channel multi-sub-region 502 is an N-ring.
  • the shield gate 404 and the isolation silicon oxide 204 are formed, they are formed by implanting N-type ions.
  • the appropriate implantation energy can also be selected according to the depth of the shielding gate 404 (distance from the surface of the silicon wafer), and multiple N-type rings and P are formed by sequentially injecting N-type ions and P-type ions multiple times.
  • a longitudinal channel multi-sub-region composed of a ring.
  • the carrier concentration of the channel multi-sub-region 502 during operation is affected by the thickness of the control gate 402 and the isolation silicon oxide 204, contributing to the formation of the trench sidewall top to the sidewall spacer of the channel multi-sub-region 502, reducing On resistance.
  • the shield gate 404 is used as a stepped field plate along the drift region of the trench sidewalls, which helps to enhance the carrier concentration of the channel multi-sub-region 502 during operation.
  • the above semiconductor device gate structure is particularly suitable for LDMOS devices, and is also applicable to other semiconductor devices which can adopt a trench gate structure.

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Abstract

一种半导体器件的栅极结构，包括沟槽栅和平面栅，平面栅包括多块相互分离的多晶硅结构(406)，该栅极结构还包括：第一导电类型掺杂区(504)，设于阱区 (503) 内，包括多个相互分离的区域，各区域电性连接至平面栅；沟槽栅包括控制栅(402)，位于沟槽栅中的上部，控制栅(402)电性连接至平面栅；沟槽栅还包括屏蔽栅(404)，为单段或纵向排列的多段结构。

Description

半导体器件的栅极结构及其制造方法 技术领域
本申请涉及半导体制造领域，特别是涉及一种半导体器件栅极结构，还涉及一种半导体器件栅极结构的制造方法。
背景技术
如何在恒定的器件长度(恒定面积、恒定导通电阻)下，优化沟槽隔离工艺、改善沟槽形貌，从而优化击穿时电场分布、提高击穿电压，进而为持续降低导通电阻Ron,sp(导通电阻)拓展优化空间，是横向扩散金属氧化物半导体场效应管(LDMOSFET)器件持续改善、优化的方向。
发明内容
根据本申请的各种实施例，提供一种半导体器件栅极结构及其制造方法。
一种半导体器件栅极结构，包括沟槽栅和平面栅，所述平面栅包括多块相互分离的多晶硅结构，所述半导体器件栅极结构还包括：阱区，为第二导电类型，与所述沟槽栅相邻且设于所述平面栅下方；第一导电类型掺杂区，设于所述阱区内，包括多个相互分离的区域，每个区域设于相邻的所述多晶硅结构下方，各所述区域电性连接至所述平面栅；所述第一导电类型和第二导电类型为相反的导电类型；源极，为第一导电类型，设于所述阱区内；所述沟槽栅包括：氧化硅填充，包括位于所述沟槽栅的沟槽侧壁的侧壁氧化硅和位于所述沟槽栅的底部的底部氧化硅，所述侧壁氧化硅越往下厚度越厚；控制栅，为多晶硅材质，位于所述沟槽栅的上部，且侧面被所述侧壁氧化硅包围，所述控制栅电性连接至所述平面栅；屏蔽栅，为多晶硅材质，为单段或纵向排列的多段结构；隔离氧化硅，填充于纵向上相邻的控制栅和屏蔽栅 之间，或填充于纵向上相邻的控制栅和屏蔽栅之间、多段结构的相邻屏蔽栅之间。
一种半导体器件的栅极结构的制造方法，包括：步骤A，在晶圆表面形成沟槽；步骤B，通过淀积向所述沟槽内填充氧化硅；步骤C，通过刻蚀去除掉沟槽内的氧化硅表面的一部分；步骤D，通过热氧化在沟槽顶部的拐角处形成氧化硅拐角结构，所述氧化硅拐角结构为从拐角处往下、位于沟槽内部的氧化硅逐渐变厚的结构；步骤E，在晶圆表面淀积含氮化合物，覆盖所述沟槽内的氧化硅表面及所述氧化硅拐角结构表面；步骤F，干法刻蚀所述含氮化合物，将沟槽内的氧化硅表面的含氮化合物去除，所述氧化硅拐角结构表面形成向沟槽内延伸的含氮化合物侧壁残留；步骤G，以所述含氮化合物侧壁残留为掩膜，通过刻蚀去除掉沟槽内的氧化硅表面的一部分；步骤H，去除所述沟槽内的含氮化合物；步骤I，向所述沟槽内填入多晶硅作为屏蔽栅；步骤J，在所述屏蔽栅上形成隔离氧化硅；步骤K，在所述隔离氧化硅上填入多晶硅作为控制栅；步骤L，通过注入第二导电类型的掺杂离子在与所述沟槽相邻的位置形成阱区；步骤M，在所述阱区上方形成多块相互分离的多晶硅结构作为平面栅；步骤N，将所述控制栅电性连接至所述平面栅。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1是一实施例中半导体器件栅极结构的制造方法的流程图；
图2至图12是一实施例中采用半导体器件栅极结构的制造方法制造的器件在制造过程中的剖视图；
图13是一实施例中将平面栅、控制栅及第一导电类型掺杂区的电位连到一起的示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
图1是一实施例中半导体器件栅极结构的制造方法的流程图，包括下列步骤：
S110，在晶圆表面形成沟槽。
可以采用本领域习知的工艺在晶圆(本实施例中为硅片)表面刻蚀出适用于沟槽栅极的深槽，具体深度可以根据器件的设计参数参照现有技术进行选择。在本实施例中，刻蚀沟槽可以采用氮化硅作为硬掩膜进行刻蚀，也就是说在刻蚀沟槽之前先图形化晶圆表面的氮化硅膜层，在露出的氮化硅层窗口处刻蚀出沟槽，刻蚀完成后沟槽顶部的周围形成有氮化硅层。在本实施例中，沟槽的刻蚀是采用反应离子刻蚀(RIE)工艺进行，在其他实施例中也可 以采用其他本领域习知的沟槽刻蚀工艺进行刻蚀。
在一个实施例中，通过外延工艺在高掺杂浓度的衬底上外延出低掺杂浓度的外延层102，刻蚀得到的沟槽是形成于外延层102中。
S120，通过淀积向沟槽内填充氧化硅。
通过淀积工艺形成氧化硅(SiO x)层的速度远大于传统的通过热氧化生长氧化硅层的速度。在本实施例中，步骤S120是采用高密度等离子化学气相淀积(HDPCVD)工艺进行氧化硅的淀积，可以获得较好的形貌。在其他实施例中也可以根据实际需求采用其他本领域习知的淀积工艺淀积氧化硅层。
淀积完后可以通过化学机械研磨(CMP)将多余的氧化硅层去除，即将露出于沟槽外面的氧化硅层去除。对于步骤S110采用氮化硅作为硬掩膜刻蚀出沟槽的实施例，CMP是将氧化硅层研磨至该氮化硅层。
S130，通过刻蚀去除掉沟槽内的氧化硅表面的一部分。
可以采用干法刻蚀，利用其各向异性获得合适的形貌。在其中一个实施例中，步骤S130选用高密度等离子刻蚀的工艺进行刻蚀。
S140，通过氧化在沟槽顶部的拐角处形成氧化硅拐角结构。
为了后续步骤中得到的含氮化合物侧壁残留能形成本方案所需的形貌，在刻蚀后通过氧化形成特殊的拐角形貌，即在沟槽内的氧化硅表面形成类似于半球形的凹面。从拐角处往下、位于沟槽内部的氧化硅逐渐变厚，从而形成圆滑的拐角，如图2所示。图2中在硅片的表面形成有沟槽，沟槽内填充有氧化硅202，沟槽顶部的周围形成有氮化硅层302。在本实施例中通过800～950摄氏度的低温氧化来得到该氧化硅拐角结构。采用低温氧化是因为发明人发现若采用较高的温度(例如1000摄氏度的牺牲氧化)，则晶圆的高浓度衬底中的掺杂离子容易反扩至低浓度的外延层102中，对器件性能产生负面影响。
S150，在晶圆表面淀积氮化硅，覆盖沟槽内的氧化硅表面及氧化硅拐角结构表面。
在本实施例中是通过化学气相淀积形成一层薄的含氮化合物，后续作为 刻蚀的硬掩膜。该含氮化合物可以是氮化硅、氮氧化硅、氮化硼、氮化钛等，考虑到普适性，可以采用本领域常用的氮化硅。
S160，干法刻蚀含氮化合物，氧化硅拐角结构表面形成向沟槽内延伸的含氮化合物侧壁残留。
参见图3，利用干法刻蚀的各向异性，将沟槽内的氧化硅202表面的含氮化合物去除，同时在氧化硅拐角结构表面形成向沟槽内延伸的含氮化合物侧壁残留304。含氮化合物侧壁残留304与沟槽内的一部分氧化硅202共同作为沟槽的侧壁结构。
S170，以含氮化合物侧壁残留为掩膜，通过刻蚀去除掉沟槽内的氧化硅表面的一部分。
参见图4，氧化硅202由于刻蚀被刻至更深的深度，同时沟槽侧壁位置处的氧化硅202因含氮化合物侧壁残留304的阻挡也会被保留下来，并且保留下来的氧化硅202从含氮化合物侧壁残留304底部往下逐渐变厚。采用含氮化合物侧壁残留304作为硬掩膜刻蚀，可以不需要光刻版，能够节省成本。为了获得越往下侧壁越厚的氧化硅202，步骤S170可以采用干法刻蚀，本实施例中是采用高密度等离子刻蚀。
步骤S170的刻蚀如果刻得过深，则就不能保证侧壁的氧化硅202形貌，故需重复以上S150～S170的步骤，通过多次刻蚀直至获得所需的底部氧化硅厚度，参见图5。也就是说，本方案可以方便地调节底部氧化硅厚度，进一步增大了降低反馈电容的空间。每次刻蚀的具体深度需要通过实验来收集数据。刻蚀至所需的底部氧化硅厚度后，沟槽内的氧化硅包括底部氧化硅和侧壁氧化硅，侧壁氧化硅的厚度从沟槽顶部至沟槽底部逐渐增厚。可以理解的，如果沟槽的深度较浅，则只需执行一次步骤S150～S170。
S210，去除沟槽内的含氮化合物。
为了将含氮化合物去除干净，可以采用湿法刻蚀，例如以浓磷酸为刻蚀剂进行刻蚀。本实施例中通过浓磷酸将氮化硅层302和含氮化合物侧壁残留304一并去除。
S220，向沟槽内填入多晶硅作为屏蔽栅。
根据屏蔽栅所需的厚度向沟槽内填入多晶硅，如图6所示。在一个实施例中，可以向沟槽内淀积过量的多晶硅，然后CMP并回刻多晶硅至所需的屏蔽栅厚度，以简化工艺。
S230，在屏蔽栅上形成隔离氧化硅。
参见图7，形成隔离氧化硅204。在一个实施例中，隔离氧化硅204可以采用生长高温氧化膜(HTO)或高密度等离子化学气相淀积氧化硅等工艺来制备。
在本实施例中，屏蔽栅404采用单段结构；在其他实施例中，屏蔽栅404也可以采用多段结构，即屏蔽栅为多层，每层之间通过一层隔离氧化硅隔开。具体可以根据沟槽的深度(受器件的耐压决定)灵活选择单段或多段。形成的屏蔽栅404作为沿沟槽侧壁漂移区的阶梯场板使用，其有助于提升沟道多子区502在工作时的载流子浓度(关于沟道多子区502的介绍具体参照后文的实施例)、降低导通电阻。在一个实施例中，假设屏蔽栅404为n段结构，则依次重复执行步骤S220和S230共n次。
S240，在隔离氧化硅上填入多晶硅作为控制栅。
继续向沟槽内、隔离氧化硅204上填入多晶硅，形成控制栅402，参见图9。在一个实施例中，步骤S240填入的多晶硅为自掺杂(in-situ)多晶硅。
在一个实施例中，步骤S240完成后可以通过化学机械研磨对控制栅402进行平坦化处理。
在本实施例中，步骤S230和S240之间还包括通过离子注入在沟槽两侧形成纵向沟道多子区502的步骤，参见图8。在本实施例中，半导体器件为N型，沟道多子区502为N型环(通过注入N型离子形成)。在其他实施例中，也可以根据屏蔽栅404的深度(距硅片表面的距离)选择合适的注入能量，通过先后注入N型离子和P型离子多次，形成由多个N型环和P型环组成的纵向沟道多子区。沟道多子区502在工作时的载流子浓度受控制栅402及隔离氧化硅204的厚度影响，有助于形成沟槽侧壁顶部至沟道多子区502的侧 壁沟道，降低导通电阻。
S250，通过注入第二导电类型的掺杂离子在与沟槽相邻的位置形成阱区。
参见图10，在本实施例中，阱区503形成于沟槽一侧的沟道多子区502上方，离子注入后可以进行推阱。
S260，在阱区上方形成多块相互分离的多晶硅结构作为平面栅。
参见图11，在硅片表面淀积一层多晶硅后，通过光刻和刻蚀形成多块多晶硅结构406。在本实施例中，部分多晶硅结构406形成于阱区503上、部分形成于沟槽上。
S270，将控制栅电性连接至平面栅。
上述半导体器件栅极结构的制造方法，采用含氮化合物侧壁残留304作为硬掩膜刻蚀，可以不需要光刻版，能够节省成本。采用淀积+刻蚀的方式形成沟槽内的氧化硅，相对于采用热氧化的方式，减少了氧化时间，提高了生产效率。
在一个实施例中，步骤S120之前还包括对沟槽进行侧壁氧化的步骤。侧壁氧化可以起到修复步骤S110的沟槽刻蚀在沟槽内壁和底部的硅表面产生的缺陷的作用，例如因反应离子刻蚀的高能粒子撞击产生的缺陷，消除该缺陷对栅氧产生的负面影响。在一个实施例中，侧壁氧化之后还可以将生成的氧化硅剥离。
在一个实施例中，步骤S260之后还包括步骤S262：通过离子注入在相邻的多晶硅结构406下方、阱区503内形成多个相互分离的第一导电类型掺杂区504。步骤S262完成后器件的剖面图如图12所示。离子注入时，步骤S260光刻的光刻胶仍然保留作为掩膜。步骤S270中还需要将第一导电类型掺杂区504也连接至平面栅，如图13所示。第一导电类型掺杂区504能够在器件导通时提升平面栅下方沟道中的载流子迁移率，降低横向沟道的导通电阻。在本实施例中，步骤S262注入的第一导电类型掺杂区504中有一处作为源极，不连接平面栅而是接体区(bulk)或接地。
本申请还提供一种半导体器件的栅极结构，其可以采用前述的制造方法 进行制造。参见图13，该栅极结构包括沟槽栅、平面栅、阱区503、第一导电类型掺杂区504及源极504a。
具体地，平面栅包括多块相互分离的多晶硅结构406。阱区503为第二导电类型，与沟槽栅相邻且设于平面栅下方。第一导电类型掺杂区504设于阱区503内，包括多个相互分离的区域，每个区域设于两相邻的多晶硅结构406下方，且各区域电性连接至平面栅。在本实施例中，半导体器件为N型器件，第一导电类型为N型，所述第二导电类型为P型。
沟槽栅包括氧化硅填充202、控制栅402、屏蔽栅404及隔离氧化硅204。具体地，氧化硅填充202包括位于沟槽栅的沟槽侧壁的侧壁氧化硅和位于沟槽栅的底部的底部氧化硅，侧壁氧化硅越往下厚度越厚。控制栅402为多晶硅材质，位于沟槽栅的上部，且侧面被侧壁氧化硅包围。控制栅402电性连接至平面栅。屏蔽栅404为多晶硅材质，在图13所示实施例中为单段结构。在其他实施例中，屏蔽栅404也可以为纵向排列的多段结构，相邻的每段屏蔽栅404之间通过隔离氧化硅204隔开。屏蔽栅404具体采用单段还是多段结构可以根据沟槽的深度灵活选择。隔离氧化硅204填充于纵向上相邻的控制栅402和屏蔽栅404之间。对于多段结构的屏蔽栅404，隔离氧化硅204还填充于相邻的每段屏蔽栅404之间。
上述半导体器件栅极结构，采用了平面栅+纵向槽栅的结构，且槽栅包括纵向的控制栅和屏蔽栅。采用分裂式的第一导电类型掺杂区，可在器件导通时提升平面栅下方沟道中的载流子迁移率，降低横向沟道的导通电阻。
在本实施例中，栅极结构还包括设于沟槽栅两侧的沟道多子区502，阱区503位于沟槽栅一侧的沟道多子区502上方。在一个实施例中，沟道多子区502为N型环。其为屏蔽栅404和隔离氧化硅204形成后，通过注入N型离子形成。在其他实施例中，也可以根据屏蔽栅404的深度(距硅片表面的距离)选择合适的注入能量，通过先后注入N型离子和P型离子多次，形成由多个N型环和P型环组成的纵向沟道多子区。沟道多子区502在工作时的载流子浓度受控制栅402及隔离氧化硅204的厚度影响，有助于形成沟槽侧 壁顶部至沟道多子区502的侧壁沟道，降低导通电阻。
屏蔽栅404作为沿沟槽侧壁漂移区的阶梯场板使用，其有助于提升沟道多子区502在工作时的载流子浓度。
上述半导体器件栅极结构尤其适用于LDMOS器件，也适用于其他可以采用沟槽栅极结构的半导体器件。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种半导体器件的栅极结构的制造方法，包括：
    步骤A，在晶圆表面形成沟槽；
    步骤B，通过淀积向所述沟槽内填充氧化硅；
    步骤C，通过刻蚀去除掉沟槽内的氧化硅表面的一部分；
    步骤D，通过热氧化在沟槽顶部的拐角处形成氧化硅拐角结构，所述氧化硅拐角结构为从拐角处往下、位于沟槽内部的氧化硅逐渐变厚的结构；
    步骤E，在晶圆表面淀积含氮化合物，覆盖所述沟槽内的氧化硅表面及所述氧化硅拐角结构表面；
    步骤F，干法刻蚀所述含氮化合物，将沟槽内的氧化硅表面的含氮化合物去除，所述氧化硅拐角结构表面形成向沟槽内延伸的含氮化合物侧壁残留；
    步骤G，以所述含氮化合物侧壁残留为掩膜，通过刻蚀去除掉沟槽内的氧化硅表面的一部分；
    步骤H，去除所述沟槽内的含氮化合物；
    步骤I，向所述沟槽内填入多晶硅作为屏蔽栅；
    步骤J，在所述屏蔽栅上形成隔离氧化硅；
    步骤K，在所述隔离氧化硅上填入多晶硅作为控制栅；
    步骤L，通过注入第二导电类型的掺杂离子在与所述沟槽相邻的位置形成阱区；
    步骤M，在所述阱区上方形成多块相互分离的多晶硅结构作为平面栅；
    步骤N，将所述控制栅电性连接至所述平面栅。
  2. 根据权利要求1所述的制造方法，其中，所述屏蔽栅为纵向排列的多段结构，相邻的屏蔽栅之间被所述隔离氧化硅隔离。
  3. 根据权利要求1所述的制造方法，其中，所述步骤M之后还包括通过离子注入在相邻多晶硅结构下方、所述阱区内形成多个相互分离的第一导电类型掺杂区的步骤，以及将各所述第一导电类型掺杂区连接至所述平面栅 的步骤；所述第一导电类型和第二导电类型为相反的导电类型。
  4. 根据权利要求1所述的制造方法，其中，所述步骤L之前还包括通过离子注入在所述沟槽两侧形成纵向沟道多子区的步骤，所述阱区形成于一侧的纵向沟道多子区的上方，所述步骤L是注入第一导电类型的离子。
  5. 根据权利要求1所述的制造方法，其中，所述步骤L之前还包括通过离子注入在所述沟槽两侧形成纵向沟道多子区的步骤，所述阱区形成于一侧的纵向沟道多子区的上方，所述步骤L包括注入第一导电类型的离子和第二导电类型的离子。
  6. 根据权利要求1所述的制造方法，其中，所述步骤B之前还包括对所述沟槽进行侧壁氧化的步骤。
  7. 根据权利要求1所述的制造方法，其中，所述步骤A是以氮化硅为掩膜刻蚀形成沟槽。
  8. 根据权利要求1所述的制造方法，其中，所述步骤B和步骤C之间，还包括通过化学机械研磨将露出于所述沟槽外面的氧化硅去除的步骤。
  9. 根据权利要求7所述的制造方法，其中，所述步骤B和步骤C之间，还包括将露出于所述沟槽外面的氧化硅研磨至所述氮化硅层的步骤。
  10. 根据权利要求1所述的制造方法，其中，还包括通过外延工艺在衬底上外延出外延层的步骤，所述外延层的掺杂浓度高于所述衬底，所述在晶圆表面形成沟槽的步骤，是在所述外延层中形成所述第一沟槽。
  11. 根据权利要求1所述的制造方法，其中，所述步骤H是以浓磷酸为刻蚀剂将所述含氮化合物去除。
  12. 根据权利要求1所述的制造方法，其中，所述步骤B是采用高密度等离子化学气相淀积工艺进行氧化硅的淀积。
  13. 根据权利要求1所述的制造方法，其中，所述步骤K之后还包括通过化学机械研磨对所述控制栅进行平坦化处理的步骤。
  14. 根据权利要求1所述的制造方法，其中，所述步骤M形成的多晶硅结构，部分形成于所述阱区上、部分形成于所述沟槽上。
  15. 根据权利要求1所述的制造方法，其中，步骤D的热氧化温度为800～950摄氏度。
  16. 根据权利要求1所述的制造方法，其中，还包括：
    依次重复执行步骤E至步骤G，直至将沟槽内的氧化硅刻蚀至所需的底部氧化硅厚度，每执行一次步骤F所述含氮化合物侧壁残留就进一步向沟槽内延伸，所述沟槽内的氧化硅包括底部氧化硅和侧壁氧化硅，所述侧壁氧化硅的厚度从沟槽顶部至沟槽底部逐渐增厚。
  17. 一种半导体器件栅极结构，包括：
    沟槽栅；
    平面栅，包括多块相互分离的多晶硅结构；阱区，为第二导电类型，与所述沟槽栅相邻且设于所述平面栅下方；
    第一导电类型掺杂区，设于所述阱区内，包括多个相互分离的区域，每个区域设于相邻的所述多晶硅结构下方，各所述区域电性连接至所述平面栅；所述第一导电类型和第二导电类型为相反的导电类型；及
    源极，为第一导电类型，设于所述阱区内；
    其中，所述沟槽栅包括：
    氧化硅填充，包括位于所述沟槽栅的沟槽侧壁的侧壁氧化硅和位于所述沟槽栅的底部的底部氧化硅，所述侧壁氧化硅越往下厚度越厚；
    控制栅，为多晶硅材质，位于所述沟槽栅的上部，且侧面被所述侧壁氧化硅包围，所述控制栅电性连接至所述平面栅；
    屏蔽栅，为多晶硅材质，且为单段结构；及
    隔离氧化硅，填充于纵向上相邻的控制栅和屏蔽栅之间。
  18. 根据权利要求17所述的半导体器件栅极结构，其中，所述第一导电类型为N型，所述第二导电类型为P型。
  19. 一种半导体器件栅极结构，包括：
    沟槽栅；
    平面栅，包括多块相互分离的多晶硅结构；
    阱区，为第二导电类型，与所述沟槽栅相邻且设于所述平面栅下方；
    第一导电类型掺杂区，设于所述阱区内，包括多个相互分离的区域，每个区域设于相邻的所述多晶硅结构下方，各所述区域电性连接至所述平面栅；所述第一导电类型和第二导电类型为相反的导电类型；及
    源极，为第一导电类型，设于所述阱区内；
    其中，所述沟槽栅包括：
    氧化硅填充，包括位于所述沟槽栅的沟槽侧壁的侧壁氧化硅和位于所述沟槽栅的底部的底部氧化硅，所述侧壁氧化硅越往下厚度越厚；
    控制栅，为多晶硅材质，位于所述沟槽栅的上部，且侧面被所述侧壁氧化硅包围，所述控制栅电性连接至所述平面栅；
    屏蔽栅，为多晶硅材质，且为纵向排列的多段结构；及
    隔离氧化硅，填充于纵向上相邻的控制栅和屏蔽栅之间、多段结构的相邻屏蔽栅之间。
  20. 根据权利要求19所述的半导体器件栅极结构，其中，所述第一导电类型为N型，所述第二导电类型为P型。
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