JP6846527B2 - 半導体デバイスのゲート構造および製造方法 - Google Patents
半導体デバイスのゲート構造および製造方法 Download PDFInfo
- Publication number
- JP6846527B2 JP6846527B2 JP2019540366A JP2019540366A JP6846527B2 JP 6846527 B2 JP6846527 B2 JP 6846527B2 JP 2019540366 A JP2019540366 A JP 2019540366A JP 2019540366 A JP2019540366 A JP 2019540366A JP 6846527 B2 JP6846527 B2 JP 6846527B2
- Authority
- JP
- Japan
- Prior art keywords
- trench
- gate
- silicon oxide
- polysilicon
- side wall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 37
- 238000004519 manufacturing process Methods 0.000 title claims description 35
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 105
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 105
- 238000000034 method Methods 0.000 claims description 42
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 38
- 229920005591 polysilicon Polymers 0.000 claims description 38
- 229910017464 nitrogen compound Inorganic materials 0.000 claims description 30
- 150000002830 nitrogen compounds Chemical class 0.000 claims description 30
- 238000005530 etching Methods 0.000 claims description 27
- 150000002500 ions Chemical class 0.000 claims description 21
- 230000003647 oxidation Effects 0.000 claims description 16
- 238000007254 oxidation reaction Methods 0.000 claims description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 239000000945 filler Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 238000000427 thin-film deposition Methods 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 238000001312 dry etching Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 238000005019 vapor deposition process Methods 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- -1 silicon nitrides Chemical class 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/66704—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Element Separation (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
204 絶縁シリコン酸化物)
402 コントロールゲート)
404 シールドゲート
406 ポリシリコン構造
503 ウエル領域
504 第1の伝導型のドープ領域
Claims (20)
- 半導体デバイスのゲート構造を製造する方法であって、
ウエハー表面上にトレンチを形成するステップと(ステップA)、
蒸着によって前記トレンチをシリコン酸化物で充填するステップと(ステップB)、
エッチングによって前記トレンチ内の前記シリコン酸化物の一部を除去するステップと(ステップC)、
熱酸化によって前記トレンチの上部コーナーにシリコン酸化物コーナー構造を形成するステップであって、前記シリコン酸化物コーナー構造は、前記トレンチ内の前記シリコン酸化物が前記コーナーから下方に徐々に厚くなる構造であるステップと(ステップD)、
ウエハー表面で窒素化合物を蒸着させて、前記シリコン酸化物の表面および前記シリコン酸化物コーナー構造の表面をカバーするステップと(ステップE)、
前記トレンチ内の前記シリコン酸化物の表面の前記窒素化合物を除去するために前記窒素化合物をドライエッチングして、前記シリコン酸化物コーナー構造の表面上の前記トレンチの中に延びる窒素化合物の側壁残留物を形成するステップと(ステップF)、
前記窒素化合物の側壁残留物をマスクとして用いてエッチングすることで前記トレンチ内の前記シリコン酸化物の一部を除去するステップと(ステップG)、
前記トレンチ内の前記窒素化合物を除去するステップと(ステップH)、
前記トレンチをシールドゲートとしてのポリシリコンで充填するステップと(ステップI)、
前記シールドゲート上に絶縁シリコン酸化物を形成するステップと(ステップJ)、
コントロールゲートとして前記絶縁シリコン酸化物上にポリシリコンを充填するステップと(ステップK)、
第2の伝導型のドープイオンを埋め込むことによって、前記トレンチに隣接するウエル領域を形成するステップと(ステップL)、
前記ウエル領域上にプレーナゲートとして互いに分離された複数のポリシリコン構造を形成するステップと(ステップM)、
前記コントロールゲートを前記プレーナゲートに電気的に接続するステップと(ステップN)、
を含む方法。 - 前記シールドゲートは、縦方向に配置された多重セグメント構造を有し、前記隣接するシールドゲートは、絶縁シリコン酸化物によって互いに分離される、請求項1に記載の方法。
- ステップMの後で、本方法は、イオンを埋め込むことによって、隣接するポリシリコン構造の下方かつ前記ウエル領域内で互いに分離された第1の伝導型の複数のドープ領域を形成するステップと、第1の伝導型のドープ領域をプレーナゲートにそれぞれ接続するステップと、をさらに含み、前記第1の伝導型および前記第2の伝導型は、反対の伝導型である、請求項1に記載の方法。
- ステップLの前で、本方法は、イオンを埋め込むことによって、前記トレンチの両側で垂直チャンネル多重キャリア領域を形成するステップをさらに含み、前記ウエル領域は、前記トレンチの片側で前記垂直チャンネル多重キャリア領域の上に形成され、第1の伝導型のイオンがステップLで埋め込まれる、請求項1に記載の方法。
- ステップLの前で、本方法は、イオンを埋め込むことによって、前記トレンチの両側で垂直チャンネル多重キャリア領域を形成するステップをさらに含み、前記ウエル領域は、前記トレンチの片側で前記垂直チャンネル多重キャリア領域の上に形成され、ステップLは、第1の伝導型のイオンおよび第2の伝導型のイオンを埋め込むステップを含む、請求項1に記載の方法。
- ステップBの前で、本方法は、前記トレンチの側壁を酸化するステップをさらに含む、請求項1に記載の方法。
- ステップAにおいて、前記トレンチは、シリコン窒化物をマスクとして用いてエッチングすることによって形成される、請求項1に記載の方法。
- ステップBとステップCとの間で、本方法は、前記トレンチの外側に露出したシリコン酸化物を化学機械研磨によって除去するステップをさらに含む、請求項1に記載の方法。
- ステップBとステップCとの間で、本方法は、前記トレンチの外側に露出したシリコン酸化物を前記シリコン窒化物と一致するまで研磨するステップをさらに含む、請求項7に記載の方法。
- 本方法は、エピタキシャルプロセスによって、基材上にエピタキシャル層をエピタキシャル成長させるステップをさらに含み、前記エピタキシャル層のドープ濃度は、前記基材のドーピング濃度よりも小さく、前記ウエハー表面上にトレンチを形成するステップにおいて、第1のトレンチが前記エピタキシャル層に形成される、請求項1に記載の方法。
- ステップHにおいて、前記窒素化合物は、エッチング液としての濃リン酸で除去される、請求項1に記載の方法。
- ステップBにおいて、シリコン酸化物は、高密度プラズマ化学蒸着プロセスを使用して蒸着される、請求項1に記載の方法。
- ステップKの後で、本方法は、化学機械研磨によって前記コントロールゲートを平坦化するステップをさらに含む、請求項1に記載の方法。
- ステップMによって形成された前記ポリシリコン構造の一部は、前記ウエル領域上に形成され、ステップMによって形成された前記ポリシリコン構造の他の部分は、前記トレンチ上に形成される、請求項1に記載の方法。
- ステップDの熱酸化温度は、800℃〜950℃の範囲である、請求項1に記載の方法。
- 前記トレンチ内の前記シリコン酸化物がエッチングされて底部シリコン酸化物の所望の厚さに達するまで、ステップE〜ステップGを連続して繰り返し、ステップFが行なわれる度に、前記窒素化合物の側壁残留物が前記トレンチの中にさらに延び、前記トレンチ内の前記シリコン酸化物は、底部シリコン酸化物および側壁シリコン酸化物を含み、前記側壁シリコン酸化物の厚さは、前記トレンチの上部から前記トレンチの底部まで徐々に厚くなる、請求項1に記載の方法。
- 半導体デバイスのゲート構造であって、
トレンチゲートと、
互いに分離された複数のポリシリコン構造を含むプレーナゲートと、
前記トレンチゲートに隣接しかつ前記プレーナゲートの下に配置される第2の伝導型のウエル領域と、
前記ウエル領域内に配置されて互いに分離された複数の領域を構成する第1の伝導型のドープ領域であって、前記領域の各々が、隣接するポリシリコン構造の下に配置され、それぞれの領域は、プレーナゲートに電気的に接続され、前記第1の伝導型および前記第2の伝導型は、反対の伝導型である、第1の伝導型のドープ領域と、
前記ウエル領域内に配置される第1の伝導型のソースと、
を備え、
前記トレンチゲートは、
前記トレンチゲートのトレンチ側壁に配置された側壁シリコン酸化物と、前記トレンチゲートの底部に配置された底部シリコン酸化物とを含み、前記側壁シリコン酸化物の厚さが下方に向かって厚くなる、シリコン酸化物充填材と、
前記トレンチゲートを覆って配置されたポリシリコン材料のコントロールゲートであって、前記コントロールゲートの側壁が、前記側壁シリコン酸化物によって囲まれ、前記コントロールゲートが、前記プレーナゲートと電気的に接続される、コントロールゲートと、
単一セグメント構造を有するポリシリコン材料のシールドゲートと、
垂直方向の隣接するコントロールゲートとシールドゲートとの間に充填される絶縁シリコン酸化物と、
を備える、半導体デバイスのゲート構造。 - 前記第1の伝導型はN型であり、前記第2の伝導型はP型である、請求項17に記載の半導体デバイスのゲート構造。
- 半導体デバイスのゲート構造であって、
トレンチゲートと、
互いに分離された複数のポリシリコン構造を含むプレーナゲートと、
前記トレンチゲートに隣接しかつ前記プレーナゲートの下に配置される第2の伝導型のウエル領域と、
前記ウエル領域内に配置されて互いに分離された複数の領域を構成する第1の伝導型のドープ領域であって、前記領域の各々が、隣接するポリシリコン構造の下に配置され、それぞれの領域は、プレーナゲートに電気的に接続され、前記第1の伝導型および前記第2の伝導型は、反対の伝導型である、第1の伝導型のドープ領域と、
前記ウエル領域内に配置される第1の伝導型のソースと、
を備え、
前記トレンチゲートは、
前記トレンチゲートのトレンチ側壁に配置された側壁シリコン酸化物と、前記トレンチゲートの底部に配置された底部シリコン酸化物とを含み、前記側壁シリコン酸化物の厚さが下方に向かって厚くなる、シリコン酸化物充填材と、
ポリシリコン材料であり前記トレンチゲートを覆って配置されたコントロールゲートであって、前記コントロールゲートの側壁が、前記側壁シリコン酸化物によって囲まれ、前記コントロールゲートが、前記プレーナゲートと電気的に接続される、コントロールゲートと、
縦方向に配置された多重セグメント構造を有するポリシリコン材料のシールドゲートと、
垂直方向の隣接するコントロールゲートとシールドゲートとの間でかつ前記多重セグメント構造のシールドゲートの間に充填される絶縁シリコン酸化物と、
を備える、半導体デバイスのゲート構造。 - 前記第1の伝導型はN型であり、前記第2の伝導型はP型である、請求項19に記載の半導体デバイスのゲート構造。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710534704.0 | 2017-07-03 | ||
CN201710534704.0A CN109216175B (zh) | 2017-07-03 | 2017-07-03 | 半导体器件的栅极结构及其制造方法 |
PCT/CN2018/094359 WO2019007344A1 (zh) | 2017-07-03 | 2018-07-03 | 半导体器件的栅极结构及其制造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2020507211A JP2020507211A (ja) | 2020-03-05 |
JP6846527B2 true JP6846527B2 (ja) | 2021-03-24 |
Family
ID=64950603
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2019540366A Active JP6846527B2 (ja) | 2017-07-03 | 2018-07-03 | 半導体デバイスのゲート構造および製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US11088253B2 (ja) |
JP (1) | JP6846527B2 (ja) |
CN (1) | CN109216175B (ja) |
WO (1) | WO2019007344A1 (ja) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
RU2764432C2 (ru) | 2017-05-15 | 2022-01-17 | Драйлок Текнолоджиз НВ | Впитывающее изделие с каналами и способ его изготовления |
CN112864222B (zh) * | 2019-11-27 | 2022-04-12 | 苏州东微半导体股份有限公司 | 半导体功率器件 |
CN111180342B (zh) * | 2020-02-18 | 2022-07-15 | 绍兴中芯集成电路制造股份有限公司 | 屏蔽栅场效应晶体管及其形成方法 |
CN111180341B (zh) * | 2020-02-18 | 2022-08-02 | 绍兴中芯集成电路制造股份有限公司 | 屏蔽栅场效应晶体管及其形成方法 |
CN114388438A (zh) * | 2020-10-22 | 2022-04-22 | 无锡华润上华科技有限公司 | 分离栅沟槽mosfet的制造方法 |
CN112201583B (zh) * | 2020-10-27 | 2024-02-27 | 上海华虹宏力半导体制造有限公司 | 包含sgt结构的mosfet器件的制作方法 |
CN113035945A (zh) * | 2021-03-15 | 2021-06-25 | 海速芯(无锡)科技有限公司 | 一种改善优值的新型场效应器件结构及其制造方法 |
CN113206145B (zh) * | 2021-04-22 | 2022-08-05 | 电子科技大学 | 改善热载流子注入的功率半导体器件 |
CN113206146B (zh) * | 2021-05-26 | 2023-03-24 | 吉林华微电子股份有限公司 | 半导体器件终端结构、制造方法及半导体器件 |
CN113644028B (zh) * | 2021-08-11 | 2023-10-03 | 重庆万国半导体科技有限公司 | 一种分离栅功率器件及其制造方法 |
CN114678275A (zh) * | 2021-12-29 | 2022-06-28 | 杭州芯迈半导体技术有限公司 | 分离栅mosfet及其制造方法 |
CN114334823A (zh) * | 2021-12-31 | 2022-04-12 | 上海晶岳电子有限公司 | 一种改善晶圆翘曲的sgt器件及其制作方法 |
GB2621389A (en) * | 2022-08-11 | 2024-02-14 | Dense Air Ltd | Small cell deployment |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4156717B2 (ja) * | 1998-01-13 | 2008-09-24 | 三菱電機株式会社 | 半導体装置 |
KR100306744B1 (ko) * | 1998-11-17 | 2001-12-17 | 오길록 | 트렌치게이트전력소자의제조방법 |
JP2004207706A (ja) * | 2002-12-10 | 2004-07-22 | Fuji Electric Device Technology Co Ltd | 半導体装置および半導体装置の製造方法 |
JP4590884B2 (ja) | 2003-06-13 | 2010-12-01 | 株式会社デンソー | 半導体装置およびその製造方法 |
WO2005065385A2 (en) * | 2003-12-30 | 2005-07-21 | Fairchild Semiconductor Corporation | Power semiconductor devices and methods of manufacture |
JP2009272453A (ja) * | 2008-05-08 | 2009-11-19 | Sanyo Electric Co Ltd | トランジスタ、半導体装置及びその製造方法 |
US8319278B1 (en) * | 2009-03-31 | 2012-11-27 | Maxpower Semiconductor, Inc. | Power device structures and methods using empty space zones |
US8174070B2 (en) * | 2009-12-02 | 2012-05-08 | Alpha And Omega Semiconductor Incorporated | Dual channel trench LDMOS transistors and BCD process with deep trench isolation |
CN102129999B (zh) * | 2010-01-20 | 2012-10-03 | 上海华虹Nec电子有限公司 | 沟槽型双层栅mos结构的制备方法 |
CN102130001B (zh) * | 2010-01-20 | 2012-10-03 | 上海华虹Nec电子有限公司 | 沟槽型双层栅功率mos器件的制备方法 |
US9048282B2 (en) * | 2013-03-14 | 2015-06-02 | Alpha And Omega Semiconductor Incorporated | Dual-gate trench IGBT with buried floating P-type shield |
JP2013125827A (ja) * | 2011-12-14 | 2013-06-24 | Toshiba Corp | 半導体装置およびその製造方法 |
CN102738240B (zh) | 2012-06-04 | 2015-05-27 | 电子科技大学 | 一种双栅功率mosfet器件 |
DE102014108963B4 (de) | 2014-06-26 | 2018-07-19 | Infineon Technologies Ag | Herstellungsverfahren für eine Halbleitervorrichtung mit Leistungstransistorzellen und lateralen Transistoren |
CN105789043B (zh) * | 2014-12-25 | 2019-03-12 | 华润微电子(重庆)有限公司 | 沟槽型半导体器件及其制作方法 |
US9812548B2 (en) * | 2015-09-08 | 2017-11-07 | Maxpower Semiconductor, Inc. | Power device having a polysilicon-filled trench with a tapered oxide thickness |
CN105355560A (zh) * | 2015-10-27 | 2016-02-24 | 上海华虹宏力半导体制造有限公司 | 具有屏蔽栅的沟槽栅mosfet的制造方法 |
CN105575781B (zh) * | 2016-01-29 | 2018-06-19 | 上海华虹宏力半导体制造有限公司 | 沟槽型超级结的制造方法 |
CN105914234A (zh) * | 2016-06-28 | 2016-08-31 | 上海华虹宏力半导体制造有限公司 | 分离栅功率mos管结构及制作方法 |
-
2017
- 2017-07-03 CN CN201710534704.0A patent/CN109216175B/zh active Active
-
2018
- 2018-07-03 WO PCT/CN2018/094359 patent/WO2019007344A1/zh unknown
- 2018-07-03 JP JP2019540366A patent/JP6846527B2/ja active Active
- 2018-07-03 US US16/483,396 patent/US11088253B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US11088253B2 (en) | 2021-08-10 |
CN109216175B (zh) | 2021-01-08 |
US20200013864A1 (en) | 2020-01-09 |
CN109216175A (zh) | 2019-01-15 |
WO2019007344A1 (zh) | 2019-01-10 |
JP2020507211A (ja) | 2020-03-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6846527B2 (ja) | 半導体デバイスのゲート構造および製造方法 | |
US9390982B2 (en) | CMOS devices with reduced leakage and methods of forming the same | |
KR101511423B1 (ko) | FinFET들 및 이를 형성하기 위한 방법들 | |
US9935011B2 (en) | Fin spacer protected source and drain regions in FinFETs | |
KR101653464B1 (ko) | 기판 격리 및 도핑되지 않은 채널을 갖는 집적 회로 구조체 및 그 형성방법 | |
US9362276B2 (en) | Semiconductor device and fabrication method | |
CN107403835B (zh) | 半导体装置及其制作工艺 | |
TWI705503B (zh) | 半導體結構和半導體製造方法 | |
US9502244B2 (en) | Manufacturing method for forming semiconductor structure | |
KR20120099863A (ko) | 트랜지스터 및 그 제조 방법 | |
US10121870B1 (en) | Semiconductor device structure with strain-relaxed buffer | |
CN103681836A (zh) | 垂直的微电子元件以及相应的制造方法 | |
US9595589B2 (en) | Transistor with performance boost by epitaxial layer | |
CN109216257B (zh) | Ldmos的隔离结构的制造方法 | |
US20160172362A1 (en) | Cmos transistors with identical active semiconductor region shapes | |
CN104752216B (zh) | 晶体管的形成方法 | |
KR100920047B1 (ko) | 수직형 트랜지스터 및 그의 형성방법 | |
JP6839297B2 (ja) | トレンチ分離構造およびその製造方法 | |
KR102350485B1 (ko) | 반도체 소자 | |
TWM620290U (zh) | 整合型溝道分離式功率元件 | |
TWI743252B (zh) | 鰭狀場效電晶體裝置與其形成方法 | |
TWI485783B (zh) | 具有封裝的壓力源區域的半導體裝置及製作方法 | |
CN112151449A (zh) | 半导体结构及其形成方法 | |
US9748147B1 (en) | Method of fabricating epitaxial layer | |
JP2009111020A (ja) | 半導体装置およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20190725 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20200813 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20200831 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20201118 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20210128 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20210301 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6846527 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |