WO2017195826A1 - 積層配線膜および薄膜トランジスタ素子 - Google Patents

積層配線膜および薄膜トランジスタ素子 Download PDF

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Publication number
WO2017195826A1
WO2017195826A1 PCT/JP2017/017690 JP2017017690W WO2017195826A1 WO 2017195826 A1 WO2017195826 A1 WO 2017195826A1 JP 2017017690 W JP2017017690 W JP 2017017690W WO 2017195826 A1 WO2017195826 A1 WO 2017195826A1
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Prior art keywords
film
less
wiring
layer
alloy
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PCT/JP2017/017690
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English (en)
French (fr)
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陽子 志田
裕史 後藤
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株式会社神戸製鋼所
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Application filed by 株式会社神戸製鋼所 filed Critical 株式会社神戸製鋼所
Priority to CN201780029216.2A priority Critical patent/CN109155243A/zh
Priority to US16/092,976 priority patent/US20190148412A1/en
Priority to KR1020187032013A priority patent/KR20180133455A/ko
Publication of WO2017195826A1 publication Critical patent/WO2017195826A1/ja

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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C2217/00—Coatings on glass
    • C03C2217/20—Materials for coating a single layer on glass
    • C03C2217/25—Metals
    • C03C2217/251—Al, Cu, Mg or noble metals
    • C03C2217/253—Cu
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C2218/00—Methods for coating glass
    • C03C2218/10—Deposition methods
    • C03C2218/15—Deposition methods from the vapour phase
    • C03C2218/154—Deposition methods from the vapour phase by sputtering
    • C03C2218/156—Deposition methods from the vapour phase by sputtering by magnetron sputtering
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C2218/00—Methods for coating glass
    • C03C2218/30—Aspects of methods for coating glass not covered above
    • C03C2218/31—Pre-treatment
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C2218/00—Methods for coating glass
    • C03C2218/30—Aspects of methods for coating glass not covered above
    • C03C2218/32—After-treatment

Definitions

  • the present invention relates to a laminated wiring film and a thin film transistor element.
  • Oxide semiconductors and low-temperature polysilicon semiconductors as semiconductor materials for thin film transistors (hereinafter also referred to as TFTs: Thin Film Transistors) used for display devices such as flat panel displays such as liquid crystal panels and organic EL (Electro Luminescence) panels and touch panels
  • TFTs Thin Film Transistors
  • LTPS Low Temperature Poly-Silicon
  • Oxide semiconductors and LTPS semiconductors have large electron mobility and can speed up TFT elements, as compared to amorphous silicon semiconductor materials that have been used conventionally.
  • the following problems occur.
  • a TFT element using an oxide semiconductor or an LTPS semiconductor it is necessary to go through a high temperature heat treatment process than a conventional element using amorphous silicon, and have to withstand heating at about 400 ° C. to 500 ° C.
  • the Cu wiring has poor adhesion to a glass substrate, a semiconductor film such as a Si (silicon) film, a metal oxide film, and the like.
  • Patent Document 1 proposes a display device provided with a Cu alloy film excellent in adhesion to a transparent substrate such as a glass substrate.
  • the Cu alloy film contains 2 to 20 atomic% in total of at least one element selected from the group consisting of Zn, Ni, Ti, Al, Mg, Ca, W, Nb, and Mn.
  • a first layer (Y) made of a Cu alloy containing Cu, a pure Cu, or a Cu alloy containing Cu as a main component and having a lower electrical resistivity than the first layer (Y) X), and the first layer (Y) is in contact with the transparent substrate.
  • Patent Document 2 discloses a transparent conductive film and a wiring film for a touch panel sensor connected to the transparent conductive film, wherein the wiring film includes at least one of alloy elements selected from the group consisting of Ni, Zn, and Mn.
  • a Cu alloy (first layer) containing 0.1 to 40 atomic% in total, and a pure Cu or a Cu alloy containing Cu as a main component and having a lower electrical resistivity than the first layer;
  • a Cu alloy wiring film for a touch panel sensor excellent in oxidation resistance is proposed, which has a laminated structure including two layers, and the second layer is connected to the transparent conductive film. .
  • an SiOx film which is an interlayer insulating film, is formed by a CVD (Chemical Vapor Deposition) method. If the SiOx film is formed at a high temperature, a film with few impurities can be formed. Since the impurities adversely affect the driving of the TFT element, the Cu wiring needs to be able to withstand the film formation of the SiOx film by the CVD method at a high temperature of 300 ° C. or more. However, Cu is a material having high affinity to oxygen. When the SiOx film is formed by the CVD method, N 2 O gas is introduced.
  • N 2 O gas is an oxygen radical in plasma, and when a SiOx film is formed on a single Cu film at a high temperature of 300 ° C. or more, oxygen radical and Cu easily react as shown in FIG. 3 to FIG. 4 , Form copper oxide and exfoliate.
  • FIGS. 3 (a) and 4 (a) and 4 (b) no film peeling is observed when the SiOx film is formed by the CVD method at a temperature of about 200 ° C.
  • film peeling occurs.
  • JP JP 2011-48323 A Japan JP 2013-120411
  • a SiOx film is formed as a gate insulating film (interlayer insulating film) by a CVD method at 300 ° C. or higher.
  • a CVD method at 300 ° C. or higher.
  • lamination of a cap layer is needed. It is generally known that a Cu-30 at% Ni alloy film is used for the cap layer. By laminating a Cu-30 at% Ni alloy film, exfoliation of the film can be suppressed even when the SiOx film is formed by the CVD method at 300 ° C. or higher as shown in FIG. 5, but heat treatment at 400 ° C. or higher is performed. The resistance of the laminated film increases.
  • the wiring width of the source / drain wiring and the gate wiring is processed to 10 ⁇ m or less.
  • the cap layer 13 protrudes beyond the wiring layer 12 to form the extension 13a, and as shown in FIG. It causes breakage of the interlayer insulating film and wiring stacked on the upper layer. Therefore, there is a need to control the wiring shape in a forward tapered shape (see FIG. 6C).
  • Patent Document 1 an element is included which causes an increase in resistance by heat treatment at 400 ° C. or higher because Ni or the like is added to the cap layer. In addition, since an element such as Zn is included to reduce the taper angle, the exposed width of the Cu wiring portion may be increased.
  • Patent Document 2 is limited to touch panel applications, and it is essential to connect to an ITO thin film, and contains Ni, which is an element that causes an increase in resistance at 500 ° C. heating.
  • the present invention has been made focusing on the above circumstances, has a low electrical resistance, is free from peeling of an interlayer insulating film formed by CVD using a SiOx film, and is electrically conductive even when heat treatment at a high temperature of 400 ° C. or higher is performed.
  • An object of the present invention is to provide a laminated wiring film without a rise in resistance.
  • Another object of the present invention is to provide a thin film TFT element provided with the laminated wiring film.
  • the element X is at least one selected from the group X consisting of Al, Mn, Zn and Ni, and the metal constituting the Cu-X alloy layer has a composition according to any one of the following (1) to (5) And a wiring pattern having a width of 10 ⁇ m or less.
  • the element of the X group is contained only in one kind, and the content is 6 at% or more and 27 at% or less.
  • the metal constituting the Cu-X alloy layer is a composition system of any one of the following (1 ′) to (5 ′), and the width of the wiring pattern is 5 ⁇ m or less Laminated wiring film as described.
  • (1 ') Only one element of the above-mentioned X group is contained, and the content is 6 at% or more and 14 at% or less.
  • (2 ') It contains 4 at% or more and 9 at% or less of Al, and further contains 5 at% or more and 10 at% or less of Mn.
  • [4] The multilayer wiring film according to [1] or [2], wherein the film thickness of the wiring layer is 50 nm or more and 1000 nm or less, and the film thickness of the Cu—X alloy layer is 5 nm or more and 200 nm or less.
  • [5] The multilayer wiring film according to [3], wherein the film thickness of the wiring layer is 50 nm or more and 1000 nm or less, and the film thickness of the Cu—X alloy layer is 5 nm or more and 200 nm or less.
  • a thin film transistor element comprising the laminated wiring film according to the above [1] and an oxide semiconductor.
  • a thin film transistor element comprising the laminated wiring film according to the above [2] and a low temperature polysilicon semiconductor or an oxide semiconductor.
  • the laminated wiring film having the configuration of the above [1] can be suitably used for a TFT element using an oxide semiconductor
  • the laminated wiring film having the configuration of the above [2] is a low temperature polysilicon semiconductor or It can be suitably used for a TFT element using an oxide semiconductor.
  • FIG. 1 is a schematic cross-sectional view illustrating the configuration of the laminated wiring film of the present invention.
  • FIG. 2 is a schematic cross-sectional view illustrating the configuration of a thin film transistor element provided with the laminated wiring film of the present invention.
  • FIG. 3 is an external view of an SiOx film formed on a Cu single film by the CVD method.
  • FIG. 3 (a) is an external view of the film formed at about 200 ° C.
  • FIG. 3 (b) is about 300 ° C. It is an external appearance photograph figure at the time of forming into a film by.
  • FIG. 4 is a cross-sectional TEM observation photograph at a magnification of 200,000 times when an SiOx film is formed at a film forming temperature of about 200 ° C.
  • FIG. 5 is an external view photograph of a SiOx film formed on a Cu-30 at% Ni / Cu laminated film by a CVD method at a film forming temperature of 200 ° C.
  • FIG. 6 is a schematic view of the wiring shape obtained by the wet etching method, in which (a) is a wiring shape in which the cap layer protrudes from the wiring layer and an extension is formed, and (b) is a reverse taper shape.
  • the wiring shape, (c) is a forward tapered wiring shape.
  • FIG. 7 is a schematic cross-sectional view illustrating another configuration of the laminated wiring film of the present invention.
  • the laminated wiring film according to the present invention will be described below.
  • the laminated wiring film of the present invention comprises a wiring layer made of Cu or a Cu alloy having an electrical resistance of 10 ⁇ cm or less, and a Cu—X alloy layer containing Cu and an X element provided on at least one of the upper layer and the lower layer of the wiring layer.
  • the element X is at least one selected from the group X consisting of Al, Mn, Zn and Ni.
  • FIG. 1 is a schematic cross-sectional view illustrating the configuration of the laminated wiring film of the present invention.
  • a laminated wiring film composed of the wiring layer 2 and the cap layer (Cu-X alloy layer) 3 is laminated in this order on the glass substrate 1 and further laminated.
  • An insulating film (SiOx) 4 is formed on the wiring film.
  • the insulating film (SiOx) 4 a gate insulating film provided between a gate electrode (Cu wiring) and an oxide semiconductor layer in a TFT is exemplified.
  • the wiring layer is a film made of Cu or a Cu alloy.
  • these films may be referred to as "Cu-based films".
  • the wiring layer is a Cu-based film, and the electric resistance thereof is 10 ⁇ cm or less.
  • the electric resistance of the wiring layer is 10 ⁇ cm or less, low electric resistance of the laminated wiring film can be realized.
  • the electric resistance of the wiring layer is preferably 5 ⁇ cm or less, more preferably 4 ⁇ cm or less.
  • the wiring layer is preferably formed of Cu.
  • Z element Z By containing the above-mentioned element Z, there are effects such as improvement of various corrosion resistances and adhesion with the substrate.
  • These Z elements may be used alone or in combination of two or more.
  • the element Z can be contained, for example, in the range of more than 0 atomic percent and 2 atomic percent or less in total.
  • the thickness of the wiring layer is preferably 50 nm or more, preferably 70 nm or more, from the viewpoint of obtaining a film having uniform film thickness and components at the time of film formation, because the specification of the electrode resistance is determined considering the performance required for the panel. More preferably, 100 nm or more is more preferable.
  • the film thickness of the wiring layer is preferably 1000 nm or less, more preferably 700 nm or less, and still more preferably 500 nm or less.
  • the Cu—X alloy layer is provided as a cap layer on at least one of the upper layer and the lower layer of the wiring layer.
  • the Cu-X alloy layer is formed of a Cu alloy containing Cu and an X element.
  • the element X is at least one selected from the group X consisting of Al, Mn, Zn and Ni.
  • the X element may be used alone or in combination of two or more.
  • the Cu alloy forming the Cu—X alloy layer contains at least one X element selected from the group X consisting of Al, Mn, Zn and Ni, with the balance being Cu and unavoidable impurities.
  • the metal constituting the Cu—X alloy layer is a composition system in which the X element is any one of the following (1) to (5).
  • the element of the X group is contained only in one kind, and the content is 6 at% or more and 27 at% or less.
  • It contains 4 at% or more and 15 at% or less of Al, and further contains 5 at% or more and 10 at% or less of Mn.
  • the electric resistance after heat treatment at 400 ° C. can be 3 ⁇ cm or less.
  • the resistance value of the electrode after the heat treatment at 400 ° C. may exceed 3 ⁇ cm. This is considered to be due to the diffusion of the X element into the wiring layer by the heat treatment.
  • the laminated wiring film provided with the Cu—X alloy layer having the above composition system can be suitably used as a Cu wiring for a TFT element using an oxide semiconductor.
  • the metal for synthesizing the Cu-X alloy layer has a composition in which the X element is any one of the following (1 ′) to (5 ′) It is preferable that it is a system.
  • the X element is any one of the following (1 ′) to (5 ′) It is preferable that it is a system.
  • (2 ') It contains 4 at% or more and 9 at% or less of Al, and further contains 5 at% or more and 10 at% or less of Mn.
  • the electrical resistance after heat treatment can be 3 ⁇ cm or less even at 500 ° C.
  • the laminated wiring film provided with the Cu—X alloy layer having the above composition system can be suitably used as a Cu wiring for a TFT element using an oxide semiconductor or an LTPS semiconductor.
  • the Mn element diffuses to the alloy surface to form a concentrated layer. Concentrated Mn is oxidized and rendered inactive. Therefore, except for the Cu element which has been oxidized at the initial stage of the reaction, it is protected by the passivated Mn oxide, oxygen is not diffused further inside the Cu--Mn film, and the progress of oxidation is suppressed. At this time, if the content of Mn falls below a predetermined range, a thickened layer may not be formed to an extent that suppresses oxidation.
  • the etching of the Cu—Mn film is promoted at the time of wiring processing using a hydrogen peroxide solution or mixed acid type etching solution used in the process of thin film transistors, The shape may not be obtained.
  • the X element is Al or Zn, it is passivated in the same manner as Mn and has an effect of protecting the surface of Cu from oxidation.
  • Al interferes with etching and Zn has an effect of promoting the etching.
  • the addition amount of Al is increased beyond a predetermined level, the etching rate becomes slower than the wiring layer, and the Cu-X alloy layer protrudes more than the wiring layer, leaving an extension. Not desirable.
  • the addition amount of Zn is increased to a predetermined amount or more, the etching rate of the Cu—X alloy layer is further accelerated, and thus a good etched shape may not be obtained.
  • Ni is an element which easily dissolves in Cu, and is diffused into Cu or a Cu alloy laminated as a wiring layer by heating.
  • the content of Ni exceeds a predetermined range, the resistance after the heat treatment increases, which is not preferable.
  • the laminated wiring film provided with the Cu—X alloy layer having the above composition system is laminated on a substrate, it is preferable to further include an adhesion layer containing Ti on the surface on the side laminated on the substrate.
  • an adhesion layer containing Ti between the semiconductor substrate and the wiring layer Ti alone, Ti alloy, Ti oxide, Ti nitride
  • Ti may be diffused into Cu due to the influence of high temperature heat treatment at the time of SiOx film formation, and wiring resistance may increase.
  • the cap layer formed of the above specific alloy layer is provided as the laminated wiring film, the diffusion of Ti into Cu can be suppressed, and the increase of the wiring resistance can be suppressed.
  • the diffusion of Ti is considered to be the reason for inhibiting the oxygen penetration into the wiring layer (Cu wiring film) by laminating the cap layer of the present invention, since oxygen is a driving source. .
  • FIG. 7 the schematic sectional drawing which illustrates the structure of the laminated wiring film at the time of using the contact
  • an insulating film (SiOx) 4 is formed on the laminated wiring film.
  • the cap layer 3 may be further provided between the adhesion layer 14 and the wiring layer 2. Further, the adhesive layer 14, the cap layer 3 and the wiring layer 2 may be stacked in this order on the glass substrate 1.
  • the thickness of the adhesive layer is preferably 10 nm or more, more preferably 15 nm or more, and still more preferably 20 nm or more.
  • the thickness of the adhesion layer is preferably 50 nm or less, more preferably 40 nm or less, and still more preferably 30 nm or less.
  • the Cu-X alloy layer is insufficient in oxidation resistance when the film thickness is thin, and impairs the etching processability when it is thick, and when the film thickness of the Cu-X alloy layer is thick, the resistance when viewed from the resistance of the entire Cu electrode becomes large. Therefore, the film thickness of the Cu—X alloy layer is preferably 5 nm or more and 200 nm or less. 10 nm or more is more preferable, 20 nm or more is further preferable, 150 nm or less is more preferable, and 100 nm or less is still more preferable.
  • the total film thickness of the wiring layer and the Cu—X alloy layer ie, the film thickness of the laminated wiring film, is preferably 55 nm or more, more preferably 70 nm or more, and still more preferably 100 nm or more.
  • the total film thickness is preferably 1200 nm or less, more preferably 700 nm or less, and still more preferably 500 nm or less.
  • the laminated wiring film of the present invention preferably has a wiring shape of a forward tapered shape as shown in FIG. If the Cu—X alloy layer does not have a shape projecting more than the wiring layer, but has a forward tapered shape, breakage of the interlayer insulating film or the wiring coated on the Cu—X alloy layer can be suppressed.
  • the taper angle of the wiring layer is preferably 100 ° or less with respect to the substrate, more preferably 30 ° to 80 ° with respect to the substrate, still more preferably 30 ° to 60 °, and 40 ° It is more preferable that the angle is ⁇ 60 °.
  • the taper angle of the wiring layer is in the above range, the exposed width of the wiring layer can be narrowed from the tapered end of the laminated wiring film. If the taper angle is small and the exposed width of the wiring layer is large, this means an increase in the area of the wiring layer not protected by the cap layer, and there is a risk of oxidation in subsequent processing. When the tapered end is oxidized by oxidation, this means that the width of the low electric resistance functioning as a wiring becomes narrow, and the wiring resistance may be increased.
  • the taper angle of the wiring layer is preferably in the range of -25% to + 50% with respect to the taper angle of the Cu single layer film having the same film thickness.
  • the taper angle of the wiring layer with respect to the taper angle of the Cu single-layer film having the same film thickness is in the above range, breakage of the interlayer insulating film or the wiring coated on the Cu-X alloy layer can be further suppressed. .
  • the wiring layer and the Cu—X alloy layer are preferably formed by sputtering.
  • the sputtering method is excellent in productivity, and an alloy film of substantially the same composition can be stably formed by using a sputtering target.
  • a sputtering method for example, any sputtering method such as a DC sputtering method, an RF sputtering method, a magnetron sputtering method, a reactive sputtering method, etc. may be adopted, and the formation conditions may be set appropriately.
  • the target is a Cu alloy containing a predetermined amount of X element, and has the same composition as the desired Cu-X alloy layer.
  • a Cu alloy sputtering target it is possible to form a Cu—X alloy layer of a desired component and composition without causing a compositional deviation.
  • two or more pure metal targets or alloy targets different in composition may be simultaneously discharged to form a film.
  • film formation may be performed while adjusting the components by tipping on a metal of an alloying element on a pure Cu target.
  • the following conditions may be mentioned as an example of the sputtering conditions.
  • Film forming apparatus DC magnetron sputtering apparatus ("CS-200" manufactured by ULVAC, Inc.)
  • Substrate Alkali-free glass ("Eagle 2000" manufactured by Corning)
  • Substrate temperature Room temperature Deposition gas: Ar gas Gas pressure: 2 mTorr Sputtering power: 300 W Degree of vacuum achievement: 1 ⁇ 10 -6 Torr or less
  • the Cu alloy sputtering target of the present invention may have any shape depending on the shape and structure of the sputtering apparatus, for example, rectangular plate, circular plate, donut plate and the like.
  • the Cu alloy sputtering target may be produced by a method of producing an ingot comprising a Cu alloy by a melt casting method, a powder sintering method, or a spray forming method, or a preform comprising a Cu alloy, that is, a final compact
  • the method may be obtained by densifying the preform by densifying means after producing an intermediate before obtaining a body.
  • the wiring pattern can be formed on the laminated wiring film of the present invention by a process such as etching. By narrowing the wiring pattern, the aperture ratio of the pixel element can be increased. Therefore, it is possible to cope with a high definition display device.
  • a TFT element using an oxide semiconductor or a low temperature polysilicon semiconductor is mounted on a high definition panel, and is required to narrow the wiring width. From such a point of view, the width of the specific wiring pattern is preferably 10 ⁇ m or less, more preferably 5 ⁇ m or less.
  • the laminated wiring film of the present invention can be applied to wiring electrodes and input devices.
  • the input device includes an input device such as a touch panel provided with input means on the display device, and an input device not provided with a display device such as a touch pad.
  • the laminated wiring film of the present invention is preferably used for a touch panel sensor.
  • the thin film transistor element of the present invention comprises a wiring layer made of Cu or a Cu alloy having an electric resistance of 10 ⁇ cm or less, and a Cu—X alloy layer containing Cu and an X element provided on at least one of the upper layer and the lower layer of the wiring layer.
  • the X element is at least one selected from the group X consisting of Al, Mn, Zn and Ni.
  • an oxide semiconductor or an LTPS semiconductor is used as an active layer of the TFT.
  • FIG. 2 is a schematic cross-sectional view illustrating the configuration of a thin film transistor element provided with the laminated wiring film of the present invention.
  • a laminated wiring film composed of a wiring layer 2 and a cap layer (Cu-X alloy layer) 3 on a glass substrate 1, an insulating film (SiOx) 4, an oxide semiconductor 5, a laminated wiring film composed of a wiring layer 6 and a cap layer (Cu-X alloy layer) 7, and an insulating film (SiOx) 8 are laminated in this order.
  • the specific alloy layers described above are preferably used as the cap layer (Cu-X alloy layer) 3 and the cap layer (Cu-X alloy layer) 7.
  • Example 1 Preparation of laminated wiring film Prepare an alkali-free glass plate with a diameter of 4 inches and a thickness of 0.7 mm as a transparent substrate, wash it with a neutral detergent, and irradiate the excimer UV lamp for 30 minutes to contaminate the surface. Was removed. On the surface-treated non-alkali glass plate, a laminated wiring film having a wiring layer shown in Table 1 and a cap layer which is a Cu—X alloy layer was formed by DC magnetron sputtering. Sample No. The wiring film 1 is a single layer film of only the wiring layer.
  • the atmosphere in the chamber is temporarily adjusted to 3 ⁇ 10 ⁇ 6 Torr before film formation, and sputtering is then performed on the substrate in the order of the wiring layer and cap layer under the following sputtering conditions to form a laminated wiring film Formed.
  • a sputtering target a pure Cu sputtering target, or a target having the same component composition as each cap layer, and a disk-shaped sputtering target having a diameter of 4 inches each was used. The following evaluation was performed using the obtained laminated wiring film.
  • Film forming apparatus DC magnetron sputtering apparatus ("CS-200" manufactured by ULVAC, Inc.)
  • Substrate Non-alkali glass plate (manufactured by Corning "Eagle 2000")
  • Substrate temperature Room temperature
  • Deposition gas Ar gas
  • Gas pressure 2 mTorr Sputtering power: 300 W
  • Degree of vacuum achievement 1 ⁇ 10 -6 Torr or less
  • the electric resistivity of the laminated wiring film was measured as follows. That is, the electrical resistance was measured by a four-terminal method for a sample in which a cap layer was formed to a film thickness described on the Cu-based film described in Table 1 on an alkali-free glass plate. The electrical resistivity was calculated from the measured electrical resistance and the total value of the film thickness of the Cu-based film and the cap layer. Next, after performing heat treatment for 1 hour each at 400 ° C. and 500 ° C. under N 2 atmosphere using an infrared lamp heater manufactured by ULVAC, Inc .: RTP-6, the electric resistance is similarly measured, and the same as above The electrical resistivity was calculated by the method.
  • a sample having an electrical resistivity of 3 ⁇ cm or less at 400 ° C. is regarded as a heat resistance for a TFT element using an oxide semiconductor
  • a sample having an electrical resistivity of 3 ⁇ cm or less at 500 ° C. is an oxide semiconductor or Passed for TFT devices using LTPS.
  • Table 1 shows the results of (2) measurement of electrical resistivity of laminated wiring film, (3) evaluation of wiring shape, taper angle, and (4) evaluation of oxidation resistance.
  • the heat resistance at 400 ° C. is 3 ⁇ cm or less
  • the wiring shape is a forward taper shape
  • the peeling at the time of forming the SiOx film by the CVD method is Those that did not meet the criteria were regarded as pass " ⁇ " as being suitable for TFT elements using oxide semiconductors, and those that did not satisfy any one of the above conditions were considered as fail " ⁇ ".
  • the electrical resistivity is 3 ⁇ cm or less by heat treatment at 400 ° C. and 500 ° C.
  • the wiring shape is a forward taper shape
  • the taper angle to the transparent substrate is 30 ° to 80 °.
  • no. 1 is an example of the Cu single film which does not have a cap layer, and exfoliation was seen at the time of film-forming of a SiOx film.
  • No. Reference numerals 2 to 13 denote laminated wiring films in which the Cu—X alloy layer, which is a cap layer, contains Cu and one element.
  • No. Nos. 5, 8 to 10, and 13 are examples satisfying the composition system (1) of the X element of the Cu-X alloy layer defined in the present invention, and the wiring shape is in a forward tapered shape, and electricity is maintained even after heat treatment at 400.degree.
  • the resistance was an electrical resistance of 3 ⁇ cm or less, and no peeling was observed even when the SiOx film was formed.
  • no. 5 and 8 are examples satisfying the composition system (1 ′) of the X element of the Cu—X alloy layer defined in the present invention, and the wiring shape is forward tapered and the taper angle is also 30 ° to 80 °. Even after the heat treatment at 400 ° C. and 500 ° C., the electric resistance was 3 ⁇ cm or less, and no peeling was observed even when the SiOx film was formed.
  • no. 14 to 39 are laminated wiring films in which the Cu—X alloy layer, which is a cap layer, contains Cu and two or more elements.
  • No. 19 to 39 are examples satisfying the composition system (2) to (5) of the X element of the Cu-X alloy layer defined in the present invention, and the wiring shape is a forward taper shape and heat treatment at 400 ° C. The electric resistance was still 3 ⁇ cm or less, and no peeling was observed even when the SiOx film was formed. On the other hand, no. 14 to 18 could not stably obtain low electrical resistance at the time of high heat treatment.
  • no. 19, 27 to 30 and 32 to 39 are examples satisfying the composition system (2 ') to (5') of the X element of the Cu-X alloy layer defined in the present invention, and the wiring shape is forward tapered Shape, with a taper angle of 30 ° to 80 °, and an electric resistance of 3 ⁇ cm or less after heat treatment at 400 ° C. and 500 ° C., and no peeling was observed even at the time of forming a SiOx film .
  • the composition system (3 ') of the X element of the Cu-X alloy layer defined in the present invention is satisfied, and the electrical resistance after the heat treatment at 500 ° C. is No. 4. It is a low value (2.0 ⁇ cm or less) compared to 22 and 23. From this result, it is understood that the content of Mn is preferably 10 at% or less when the Cu—Zn—Mn alloy layer is used.
  • the composition system (5 ') of the X element of the Cu-X alloy layer defined in the present invention is satisfied, and the electrical resistance after heat treatment at 500.degree. It is a low value (2.3 ⁇ cm) compared to 35, 36 and 39. From this result, it is understood that the content of Ni is preferably 6 at% or more when the Cu-Al-Ni alloy layer is used.
  • Example 2 The laminated wiring film in the case of using the adhesion layer containing Ti was produced by the following procedure. Specifically, as in the case of Example 1, a cap layer which is the adhesion layer, the wiring layer and the Cu-X alloy layer shown in Table 2 on an alkali-free glass plate as a transparent substrate by DC magnetron sputtering. Were sequentially formed. Sample No. The wiring film 40 is a laminated film of only the adhesion layer and the wiring layer. The film forming conditions for the adhesion layer, the wiring layer and the cap layer are the same as in the case of the first embodiment.
  • the measurement of the electrical resistivity and the evaluation of the oxidation resistance were performed under the same conditions as in Example 1. Further, according to the above results, it is considered that it is suitable for a TFT element using an oxide semiconductor that has an electrical resistivity of 3 ⁇ cm or less by heat treatment at 400 ° C. and no SiOx film formation by CVD method. "O”, and one which does not satisfy even one of the above conditions is considered as "X”.
  • no. 40 is an example of a laminated film of only the adhesion layer and the wiring layer, and peeling was observed at the time of forming the SiOx film.
  • the electric resistance did not satisfy 3 ⁇ cm or less.
  • No. 41 is an example which does not satisfy composition system (1) of X element of the Cu-X alloy layer specified in the present invention, and although peeling was not seen at the time of film-forming of a SiOx film, either 400 ° C or 500 ° C. The electric resistance did not satisfy 3 ⁇ cm or less even after the heat treatment of
  • no. 42 to 46 are examples satisfying the composition system (1) to (5) of the X element of the Cu-X alloy layer defined in the present invention, and the electrical resistance after heat treatment at either 400 ° C. or 500 ° C. Of 3 ⁇ cm or less, and no peeling was observed at the time of film formation of the SiOx film.

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Abstract

本発明は、電気抵抗が１０μΩｃｍ以下のＣｕまたはＣｕ合金からなる配線層と、該配線層の上層および下層のうちの少なくとも一方に設けられるＣｕとＸ元素を含むＣｕ－Ｘ合金層とを備え、Ｘ元素は、Ａｌ、Ｍｎ、ＺｎおよびＮｉからなるＸ群から選ばれる少なくとも１種であり、Ｃｕ－Ｘ合金層を構成する金属が、特定の組成系である積層配線膜に関する。本発明の積層配線膜によれば、低い電気抵抗であり、ＣＶＤ法による層間絶縁膜のＳｉＯｘ成膜での剥離が無く、かつ４００℃以上の高温熱処理を行っても電気抵抗上昇の無い積層配線膜を提供することができる。

Description

積層配線膜および薄膜トランジスタ素子
　本発明は、積層配線膜および薄膜トランジスタ素子に関する。
　液晶パネルや有機ＥＬ（Ｅｌｅｃｔｒｏ　Ｌｕｍｉｎｅｓｃｅｎｃｅ）パネルなどのフラットパネルディスプレイやタッチパネルなどの表示装置に用いられる薄膜トランジスタ（以下、ＴＦＴ：Ｔｈｉｎ　Ｆｉｌｍ　Ｔｒａｎｓｉｓｔｏｒともいう）の半導体材料として、酸化物半導体や低温ポリシリコン半導体（以下、ＬＴＰＳ：Ｌｏｗ　Ｔｅｍｐｅｒａｔｕｒｅ　Ｐｏｌｙ‐Ｓｉｌｉｃｏｎともいう）が知られている。
　酸化物半導体やＬＴＰＳ半導体は、従来利用されているアモルファスシリコン半導体材料と比較して、電子移動度が大きくＴＦＴ素子を高速化できる。
　一方で、配線材料を低抵抗化することでＴＦＴ素子の駆動速度を速くする検討が行われている。従来のフラットパネルディスプレイの電極配線にはＡｌ（アルミニウム）薄膜やＩＴＯ（Ｉｎｄｉｕｍ　Ｔｉｎ　Ｏｘｉｄｅ）薄膜が使用されてきたが、より電気抵抗の低いＣｕ（銅）電極配線やＣｕ合金電極配線の適用が提案されている。
　しかし、Ｃｕ配線を用いる場合、以下のような課題が生じる。たとえば、酸化物半導体やＬＴＰＳ半導体を用いたＴＦＴ素子では、従来のアモルファスシリコンを用いた素子より高温熱処理プロセスを経由しなければならず、４００℃～５００℃程度の加熱に耐えなければならない。また、Ｃｕ配線は、ガラス基板、Ｓｉ（シリコン）膜などの半導体膜、金属酸化物膜などとの密着性が悪い。
　上記Ｃｕを用いた技術として、特許文献１には、ガラス基板などの透明基板との密着性に優れたＣｕ合金膜を備えた表示装置が提案されている。特許文献１の表示装置において、Ｃｕ合金膜は、Ｚｎ，Ｎｉ，Ｔｉ，Ａｌ，Ｍｇ，Ｃａ，Ｗ，ＮｂおよびＭｎよりなる群から選択される少なくとも１種の元素を合計で２～２０原子％含むＣｕ合金からなる第一層（Ｙ）と、純Ｃｕ、またはＣｕを主成分とするＣｕ合金であって前記第一層（Ｙ）よりも電気抵抗率の低いＣｕ合金からなる第二層（Ｘ）と、を含む積層構造を有し、第一層（Ｙ）が透明基板と接触していることを特徴とする。上記構成により、透明基板とＣｕ合金膜におけるＣｕの密着性と低電気抵抗を実現している。
　特許文献２には、透明導電膜、および前記透明導電膜と接続するタッチパネルセンサー用の配線膜において、前記配線膜は、Ｎｉ、Ｚｎ、およびＭｎよりなる群から選択される合金元素の少なくとも一種を合計量で０．１～４０原子％含むＣｕ合金（第１層）と、純ＣｕまたはＣｕを主成分とするＣｕ合金であって前記第１層よりも電気抵抗率の低いＣｕ合金からなる第２層と、を含む積層構造を有し、前記第２層は、前記透明導電膜と接続されていることを特徴とする耐酸化性に優れたタッチパネルセンサー用Ｃｕ合金配線膜が提案されている。
　ＴＦＴ素子形成プロセスにおいて、層間絶縁膜であるＳｉＯｘ膜はＣＶＤ（Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法で成膜する。ＳｉＯｘ膜は高温で成膜する方が、不純物の少ない膜を成膜することができる。不純物は、ＴＦＴ素子の駆動に悪影響を与えるため、Ｃｕ配線は３００℃以上の高温のＣＶＤ法によるＳｉＯｘ膜の成膜に耐えうる必要性がある。しかしながら、Ｃｕは酸素と親和性が高い材料である。ＣＶＤ法でＳｉＯｘ膜を成膜する場合、Ｎ２Ｏガスを導入する。Ｎ２Ｏガスはプラズマ中で酸素ラジカルになっており、Ｃｕ単膜に３００℃以上の高温でＳｉＯｘ膜を成膜した場合、図３～図４のように酸素ラジカルとＣｕが容易に反応し、酸化銅を形成して剥離する。図３（ａ）および図４（ａ）、（ｂ）に示したように、約２００℃の温度でＣＶＤ法によりＳｉＯｘ膜を成膜した場合には膜剥離は見られないが、図３（ｂ）に示したように、約３００℃の温度で成膜した場合には膜剥離が発生してしまう。
日本国特開２０１１－４８３２３号公報 日本国特開２０１３－１２０４１１号公報
　上記したように、酸化物半導体やＬＴＰＳ半導体を用いたＴＦＴ素子では、ゲート絶縁膜（層間絶縁膜）として、３００℃以上でのＣＶＤ法によるＳｉＯｘ膜が形成されるため、Ｃｕ配線にはＳｉＯｘ成膜時のダメージを保護するため、キャップ層の積層が必要となる。キャップ層にはＣｕ－３０ａｔ％Ｎｉ合金膜を用いることが一般的に知られている。Ｃｕ－３０ａｔ％Ｎｉ合金膜を積層することで、図５のように３００℃以上のＣＶＤ法によるＳｉＯｘ膜の成膜でも膜の剥離を抑制することができるが、４００℃以上の熱処理を行うと積層膜の抵抗が上昇する。
　また、酸化物半導体やＬＴＰＳ半導体を用いたＴＦＴ素子を搭載したフラットパネルディスプレイは、高精細なパネルに利用が見込まれる。高精細パネルでは、開口率を上げるため、ソースドレイン配線やゲート配線の配線幅を１０μｍ以下に加工する。配線形状について、キャップ層１３が図６（ａ）のように配線層１２よりも張り出して延出部１３ａが形成される場合と、図６（ｂ）のように逆テーパー状になる場合は、その上層に積層する層間絶縁膜や配線の破断の原因になる。そのため配線形状は順テーパー状（図６（ｃ）参照）に制御する必要性がある。また、順テーパー状の配線形状が得られる場合も、基板１１に対する配線層１２のテーパー角度が小さい場合は、端部のＣｕ配線部の露出幅が大きくなる。そのため、テーパー角度も制御する必要性がある。
　特許文献１では、Ｎｉ等がキャップ層に添加されていることで４００℃以上の熱処理で抵抗上昇を招く元素を含んでいる。また、Ｚｎ等のテーパー角度を小さくする元素を含んでいるため、Ｃｕ配線部の露出幅が大きくなる場合がある。特許文献２は、タッチパネル用途に限定されており、ＩＴＯ薄膜との接続が必須であるし、５００℃加熱で抵抗上昇を起こす元素であるＮｉを含んでいる。
　本発明は、上記事情に注目してなされたものであり、低い電気抵抗であり、ＣＶＤ法による層間絶縁膜のＳｉＯｘ成膜での剥離が無く、かつ４００℃以上の高温熱処理を行っても電気抵抗上昇の無い積層配線膜を提供することを課題とする。また、本発明は、該積層配線膜を備えた薄膜ＴＦＴ素子を提供することも課題とする。
　本発明者らは、鋭意検討を重ねた結果、特定の合金層により形成されるキャップ層を備えたＣｕ積層配線膜が、上記課題を解決できることを見出し、本発明を完成するに至った。
　すなわち、本発明は、以下の［１］～［７］に係るものである。
［１］電気抵抗が１０μΩｃｍ以下のＣｕまたはＣｕ合金からなる配線層と、該配線層の上層および下層のうちの少なくとも一方に設けられるＣｕとＸ元素を含むＣｕ－Ｘ合金層とを備え、前記Ｘ元素は、Ａｌ、Ｍｎ、ＺｎおよびＮｉからなるＸ群から選ばれる少なくとも１種であり、前記Ｃｕ－Ｘ合金層を構成する金属が、下記（１）～（５）のいずれか１つの組成系であり、配線パターンの幅が１０μｍ以下であることを特徴とする積層配線膜。
（１）前記Ｘ群の元素を１種類のみ含み、その含有量が６ａｔ％以上２７ａｔ％以下である。
（２）Ａｌを４ａｔ％以上１５ａｔ％以下含み、さらにＭｎを５ａｔ％以上１０ａｔ％以下含む。
（３）Ｚｎを５ａｔ％以上１０ａｔ％以下含み、さらにＭｎを５ａｔ％以上２６ａｔ％以下含む。
（４）Ｚｎを４ａｔ％以上１４ａｔ％以下含み、さらにＡｌを５ａｔ％以上１５ａｔ％以下含む。
（５）Ａｌを５ａｔ％以上１０ａｔ％以下含み、さらにＮｉを２ａｔ％以上１０ａｔ％以下含む。
［２］前記Ｃｕ－Ｘ合金層を構成する金属が、下記（１’）～（５’）のいずれか１つの組成系であり、配線パターンの幅が５μｍ以下である、前記［１］に記載の積層配線膜。
（１’）前記Ｘ群の元素を１種類のみ含み、その含有量が６ａｔ％以上１４ａｔ％以下である。
（２’）Ａｌを４ａｔ％以上９ａｔ％以下含み、さらにＭｎを５ａｔ％以上１０ａｔ％以下含む。
（３’）Ｚｎを５ａｔ％以上１０ａｔ％以下含み、さらにＭｎを５ａｔ％以上１０ａｔ％以下含む。
（４’）Ｚｎを４ａｔ％以上１４ａｔ％以下含み、さらにＡｌを５ａｔ％以上１０ａｔ％以下含む。
（５’）Ａｌを５ａｔ％以上１０ａｔ％以下含み、さらにＮｉを６ａｔ％以上１０ａｔ％以下含む。
［３］基板に積層される積層配線膜であって、前記基板に積層される側の表面に、Ｔｉを含む密着層をさらに有する、前記［１］または［２］に記載の積層配線膜。
［４］前記配線層の膜厚が５０ｎｍ以上１０００ｎｍ以下であり、前記Ｃｕ－Ｘ合金層の膜厚が５ｎｍ以上２００ｎｍ以下である、前記［１］または［２］に記載の積層配線膜。
［５］前記配線層の膜厚が５０ｎｍ以上１０００ｎｍ以下であり、前記Ｃｕ－Ｘ合金層の膜厚が５ｎｍ以上２００ｎｍ以下である、前記［３］に記載の積層配線膜。
［６］前記［１］記載の積層配線膜と、酸化物半導体を含むことを特徴とする薄膜トランジスタ素子。
［７］前記［２］記載の積層配線膜と、低温ポリシリコン半導体または酸化物半導体を含むことを特徴とする薄膜トランジスタ素子。
　本発明によれば、低い電気抵抗とＣＶＤ法による層間絶縁膜のＳｉＯｘ成膜で剥離が無く、かつ４００℃以上の高温熱処理を行っても電気抵抗上昇の無いＣｕ配線用の積層配線膜およびＴＦＴ素子を提供することができる。特に、上記［１］の構成を備えた積層配線膜は、酸化物半導体を用いるＴＦＴ素子に好適に用いることができ、上記［２］の構成を備えた積層配線膜は、低温ポリシリコン半導体または酸化物半導体を用いるＴＦＴ素子に好適に用いることができる。
図１は、本発明の積層配線膜の構成を例示する概略断面図である。 図２は、本発明の積層配線膜を備えた薄膜トランジスタ素子の構成を例示する概略断面図である。 図３は、Ｃｕ単膜上にＣＶＤ法でＳｉＯｘ膜を成膜した時の外観写真図であり、（ａ）は約２００℃で成膜した場合の外観写真図、（ｂ）は約３００℃で成膜した場合の外観写真図である。 図４は、Ｃｕ単膜上にＣＶＤ法で、約２００℃の成膜温度でＳｉＯｘ膜を成膜した時の、倍率２０万倍の断面ＴＥＭ観察写真図であり、（ａ）は積層膜の全体図、（ｂ）は表面の拡大図である。 図５は、Ｃｕ－３０ａｔ％Ｎｉ／Ｃｕ積層膜上に、成膜温度２００℃のＣＶＤ法でＳｉＯｘ膜を成膜した時の外観写真図である。 図６は、ウェットエッチング法で得られる配線形状の概略図であり、（ａ）はキャップ層が配線層よりも張り出して、延出部が形成された配線形状、（ｂ）は逆テーパー状の配線形状、（ｃ）は順テーパー状の配線形状である。 図７は、本発明の積層配線膜の他の構成を例示する概略断面図である。
　以下、本発明に係る積層配線膜について説明する。
（積層配線膜）
　本発明の積層配線膜は、電気抵抗が１０μΩｃｍ以下のＣｕまたはＣｕ合金からなる配線層と、該配線層の上層および下層のうちの少なくとも一方に設けられるＣｕとＸ元素を含むＣｕ－Ｘ合金層とを備え、前記Ｘ元素は、Ａｌ、Ｍｎ、ＺｎおよびＮｉからなるＸ群から選ばれる少なくとも１種である。
　図１は、本発明の積層配線膜の構成を例示する概略断面図である。図１に示すように、本実施形態においては、ガラス基板１上に配線層２およびキャップ層（Ｃｕ－Ｘ合金層）３から構成される積層配線膜がこの順序で積層されており、更に積層配線膜上に絶縁膜（ＳｉＯｘ）４が形成されている。絶縁膜（ＳｉＯｘ）４としては、ＴＦＴにおけるゲート電極（Ｃｕ配線）と酸化物半導体層の間に設けられるゲート絶縁膜などが例示される。
（配線層）
　配線層はＣｕまたはＣｕ合金からなる膜である。以下、これらの膜を「Ｃｕ系膜」ということがある。配線層を導電層として形成する場合、該配線層はＣｕ系膜であって、その電気抵抗は１０μΩｃｍ以下である。配線層の電気抵抗が１０μΩｃｍ以下であることで、積層配線膜の低電気抵抗を実現することができる。積層配線膜の電気抵抗をより低くし、導電性を改善するため、配線層の電気抵抗は、５μΩｃｍ以下であることが好ましく、４μΩｃｍ以下であることがより好ましい。また、ＣｕはＣｕ合金よりも電気抵抗が低いため、配線層はＣｕにより形成されることが好ましい。
　配線層を形成するＣｕ合金としては、Ｔｉ、Ｍｎ、Ｆｅ、Ｃｏ、Ｎｉ、ＧｅおよびＺｎよりなるＺ群から選択される少なくとも１種のＺ元素を含み、残部がＣｕおよび不可避不純物よりなる合金が挙げられる。上記Ｚ元素を含むことによって、各種耐食性や基板との密着性が改善するなどの効果がある。これらのＺ元素は、単独で用いてもよいし２種以上を併用してもよい。Ｚ元素は、例えば合計で０原子％超２原子％以下の範囲で含有させることができる。
　配線層の膜厚は、パネルに求められる性能から考えて電極抵抗のスペックが決まるため、成膜時に膜厚や成分の均一な膜を得る観点から、５０ｎｍ以上とすることが好ましく、７０ｎｍ以上がより好ましく、１００ｎｍ以上が更に好ましい。一方、生産性とエッチング加工性を確保する観点から、配線層の膜厚は、１０００ｎｍ以下であることが好ましく、７００ｎｍ以下がより好ましく、５００ｎｍ以下が更に好ましい。
（Ｃｕ－Ｘ合金層）
　Ｃｕ－Ｘ合金層は、キャップ層として配線層の上層および下層のうちの少なくとも一方に設けられる。配線層の少なくとも一方の面にキャップ層を設けることで、４００℃以上５００℃以下の高温熱処理においてもＣｕ系膜の電気抵抗の上昇を抑え、また、ＳｉＯｘ成膜での膜剥離を抑制することができる。
　Ｃｕ－Ｘ合金層はＣｕとＸ元素を含むＣｕ合金により形成される。Ｘ元素は、Ａｌ、Ｍｎ、ＺｎおよびＮｉからなるＸ群から選ばれる少なくとも１種である。Ｘ元素は、１種を単独で用いてもよいし２種以上を併用してもよい。Ｃｕ－Ｘ合金層を形成するＣｕ合金は、Ａｌ、Ｍｎ、ＺｎおよびＮｉからなるＸ群から選ばれる少なくとも１種のＸ元素を含み、残部がＣｕおよび不可避不純物よりなる。
　本発明において、Ｃｕ－Ｘ合金層を構成する金属は、そのＸ元素が、下記（１）～（５）のいずれか１つの組成系である。
（１）前記Ｘ群の元素を１種類のみ含み、その含有量が６ａｔ％以上２７ａｔ％以下である。
（２）Ａｌを４ａｔ％以上１５ａｔ％以下含み、さらにＭｎを５ａｔ％以上１０ａｔ％以下含む。
（３）Ｚｎを５ａｔ％以上１０ａｔ％以下含み、さらにＭｎを５ａｔ％以上２６ａｔ％以下含む。
（４）Ｚｎを４ａｔ％以上１４ａｔ％以下含み、さらにＡｌを５ａｔ％以上１５ａｔ％以下含む。
（５）Ａｌを５ａｔ％以上１０ａｔ％以下含み、さらにＮｉを２ａｔ％以上１０ａｔ％以下含む。
　Ｃｕ－Ｘ合金層を形成するＣｕ合金中のＸ元素の含有量が上記（１）～（５）であると、４００℃での熱処理後の電気抵抗を３μΩｃｍ以下とすることができる。前記範囲を超えてＸ元素を含有すると、４００℃熱処理後の電極の抵抗値が３μΩｃｍ超える場合がある。これは、熱処理によってＸ元素が配線層中に拡散するためと考えられる。
　上記組成系を有するＣｕ－Ｘ合金層を備えた積層配線膜は、酸化物半導体を用いたＴＦＴ素子用のＣｕ配線として好適に使用することができる。
　熱処理の温度が４００℃を超え、５００℃以下で処理する場合は、Ｃｕ－Ｘ合金層を合成する金属が、そのＸ元素が、下記（１’）～（５’）のいずれか１つの組成系であることが好ましい。
（１’）前記Ｘ群の元素を１種類のみ含み、その含有量が６ａｔ％以上１４ａｔ％以下である。
（２’）Ａｌを４ａｔ％以上９ａｔ％以下含み、さらにＭｎを５ａｔ％以上１０ａｔ％以下含む。
（３’）Ｚｎを５ａｔ％以上１０ａｔ％以下含み、さらにＭｎを５ａｔ％以上１０ａｔ％以下含む。
（４’）Ｚｎを４ａｔ％以上１４ａｔ％以下含み、さらにＡｌを５ａｔ％以上１０ａｔ％以下含む。
（５’）Ａｌを５ａｔ％以上１０ａｔ％以下含み、さらにＮｉを６ａｔ％以上１０ａｔ％以下含む。
　Ｃｕ－Ｘ合金層を形成するＣｕ合金中のＸ元素の含有量が上記（１’）～（５’）であると、５００℃においても熱処理後の電気抵抗を３μΩｃｍ以下とすることができる。
　上記組成系を有するＣｕ－Ｘ合金層を備えた積層配線膜は、酸化物半導体もしくはＬＴＰＳ半導体を用いたＴＦＴ素子用のＣｕ配線として好適に使用することができる。
　Ｃｕ－Ｍｎ膜を酸化雰囲気中で加熱したり、もしくは酸素プラズマ存在下で処理するとＭｎ元素が合金表面に拡散して濃化層を形成する。濃化したＭｎは酸化され不導態化する。そのため反応初期に酸化されてしまったＣｕ元素以外は不導態化したＭｎ酸化物によって保護され、それ以上Ｃｕ－Ｍｎ膜内部に酸素が拡散せず、酸化の進行を抑制する効果がある。このとき、Ｍｎの含有量が所定範囲を下回ると、酸化を抑制するほどの濃化層が形成できない場合がある。またＭｎの含有量が所定範囲を超えると、薄膜トランジスタの工程で用いられる過酸化水素水や混酸系のエッチング液を用いた配線加工時に、Ｃｕ－Ｍｎ膜のエッチングが促進されるため、良好な配線形状が得られない場合がある。
　Ｘ元素がＡｌ、Ｚｎの場合も、Ｍｎ同様に不動態化し、Ｃｕの表面を酸化から保護する効果がある。しかしながら、これらのＸ元素は過酸化水素水や混酸系のエッチング液を用いたとき、Ａｌはエッチングを妨げ、Ｚｎはエッチングを促進する効果がある。これらの元素を添加したとき、Ａｌは所定以上に添加量を増やすと、配線層よりもエッチング速度が遅くなり、Ｃｕ－Ｘ合金層が配線層よりも張り出してしまい、延出部が残るため、好ましくない。また、Ｚｎは所定以上に添加量を増やすと、Ｃｕ－Ｘ合金層のエッチング速度をより促進するため、良好なエッチング形状が得られない場合がある。
　Ｘ元素がＮｉの場合、Ｎｉの含有量が所定範囲を下回ると、酸化からの保護の効果が十分でないため、好ましくない。また、ＮｉはＣｕに対して固溶しやすい元素であり、加熱によって配線層として積層するＣｕまたはＣｕ合金内に拡散する。Ｎｉの含有量が所定範囲を超えると、加熱処理後の拡散によって抵抗が増加するため、好ましくない。
　上記組成系を有するＣｕ－Ｘ合金層を備えた積層配線膜は、基板に積層される場合において、前記基板に積層される側の表面に、Ｔｉを含む密着層をさらに有することが好ましい。半導体基板（絶縁体）と配線層（Ｃｕ金属）との密着性を向上させるべく、半導体基板と配線層との間にＴｉを含む密着層（Ｔｉ単体、Ｔｉ合金、Ｔｉ酸化物、Ｔｉ窒化物など）を設けることがあるが、ＳｉＯｘ成膜時の高温熱処理による影響で、Ｃｕ中にＴｉが拡散して、配線抵抗が上昇するおそれがある。一方、積層配線膜として上述の特定の合金層により形成されるキャップ層を設けた場合には、ＴｉのＣｕ中への拡散を抑制でき、配線抵抗の上昇を抑制することができる。
　その理由については明らかではないが、Ｔｉの拡散は酸素が駆動源になるため、本発明のキャップ層を積層することにより配線層（Ｃｕ配線膜）中への酸素進入を阻害するためと考えられる。
　なお、Ｔｉを含む密着層を用いた場合の積層配線膜の構成を例示する概略断面図を図７に示す。図７に示すように、本実施形態においては、ガラス基板１上に密着層１４、配線層２およびキャップ層（Ｃｕ－Ｘ合金層）３から構成される積層配線膜がこの順序で積層されており、更に積層配線膜上に絶縁膜（ＳｉＯｘ）４が形成されている。なお、本実施形態に対し、さらに密着層１４と配線層２との間にキャップ層３を有する形態であってもよい。また、ガラス基板１上に密着層１４、キャップ層３および配線層２がこの順序で積層された形態であってもよい。
　密着層の膜厚は１０ｎｍ以上とすることが好ましく、１５ｎｍ以上がより好ましく、２０ｎｍ以上が更に好ましい。また、密着層の膜厚は、５０ｎｍ以下とすることが好ましく、４０ｎｍ以下がより好ましく、３０ｎｍ以下が更に好ましい。密着層の膜厚が前記範囲であることにより、基板との間に均一な密着層を形成することができ、皮膜の密着性を確保できる。
　Ｃｕ－Ｘ合金層は、膜厚が薄いと耐酸化性が不十分となり、厚いとエッチング加工性を損なううえ、Ｃｕ－Ｘ合金層の膜厚が厚いとＣｕ電極全体の抵抗でみたときの抵抗が大きくなってしまう。このため、Ｃｕ－Ｘ合金層の膜厚は５ｎｍ以上２００ｎｍ以下であることが好ましい。Ｃｕ－Ｘ合金層の膜厚は、１０ｎｍ以上がより好ましく、２０ｎｍ以上が更に好ましく、１５０ｎｍ以下がより好ましく、１００ｎｍ以下が更に好ましい。
　配線層とＣｕ－Ｘ合金層の合計膜厚、すなわち積層配線膜の膜厚は、５５ｎｍ以上とすることが好ましく、７０ｎｍ以上がより好ましく、１００ｎｍ以上が更に好ましい。また、前記合計膜厚は、１２００ｎｍ以下とすることが好ましく、７００ｎｍ以下がより好ましく、５００ｎｍ以下が更に好ましい。積層配線膜の膜厚が前記範囲であると、安価で成膜が可能であり、かつ良好な配線形状を得ることができる。
　本発明の積層配線膜は、配線形状が図６（ｃ）に示したような順テーパー形状であることが好ましい。Ｃｕ－Ｘ合金層が配線層よりも張り出した形状ではなく、順テーパー形状であると、Ｃｕ－Ｘ合金層上に被覆される層間絶縁膜や配線の破綻を抑制することができる。
　配線層のテーパー角度は、基板に対して１００°以下であることが好ましく、基板に対して３０°～８０°であることがより好ましく、３０°～６０°であることがさらに好ましく、４０°～６０°であることが更に好ましい。配線層のテーパー角度が前記範囲であると、積層配線膜のテーパー端部から、配線層の露出幅を狭くすることができる。テーパー角度が小さく配線層の露出幅が大きい場合、キャップ層で保護されていない配線層面積の増加を意味しており、その後の処理で酸化される恐れがある。酸化によってテーパー端部が酸化した場合、電気抵抗が低い配線として機能する幅が狭くなることを意味しており、配線抵抗が増加する恐れがある。
　また、配線層のテーパー角度は、同じ膜厚のＣｕ単層膜のテーパー角度に対して、－２５％～＋５０％の範囲であることが好ましい。同じ膜厚のＣｕ単層膜のテーパー角度に対する配線層のテーパー角度が前記範囲であることにより、Ｃｕ－Ｘ合金層上に被覆される層間絶縁膜や配線の破綻をより一層抑制することができる。
　本発明において、配線層とＣｕ－Ｘ合金層は、スパッタリング法により成膜することが好ましい。スパッタリング法は生産性に優れ、スパッタリングターゲットを用いれば、ほぼ同じ組成の合金膜を安定して成膜できる。スパッタリング法としては、例えばＤＣスパッタリング法、ＲＦスパッタリング法、マグネトロンスパッタリング法、反応性スパッタリング法等のいずれのスパッタリング法を採用してもよく、その形成条件は適宜設定すればよい。
　上記スパッタリング法で、例えば、Ｃｕ－Ｘ合金層を形成するには、上記ターゲットとして、Ｘ元素を所定量含有するＣｕ合金からなるものであって、所望のＣｕ－Ｘ合金層と同一の組成のＣｕ合金スパッタリングターゲットを用いれば、組成ズレすることなく、所望の成分・組成のＣｕ－Ｘ合金層を形成できる。または、組成の異なる二つ以上の純金属ターゲットや合金ターゲットを用い、これらを同時に放電させて成膜してもよい。または、純Ｃｕターゲットに合金元素の金属をチップオンすることにより成分を調整しながら成膜してもよい。
　Ｃｕ－Ｘ合金層をスパッタリング法で成膜する場合、スパッタリング条件の一例として、以下の条件が挙げられる。（スパッタリング条件）
　成膜装置：ＤＣマグネトロンスパッタリング装置（ＵＬＶＡＣ社製「ＣＳ－２００」）
　基板：無アルカリガラス（コーニング社製「イーグル２０００」）
　基板温度：室温
　成膜ガス：Ａｒガス
　ガス圧：２ｍＴｏｒｒ
　スパッタパワー：３００Ｗ
　真空到達度：１×１０－６Ｔｏｒｒ以下
　本発明のＣｕ合金スパッタリングターゲットは、その形状が、スパッタリング装置の形状や構造に応じて任意の形状、例えば角型プレート状、円形プレート状、ドーナツプレート状等のものが挙げられる。上記Ｃｕ合金スパッタリングターゲットの製造方法としては、溶解鋳造法や粉末焼結法、スプレイフォーミング法で、Ｃｕ合金からなるインゴットを製造して得る方法や、Ｃｕ合金からなるプリフォーム、即ち最終的な緻密体を得る前の中間体を製造した後、該プリフォームを緻密化手段により緻密化して得られる方法が挙げられる。
　配線パターンは、本発明の積層配線膜に対して、エッチング等の処理により形成することができる。配線パターンを細くすると、画素素子の開口率を上げることができる。そのため、高精細な表示装置に対応することができる。酸化物半導体や低温ポリシリコン半導体を用いたＴＦＴ素子は、高精細パネルに搭載されており、配線幅を細くするよう求められる。このような観点から、具体的な配線パターンの幅は、１０μｍ以下にすることが好ましく、より好ましくは５μｍ以下である。
　上記Ｃｕ－Ｘ合金層以外の各層の成膜方法は、本発明の技術分野において通常用いられる方法を適宜採用することができる。
　本発明の積層配線膜は、配線電極や入力装置に適用することができる。入力装置には、タッチパネルなどのように表示装置に入力手段を備えた入力装置や、タッチパッドのような表示装置を有さない入力装置が含まれる。特に本発明の積層配線膜は、タッチパネルセンサーに好ましく用いられる。
　続いて、本発明に係る薄膜トランジスタ素子について説明する。
（薄膜トランジスタ素子）
　本発明の薄膜トランジスタ素子は、電気抵抗が１０μΩｃｍ以下のＣｕまたはＣｕ合金からなる配線層と、該配線層の上層および下層のうちの少なくとも一方に設けられるＣｕとＸ元素を含むＣｕ－Ｘ合金層とを備え、前記Ｘ元素は、Ａｌ、Ｍｎ、ＺｎおよびＮｉからなるＸ群から選ばれる少なくとも１種である積層配線膜を用いることを特徴とする。また、ＴＦＴの活性層として、酸化物半導体もしくはＬＴＰＳ半導体が用いられる。
　図２は、本発明の積層配線膜を備えた薄膜トランジスタ素子の構成を例示する概略断面図である。図２に示すように、本実施形態においては、ガラス基板１上に配線層２およびキャップ層（Ｃｕ－Ｘ合金層）３から構成される積層配線膜、絶縁膜（ＳｉＯｘ）４、酸化物半導体５、配線層６およびキャップ層（Ｃｕ－Ｘ合金層）７から構成される積層配線膜、絶縁膜（ＳｉＯｘ）８がこの順序で積層されている。キャップ層（Ｃｕ－Ｘ合金層）３およびキャップ層（Ｃｕ－Ｘ合金層）７として、上述した特定の合金層が好適に用いられる。
　以下に、実施例及び比較例を挙げて本発明をさらに具体的に説明するが、本発明は、これらの実施例に限定されるものではなく、その趣旨に適合し得る範囲で変更を加えて実施することも可能であり、それらはいずれも本発明の技術的範囲に包含される。
＜実施例１＞
（１）積層配線膜の作製
　透明基板として、直径４インチ、板厚が０．７ｍｍの無アルカリ硝子板を用意し、中性洗剤で洗浄後、エキシマＵＶランプに３０分間照射して表面の汚染を除去した。この表面処理した無アルカリ硝子板上に、ＤＣマグネトロンスパッタリング法により、表１に示す配線層とＣｕ－Ｘ合金層であるキャップ層を備えた積層配線膜を成膜した。なお、試料Ｎｏ．１の配線膜は配線層のみの単層膜である。
　成膜にあたっては、成膜前にチャンバー内の雰囲気を一旦、３×１０－６Ｔｏｒｒに調整してから、前記基板上に配線層、キャップ層の順に下記スパッタリング条件でスパッタリングを行い、積層配線膜を形成した。スパッタリングターゲットとしては、純Ｃｕスパッタリングターゲット、または各キャップ層と同一の成分組成のターゲットであって、いずれも直径４インチの円盤型スパッタリングターゲットを用いた。得られた積層配線膜を用いて下記の評価を行った。
（スパッタリング条件）
　成膜装置：ＤＣマグネトロンスパッタリング装置（ＵＬＶＡＣ社製「ＣＳ－２００」）
　基板：無アルカリ硝子板（コーニング社製「イーグル２０００」）
　基板温度：室温
　成膜ガス：Ａｒガス
　ガス圧：２ｍＴｏｒｒ
　スパッタパワー：３００Ｗ
　真空到達度：１×１０－６Ｔｏｒｒ以下
（２）積層配線膜の電気抵抗率の測定
　積層配線膜の電気抵抗率を、次の通り測定した。即ち、無アルカリ硝子板上に表１に記載のＣｕ系膜上にキャップ層を記載の膜厚で成膜したサンプルを４端子法で電気抵抗を測定した。測定した電気抵抗とＣｕ系膜とキャップ層の膜厚の合計値から電気抵抗率を算出した。次いで、ＵＬＶＡＣ社製の赤外線ランプ加熱装置：ＲＴＰ－６を用い、Ｎ２雰囲気下で４００℃と５００℃のそれぞれで１時間の熱処理を行った後、同様に電気抵抗を測定し、上記同様の方法で電気抵抗率を算出した。
　その結果を表１に示す。本実施例では、４００℃で電気抵抗率が３μΩｃｍ以下の試料を、酸化物半導体を用いたＴＦＴ素子向けの耐熱性として合格とし、５００℃で電気抵抗率が３μΩｃｍ以下の試料を酸化物半導体もしくはＬＴＰＳを用いたＴＦＴ素子向けに合格とした。
（３）配線形状、テーパー角度の評価
　フォトレジストを用いて積層配線膜上にラインおよびスペースからなるレジストパターンを形成した。試料Ｎｏ．２～３９に記載する積層配線膜について、三菱ガス化学株式会社製の過水系エッチング液でエッチング加工を行い、その後、アセトンに浸漬してレジストを除去して透明基板ごと劈開した。次いで、上記エッチング加工を行った試料について、株式会社日立パワーソリューションズ製の電子顕微鏡：Ｓ－４０００を用いて、その断面形状を観察した。図６（ａ）に示したように、キャップ層１３が配線層１２よりも張り出して延出部１３ａが形成されたものを「延出部有り」、図６（ｂ）に示したように逆テーパー状になっているものを「逆テーパー形状」、図６（ｃ）に示したように順テーパー状になっているものを「順テーパー形状」と評価した。
　続いて、試料Ｎｏ．１～３９に記載する積層配線膜について、断面形状より、透明基板に対するテーパー角度を測定した。また、同方法で作製した試料Ｎｏ．１のＣｕ単膜のテーパー角度に対する配線層のテーパー角度の比率を、下記式（１）により計算した。なお、透明基板に対するテーパー角度が３０°～８０°であるものを合格とし、特に試料Ｎｏ．１のＣｕ単膜のテーパー角度に対する配線層のテーパー角度の比率が－２５％～＋５０％の範囲内の角度で加工できたものをより優れたものであると判断した。その結果を表１に示す。
　Ｃｕ単膜に対するテーパー角度の比率（％）＝［（Ｃｕ単膜のテーパー角度）－（積層配線膜のテーパー角度）］／（Ｃｕ単膜のテーパー角度）・・・（１）
（４）耐酸化の評価
　積層配線膜のキャップ層上に、サムコ株式会社製のプラズマＣＶＤ装置：ＰＤ－２２０ＭＬを用いてＳｉＯｘ膜を成膜した。成膜にはＳｉＨ４とＮ２Ｏガスを用い、膜厚２５０ｎｍのＳｉＯｘ膜を成膜し、目視により外観を検査し、ＳｉＯｘ膜の剥離の有無を確認した。その結果を表１に示す。なお、耐酸化が不足している場合、ＳｉＯｘ膜の成膜時に膜の表面の酸化が進み、色ムラやさらには界面の体積膨張によってＳｉＯｘ膜の膜剥がれが生じるため、好ましくない。
　上記（２）積層配線膜の電気抵抗率の測定、（３）配線形状、テーパー角度の評価、および（４）耐酸化の評価の結果を、表１に示す。
　また、上記（２）～（４）項の結果より、４００℃熱処理で電気抵抗率が３μΩｃｍ以下であって、配線形状が順テーパー形状であり、かつＣＶＤ法でＳｉＯｘ成膜した際の剥離が無いものを、酸化物半導体を用いたＴＦＴ素子向けに好適であるとして合格『○』とし、上記条件のいずれか１つでも満たさないものを不合格『×』とした。
　加えて、４００℃および５００℃熱処理で電気抵抗率が３μΩｃｍ以下であって、配線形状が順テーパー形状であり、かつ、透明基板に対するテーパー角度が３０°～８０°であり、加えてＣＶＤ法でＳｉＯｘ成膜した際に剥離が無いものを、酸化物半導体および低温ポリシリコン半導体を用いたＴＦＴ素子向けに好適であるとして合格『○』とし、上記条件のいずれか１つでも満たさないものを不合格『×』とした。
　結果をあわせて表１に示す。
Figure JPOXMLDOC01-appb-T000001
　表１の結果より、次のことがわかる。まず、Ｎｏ．１は、キャップ層を有さないＣｕ単膜の例であり、ＳｉＯｘ膜の成膜時において剥離が見られた。続いて、Ｎｏ．２～１３は、キャップ層であるＣｕ－Ｘ合金層が、Ｃｕと１種の元素を含む積層配線膜である。Ｎｏ．５、８～１０、１３は、本発明で規定するＣｕ－Ｘ合金層のＸ元素の組成系（１）を満たす例であり、配線形状が順テーパー状であり、４００℃の熱処理後も電気抵抗が３μΩｃｍ以下の電気抵抗であり、ＳｉＯｘ膜の成膜時においても剥離は認められなかった。これに対し、Ｎｏ．３、６は、高熱処理時の低電気抵抗を安定して得ることができず、かつ、Ｎｏ．３は、Ｃｕ－Ｘ合金層に延出部が形成された配線形状となった。Ｎｏ．２、４、７、１１および１２は、ＳｉＯｘ膜の成膜時において剥離が見られた。
　特に、Ｎｏ．５と８は、本発明で規定するＣｕ－Ｘ合金層のＸ元素の組成系（１’）を満たす例であり、配線形状が順テーパー状であり、且つテーパー角度も３０°～８０°であり、４００℃と５００℃の熱処理後のいずれにおいても３μΩｃｍ以下の電気抵抗であり、ＳｉＯｘ膜の成膜時においても剥離は認められなかった。
　また、Ｎｏ．１４～３９は、キャップ層であるＣｕ－Ｘ合金層が、Ｃｕと２種以上の元素を含む積層配線膜である。Ｎｏ．１９～３９は、本発明で規定するＣｕ－Ｘ合金層のＸ元素の組成系（２）～（５）のいずれかを満たす例であり、配線形状が順テーパー状であり、４００℃の熱処理後も電気抵抗が３μΩｃｍ以下の電気抵抗であり、ＳｉＯｘ膜の成膜時においても剥離は認められなかった。これに対し、Ｎｏ．１４～１８は高熱処理時の低電気抵抗を安定して得ることができなかった。
　特に、Ｎｏ．１９、２７～３０および３２～３９は、本発明で規定するＣｕ－Ｘ合金層のＸ元素の組成系（２’）～（５’）のいずれかを満たす例であり、配線形状が順テーパー状であり、且つテーパー角度も３０°～８０°であり、４００℃と５００℃の熱処理後のいずれにおいても３μΩｃｍ以下の電気抵抗であり、ＳｉＯｘ膜の成膜時においても剥離は認められなかった。
　なお、Ｎｏ．２２～２６のＣｕ－Ｚｎ－Ｍｎ合金層に着目すると、Ｎｏ．２４～２６の例においては、本発明で規定するＣｕ－Ｘ合金層のＸ元素の組成系（３’）を満たしており、かつ、５００℃の熱処理後の電気抵抗がＮｏ．２２および２３に比べて低い値（２．０μΩｃｍ以下）となっている。この結果より、Ｃｕ－Ｚｎ－Ｍｎ合金層を用いた場合の、Ｍｎの含有量は１０ａｔ％以下が好ましいことがわかる。
　また同様に、Ｎｏ．３５～３９のＣｕ－Ａｌ－Ｎｉ合金層に着目すると、Ｎｏ．３７および３８の例においては、本発明で規定するＣｕ－Ｘ合金層のＸ元素の組成系（５’）を満たしており、かつ、５００℃の熱処理後の電気抵抗がＮｏ．３５、３６および３９に比べて低い値（２．３μΩｃｍ）となっている。この結果より、Ｃｕ－Ａｌ－Ｎｉ合金層を用いた場合の、Ｎｉの含有量は６ａｔ％以上が好ましいことがわかる。
＜実施例２＞
　Ｔｉを含む密着層を用いた場合の積層配線膜を下記の手順により作製した。具体的には、実施例１の場合と同様に、透明基板としての無アルカリ硝子板上に、ＤＣマグネトロンスパッタリング法により、表２に示す密着層、配線層およびＣｕ－Ｘ合金層であるキャップ層を備えた積層配線膜を順次成膜した。なお、試料Ｎｏ．４０の配線膜は密着層および配線層のみの積層膜である。密着層、配線層およびキャップ層の成膜条件は、実施例１の場合と同様である。
　上記のようにして得られた積層配線膜について、実施例１の場合と同じ条件で、電気抵抗率の測定および耐酸化の評価を行った。また、上記結果より、４００℃熱処理で電気抵抗率が３μΩｃｍ以下であって、ＣＶＤ法でＳｉＯｘ成膜した際の剥離が無いものを、酸化物半導体を用いたＴＦＴ素子向けに好適であるとして合格『○』とし、上記条件のいずれか１つでも満たさないものを不合格『×』とした。
　加えて、４００℃および５００℃熱処理で電気抵抗率が３μΩｃｍ以下であって、ＣＶＤ法でＳｉＯｘ成膜した際に剥離が無いものを、酸化物半導体および低温ポリシリコン半導体を用いたＴＦＴ素子向けに好適であるとして合格『○』とし、上記条件のいずれか１つでも満たさないものを不合格『×』とした。
　積層配線膜の電気抵抗率の測定、耐酸化の評価、および酸化物半導体または低温ポリシリコン半導体を用いたＴＦＴ素子への適合性の結果をまとめて表２に示す。
Figure JPOXMLDOC01-appb-T000002
　表２の結果より、次のことがわかる。まず、Ｎｏ．４０は、密着層および配線層のみの積層膜の例であり、ＳｉＯｘ膜の成膜時において剥離が見られた。また、５００℃の熱処理後において電気抵抗が３μΩｃｍ以下を満たさなかった。続いて、Ｎｏ．４１は、本発明で規定するＣｕ－Ｘ合金層のＸ元素の組成系（１）を満たさない例であり、ＳｉＯｘ膜の成膜時において剥離が見られなかったものの、４００℃および５００℃いずれの熱処理後においても電気抵抗が３μΩｃｍ以下を満たさなかった。
　これに対し、Ｎｏ．４２～４６は、本発明で規定するＣｕ－Ｘ合金層のＸ元素の組成系（１）～（５）のいずれかを満たす例であり、４００℃および５００℃いずれの熱処理後においても電気抵抗が３μΩｃｍ以下を満たし、ＳｉＯｘ膜の成膜時において剥離が見られなかった。
　本発明を特定の態様を参照して詳細に説明したが、本発明の精神と範囲を離れることなく様々な変更および修正が可能であることは、当業者にとって明らかである。なお、本出願は、２０１６年５月１３日付けで出願された日本特許出願（特願２０１６－０９７３２１）及び２０１７年４月１１日付けで出願された日本特許出願（特願２０１７－０７８５０５）に基づいており、その全体が引用により援用される。
１　ガラス基板
２　配線層
３　キャップ層（Ｃｕ－Ｘ合金層）
４　絶縁膜（ＳｉＯｘ）
５　酸化物半導体
６　配線層
７　キャップ層（Ｃｕ－Ｘ合金層）
８　絶縁膜（ＳｉＯｘ）
１１　基板
１２　配線層
１３　キャップ層
１３ａ　延出部
１４　密着層

Claims (7)

  1. 　電気抵抗が１０μΩｃｍ以下のＣｕまたはＣｕ合金からなる配線層と、該配線層の上層および下層のうちの少なくとも一方に設けられるＣｕとＸ元素を含むＣｕ－Ｘ合金層とを備え、
    　前記Ｘ元素は、Ａｌ、Ｍｎ、ＺｎおよびＮｉからなるＸ群から選ばれる少なくとも１種であり、
    　前記Ｃｕ－Ｘ合金層を構成する金属が、下記（１）～（５）のいずれか１つの組成系であり、
    　配線パターンの幅が１０μｍ以下であることを特徴とする積層配線膜。
    （１）前記Ｘ群の元素を１種類のみ含み、その含有量が６ａｔ％以上２７ａｔ％以下である。
    （２）Ａｌを４ａｔ％以上１５ａｔ％以下含み、さらにＭｎを５ａｔ％以上１０ａｔ％以下含む。
    （３）Ｚｎを５ａｔ％以上１０ａｔ％以下含み、さらにＭｎを５ａｔ％以上２６ａｔ％以下含む。
    （４）Ｚｎを４ａｔ％以上１４ａｔ％以下含み、さらにＡｌを５ａｔ％以上１５ａｔ％以下含む。
    （５）Ａｌを５ａｔ％以上１０ａｔ％以下含み、さらにＮｉを２ａｔ％以上１０ａｔ％以下含む。
  2. 　前記Ｃｕ－Ｘ合金層を構成する金属が、下記（１’）～（５’）のいずれか１つの組成系であり、
    　配線パターンの幅が５μｍ以下である、請求項１に記載の積層配線膜。
    （１’）前記Ｘ群の元素を１種類のみ含み、その含有量が６ａｔ％以上１４ａｔ％以下である。
    （２’）Ａｌを４ａｔ％以上９ａｔ％以下含み、さらにＭｎを５ａｔ％以上１０ａｔ％以下含む。
    （３’）Ｚｎを５ａｔ％以上１０ａｔ％以下含み、さらにＭｎを５ａｔ％以上１０ａｔ％以下含む。
    （４’）Ｚｎを４ａｔ％以上１４ａｔ％以下含み、さらにＡｌを５ａｔ％以上１０ａｔ％以下含む。
    （５’）Ａｌを５ａｔ％以上１０ａｔ％以下含み、さらにＮｉを６ａｔ％以上１０ａｔ％以下含む。
  3. 　基板に積層される積層配線膜であって、前記基板に積層される側の表面に、Ｔｉを含む密着層をさらに有する、請求項１または２に記載の積層配線膜。
  4. 　前記配線層の膜厚が５０ｎｍ以上１０００ｎｍ以下であり、前記Ｃｕ－Ｘ合金層の膜厚が５ｎｍ以上２００ｎｍ以下である、請求項１または２に記載の積層配線膜。
  5. 　前記配線層の膜厚が５０ｎｍ以上１０００ｎｍ以下であり、前記Ｃｕ－Ｘ合金層の膜厚が５ｎｍ以上２００ｎｍ以下である、請求項３に記載の積層配線膜。
  6. 　請求項１記載の積層配線膜と、酸化物半導体を含むことを特徴とする薄膜トランジスタ素子。
  7. 　請求項２記載の積層配線膜と、低温ポリシリコン半導体または酸化物半導体を含むことを特徴とする薄膜トランジスタ素子。
PCT/JP2017/017690 2016-05-13 2017-05-10 積層配線膜および薄膜トランジスタ素子 WO2017195826A1 (ja)

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JP2020012190A (ja) * 2018-07-20 2020-01-23 株式会社アルバック 密着膜用ターゲット、配線層、半導体装置、液晶表示装置
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JPWO2020213232A1 (ja) 2019-04-19 2021-05-06 株式会社アルバック Ｃｕ合金ターゲット
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