TW201030819A - Al alloy film for display device, thin film transistor substrate, method for manufacturing same, and display device - Google Patents

Abstract

Disclosed is an Al alloy film for display devices, which enables omission of a barrier metal layer between the Al alloy film and a semiconductor layer of a TFT, and also enables reduction of the number of processes required for manufacturing a TFT substrate. Specifically disclosed is an Al alloy film for display devices, which is directly connected, on the substrate of a display device, with a semiconductor layer of a thin film transistor. The Al alloy film contains 0.05-0.5 atom% of at least one element selected from a group consisting of Co, Ni and Ag, and 0.2-1.0 atom% of either Ge and/or Cu. The Al alloy film is patterned by dry etching.

Description

201030819 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to an aluminum (A1) alloy film for a display device, a thin film electromorphic substrate, a method for producing the same, and a display device. More specifically, the A1 alloy film for a display device in which the semiconductor layer of the crystal is directly connected and patterned by dry etching is preferably an A1 alloy film for a display device which can be directly connected to the transparent conductive film. . The φ A1 alloy film of the present invention can be applied to, for example, a flat panel display (display device) such as a liquid crystal display or an organic EL display. [Prior Art] In an active matrix liquid crystal display device such as a liquid crystal display, a thin film transistor: a Thin Film Transistor (hereinafter referred to as "TFT") is used as a switching element. The basic structure of a conventional TFT substrate is shown in Fig. 1. As shown in Fig. 1, the TFT element has: a gate electrode 2 for controlling the on/off of the TFT formed on the glass substrate 1, and a semiconductor germanium layer 4 provided via the gate insulating film 3; A drain electrode 5 and a source electrode 6 connected thereto. A transparent conductive film (transparent pixel electrode) 7 used for the pixel electrode of the liquid crystal display unit is additionally connected to the drain electrode 5. The A1 alloy is widely used for the wiring metal used for the gate electrode 2, the gate electrode 5, and the source electrode 6 for reasons such as low resistance (specific resistance) and easy processing. Conventionally, the interface between the A1 alloy wiring (A1 alloy film) and the transparent conductive film 7, and/or the interface between the A1 alloy film and the semiconductor germanium layer 4 of the TFT, -5-201030819, are not directly in contact with each other. A barrier metal layer 11 made of a high melting point metal such as Mo, Cr, Ti, or W is provided. When the A1 alloy film is directly connected to the semiconductor layer of the TFT without interposing the barrier metal layer 11, the subsequent process (for example, a film formation process such as an insulating layer formed on the TFT, or sintering or annealing, etc.) In the thermal history in thermal engineering or the like, A1 diffuses in the semiconductor layer to lower the TFT characteristics or increase the resistance of the A1 alloy. For example, after the formation of the A1 alloy film, the tantalum nitride film (protective film) is formed at a temperature of about 100 to 300 ° C by a CVD method or the like, but since A1 is easily oxidized, if the barrier metal layer 1 is not provided, 1. A convex protrusion called a hillock is formed on the surface of the A1 alloy film, which causes problems such as deterioration in picture display quality. In addition, if the barrier metal layer 11 is not provided, A1 is easily oxidized due to oxygen generated in the film formation process of the liquid crystal display device or oxygen added during film formation, and there is also an A1 alloy film and a transparent conductive film. The interface of the (pixel electrode) or the interface between the A1 alloy film and the semiconductor layer forms an insulating layer of the A1 oxide, and the contact resistance (contact resistance) is increased. However, in order to form the barrier metal layer 11, in addition to the sputtering device for film formation required for the formation of the gate electrode 2 or the source electrode 6 or even the gate electrode 5, it is necessary to separately provide a film forming chamber for forming a barrier metal. . With the mass production of liquid crystal displays, the progress of cost reduction has been made, and the increase in manufacturing cost or the decrease in productivity due to the formation of the barrier metal layer cannot be ignored. Therefore, even if the barrier metal layer between the A1 alloy film and the semiconductor layer is omitted, the Si direct contact technique which solves the above problems of the TFT 201030819 reduction or the increase in resistance due to the mutual diffusion of A1 and Si, etc. It is proposed (for example, Patent Documents 1 to 3). In the case of using an A1 alloy containing 0.1 to 6 atom% of Ni, a Ni-containing precipitate such as a telluride which prevents diffusion of A1 and Si is formed at the interface with the semiconductor layer. Further, Patent Document 2 describes that an Al alloy containing Si and La is further contained in Ni, and the effect of suppressing the mutual diffusion of A1 and Si is further enhanced by adding Si, and by adding La, the Al-Ni-Si alloy is added. φ The technical content of the rise resistance. Further, Patent Document 3 discloses a technique for preventing mutual diffusion of A1 and Si by providing a nitride layer (nitrogen-containing layer) at the interface between the A1 alloy film and the semiconductor layer. Further, Patent Documents 4 to 6 disclose an A1 alloy containing an alloy component such as Ni as a direct contact technique for ITO which omits a barrier gold layer between the A1 alloy film and the transparent conductive film. On the other hand, in the manufacture of a TFT substrate, the reduction in the number of manufacturing processes is reviewed for the purpose of reducing the manufacturing cost or improving the productivity. In general, a φ TFT substrate is formed by forming a film forming process of a metal film such as A1 on a substrate, coating a photosensitive material (photoresist), performing photolithography on exposure and development, and etching the metal film. Most of the engineering such as the etching process of the wiring pattern and the peeling process of peeling off the residual photosensitive material are manufactured. Therefore, it is expected that the cost reduction can be achieved by the simplification of the process. Therefore, a method of reducing the number of reticle used in the photolithography project to reduce the number of light lithography engineering has been proposed. For example, Patent Document 7 discloses a method of patterning by performing halftone exposure by passing a channel region of a TFT through a halftone mask. The halftone exposure method is a method in which the intermediate portion (semi-transmissive portion) is provided in addition to the transmission portion 201030819 and the light shielding portion. By exposure to halftone, three exposure levels of the exposed portion, the intermediate exposed portion, and the unexposed portion are presented in one exposure, and two kinds of resists (photosensitive materials) can be formed after development. By using the difference in the thickness of the resist as described above, the halftone exposure system can pattern the mask with a smaller number than usual, thereby increasing the production efficiency. [PRIOR ART DOCUMENT] [Patent Document 1] JP-A-2008-81385 [Patent Document 2] JP-A-2008-1 0844 [Patent Document 3] JP-A-2008-10801 [Patent Document 5] JP-A-2005-303003 [Patent Document 5] JP-A-2005-303003 (Patent Document 6) JP-A-2006-23388 (Patent Document 7) JP-A-2002-55364 SUMMARY OF THE INVENTION (Problems to be Solved by the Invention) An object of the present invention is to provide a novel metal layer which can omit a barrier metal layer between an A1 alloy film and a semiconductor layer of a TFT, and can reduce the number of manufacturing processes of the TFT substrate. Si direct contact technology. In detail, there is provided a TFT which can obtain good TFT characteristics even when the A1 alloy film is directly connected to the semiconductor layer of the TFT and can realize formation of TFT by -8 - 201030819 photolithography using halftone exposure. The novel Si direct contact technology is further reduced in the number of manufacturing processes at the time of the substrate. Another object of the present invention is to provide a novel ITO direct contact technique which can maintain low electrical resistance while ensuring good heat resistance even if the A1 alloy film is directly connected to the transparent conductive film. (Means for Solving the Problem) Φ The gist of the present invention is as follows. (1) An A1 alloy film for a display device, which is an A1 alloy film for a display device directly connected to a semiconductor layer of a thin film transistor on a substrate of a display device, wherein the A1 alloy film contains 〇. 5 to 0.5 atom % is selected from at least one selected from the group consisting of Co, 'Ni, and Ag, and at least one of 0.2 to 1.0 at% of Ge and Cu, and patterned by dry etching. (2) The A1 alloy film for a display device according to (1), wherein φ contains at least one of 0.05 to 0.3 atomic % of a rare earth element. (3) The A1 alloy film for a display device according to (1), wherein the A1 alloy film is directly connected to the transparent conductive film. (4) The A1 alloy film for a display device according to (2), wherein the A1 alloy film is directly connected to the transparent conductive film. (5) A thin film transistor substrate comprising the A1 alloy film for a display device according to any one of (1) to (4). (6) A display device comprising the thin film transistor substrate of the above (5), wherein the method for manufacturing a thin film transistor substrate is a thin film transistor on a substrate of a display device And a method of manufacturing a thin film transistor substrate of an A1 alloy film directly connected to a semiconductor layer of the thin film transistor, wherein the A1 alloy film contains 0.05 to 0.5 atomic % selected from Co,

At least one of a group of Ni and Ag, and at least one of 0.2 to 1.0 atom% of Ge and Cu, comprising: 形成 a resist formed on the A1 alloy film by photolithography using halftone exposure The engineering of the pattern; and the process of simultaneously forming the contact hole by simultaneously removing the semiconductor layer and the AI alloy film formed on the channel region by dry etching. (8) The method for producing a thin film transistor substrate according to the above aspect, wherein the A1 alloy film further contains at least one of 0.05 to 0.3 at% of a rare earth element. φ (Effect of the Invention) In the present invention, an A1 alloy film for wiring which is directly connectable to a semiconductor layer of a TFT is used, and an A1 alloy film which is excellent in dry etching property is used, and thus can be simultaneously removed by TFT by dry etching. The semiconductor layer on the channel region and the A1 alloy film form a contact hole. Therefore, when the A1 alloy film of the present invention is used, a display device which is excellent in productivity, low in cost, and high in performance can be obtained. -10-201030819 [Embodiment] The present invention is characterized in that the barrier metal layer between the semiconductor layer of the TFT and the A1 and the gold film can be omitted, and the wiring A1 alloy can be patterned by dry etching. In other words, (i) each contains at least one selected from the group consisting of Co, Ni, and Ag (hereinafter sometimes referred to as group X1), and Ge and/or Cu (hereinafter sometimes referred to as a group). The A1-X1-X2 alloy film of X2) and (Π) are preferably an A1-X1-X2- rare earth element alloy film containing a rare earth element of a predetermined amount of φ in the alloy film. Since the A1 alloy film is extremely excellent in dry etching property, when the channel portion is subjected to halftone exposure using the A1 alloy film, the semiconductor layer and the A1 alloy film formed on the channel region of the TFT can be simultaneously removed, thereby shortening the manufacturing process. . " In contrast, the widely used A1 alloy film (for example, laminated)

A high melting point metal such as Mo, Cr, or W, a pure A1, a laminated film of the high melting point metal, or an Al-Nd film or the like) has a very low dry etching rate, and therefore cannot be patterned by dry etching or the like. A TFT with high shape accuracy is obtained. Among them, although the dry etching rate of the above laminated film using Ti as a high melting point metal is not too low, there is a problem that the laminated film itself has a very high electrical resistance and the like, and it cannot be used. _ "Dry etching" in this specification means not only removing the object to be etched (interlayer insulating film, A1 alloy film, or semiconductor layer), but also cleaning the surface of the A1 alloy film after the contact hole reaches the A1 alloy film. For the purpose of the oxidation, the surface of the A1 alloy film is exposed to an etching gas. In the present specification, "dry etching property" means: (i) -11 - 201030819 after etching, the amount of residue generation is small, and the (ϋ) etching rate ratio is high. Specifically, when the characteristics of (i) and (Π) are evaluated by the method described in the examples below, it is satisfied that: (i) the residue after etching does not occur, and (ii) the etching ratio is 0.8. The above is called "dry etching is good". The A1 alloy film satisfying these characteristics is extremely excellent in dry etching property, so that the semiconductor layer formed on the channel region and the Al alloy film can be simultaneously removed to form contact holes. In addition, the tightness of the wiring size and shape can be precisely controlled. Here, the "etching ratio" is an index of the etching difficulty of the obtained A1 alloy film by plasma irradiation. In the present specification, the etching rate ratio is a ratio of the etching rate of the A1 alloy film based on the etching rate of the pure A1 having a good etching rate (that is, when the uranium engraving rate of the A1 alloy film is set to N1, the purity is The ratio of the ratio of N1 / N2 when the etching rate of A1 is N2 is expressed. The higher the etching rate ratio, the shorter the dry etching treatment time and the higher the productivity. The elements constituting the A1-X1-X2 alloy film of the present invention are explained in detail below. [Incorporating at least one selected from the group consisting of Co, Ni', and Ag (Group XI) to 0.05 to 0.5 atom%] The element of Group XI has an interface concentration at the interface between the A1 alloy film and the semiconductor layer. An element which forms a telluride compound layer to reduce the mutual diffusion of A1 and S i . Further, the elements of the group XI have a function of reducing the contact resistance of the A1 alloy film and the semiconductor layer and/or the transparent conductive film. Further, if the amount of the group XI is within the above range, the dry etching property is extremely excellent as shown in the later-described embodiment. The elements of group X 1 can be added as single -12- 201030819, or more than two types can be used. In order to fully exert these effects, the total amount of the elements of the group XI (the individual amount when it is contained alone) is 0.05 atom% or more. A preferred total amount of the group XI is 0.1 atom% or more. However, when the total amount of the elements of the group XI is excessive, the dry etching property is lowered. Therefore, the total amount of the elements of the group XI is 0.5 atom% or less. A preferred total amount of the elements of the group XI is 0.4 atom% or less. [Ge and/or Cu (Group X2) is formed to be 0.2 to 1.0 at%] The element of the group X2 has a function of refining the crystal of the A1 alloy film to prevent the atom from moving at the crystal grain boundary, thereby suppressing A1. The role of interdiffusion with Si. Further, if the amount of the group X2 is within the above range, the dry etching property is extremely excellent as shown in the later examples. The elements of group X2 can be added individually or both. In order to fully exert the above-described effects, the amount of the elements of the group X2 (the amount which is a single amount when it is contained alone) is set to 0.2 atom% or more. A preferred total amount of the group X2 is 0.3 atom% or more, and more preferably 0.4 atom% or more. However, when the total amount of the elements of the group X2 is excessive, the dry etching property is lowered. Therefore, the total amount of the elements of the group X2 is 1.0 atom% or less. A preferred total amount of the elements of the group X2 is 0.8 atom% or less, more preferably 〇6 atom% or less. The basic components of the A1 alloy film used in the present invention are as described above, and the residue is A1 and unavoidable impurities. Further, the A1 alloy film may contain at least one of -13-201030819 rare earth elements in the range of 0.05 to 0.3 atom%, thereby preventing hillock formation on the surface of the A1 alloy film and improving heat resistance. The rare earth element may be contained alone or in combination of two or more. Here, the above rare earth element means an element group in which a lanthanoid element (in the periodic table, a total of 15 elements from La of atom number 57 to Lu such as atom number 71) plus Sc (钪) and Y (钇). . The preferred rare earth element used in the present invention is at least one selected from the group consisting of Nd, Gd, La, Y, Ce, Pr, and Dy. In order to fully exhibit the above-described effects, a preferred total amount of the rare earth elements (in the case where _ alone is a single amount) is 〇. 5 atom% or more. A more preferable total amount of the rare earth element is 0.1 atom% or more. However, when the total amount of the rare earth elements is excessive, the electric resistance of the A1 alloy film becomes large, and it is not suitable as a wiring material. Therefore, the preferred total amount of the rare earth elements is set to 0.3 'at% or less. A more preferable total amount of the rare earth element is 0.2 atom% or less - 〇 As described above, the A1 alloy film of the present invention is excellent in dry etching property. The dry etching process used in the present invention will be described below. © In a dry etching process, a material gas containing a halogen gas such as Cl 2 is generally plasma-charged on a substrate placed in a vacuum vessel by high frequency power. The other high-frequency power is applied to the susceptor of the substrate (the material to be etched), and the ions drawn into the plasma on the substrate are anisotropically patterned by ion-assisted reaction with the reactive plasma. In the case of a dry etching gas, c 12 and B C 13 are preferably cited. For example, when a representative Cl 2 gas is used as the etching gas,

The Ch gas is dissociated by the plasma to form a C1 radical. The C1 free -14 - 201030819 is highly reactive, and adsorbed on the A1 alloy film as an object to be etched, and a chloride is formed on the surface of the A1 alloy film. In the substrate on which the A1 alloy film is formed, a high-frequency bias is applied, so that ions in the plasma are accelerated and incident on the surface of the A1 alloy film, and the chloride is evaporated by the ion bombardment effect, and is placed thereon. The outside of the vacuum container of the substrate is exhausted. In order to perform dry etching efficiently, it is preferred that the vapor pressure of the generated chloride is high. If the vapor pressure is high, the chloride can be evaporated by the surface temperature of the A1 alloy film or the physical assistance of the φ ion. On the other hand, when the vapor pressure of the chloride is low, the chloride residue remains on the surface without being evaporated, so that etching residue (etch residue occurring in dry etching) occurs. Here, the dry etching is not limited to the above-described method, and a method conventionally used by those skilled in the art can be used (refer to "Dry etching for VLSI", by AJ van Roosmalen et al., 1791 Plenum Press New York. , put its contents here for reference). 〇 The present invention is not limited to the method of the dry etching treatment or the apparatus used for the dry etching treatment. For example, a dry etching process which is widely used as shown in Fig. 7 can be used for the usual dry etching process. In the embodiment to be described later, the ICP (Inductively Coupled Plasma) type dry etching apparatus shown in Fig. 7 is used. Hereinafter, a typical dry etching process using the dry etching apparatus of Fig. 7 will be described, but the invention is not limited thereto. In the apparatus of Fig. 7, a dielectric window 62' is attached to the upper portion of the chamber 61. A 1-turn antenna 63 is placed on the dielectric window 62. The plasma generation of Fig. 7 -15- 201030819 The device is called a so-called TCP (Transfer Coupled Plasma) of the flat type. The antenna 63 is introduced into the high frequency power 64 of 13.56 MHz through the integrator 65. The chamber 61 has a process gas introduction port 66, thereby introducing an etching gas containing a halogen gas such as Cl2. The substrate (etched material) 67 is placed on the susceptor 68. The susceptor 68 is formed as an electrostatic chuck 69 which can be chucked by an electrostatic force by electric charge flowing from the glory to the substrate. A member called a collar 70 of quartz glass is placed around the periphery of the susceptor 68. The halogen gas system introduced into the chamber 61 is formed into an excited state and plasmad by a dielectric magnetic field generated by applying high frequency power to the antenna 63 located on the dielectric window 62. Further, the susceptor 68 is introduced into the high-frequency power 72 of 70 kHz through the integrator 71, and a high-frequency bias is applied to the substrate (the uranium-engraved material) 67 placed on the susceptor 68. By the high-frequency bias, ions in the plasma are pulled into the substrate in an anisotropic manner, and anisotropic etching such as vertical etching can be performed. The etching gas (process gas) used in the dry etching process is typically exemplified by a halogen gas, a boride of a halogen gas, and a mixed gas of a rare gas. The composition of the mixed gas is not limited thereto, and for example, hydrogen bromide or carbon tetrafluoride may be additionally added. Although the flow rate ratio of the mixed gas is not particularly limited, when a mixed gas of, for example, Ar and Cl2 and BC13 is used, it is preferably adjusted in the vicinity of Ar: Cl2: BCl3 = 300 sccm: 120 sccm: 60 sccm. After the etching, in order to prevent the reaction product of the resist or the wiring pattern attached to the A1 alloy film from reacting with the moisture in the air, hydrochloric acid (-16-201030819 HC1) is generated to corrode the back end of the A1 alloy film (after Corrosion), in the case where the atmosphere in the chamber is not opened, it is preferable to perform the resist removal by oxygen ashing (ash) under vacuum. After that, the atmosphere in the chamber is opened, but it is preferable to wash it with pure water or the like after the atmosphere is opened. In the present invention, the dry etching can be used in the etching of the A1 alloy film or the Si semiconductor layer and in the entire process of forming the contact holes, whereby the φ productivity is remarkably improved. The A1 alloy film of the present invention is preferably formed by using a sputtering target (hereinafter sometimes referred to as "target") by a sputtering method. This is based on a film formed by an ion plating method, an electron beam evaporation method, or a vacuum vapor deposition method, and it is easy to form a film having a uniform surface uniformity of a component or a film thickness. Further, when the above-described sputtering method is used to form the A1 alloy film of the present invention, it is preferable to use the same composition as the A1 alloy film of the present invention as the above-mentioned target (for the A1-Xb X2 alloy, the residue: A1 and an unavoidable impurity, preferably a above-mentioned A1-X1-X2-rare-earth element alloy containing a rare earth element, a residue: A1 and an unavoidable impurity), thereby obtaining a substance The A1 alloy film satisfies the desired composition. The shape of the target includes any shape (angular plate shape, circular plate shape, donut plate shape, etc.) which is processed in accordance with the shape or structure of the sputtering apparatus. In the method for producing the above-mentioned target material, a method of producing an ingot of -17-201030819 composed of an A1-based alloy by a melt casting method, a powder sintering method, or a spray molding method, or a method of manufacturing the product by A1 is exemplified. A preform made of a base alloy (preform 'the intermediate before the final dense body is obtained), and then the preform is densified by a densification means. The present invention also includes a TFT substrate including the above A1 alloy film or a display device including the TFT substrate. Specifically, a display device in which the A1 alloy film is used for a source electrode and/or a drain electrode of a TFT and a signal line, and a display device in which a drain electrode and a transparent conductive film are directly connected are listed; The above A1 alloy film is used for a display device such as a gate electrode and a scanning line. Here, the gate electrode and the scanning line, and the source electrode and/or the drain electrode and the signal line are preferably of the same composition. As described above, the present invention is characterized in that it has a good dry etching property and a composition of an Al alloy film which can be patterned by dry etching, and a TFT substrate or a display device other than the A1 alloy film. The requirements are not particularly limited, and even in the present invention, ordinary users in such fields can be employed. © For example, a polycrystalline germanium or an amorphous germanium is used for the semiconductor layer used for the TFT substrate. Further, examples of the transparent conductive film (transparent pixel electrode) used for the TFT substrate include indium tin oxide (ITO) or indium zinc oxide (IZO). The substrate used for the TFT substrate is also not particularly limited, and examples thereof include a glass substrate or a tantalum substrate. Next, a method of manufacturing the above TFT substrate will be described. The manufacturing method of the present invention is a method for manufacturing a thin film transistor substrate having a semiconductor layer of a thin film transistor and a semiconductor film directly connected to the semiconductor layer of the thin film transistor -18-201030819 on the substrate of the display device 'Characteristics include: a photolithography method using halftone exposure' in the foregoing. The A1 alloy film is formed into a resist pattern; and the semiconductor layer formed on the channel region by dry etching 'the aforementioned A1 The alloy film is simultaneously removed to form a contact hole. According to the present invention, since an A1 alloy film excellent in dry etching property is used, the manufacturing process of a TFT substrate using halftone exposure can be remarkably shortened. The details are described below using the embodiments of the present invention and the related embodiments. However, in the case of patterning a TFT channel portion using a halftone mask, in the conventional example, it is necessary to have two wet etchings, 2 In the first embodiment of the present invention, as described in the first embodiment of the present invention to be described later, it is preferable to use one-time dry etching and one dry etching. Alternatively, as shown in the second embodiment of the present invention, which will be described later, when the A1 alloy film is patterned, dry etching is performed instead of the wet uranium engraving, and only dry etching may be performed twice. Further, even if the manufacturing process is shortened as described above, the channel region Φ region having high shape accuracy can be obtained (see the channel region sectional view of Fig. 6 which will be described later). In the following, a preferred embodiment of the method for manufacturing a TFT substrate of the present invention which is exposed by halftone will be described with reference to the drawings. The following 'in terms of amorphous ruthenium film, the representative list has an undoped amorphous sand film with undoped P (phosphorus) [intrinsic layer" in the figure is a-Si(i) It is described that the TFT substrate doped with the p-doped amorphous germanium film is described, but the present invention is not limited thereto. For example, a polycrystalline germanium film may be used instead of the above-described flat crystal germanium film. Further, although an ιτο film is used as the transparent pixel electrode, an IZ〇-19-201030819 film (InOx-ZnOx-based conductive oxide film) can also be used. In addition, the A1 alloy film used in the present invention has been experimentally confirmed not only for a liquid crystal display device but also for a reflective electrode such as a reflective liquid crystal display device or a connector (TAB) for external signal input and output. The connection electrode can also be applied. (Conventional Embodiment) First, a preferred embodiment of the conventional method will be described with reference to the drawings of Figs. 2A to 2K. Here, a laminated film (a total thickness of about 400 nm) in which a Mo film having a thickness of about 50 nm and a pure A1 having a thickness of about 300 nm and a Mo film having a thickness of about 50 nm (total thickness: about 400 nm) are laminated is used as a source-drain electrode and a gate electrode. Wiring material used. First, a laminated film having a thickness of about 400 nm is formed on a glass substrate (transparent substrate) by a sputtering method. The film formation temperature of the sputtering is about 100 °C. The laminated film is patterned by wet etching using a first mask to form a gate electrode and a scanning line (see Fig. 2A). At this time, in order to improve the coverage of the gate insulating film, it is preferable to etch the peripheral edge of the laminated film to a tapered shape of about 30 to 40. Next, a gate insulating film (see Fig. 2B) is formed by a tantalum nitride film (SiNx) having a thickness of about 300 nm, for example, by a plasma CVD method or the like. The film formation temperature of the plasma CVD method is about 280 °C. Next, for example, a method of plasma CVD is used to sequentially form a hydrogenated amorphous germanium film having a thickness of about 5 nm on the gate insulating film [a-Si(i) in the drawing], and doped phosphorus. (P) an n + -type hydrogenated 201030819 amorphous germanium film having a thickness of about 5 〇 nm [a-Si (n+) in the figure], and then layering the above layer having a thickness of about 300 nm continuously using a sputtering method thereon Film accumulation (see Figure 2C). - The film formation temperature of the sputtering is about 10 (TC. Next, after halftone exposure (refer to FIG. 2D) using a halftone mask (. 2nd mask), the source is included by wet etching The region of the pole/drain electrode is patterned in an island shape (see FIG. 2E). The details of the halftone exposure are not particularly limited in the present invention, and φ can be used by those skilled in the art. Method (refer to: US Patent 7, 259, 045 B2, the contents of which are hereby incorporated by reference), in which a portion of a halftone mask is removed by halftone exposure (in part 2E, part A, equivalent to half) The transmissive portion in the color tone exposure has a resist remaining, and thus is not patterned by wet etching. ' Further, as shown in FIG. 2F, the hydrogenated amorphous germanium film [a-Si] is dry-etched. (i)] and a portion of the n + -type hydrogenated amorphous germanium film [a-Si(n + )] doped with phosphorus is removed, whereby an a-Si island is formed on the gate insulating film. Ashing, as shown in Figure 2G, the resist is reduced, and the residual resist on the channel area is removed. The resist is a mask, and after removing the laminated film on the channel region by wet etching (Fig. 2H), the phosphorus-doped n + -type hydrogenated amorphous germanium on the channel region is removed by dry etching. Film [a-Si(n+)] (Fig. 21). Thus, only the hydrogenated amorphous ruthenium film U-Si(i) is left in the channel region. Then, for example, an electric paddle CVD apparatus or the like is used to form a film. A tantalum nitride film having a thickness of about 300 nm is formed to form a protective film. The film formation temperature at this time is, for example, about 250 ° C. Then, the photoresist layer 21 - 201030819 is formed on the tantalum nitride film, and then used. 3 Masking the tantalum nitride film by forming a contact hole in a tantalum nitride film by, for example, dry etching (see FIG. 2J). At the same time, 'TAB (on the gate electrode corresponding to the end of the panel) A contact hole (not shown) is formed in the connected portion of the joint. Next, the photoresist layer is peeled off using, for example, an amine-based stripping liquid, for example, by ashing by oxygen plasma. For example, in the range of time (about 8 hours), an ITO film having a thickness of about 40 nm is formed, and a fourth photomask is used. Patterning is performed by wet etching (refer to FIG. 2K), thereby forming a transparent pixel electrode (IT film). If it is simultaneously connected to the TAB of the gate electrode of the panel end, in order to be bonded to the TAB. The ITO film is patterned to complete the TFT substrate (not shown). As described above, in the conventional embodiment using the above-mentioned laminated film having a barrier layer, it is necessary to use a total of 2 wet etchings. In the first embodiment, the first embodiment of the present invention is as follows: (1) In the first embodiment of the present invention, the semiconductor layer and the A1 alloy film formed on the channel region are removed by one-time oxygen ashing and one-time dry etching. The drawings of Fig. 3H illustrate a preferred embodiment of the present invention. In the present embodiment, an A1-0.2 atomic % C 〇 -0.5 atomic % Ge-0.2 atomic % La alloy film having a thickness of about 200 nm is used as a wiring material for the source-electrode electrode and the gate electrode. In this regard, it is quite different from the conventional example described above. The above-mentioned A1 alloy film is excellent in dry etching property (see the example described later), and therefore, in the present embodiment, the semiconductor layer formed on the channel region and the -Al alloy film can be continuously removed simultaneously by dry etching. Compared with the conventional example described above, the manufacturing process can be particularly shortened. On the other hand, the A1 laminated film containing the high melting point metal (barrier layer) of Mo used in the above-described embodiment has a very low dry etching rate, and therefore, if the laminated film is to be removed by dry etching, During this time, the resist will be completely eliminated, so that even the parts that should not be removed are removed. In addition to this φ, the amorphous ruthenium film has a very high dry etch rate, so if the laminated film is to be removed by dry etching, the hydrogenated amorphous ruthenium film [a-Si(i)] on the non-channel region is removed. Thereafter, the tantalum nitride film underneath is excessively etched. As a result, a TFT having high shape accuracy cannot be obtained. First, the third to third embodiments are the same as the second to second embodiments, and the description thereof is omitted. Next, halftone exposure (see FIG. 3D) is performed using a halftone mask (second mask), and then the region including the source/drain electrodes is patterned in an island shape by wet etching. (see Figure 3E). Among them, a portion of the halftone mask which is removed by halftone exposure has a resist remaining, and thus is not patterned by wet etching. Further, as shown in FIG. 3F, the portion (residual resist portion) from which one half of the halftone mask is removed by halftone exposure is removed by dry etching, and the hydrogenated amorphous germanium film is removed [a-Si (i )] and the phosphorus-doped n+ type hydrogenated amorphous ruthenium film [a-Si (n+)], while continuously removing the A1 alloy film formed on the channel region and the n + -type hydrogenated amorphous ruthenium film [a-Si (n+) )]. As described above, according to the present embodiment, the -23-201030819 A1 alloy film formed on the channel region and the n + -type hydrogenated amorphous ruthenium film [a-Si ( n+ )] underlying the channel region are collectively removed. Thereby, only the hydrogenated amorphous ruthenium film [a-Si(i)] remains in the channel region. Therefore, by using the present embodiment of the A1 alloy film of the present invention, the semiconductor layer and the Al alloy film formed on the channel region can be removed by one wet etching and one dry etching, in accordance with a conventional example. Compared to the manufacturing process. Next, the TFT substrate is completed through the processes of the 3G and 3GH. These engineering systems are the same as the above-described 2J and 2K drawings, and therefore, the description thereof will be omitted. The TFT substrate-based drain electrode fabricated as described above is in direct contact with the transparent pixel electrode, and the gate electrode and the ITO film for TAB connection are also in direct contact. (Embodiment 2 of the present invention) This embodiment is an improved embodiment of the first embodiment of the present invention, and is the same as the embodiment H1 except that only the work of Fig. 3E is different. Therefore, the illustration of the embodiment is omitted, and only the different items will be described below. In the present embodiment, in the third embodiment of the first embodiment, the wet etching is replaced by dry etching, and the region including the source/drain electrodes is patterned in an island shape. As described above, the dry etching property of the A1 alloy film of the present invention is extremely excellent, and therefore the dry etching can be used for the work. Here, if the process is performed by dry etching, a portion of the halftone mask removed by halftone exposure (the portion of the residue -24-201030819 retention agent) can also be patterned by dry etching. Therefore, according to the present embodiment, the semiconductor layer formed on the channel region and the Al alloy film can be removed by dry etching twice, and the manufacturing process can be shortened as compared with the conventional example. [Examples] The present invention will be more specifically described by the following examples, but the present invention is not limited by the following examples, and may be practiced with the modifications described above, which are included in the scope of the following. Within the technical scope of the present invention. In the following, "Atom %" is simply referred to as "%". (Example 1) In the present embodiment, Al-x%Co-0.5%Ge-0.2%La in which the amount of Co was changed in the range of 0 to 1.2%, and the amount of Ge in the range of 0 to 1.2% were used. The Al-0.2%Co-x%Ge-0.2°/〇La was changed within the ® as the A1 alloy film, and the dry etching characteristics were evaluated. For the comparison, pure A1 was used for the same experiment. Specifically, on an alkali-free glass base plate having a diameter of 6 吋 and a thickness of 0.5 mm (manufactured by Corning Co., Ltd., #1 73 7 glass), cerium oxide (SiOx) having a thickness of 200 nm was formed at a substrate temperature of about 250 °C. After the film, a pure A1 film or each of the above A1 alloy films was formed under the following film forming conditions. Ambient gas = argon, pressure = 3 mTorr, thickness = 200 nm. Next, by the photolithography of the g-line, the positive photoresist (phenolic resin-25-201030819; TSMC8900 manufactured by Tokyo Chemical Industry Co., Ltd.) has a thickness of Ι.Ομιη) is formed into a strip shape having a line width of 2.0 μm. Next, dry etching was performed using the dry uranium etching apparatus shown in Fig. 7 described above under the following etching conditions. (etching conditions)

Ar/Cl2/BCl3 : 3 00sccm/120sccm/60sccm Power applied to the antenna (source RF): 500W

Substrate bias: 60W Process pressure (gas pressure): 14mT〇rr Substrate temperature: susceptor temperature (2(TC) (etch rate ratio) Thickness (etching thickness) of pure A1 film after etching and each A1 alloy film The measurement was performed, and the results were statistically processed by the least square method to calculate the etching rate (N2) of the pure A1 film and the etching rate (N 1 ) of each A1 alloy film, and the ratio of N 1 /N 2 was set to " In the present embodiment, the etching rate ratio is set to 8% or more. In the fourth drawing (a), the Al-x%Co-0.5%Ge-0.2%La alloy film is shown. The relationship between the amount of Co and the etching ratio, and the relationship between the amount of Ge in the A1-0.2% Co-x%Ge-0.2% La alloy film and the etching ratio is shown in Fig. 4(b). Each line of "90%" is for reference, and each line of 80% and 90% of the etching rate of pure A1 is drawn. As shown in the figures, it is understood that the amounts specified in the present invention are respectively included. -26- 201030819

Both the Co and Ge A1 alloy films are excellent in dry etching properties. (Presence or absence of residue after dry etching) In addition, an A1-0.2% Co-0.5% Ge-0.2% La alloy film satisfying the requirements of the present invention was used to investigate whether or not there was residue after dry etching. In the sample of the A1 alloy film, the surface of the glass substrate which was etched at a time required to be etched to the etching depth of the film thickness portion was observed at S EM φ (magnification: 3000 times). The diameter (corresponding to the diameter of the circle) is a residue of 〇.5 μηι or more. The SEM observation photograph thus obtained is shown in Fig. 5 (a) and (b). Fig. 5(a) is a photograph enlarged to 3000 times, and Fig. 5(b) is a photograph enlarged to 1000 times. As shown in the figures, if the above A1 alloy film was used, the residue after dry etching was not observed at all. Although not shown in the drawings, the same results as described above were obtained in the same manner for the other A1 alloy films satisfying the requirements of the present invention. Φ From the above results, it was confirmed that the use of the A1 alloy film satisfying the requirements of the present invention can provide a very high etching rate ratio, and the residue after dry etching is not observed, and the dry etching property is extremely excellent. For reference, FIG. 6 shows a cross-sectional shape in the vicinity of the channel region when the TFT substrate is fabricated by using the above-described A1-0.2% C〇-0.5% Ge-0.2% La alloy film according to the embodiment of the present invention. Electron micrograph (magnification 50,000 times). As shown in Fig. 6, it was confirmed that a TFT having a high shape accuracy can be obtained by using the A1 alloy film of the present invention. -27-201030819 (Example 2) In this example, an A1 alloy film of A丨-0.2% Co-0.5% Ge-0.2% La was used, and (1) A1 alloy film and semiconductor were respectively measured by the following methods. The contact resistance of the layer (amorphous germanium) and (2) the contact resistance between the A1 alloy film and the ITO film. (1) Contact resistance of A1 alloy film and semiconductor layer In order to investigate the contact resistance of the A1 alloy film and the semiconductor layer (amorphous germanium), according to the drawings of Fig. 8 (a) to (g), by the TLm method ( Transfer Length Method) to form the TLM component. First, the method of fabricating the TLM device will be described using Figs. 8(a) to 8(g). Next, the principle of measurement by the TLM method will be described using Figs. 9(a) and (b) and Fig. 10 . First, a low-resistance amorphous germanium film 1 doped with impurities (P) having a thickness of about 200 nm was formed on a glass substrate by a plasma CVD method at a film thickness of about 200 nm. Next, in the same plasma CVD apparatus, only nitrogen gas is supplied to generate plasma, and the surface of the low-resistance amorphous germanium film 1 is treated with nitrogen plasma for 30 seconds to form a nitrogen-containing layer (Fig. 8(a) ). The RF power density applied to the plasma was about 0.3 W/cm2. Then, the low-resistance amorphous germanium film 2 doped with impurities (P) is continuously formed again without being taken out by the CVD apparatus (Fig. 8(a)). The film thickness of the low-resistance amorphous germanium film 2 is l〇nm. An A1-based alloy film (A1-0.6 atom% Ni-0.5 atom% Cu-0.3 atom% La) having a film thickness of about 300 nm was formed thereon (Fig. 8(b)). After the resist is patterned by photolithography 201030819 (Fig. 8(c)), the A1 alloy is etched with the resist as a mask, thereby forming a plurality of electrodes as shown in Fig. 8(d) . Here, the distance between the electrodes is varied. Further, dry etching is performed again, and the resist is patterned by photolithography. At this time, all the electrode patterns were covered with a resist as shown in Fig. 8(e). This is used as a mask to remove the low-resistance amorphous germanium film on the outer peripheral portion of the electrode pattern (Fig. 8(f)). Finally, heat treatment was performed at 300 ° C for 30 minutes to form an Al-Si diffusion layer (Fig. 8 (g)). φ Next, the principle of measurement of the contact resistance by the TLM method will be described with reference to Figs. 9(a) and (b) and Fig. 1 . In Fig. 9, a cross-sectional view (Fig. 9(b)) and a top view (Fig. 9(a)) showing the wiring structure of Fig. 8(g) in a pattern are shown. Here, in the Fig. 9 (a) and (b), the Al-Si diffusion layer is omitted. * First, in the wiring structure of Fig. 8(g), the electrode-to-electrode distance (conversion length, L) is changed as shown in Fig. 9(b) to measure the current-voltage characteristics between the plurality of electrodes, and each electrode is obtained. The resistance 値 between (electrode-semiconductor layer θ electric φ pole). Here, the resistance 値 between the electrodes at a total of five points was obtained. When the resistance 値 (Ω) between the electrodes thus obtained is plotted on the vertical axis and the distance between electrodes (L, Mm) is plotted on the horizontal axis, the graph of Fig. 10 can be obtained. In the graph of Fig. 10, 値 of the y-intercept corresponds to 値(2Rc) which is twice the contact resistance Rc, and 値 of the X intercept corresponds to the effective contact length (LT: transfer length). Above, connect the 'contact resistivity P'. The following formula is expressed.

p c=Rc*Lt*Z -29- 201030819 In the above formula, the Z system shows the electrode width as shown in Fig. 9(a). As a result, the contact resistivity of the above A1 alloy film and the semiconductor layer was about 0.3 Ω · cm 2 . Therefore, it is understood that the contact resistance with the semiconductor layer can be suppressed to be extremely low by using the A1 alloy film of the present invention. (2) Contact resistance of A1 alloy film and ITO film The above-mentioned contact resistance was measured by the Kelvin pattern (contact hole size: ΙΟμπι square) shown in Fig. 1 and subjected to 4-terminal measurement. ΙΤΟ-Α1 alloy or ΙΖΟ-Α1 alloy flow current, other terminals to determine the voltage drop between ΙΤΟ-Α1 alloy or ΙΖΟ-Α1 alloy). Specifically, the current I is passed between 11 and 11 in Fig. 11, and the voltage V between V^V2 is monitored, whereby the contact resistance R of the connection portion C is obtained as [R = (Vi - Va) / 12]. As a result, the contact resistivity of the above A1 alloy film and the ITO film was 3. Οχ 1 〇 4 Ω / cm 2 or less. Therefore, it has been found that when the ruthenium alloy film of the present invention is used, the contact resistance with the ITO film is also suppressed to be extremely low. From the above results, it was confirmed that the contact resistance with the semiconductor layer and the contact resistance with the ITO film were also suppressed to be low when the A1 alloy film was used. Further, although not shown in the present embodiment, the same results as described above are similarly obtained for other A1 alloy films satisfying the requirements of the present invention, and the present application will be described in more detail with reference to specific embodiments, but Various changes or modifications can be made without departing from the spirit and scope of the invention, as will be apparent to those skilled in the art. -30- 201030819 This application is based on a patent application filed on Nov. 20, 2008 (Japanese Patent Application No. 2008-297203), the contents of which are hereby incorporated by reference. [Industrial Applicability] In the present invention, the A1 alloy film for wiring which is directly connected to the semiconductor layer of the TFT is used, and the A1 φ alloy film which is excellent in dry etching property is used, so that it can be simultaneously dried by dry etching. The semiconductor layer and the Al alloy film formed on the channel region of the TFT are removed to form a contact hole. Therefore, when the A1 alloy film of the present invention is used, a display device which is excellent in productivity, low in cost, and high in performance can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional thin film transistor substrate. Fig. 2A is an explanatory view showing an example of a manufacturing process of the TFT substrate Φ of the conventional embodiment in order. Fig. 2B is an explanatory view showing an example of a manufacturing process of a TFT substrate of a conventional embodiment in order. Fig. 2C is an explanatory view showing an example of a manufacturing process of a TFT substrate of a conventional embodiment in order. Fig. 2D is an explanatory view showing an example of a manufacturing process of a TFT substrate of a conventional embodiment in order. Fig. 2E is an explanatory view showing an example of a manufacturing process of a TFT substrate of a conventional embodiment in order. -31 - 201030819 FIG. 2F is an explanatory view showing an example of a manufacturing process of a TFT substrate of a conventional embodiment in order. Fig. 2G is an explanatory view showing an example of a manufacturing process of a TFT substrate according to a conventional embodiment. Fig. 2H is an explanatory view showing an example of a manufacturing process of a TFT substrate of a conventional embodiment in order. Fig. 21 is an explanatory view showing an example of a manufacturing process of a TFT substrate of a conventional embodiment in order. φ 2J is an explanatory view showing an example of a manufacturing process of a TFT substrate of a conventional embodiment in order. Fig. 2K is an explanatory view showing an example of a manufacturing process of a TFT substrate of a conventional embodiment in order. Fig. 3A is an explanatory view showing an example of a manufacturing process of a TFT substrate-board according to an embodiment of the present invention in order. Fig. 3B is an explanatory view showing an example of a manufacturing process of a TFT substrate according to an embodiment of the present invention in order. @3C is an explanatory view showing an example of a manufacturing process of a TFT substrate according to an embodiment of the present invention in order. Fig. 3D is an explanatory view showing an example of a manufacturing process of a TFT substrate according to an embodiment of the present invention in order. Fig. 3E is an explanatory view showing an example of a manufacturing process of a TFT substrate according to an embodiment of the present invention in order. Fig. 3F is an explanatory view showing an example of a manufacturing process of a TFT substrate according to an embodiment of the present invention in order. -32-201030819 Fig. 3G is an explanatory view showing an example of a manufacturing process of a TFT substrate according to an embodiment of the present invention in order. Fig. 3 is an explanatory view showing an example of a manufacturing process of a TFT substrate according to an embodiment of the present invention in order. Fig. 4(a) is a graph showing the relationship between the amount of Co and the etching ratio in the A1 alloy film used in the examples, and Fig. 4(b) shows the A1 alloy film used in the examples. The relationship between the amount of Ge in the medium and the ratio of the etching rate is added by φ to the graph. Fig. 5(a) shows an SEM observation photograph of the A1 alloy film used in the examples, a magnification of 3 000 times the surface state of the glass substrate after dry etching, and Fig. 5(b) shows the use of the examples for the examples. A1 alloy film, SEM' observation photograph of the surface state of the glass substrate after dry etching at a magnification of 1,000,000 times. Fig. 6 is an electron micrograph showing the cross-sectional shape in the vicinity of the channel region of the TFT substrate obtained in the examples. φ Fig. 7 is a schematic view of the apparatus for dry etching used in the examples. Fig. 8 (a) to (g) show the engineering drawings of the TLM element for investigating the contact resistance of the A1 alloy film and the semiconductor layer (amorphous germanium). Fig. 9 (a) and (b) are diagrams showing the principle of measurement of contact resistance by a TLM element, and Fig. 9 (a) is a top view of a mode display wiring structure [Fig. 9 (b) A cross-sectional view showing the wiring structure in a mode. Figure 10 is a graph showing the relationship between the distance between electrodes and the resistance. -33- 201030819 Fig. 11 is a view showing a Kjeldahl pattern (TEG pattern) used for measurement of the contact resistivity (connection resistivity) between the A1 alloy film and the transparent conductive film. [Description of main component symbols] 1 : Glass substrate 2 : Rattle electrode 2a : Gate pad _ 3 : Gate insulating film 4 : Semiconductor 矽 layer 5 : Dip electrode 6 : Source electrode 7 : Transparent conductive film (transparent pixel Electrode) - 8 : Source connector (TAB) 9 : Gate connector (TAB) 10 : Protective insulation layer @ 1 1 : Barrier metal layer 61 : Chamber 62 : Dielectric window 6 3 : Antenna 64 : High frequency power (Antenna Side) 65: Integrator (antenna side) _ 66 : Process gas inlet 6 7 : Substrate (etched material) -34- 201030819 68 : Base 69 : Media chuck 70 : Collar 71 : Integrator (substrate side) 72 : High frequency power (substrate side)

Claims (1)

201030819 VII. Patent application: 1. An aluminum alloy film for a display device, which is an aluminum alloy film for a display device directly connected to a semiconductor layer of a thin film transistor on a substrate of a display device, and is characterized in that: the aluminum alloy film And at least one selected from the group consisting of Co, Ni, and Ag, and at least one of 0.2 to 1.0 at% of Ge and Cu, and patterned by dry etching. By. 2. The aluminum alloy film for a display device according to the first aspect of the invention, wherein the film further contains at least one of 0.05 to 0.3 atomic % of a rare earth element. 3. The aluminum alloy film for a display device according to claim 1, wherein the aluminum alloy film is directly connected to the transparent conductive film. 4. The aluminum alloy film for a display device according to claim 2, wherein the aluminum alloy film is directly connected to the transparent conductive film. A thin film transistor substrate characterized by having an aluminum alloy film for a display device according to any one of the first to fourth aspects of the invention. 6. A display device comprising: a thin film transistor substrate having the fifth application of the patent application. 7. A method of manufacturing a thin film transistor substrate, comprising: a semiconductor layer having a thin film transistor; and a thin film transistor substrate having an aluminum alloy film directly connected to the semiconductor layer of the thin film transistor, on a substrate of the display device The manufacturing method is characterized in that: the aluminum alloy film contains 0.05 to 0.5 at% of at least one selected from the group consisting of Co, Ni, and Ag, and at least 1 of 0.2 to 1.0% by atom of Ge and Cu. , -36- 201030819 includes: a photolithography method using halftone exposure 'in the foregoing aluminum alloy film shape. The process of forming a resist pattern; and the above semiconductor layer to be formed on the channel region by dry etching And the above-mentioned aluminum alloy film is simultaneously removed to form a contact hole. 8. The method of producing a thin film transistor substrate according to claim 7, wherein the aluminum alloy film further contains at least one of rare earth elements of 5 to 0.3 atom%. -37-