TWI504765B - Cu alloy film, and a display device or an electronic device provided therewith - Google Patents
Cu alloy film, and a display device or an electronic device provided therewith Download PDFInfo
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
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- C22C9/00—Alloys based on copper
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- C—CHEMISTRY; METALLURGY
- C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
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- C22C9/00—Alloys based on copper
- C22C9/05—Alloys based on copper with manganese as the next major constituent
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- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
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- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/14—Metallic material, boron or silicon
- C23C14/16—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon
- C23C14/165—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon by cathodic sputtering
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- H—ELECTRICITY
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
Description
本發明係關於在基板上與基板及/或絕緣膜直接接觸的Cu合金膜。本發明之Cu合金膜係適於被使用為例如液晶顯示器、有機EL顯示器等平面顯示裝置；ULSI(超大規模積體電路)、ASIC(Application Specific Integrated Circuit，特定應用積體電路)、二極體、薄膜電晶體、薄膜電晶體基板等電子裝置等所被使用的配線材料及電極材料。以下具代表性提出液晶顯示裝置來作說明，惟並非為限定於此的要旨。The present invention relates to a Cu alloy film that is in direct contact with a substrate and/or an insulating film on a substrate. The Cu alloy film of the present invention is suitably used as a flat display device such as a liquid crystal display or an organic EL display; ULSI (Ultra Large Integrated Circuit), ASIC (Application Specific Integrated Circuit), and a diode A wiring material and an electrode material used for an electronic device such as a thin film transistor or a thin film transistor substrate. Hereinafter, a liquid crystal display device will be described as a representative, but it is not limited thereto.
由小型的行動電話，至超過30吋的大型電視等在各領域中所被使用的液晶顯示裝置係由以下所構成：將薄膜電晶體(以下稱為「TFT」)作為切換元件，構成像素電極的透明導電膜(氧化物導電膜)；閘極配線及源極-汲極配線等配線部；具備有非晶矽(a-Si)或多晶矽(p-Si)等Si半導體層的TFT基板；具備有對TFT基板隔著預定間隔而相對向配置的共通電極的對向基板；及被填充在TFT基板與對向基板之間的液晶層。A liquid crystal display device used in various fields, such as a small mobile phone and a large TV of more than 30 inches, is composed of a thin film transistor (hereinafter referred to as "TFT") as a switching element, and constitutes a pixel electrode. a transparent conductive film (oxide conductive film); a wiring portion such as a gate wiring and a source-drain wiring; and a TFT substrate including a Si semiconductor layer such as amorphous germanium (a-Si) or polycrystalline germanium (p-Si); An opposite substrate having a common electrode that faces the TFT substrate with a predetermined interval therebetween; and a liquid crystal layer that is filled between the TFT substrate and the counter substrate.
在液晶顯示器所代表的顯示裝置的配線，至今係使用一種鋁(Al)合金膜。但是隨著顯示裝置的大型化及高畫質化的進展，因配線電阻較大而起的訊號延遲及電力損失等問題逐漸明顯化。因此，以配線材料而言，比Al為更低 電阻的銅(Cu)備受矚目。Al的電阻率為2.5×10-6 Ω．cm，相對於此，Cu的電阻率較低，為1.6×10-6 Ω．cm。In the wiring of a display device represented by a liquid crystal display, an aluminum (Al) alloy film has hitherto been used. However, as the size of the display device has increased and the image quality has progressed, problems such as signal delay and power loss due to large wiring resistance have become apparent. Therefore, copper (Cu) which is lower in resistance than Al is attracting attention in terms of wiring materials. The resistivity of Al is 2.5×10 -6 Ω. Cm, in contrast, Cu has a low resistivity of 1.6 × 10 -6 Ω. Cm.
但是，Cu與玻璃基板的密接性低而會有剝離的問題。而且，由於與玻璃基板的密接性低，因此Cu會有難以進行用以加工成配線形狀的濕式蝕刻的問題。因此，用以使Cu與玻璃基板的密接性提升的各種技術已被提出。However, the adhesion between Cu and the glass substrate is low and there is a problem of peeling. Further, since the adhesion to the glass substrate is low, there is a problem that it is difficult to perform wet etching for processing into a wiring shape. Therefore, various techniques for improving the adhesion between Cu and a glass substrate have been proposed.
例如專利文獻1~3係揭示一種在Cu配線與玻璃基板之間介在鉬(Mo)或鉻(Cr)等高熔點金屬層而達成密接性提升的技術。但是在該等技術中，將高熔點金屬層進行成膜的工程會增加，顯示裝置的製造成本會增大。此外，由於使Cu與高熔點金屬(Mo等)的異種金屬相層積，因此在濕式蝕刻時，會有在Cu與高熔點金屬的界面發生腐蝕之虞。而且，在該等異種金屬中，會在蝕刻率產生差異，因此會產生無法將配線剖面形成為所期望的形狀(例如錐角為45~60°左右的形狀)的問題。此外，高熔點金屬，例如Cr的電阻率(12.9×10-6 Ω．cm)比Cu高，因配線電阻所造成的訊號延遲或電力損失會形成問題。For example, Patent Literatures 1 to 3 disclose a technique in which a high melting point metal layer such as molybdenum (Mo) or chromium (Cr) is interposed between a Cu wiring and a glass substrate to achieve adhesion improvement. However, in such techniques, the process of forming a high-melting-point metal layer into a film increases, and the manufacturing cost of the display device increases. Further, since Cu is laminated with a dissimilar metal of a high melting point metal (Mo or the like), corrosion may occur at the interface between Cu and a high melting point metal during wet etching. Further, in such dissimilar metals, a difference in etching rate occurs, and thus there is a problem in that the wiring cross section cannot be formed into a desired shape (for example, a taper angle of about 45 to 60°). Further, the resistivity (12.9 × 10 -6 Ω·cm) of the high melting point metal such as Cr is higher than that of Cu, and signal delay or power loss due to the wiring resistance may cause a problem.
專利文獻4係揭示一種在Cu配線與玻璃基板之間，介在鎳或鎳合金與高分子系樹脂膜作為密接層的技術。但是，在該技術中，在顯示器(例如液晶面板)製造時的高溫退火工程中，會有樹脂膜劣化、密接性降低之虞。Patent Document 4 discloses a technique in which a nickel or a nickel alloy and a polymer resin film are used as an adhesion layer between a Cu wiring and a glass substrate. However, in this technique, in the high-temperature annealing process at the time of manufacture of a display (for example, a liquid crystal panel), the resin film may deteriorate and the adhesiveness may fall.
專利文獻5係揭示一種在Cu配線與玻璃基板之間，介在氮化銅作為密接層的技術。但是，氮化銅本身若接受高溫的熱履歷時會分解，因此在該技術中，若顯示器(例 如液晶面板)製造時的退火工程成為高溫時，會有密接性降低之虞。Patent Document 5 discloses a technique in which a copper nitride is used as an adhesion layer between a Cu wiring and a glass substrate. However, since copper nitride itself decomposes when it receives a high-temperature heat history, in this technique, if a display (for example) When the annealing process at the time of manufacture of a liquid crystal panel becomes a high temperature, the adhesiveness will fall.
另一方面，在專利文獻6係揭示一種含有Mn的Cu合金配線材料。在專利文獻6中係記載藉由嚴謹控制成膜氣體環境(含氧量100ppm的Ar氣體環境)，使得以抑制Cu氧化的Mn氧化物被膜形成在表面或界面，藉此可達成密接性提升與電阻率低減化的要旨。On the other hand, Patent Document 6 discloses a Cu alloy wiring material containing Mn. Patent Document 6 describes that by strictly controlling the film formation gas atmosphere (Ar gas atmosphere having an oxygen content of 100 ppm), the Mn oxide film which suppresses Cu oxidation is formed on the surface or the interface, whereby adhesion improvement and adhesion can be achieved. The purpose of reducing the resistivity is low.
[先前技術文獻][Previous Technical Literature]
[專利文獻][Patent Literature]
[專利文獻1]日本特開平7-66423號公報[Patent Document 1] Japanese Patent Laid-Open No. Hei 7-66423
[專利文獻2]日本特開平8-8498號公報[Patent Document 2] Japanese Patent Laid-Open No. Hei 8-8498
[專利文獻3]日本特開平8-138461號公報[Patent Document 3] Japanese Patent Laid-Open No. Hei 8-138461
[專利文獻4]日本特開平10-186389號公報[Patent Document 4] Japanese Patent Laid-Open No. Hei 10-186389
[專利文獻5]日本特開平10-133597號公報[Patent Document 5] Japanese Patent Laid-Open No. Hei 10-133597
[專利文獻6]國際公開第2006/025347號小冊[Patent Document 6] International Publication No. 2006/025347
但是，在專利文獻6中，使得成膜條件非常嚴謹來形成所希望的氧化被膜，極為缺乏實用性。此外，在專利文獻6所記載的配線材料中，熱處理後的電阻率未充分降低，使用該配線材料的液晶顯示裝置會擔負發熱或消耗電力高的問題。尤其，液晶顯示裝置等在其製造過程中被曝露在約250℃以上的熱履歷(例如SiO2 膜等絕緣膜成膜時或 成膜後的熱處理等)，上述熱履歷(熱處理)後，強烈切盼低電阻率的配線材料。However, in Patent Document 6, the film formation conditions are very strict to form a desired oxide film, which is extremely ineffective. Further, in the wiring material described in Patent Document 6, the resistivity after the heat treatment is not sufficiently lowered, and the liquid crystal display device using the wiring material has a problem of high heat generation or high power consumption. In particular, a liquid crystal display device or the like is exposed to a heat history of about 250 ° C or higher during the manufacturing process (for example, when an insulating film such as a SiO 2 film is formed, or after heat treatment after film formation), after the heat history (heat treatment), it is strong. Look forward to low resistivity wiring materials.
本發明係著重在上述情形而研創者，其目的在提供一種具有與基板及/或絕緣膜的高密接性，而且在液晶顯示裝置等的製造過程中所被施行的熱處理之後，亦具有低電阻率的新穎的Cu合金膜。The present invention has been made in view of the above circumstances, and an object thereof is to provide a high electrical resistance to a substrate and/or an insulating film, and also has a low electrical resistance after heat treatment performed in a manufacturing process of a liquid crystal display device or the like. The rate of the novel Cu alloy film.
本發明係提供以下之Cu合金膜、顯示裝置及電子裝置。The present invention provides the following Cu alloy film, display device, and electronic device.
(1)一種Cu合金膜，其係在基板上與基板及/或絕緣膜直接接觸的Cu合金膜，其特徵為：前述Cu合金膜係由層積構造所構成，該層積構造係由基板側依序包含：含有選自由Ag、Au、C、W、Ca、Mg、Al、Sn、B及Ni所成群組的至少一種元素X作為合金成分的Cu-Mn-X合金層(第一層)；及由純Cu、或以Cu為主成分的Cu合金且為電阻率低於前述第一層的Cu合金所成的層(第二層)。(1) A Cu alloy film which is a Cu alloy film which is in direct contact with a substrate and/or an insulating film on a substrate, wherein the Cu alloy film is composed of a laminated structure, and the laminated structure is a substrate. The side sequence includes: a Cu-Mn-X alloy layer containing at least one element X selected from the group consisting of Ag, Au, C, W, Ca, Mg, Al, Sn, B, and Ni as an alloy component (first And a layer of Cu alloy composed of pure Cu or Cu as a main component and having a lower resistivity than the first layer of Cu alloy (second layer).
(2)如(1)所記載之Cu合金膜，其中，前述第一層中的Mn含量為1.0~20原子%。(2) The Cu alloy film according to (1), wherein the Mn content in the first layer is 1.0 to 20 atom%.
(3)如(1)或(2)所記載之Cu合金膜，其中，前述第一層中的X元素的合計量為0.2~10原子%。(3) The Cu alloy film according to (1) or (2), wherein the total amount of the X elements in the first layer is 0.2 to 10 atom%.
(4)如(1)至(3)中任一者所記載之Cu合金膜，其中，前述第一層的膜厚為5~100nm。The Cu alloy film according to any one of (1) to (3) wherein the first layer has a film thickness of 5 to 100 nm.
(5)如(1)至(4)中任一者所記載之Cu合金膜，其中， 前述第二層的膜厚為100nm以上。(5) The Cu alloy film according to any one of (1) to (4), wherein The film thickness of the second layer is 100 nm or more.
(6)一種顯示裝置，其係具備有：基板及/或絕緣膜；及如(1)至(5)中任一者所記載之Cu合金膜，前述基板及/或前述絕緣膜、與前述Cu合金膜係直接連接。(6) A display device comprising: a substrate and/or an insulating film; and the Cu alloy film according to any one of (1) to (5), the substrate and/or the insulating film, and the foregoing The Cu alloy film is directly connected.
(7)如(6)所記載之顯示裝置，其中，前述絕緣膜係由SiO2 、SiON、或SiN所構成。(7) The display device according to (6), wherein the insulating film is made of SiO 2 , SiON, or SiN.
(8)一種電子裝置，其係具備有：基板及/或絕緣膜；及如(1)至(5)中任一者所記載之Cu合金膜，前述基板及/或前述絕緣膜、與前述Cu合金膜係直接連接。(8) An electronic device comprising: a substrate and/or an insulating film; and the Cu alloy film according to any one of (1) to (5), the substrate and/or the insulating film, and the The Cu alloy film is directly connected.
(9)如(8)所記載之電子裝置，其中，前述絕緣膜係由SiO2 、SiON、或SiN所構成。(9) The electronic device according to (8), wherein the insulating film is made of SiO 2 , SiON, or SiN.
藉由本發明，可提供一種即使與基板及/或絕緣膜直接連接，亦為與該等之密接性優異的顯示裝置用或電子裝置用的Cu合金膜。此外，藉由本發明，可提供一種即使未施行特別的熱處理，亦可在顯示裝置或電子裝置等之製造過程中的熱履歷後實現屬於Cu系材料之特徵的低電阻率的Cu合金膜。According to the present invention, it is possible to provide a Cu alloy film for a display device or an electronic device which is excellent in adhesion to the substrate and/or the insulating film. Further, according to the present invention, it is possible to provide a low-resistivity Cu alloy film which is characterized by a Cu-based material after the heat history in the manufacturing process of a display device or an electronic device, without performing a special heat treatment.
本發明人等為了提供一種即使省略Ti或Mo等高熔點金屬(障壁金屬層)而將Cu合金膜與基板及/或絕緣膜直接作電性連接，亦為與該等的密接性優異，而且膜本身的電 阻率低，而且在顯示裝置等之製造過程中的熱履歷之後亦可使電阻率未上升而維持低電阻率，而且具有加工性優異的特性的新穎的Cu合金膜，而不斷研究。結果發現若使用以包含：在Cu-Mn合金添加選自由Ag、Au、C、W、Ca、Mg、Al、Sn、B及Ni所成群組的至少一種元素(以下有時稱為X或X元素)的Cu-Mn-X合金(第一層)、及由純Cu、或以Cu為主成分的Cu合金且電阻率低於第一層的Cu合金所成的第二層的層積構造所構成的Cu合金膜，即達成所預期的目的，而完成本發明。In order to provide a high-melting-point metal (barrier metal layer) such as Ti or Mo, the inventors of the present invention provide electrical connection between the Cu alloy film and the substrate and/or the insulating film, and are excellent in adhesion thereto. The electricity of the membrane itself A novel Cu alloy film having a low resistivity and a low resistivity without increasing the resistivity and having excellent workability after the heat history in the manufacturing process of the display device or the like can be continuously studied. As a result, it has been found to be used to include at least one element selected from the group consisting of Ag, Au, C, W, Ca, Mg, Al, Sn, B, and Ni in the Cu-Mn alloy (hereinafter sometimes referred to as X or a Cu-Mn-X alloy (first layer) of the X element), and a second layer of a Cu alloy composed of pure Cu or a Cu alloy mainly composed of Cu and having a lower specific resistance than the first layer The present invention has been completed by constructing a Cu alloy film which is constructed to achieve the intended purpose.
以下一面參照第1圖，一面說明本發明之較佳實施形態，惟本發明並非限定於此。其中，在第1圖中係顯示底部閘極型之例，但是並非限定於此，亦包含頂部閘極型。此外，在第1圖中，係使用非晶Si作為Si半導體層，但是並非限定於此，亦可使用例如多晶矽等。此外，在第1圖中係使用SiO2 作為閘極絕緣膜或保護膜，但是並非限定於此，例如可為SiON，亦可為SiN。Hereinafter, preferred embodiments of the present invention will be described with reference to Fig. 1, but the present invention is not limited thereto. Although the example of the bottom gate type is shown in FIG. 1, it is not limited to this, and the top gate type is also included. Further, in the first embodiment, amorphous Si is used as the Si semiconductor layer. However, the present invention is not limited thereto, and for example, polycrystalline germanium or the like may be used. Further, in the first embodiment, SiO 2 is used as the gate insulating film or the protective film. However, the present invention is not limited thereto, and may be, for example, SiON or SiN.
第1圖所示之TFT基板係具有由基板20側依序層積閘極電極(由本發明之第一層2a與第二層2所構成的Cu合金)、閘極絕緣膜3(圖中為SiO2 )、Si半導體層4、源極電極/汲極電極(圖中為Mo層11、Al層5的二層構造)、保護層10(圖中為SiO2 )、透明像素電極(7、8、9)的配線構造(底部閘極型)。The TFT substrate shown in Fig. 1 has a gate electrode (a Cu alloy composed of the first layer 2a and the second layer 2 of the present invention) and a gate insulating film 3 in this order from the substrate 20 side (in the figure SiO 2 ), Si semiconductor layer 4, source electrode/drain electrode (two layers of Mo layer 11 and Al layer 5 in the figure), protective layer 10 (SiO 2 in the drawing), transparent pixel electrode (7, 8, 9) wiring structure (bottom gate type).
本發明之Cu合金膜係由基板側依序包含第一層與第二層的層積構造。第一層係由在Cu-Mn合金添加X元素(選自由Ag、Au、C、W、Ca、Mg、Al、Sn、B及Ni所成群組的至少一種元素)的Cu-Mn-X合金所構成。亦即，本發明之第一層係在含有屬於密接性提升元素的Mn、及X元素(選自由Ag、Au、C、W、Ca、Mg、Al、Sn、B及Ni所成群組的至少1種元素)之二者方面具有特徵。上述X元素係一面有效發揮藉由添加Mn所達成的密接性提升作用，而且一面大幅有助於Cu合金膜本身的電阻率或熱處理後的電阻率的低減化的元素。尤其在後述實施例中獲得證實，若使用由上述第一層與後述第二層所構成之本發明之Cu合金膜時，可將成膜後、及熱處理後的電阻率抑制為較低。The Cu alloy film of the present invention includes a laminated structure of the first layer and the second layer in this order from the substrate side. The first layer is Cu-Mn-X added with a X element (at least one element selected from the group consisting of Ag, Au, C, W, Ca, Mg, Al, Sn, B, and Ni) in the Cu-Mn alloy. Made up of alloys. That is, the first layer of the present invention is composed of Mn and the X element (selected from the group consisting of Ag, Au, C, W, Ca, Mg, Al, Sn, B, and Ni) which are adhesion promoting elements. Both of the at least one element have characteristics. The X element is an element which effectively exerts an adhesion improving effect by adding Mn, and contributes greatly to the resistivity of the Cu alloy film itself or the decrease in the resistivity after heat treatment. In particular, it has been confirmed in the examples described later that when the Cu alloy film of the present invention comprising the first layer and the second layer described later is used, the electrical resistivity after film formation and after heat treatment can be suppressed to be low.
在本發明中，Mn之較佳含量為1.0原子%以上、20原子%以下。若Mn的含量未達1.0原子%，會有與基板及/或絕緣膜的密接性不充分且無法獲得充分的特性之虞。若考慮與基板等的密接性提升，Mn含量愈多愈好，但是若超過20原子%，藉由Cu合金成膜時或成膜後的熱處理(包含例如在成膜SiN膜的絕緣膜的工程等顯示裝置的製造過程中的熱履歷)，Cu-Mn-X中的Mn及X會在第二層擴散，而有Cu合金膜本身的電阻率變高之虞，故較不理想。Mn的較佳含量為2.0原子%以上、15.0原子%以下，更佳為5.0原子%以上、12.5原子%以下。In the present invention, the preferable content of Mn is 1.0 atom% or more and 20 atom% or less. When the content of Mn is less than 1.0 atomic%, the adhesion to the substrate and/or the insulating film may be insufficient, and sufficient characteristics may not be obtained. When the adhesion to the substrate or the like is increased, the Mn content is preferably as large as possible, but if it exceeds 20 atom%, the heat treatment by the Cu alloy film formation or after the film formation (including, for example, the process of forming the insulating film of the SiN film) In the heat history in the manufacturing process of the display device, Mn and X in Cu-Mn-X are diffused in the second layer, and the resistivity of the Cu alloy film itself is high, which is not preferable. The content of Mn is preferably 2.0 atom% or more and 15.0 atom% or less, more preferably 5.0 atom% or more and 12.5 atom% or less.
在本發明中，上述X元素可單獨含有，亦可併用2種 以上。上述X元素之較佳含量(單獨量或合計量)為0.2原子%以上、10原子%以下。X元素含量係可以與上述Mn的關係來適當設定。若X元素的含量為未達0.2原子%，會有藉由添加X元素所達成的上述密接性提升作用、熱處理後的電阻率低減效果未被充分發揮之虞。若X元素的含量超過10原子%，會有熱處理後的電阻率較高之虞，故較不理想。X元素的較佳含量為0.4原子%以上、7原子%以下，更佳為0.5原子%以上、3原子%以下。In the present invention, the above X element may be contained alone or in combination of two the above. The preferred content (individual amount or total amount) of the above X element is 0.2 atom% or more and 10 atom% or less. The content of the X element can be appropriately set in accordance with the relationship of the above Mn. When the content of the X element is less than 0.2 atomic%, the adhesion improving effect by the addition of the X element and the effect of reducing the resistivity after the heat treatment are not sufficiently exhibited. When the content of the X element exceeds 10 atom%, the electrical resistivity after heat treatment is high, which is not preferable. The content of the X element is preferably 0.4 atom% or more and 7 atom% or less, more preferably 0.5 atom% or more and 3 atom% or less.
本發明之Cu-Mn-X合金層之較佳膜厚為5nm以上、100nm以下。若膜厚未達5nm，Cu-Mn-X合金層因成膜時或成膜後的熱處理而發生與基板的剝離，會有密接性降低的情形。由防止剝離的觀點來看，更佳為10nm以上。而且，若膜厚超過100nm，由於會有Cu合金膜本身的配線電阻上升之虞，故較不理想。由抑制配線電阻上升的觀點來看，較佳膜厚為50nm以下。The Cu-Mn-X alloy layer of the present invention preferably has a film thickness of 5 nm or more and 100 nm or less. When the film thickness is less than 5 nm, the Cu-Mn-X alloy layer may be peeled off from the substrate due to heat treatment at the time of film formation or after film formation, and the adhesion may be lowered. From the viewpoint of preventing peeling, it is more preferably 10 nm or more. Further, when the film thickness exceeds 100 nm, the wiring resistance of the Cu alloy film itself is increased, which is not preferable. From the viewpoint of suppressing an increase in wiring resistance, the film thickness is preferably 50 nm or less.
此外，為了防止通電時配線部分的發熱溫度上升的問題，必須將Cu合金膜全體(第一層+第二層)的電阻抑制為較低。本發明之Cu-Mn-X合金層(第一層)的膜厚的比例係相對Cu合金膜(第一層+第二層)的膜厚，較佳為50%以下，更佳為20%以下。Further, in order to prevent the problem of an increase in the heat generation temperature of the wiring portion at the time of energization, it is necessary to suppress the electric resistance of the entire Cu alloy film (first layer + second layer) to be low. The film thickness ratio of the Cu-Mn-X alloy layer (first layer) of the present invention is preferably 50% or less, more preferably 20%, with respect to the film thickness of the Cu alloy film (first layer + second layer). the following.
其中，本發明中所使用的第一層係分別含有上述元素，殘部：Cu及不可避免雜質。不可避免雜質的合計量並未特別限定，可含有0.5原子%以下，亦可例如含有0.1原子%以下的Si。Among them, the first layer used in the present invention contains the above elements, and the residue: Cu and inevitable impurities. The total amount of the unavoidable impurities is not particularly limited, and may be 0.5 atom% or less, and may contain, for example, 0.1 atom% or less of Si.
本發明中的Cu合金膜中的第二層係被形成在第一層之上(正上方)，以純Cu、或以Cu為主成分的Cu合金且為電阻率低於第一層的Cu合金所構成。藉由設置如上所示之第二層，可將Cu合金膜全體的電阻抑制為較低。The second layer in the Cu alloy film of the present invention is formed on the first layer (directly above), pure Cu, or a Cu alloy mainly composed of Cu and is a Cu alloy having a lower resistivity than the first layer. Composition. By providing the second layer as shown above, the electric resistance of the entire Cu alloy film can be suppressed to be low.
在本發明中電阻率低於第一層的Cu合金意指與上述第一層相比，以電阻率較低的方式適當控制合金元素的種類及/或含量的Cu合金。例如亦可參照文獻記載的數值，適當選擇電阻率低的元素(較佳為電阻率與純Cu合金同等、或其以下的元素)，即使為電阻率高於純Cu合金的元素，若減少含量，即可減低電阻率，因此可適用於第二層的合金元素並不一定限定於電阻率低的元素，若按照作為第一層的Cu-Mn-X合金層的具體電阻率來適當選擇即可。In the present invention, the Cu alloy having a lower specific resistance than the first layer means a Cu alloy which appropriately controls the kind and/or content of the alloying element in a manner of lower resistivity than the above first layer. For example, an element having a low specific resistance (preferably an element having a resistivity equal to or lower than that of a pure Cu alloy) can be appropriately selected according to the numerical values described in the literature, and even if the resistivity is higher than that of the element of the pure Cu alloy, the content is reduced. Therefore, the resistivity can be reduced, so that the alloying element applicable to the second layer is not necessarily limited to an element having a low specific resistance, and is appropriately selected according to the specific resistivity of the Cu-Mn-X alloy layer as the first layer. can.
第二層中的純Cu係指Cu及殘部不可避免雜質，以Cu為主成分係指第二層中的Cu為99原子%以上，由減低電阻的觀點來看，較佳為99.5原子%以上為Cu，殘部為上述元素及不可避免雜質。不可避免雜質的合計量並未特別限定，可含有0.5原子%以下，例如亦可含有0.1原子%以下的Si。The pure Cu in the second layer means Cu and the inevitable impurities in the residue, and Cu as the main component means that Cu in the second layer is 99 atom% or more, and from the viewpoint of reducing electric resistance, it is preferably 99.5 atom% or more. In the case of Cu, the residue is the above element and inevitable impurities. The total amount of the unavoidable impurities is not particularly limited, and may be 0.5 atom% or less, and may be, for example, 0.1 atom% or less.
本發明之第二層之較佳膜厚為100nm以上、1μm以下。若膜厚為未達100nm，會有電阻率的減低效果不充分的情形。此外，若膜厚超過1μm，由於膜容易剝離，故較不理想。更佳的膜厚為200nm以上、600nm以下。The film thickness of the second layer of the present invention is preferably 100 nm or more and 1 μm or less. If the film thickness is less than 100 nm, the effect of reducing the resistivity may be insufficient. Further, when the film thickness exceeds 1 μm, the film is easily peeled off, which is not preferable. A more preferable film thickness is 200 nm or more and 600 nm or less.
此外，上述Cu合金膜全體(第一層+第二層)的膜厚若按照所需特性來適當設定即可，若在上述第一層與第二層的膜厚範圍內作適當調節即可，但是由生產效率的觀點來看，較佳為1μm以下，更佳為600nm以下。關於下限，由將電阻率抑制為較低的觀點來看，為了發揮上述特性，較佳為150nm以上，更佳為200nm以上為宜。Further, the film thickness of the entire Cu alloy film (first layer + second layer) may be appropriately set according to desired characteristics, and may be appropriately adjusted within the film thickness range of the first layer and the second layer. However, from the viewpoint of production efficiency, it is preferably 1 μm or less, more preferably 600 nm or less. The lower limit is preferably 150 nm or more, and more preferably 200 nm or more in order to exhibit the above characteristics from the viewpoint of suppressing the specific resistance.
本發明中的Cu合金膜(第一層、第二層)所含有的各合金元素的含量係可藉由例如ICP發光分析(感應耦合電漿發光分析)法來求出，各層的各合金元素的含量若在各層成膜後進行測定即可。此外，第一層的膜厚及第二層的膜厚係可藉由觸針型段差計KLA-TENCOR公司製α-step來測定各個。The content of each alloying element contained in the Cu alloy film (first layer, second layer) in the present invention can be determined by, for example, ICP luminescence analysis (inductively coupled plasma luminescence analysis), and each alloying element of each layer The content may be measured after each layer is formed into a film. Further, the film thickness of the first layer and the film thickness of the second layer can be measured by α-step manufactured by KLA-TENCOR Co., Ltd., a stylus type step meter.
以下記載本發明之Cu合金膜(第一層+第二層)之較佳成膜方法，但是本發明之Cu合金膜之成膜方法並非限定於此，亦可以各種方法成膜。Although a preferred film forming method of the Cu alloy film (first layer + second layer) of the present invention is described below, the film forming method of the Cu alloy film of the present invention is not limited thereto, and a film may be formed by various methods.
具有上述層積構造之本發明之Cu合金膜係以藉由濺鍍法成膜為佳。具體而言，在藉由濺鍍法來成膜出構成上述第一層的材料後，在其上藉由濺鍍法來成膜構成上述第二層的材料，藉此形成為層積構造即可。The Cu alloy film of the present invention having the above laminated structure is preferably formed by sputtering. Specifically, after the material constituting the first layer is formed by a sputtering method, a material constituting the second layer is formed thereon by a sputtering method, thereby forming a laminated structure. can.
本發明中所使用的上述Cu合金膜係如上所述，以藉由濺鍍法來成膜為佳。濺鍍法係指在真空中導入Ar等惰性氣體，在基板與濺鍍靶材(以下有時稱為靶材)之間形成電漿放電，使藉由該電漿放電而離子化的Ar衝撞上述靶材，趕出該靶材的原子而堆積在基板上來製作薄膜的方法 。若使用濺鍍法，可成膜出與濺鍍靶材為大致相同組成的Cu合金膜。亦即，相較於以離子鍍著法或電子束蒸鍍法、真空蒸鍍法所形成的薄膜，可輕易形成成分或膜厚的膜面內均一性優異的薄膜，而且可在as-deposited狀態下形成合金元素均一固溶的薄膜，因此可有效呈現高溫耐氧化性。以濺鍍法而言，係可採用例如DC濺鍍法、RF濺鍍法、磁控管濺鍍法、反應性濺鍍法等任何濺鍍法，其形成條件若適當設定即可。The above-described Cu alloy film used in the present invention is preferably formed by sputtering by the sputtering method as described above. The sputtering method refers to introducing an inert gas such as Ar into a vacuum, forming a plasma discharge between the substrate and the sputtering target (hereinafter sometimes referred to as a target), and causing an Ar collision by ionization of the plasma discharge. The above target material, which is obtained by ejecting atoms of the target and depositing on a substrate to form a film . When a sputtering method is used, a Cu alloy film having substantially the same composition as that of the sputtering target can be formed. That is, a thin film having excellent in-plane uniformity of a component or a film thickness can be easily formed as compared with a film formed by an ion plating method, an electron beam evaporation method, or a vacuum vapor deposition method, and can be as-deposited. In the state, a film in which the alloying elements are uniformly dissolved is formed, so that high temperature oxidation resistance can be effectively exhibited. In the sputtering method, any sputtering method such as a DC sputtering method, an RF sputtering method, a magnetron sputtering method, or a reactive sputtering method can be employed, and the formation conditions can be appropriately set.
若使用濺鍍法，可成膜與濺鍍靶材大致相同組成的Cu合金層，因此濺鍍靶材的組成係可使用不同組成的Cu合金靶材來調整，或者亦可藉由將合金元素的金屬覆晶在純Cu靶材來調整。在上述濺鍍法中，例如在形成上述Cu-Mn-X合金膜時，以上述靶材而言，由含有預定量的Mn及X元素的Cu合金所構成者，若使用與所希望的Cu-Mn-X合金膜相同組成的濺鍍靶材，不會有組成偏差的情形，可形成所希望的成分/組成的Cu-Mn-X合金膜，故較佳。此外，在形成上述第二層時，以上述靶材而言，藉由純Cu靶材、或將合金元素的金屬覆晶在純Cu靶材，可形成所希望的組成的第二層。If a sputtering method is used, a Cu alloy layer having substantially the same composition as that of the sputtering target can be formed, and thus the composition of the sputtering target can be adjusted using a Cu alloy target having a different composition, or by using an alloying element. The metal flip chip is adjusted in a pure Cu target. In the sputtering method, for example, when the Cu-Mn-X alloy film is formed, the target material is composed of a Cu alloy containing a predetermined amount of Mn and X elements, and a desired Cu is used. A sputtering target having the same composition of the -Mn-X alloy film is preferable because it does not have a composition variation and can form a Cu-Mn-X alloy film having a desired composition/composition. Further, when the second layer is formed, the second layer having a desired composition can be formed by the pure Cu target or the metal of the alloy element on the pure Cu target.
其中，在濺鍍法中，會有在所成膜的Cu合金膜的組成與濺鍍靶材的組成之間，稍微發生偏差的情形。但是該偏差大概在數原子%以內。因此，若將濺鍍靶材的組成最大亦在±10原子%的範圍內進行控制，可將所希望的組成的Cu合金膜進行成膜。Among them, in the sputtering method, there is a slight variation between the composition of the formed Cu alloy film and the composition of the sputtering target. However, the deviation is approximately within a few atomic %. Therefore, if the composition of the sputtering target is controlled to the maximum within ±10 atom%, a Cu alloy film having a desired composition can be formed into a film.
靶材的形狀係包含按照濺鍍裝置的形狀或構造，加工成任意形狀(角型板狀、圓形板狀、甜甜圈板狀等)者。The shape of the target is processed into an arbitrary shape (angular plate shape, circular plate shape, donut plate shape, etc.) according to the shape or structure of the sputtering apparatus.
以上述靶材之製造方法而言，列舉有：以熔解鑄造法或粉末燒結法、噴霧成型法，製造由Cu基合金所成的合金錠而得的方法、或在製造出由Cu基合金所成的預成型體(獲得最終緻密體之前的中間體)後，藉由緻密化手段將該預成型體緻密化而得的方法。Examples of the method for producing the above-mentioned target include a method of producing an alloy ingot formed of a Cu-based alloy by a melt casting method, a powder sintering method, or a spray molding method, or a method of producing a Cu-based alloy. The formed preform (the intermediate before the final dense body) is obtained by densifying the preform by a densification means.
本發明中所使用的Cu合金膜由於電阻低、而且與基板及/或絕緣膜的密接性優異，因此適於作為與該等直接接觸的配線膜及電極用的膜來使用。在本發明中，較佳為源極電極及/或汲極電極由上述Cu合金膜所構成，關於其他配線部(例如閘極電極)的成分組成，並未特別限定。而且，本發明中所使用的Cu合金膜係可進行微細加工。Since the Cu alloy film used in the present invention has low electrical resistance and excellent adhesion to a substrate and/or an insulating film, it is suitably used as a wiring film and an electrode film which are in direct contact with the film. In the present invention, it is preferable that the source electrode and/or the drain electrode are composed of the above-described Cu alloy film, and the composition of the other wiring portion (for example, the gate electrode) is not particularly limited. Further, the Cu alloy film used in the present invention can be subjected to microfabrication.
例如可以上述Cu合金膜來構成TFT基板中的閘極電極、掃描線、訊號線中的汲極配線部等Cu合金配線的全部，此時，可將TFT基板中的Cu合金配線的全部設為同一成分組成。For example, all of the Cu alloy wirings such as the gate electrode, the scanning line, and the drain wiring portion in the signal line in the TFT substrate can be formed by the above-described Cu alloy film. In this case, all of the Cu alloy wirings in the TFT substrate can be set. The same composition.
上述Cu合金膜係與基板及/或絕緣膜直接作電性連接，較佳為作為閘極電極用配線膜來使用。上述Cu合金膜較佳為與構成源極電極/汲極電極的金屬配線膜作電性連接。或者，上述Cu合金膜較佳為與構成像素電極的透明導電膜(具代表性為ITO、IZO、ZnO等)直接連接。或者，上述Cu合金膜亦可適用於供對外部輸出入訊號之用所被使用的TAB連接電極等。The Cu alloy film is directly electrically connected to the substrate and/or the insulating film, and is preferably used as a wiring film for a gate electrode. The Cu alloy film is preferably electrically connected to a metal wiring film constituting a source electrode/drain electrode. Alternatively, the Cu alloy film is preferably directly connected to a transparent conductive film (typically ITO, IZO, ZnO, or the like) constituting the pixel electrode. Alternatively, the Cu alloy film may be applied to a TAB connection electrode or the like which is used for external input and output signals.
本發明係在上述Cu合金膜具有特徵，其他構成要件並未特別限定。The present invention is characterized by the above-described Cu alloy film, and other constituent elements are not particularly limited.
例如半導體通道層係具代表性地使用矽(Si)，列舉非晶矽、氫化非晶矽、多晶或微晶矽、單晶矽等。For example, a semiconductor channel layer is typically made of bismuth (Si), and examples thereof include amorphous germanium, hydrogenated amorphous germanium, polycrystalline or microcrystalline germanium, single crystal germanium, and the like.
此外，以構成像素電極的透明導電膜而言，列舉液晶顯示裝置等平常所使用的氧化物導電膜，列舉例如由包含選自由In、Ga、Zn、及Sn所成群組的至少1種元素的氧化物所成的導電膜。具代表性例示非晶ITO或poly-ITO、IZO、ZnO等。In addition, examples of the transparent conductive film constituting the pixel electrode include an oxide conductive film which is generally used in a liquid crystal display device and the like, and examples thereof include at least one element selected from the group consisting of In, Ga, Zn, and Sn. A conductive film formed by an oxide. Representative examples of amorphous ITO or poly-ITO, IZO, ZnO, and the like are exemplified.
此外，閘極絕緣膜等絕緣膜或形成在半導體之上的保護膜並未特別限定，列舉有平常所使用者，例如SiO2 、SiON、SiN等。Further, the insulating film such as the gate insulating film or the protective film formed on the semiconductor is not particularly limited, and examples thereof include ordinary users such as SiO 2 , SiON, SiN, and the like.
基板若為被使用在液晶顯示裝置等者，則並未特別限定。具代表性列舉玻璃基板等所代表的透明基板。玻璃基板的材料若為使用在顯示裝置者，並未特別限定，列舉例如無鹼玻璃、高應變點玻璃、鈉鈣玻璃等。或者亦可使用可撓性樹脂薄膜、金屬箔等。The substrate is not particularly limited as long as it is used in a liquid crystal display device or the like. A representative transparent substrate represented by a glass substrate or the like is exemplified. The material of the glass substrate is not particularly limited as long as it is used in a display device, and examples thereof include alkali-free glass, high strain point glass, and soda lime glass. Alternatively, a flexible resin film, a metal foil, or the like can be used.
在製造具備有上述配線構造的顯示裝置時，除了滿足本發明之規定，而且將Cu合金膜曝露在250℃以上且為0.5小時以上的熱處理(熱處理)以外，並未特別限定，若採用顯示裝置的一般工程即可。In the case of manufacturing a display device having the above-described wiring structure, the heat treatment (heat treatment) of exposing the Cu alloy film to 250 ° C or more and 0.5 hours or more is not particularly limited, and a display device is used. General engineering can be.
以下一面參照第1圖，一面說明本發明之較佳實施形態，亦即使用非晶矽之液晶顯示器用TFT元件之製造方法。但是，並非為本發明限定於此之主旨。在第1圖中係顯 示在基板形成有閘極電極之所謂底部型的TFT元件構造，但是並非限定於此，亦可使用基板照原樣，而將基板以外的構成要素的配列上下相反之所謂頂部型的TFT元件構造。此外，在第1圖中，係在閘極電極使用本發明之Cu合金膜，但是並非限定於此，亦可在源極電極/汲極電極使用本發明之Cu合金膜。此外，只要滿足本發明之要件，閘極電極與源極電極/汲極電極可為同一組成，亦可為不同的組成。Hereinafter, a preferred embodiment of the present invention, that is, a method of manufacturing a TFT element for a liquid crystal display using amorphous germanium, will be described with reference to FIG. However, the present invention is not limited thereto. Shown in Figure 1 The so-called bottom type TFT element structure in which the gate electrode is formed on the substrate is not limited thereto, and a so-called top type TFT element structure in which the arrangement of the components other than the substrate is reversed may be used as it is. Further, in the first embodiment, the Cu alloy film of the present invention is used for the gate electrode. However, the present invention is not limited thereto, and the Cu alloy film of the present invention may be used for the source electrode/drain electrode. Further, as long as the requirements of the present invention are satisfied, the gate electrode and the source electrode/drain electrode may have the same composition or may have different compositions.
首先，在基板20上，使用濺鍍等方法，在Ar氣體環境下將厚度20nm左右的Cu-Mn-X合金層2a進行蒸鍍後，接著將厚度300nm左右之以Cu為主成分的第二層2進行蒸鍍，而成膜出Cu合金膜。濺鍍的成膜溫度係設為例如室溫。其中，若在氮或氧存在下成膜出Cu-Mn-X合金層時，由於與基板或絕緣膜的密接性會提升，故較為理想。添加方法可為在成膜中使用添加經Ar稀釋的氮或氧作為製程氣體的方法，亦可為使用含有氧或氮的靶材來進行成膜的方法等。First, on the substrate 20, a Cu-Mn-X alloy layer 2a having a thickness of about 20 nm is vapor-deposited in an Ar gas atmosphere by a method such as sputtering, and then a second portion having a thickness of about 300 nm and containing Cu as a main component is formed. The layer 2 is vapor-deposited to form a Cu alloy film. The film formation temperature of the sputtering is set to, for example, room temperature. Among them, when a Cu-Mn-X alloy layer is formed in the presence of nitrogen or oxygen, the adhesion to the substrate or the insulating film is improved, which is preferable. The addition method may be a method in which nitrogen or oxygen diluted with Ar is added as a process gas in the film formation, or a method of forming a film using a target containing oxygen or nitrogen.
接著，在藉由光微影而將阻劑膜圖案化後，將阻劑膜作為遮罩而將Cu合金膜進行蝕刻，藉此形成閘極電極(2、2a)及接續此的配線膜(圖中未顯示)。Next, after patterning the resist film by photolithography, the resist film is used as a mask to etch the Cu alloy film, thereby forming gate electrodes (2, 2a) and wiring films (continuously) Not shown in the figure).
接著，使用例如電漿CVD法等方法，層積厚度約200nm左右的絕緣性基底層3(例如SiN膜)。該絕緣性基底層3被稱為閘極絕緣層。電漿CVD法的成膜溫度設為例如約350℃。接著，使用例如電漿CVD法等方法，在絕 緣性基底層3之上，依序層積厚度200nm左右的未摻雜氫化非晶矽膜(a-Si：H)及厚度約80nm左右之摻雜磷的n+型氫化非晶矽膜(n+ a-Si：H)。該層積膜係與Si半導體層4相對應。n+ 型氫化非晶矽膜係藉由進行例如以SiH4 PH3 為原料的電漿CVD來形成。Next, an insulating underlayer 3 (for example, an SiN film) having a thickness of about 200 nm is laminated by a method such as a plasma CVD method. This insulating base layer 3 is referred to as a gate insulating layer. The film formation temperature of the plasma CVD method is set to, for example, about 350 °C. Next, an undoped hydrogenated amorphous germanium film (a-Si:H) having a thickness of about 200 nm and a thickness of about 80 nm are laminated on the insulating underlayer 3 by a method such as a plasma CVD method. An n+-type hydrogenated amorphous ruthenium film of heterophosphorus (n + a-Si:H). This laminated film corresponds to the Si semiconductor layer 4. The n + -type hydrogenated amorphous ruthenium film is formed by, for example, plasma CVD using SiH 4 PH 3 as a raw material.
接著，在n+型氫化非晶矽膜(n+ a-Si：H)之上，使用濺鍍等方法，對厚度200nm左右的金屬薄膜(在此，Mo/Al的2層的膜(圖中11/5、及6/11)進行蒸鍍。濺鍍的成膜溫度例如設為室溫。之後，例如在真空中進行熱處理。接著，藉由光微影將阻劑膜圖案化後，以阻劑膜為遮罩來對上述金屬薄膜進行蝕刻，藉此將第1圖的源極電極(圖中11與5)、汲極電極(圖中11與6)圖案化後，另外以源極電極及汲極電極為遮罩，將n+ 型氫化非晶矽膜進行乾式蝕刻來去除。Next, on a n+ type hydrogenated amorphous germanium film (n + a-Si:H), a metal thin film having a thickness of about 200 nm is used by sputtering or the like (here, a two-layer film of Mo/Al (in the figure) 11/5, and 6/11) vapor deposition is performed. The film formation temperature of the sputtering is set to room temperature, for example, and then heat-treated, for example, in a vacuum. Then, the resist film is patterned by photolithography, and then The resist film is a mask to etch the metal thin film, thereby patterning the source electrode (11 and 5 in the figure) and the drain electrode (11 and 6 in the figure) of FIG. 1 and further using the source. The electrode and the drain electrode are masks, and the n + -type hydrogenated amorphous germanium film is subjected to dry etching to remove it.
接著，例如使用電漿氮化裝置等，形成厚度300nm左右的Si氮化膜(保護膜)10。此時的成膜係在約270℃下進行。接著，在Si氮化膜10上將阻劑圖案化，藉由進行乾式蝕刻等來形成接觸孔。Next, a Si nitride film (protective film) 10 having a thickness of about 300 nm is formed, for example, using a plasma nitriding apparatus or the like. The film formation at this time was carried out at about 270 °C. Next, a resist is patterned on the Si nitride film 10, and a contact hole is formed by dry etching or the like.
接著，使用例如胺系等之剝離液來將光阻層(未圖示)剝離。最後，成膜厚度50nm左右的ITO膜(在氧化銦添加10質量%的氧化錫)。接著，進行藉由濕式蝕刻所致之圖案化，形成透明像素電極(圖中7、8、9)，最終獲得第1圖的TFT元件或TFT基板。Next, the photoresist layer (not shown) is peeled off using a peeling liquid such as an amine system. Finally, an ITO film having a film thickness of about 50 nm was formed (10% by mass of tin oxide was added to indium oxide). Next, patterning by wet etching is performed to form transparent pixel electrodes (7, 8, and 9 in the drawing), and finally the TFT element or TFT substrate of Fig. 1 is obtained.
以下列舉實施例，更具體說明本發明，但是本發明並非受到以下實施例限制，亦可在可適於上述/下述主旨的範圍內施加變更來實施，該等均包含在本發明之技術範圍內。在本實施例中，使用藉由以下方法所製作的試料，來測定基板與Cu合金膜的密接性、熱處理後的電阻率。The present invention will be more specifically described by the following examples, but the present invention is not limited by the following examples, and may be practiced with a modification within the scope of the above-mentioned/the following, which are all included in the technical scope of the present invention. Inside. In the present embodiment, the adhesion between the substrate and the Cu alloy film and the electrical resistivity after the heat treatment were measured using the sample prepared by the following method.
首先，在玻璃基板上藉由電漿CVD法，成膜出膜厚200nm之摻雜雜質(P)的低電阻的非晶矽膜(n-a-Si：H層)。該低電阻非晶矽膜(n-a-Si：H層)係藉由進行以SiH4 、PH3 為原料的電漿CVD而形成。電漿CVD的成膜溫度係設為320℃。First, a low-resistance amorphous germanium film (na-Si: H layer) of a doping impurity (P) having a film thickness of 200 nm was formed on a glass substrate by a plasma CVD method. The low-resistance amorphous germanium film (na-Si:H layer) is formed by plasma CVD using SiH 4 and PH 3 as raw materials. The film formation temperature of the plasma CVD was set to 320 °C.
接著，在該低電阻非晶矽膜上，以表1、2所示條件(Mn含量、膜厚)成膜出Cu-Mn-X合金層(第一層)後，在第一層之上，以成為表1、2所示厚度的方式成膜出純Cu層作為第二層。Next, on the low-resistance amorphous germanium film, a Cu-Mn-X alloy layer (first layer) was formed under the conditions (Mn content, film thickness) shown in Tables 1 and 2, and then on the first layer. A pure Cu layer was formed as a second layer so as to have the thickness shown in Tables 1 and 2.
其中，使用島津製作所製商品名「HSM-552」作為濺鍍裝置，藉由DC磁控管濺鍍法[背壓：0.27×10-3 Pa以下，環境氣體：Ar，Ar氣體壓力：2mTorr，Ar氣體流量：30sccm，濺鍍功率：DC260W，極間距離：50.4mm，基板溫度：25℃(室溫)]，在基板上成膜出表1、2所示之Cu合 金膜或純Cu膜而得配線膜的試料。Among them, the product name "HSM-552" manufactured by Shimadzu Corporation was used as a sputtering device by DC magnetron sputtering [back pressure: 0.27 × 10 -3 Pa or less, ambient gas: Ar, Ar gas pressure: 2 mTorr, Ar gas flow rate: 30 sccm, sputtering power: DC260W, interelectrode distance: 50.4 mm, substrate temperature: 25 ° C (room temperature)], and a Cu alloy film or a pure Cu film shown in Tables 1 and 2 was formed on the substrate. The sample of the wiring film is obtained.
在純Cu膜的形成係在濺鍍靶材使用純Cu。此外，在各種合金成分的Cu合金膜的形成係使用在真空溶解法中所作成的濺鍍靶材。In the formation of a pure Cu film, pure Cu is used in the sputtering target. Further, in the formation of a Cu alloy film of various alloy compositions, a sputtering target formed in a vacuum dissolution method is used.
上述Cu合金膜的組成係使用ICP發光分光分析裝置(島津製作所製的ICP發光分光分析裝置「ICP-8000型」)，進行定量分析來作確認。此外，各層的膜厚係藉由觸針型段差計KLA-TENCOR公司製α-step來測定。The composition of the above-mentioned Cu alloy film was confirmed by quantitative analysis using an ICP emission spectroscopic analyzer (ICP-8000 type ICP emission spectrometer manufactured by Shimadzu Corporation). Further, the film thickness of each layer was measured by α-step manufactured by KLA-TENCOR Co., Ltd., a stylus type step meter.
接著，使用光微影技術，將阻劑膜圖案化，將阻劑作為遮罩來對上述各試料的層積Cu合金膜(第一層、第二層)進行蝕刻，藉此形成密接性試驗用圖案。此外，為供比較，亦備妥僅由純Cu所成的試料(No.1)(在電阻率的評估中亦同樣地作為比較例來製作)。Next, the resist film was patterned by photolithography, and the laminated Cu alloy film (first layer, second layer) of each of the above samples was etched using a resist as a mask to form an adhesion test. Use patterns. Further, for comparison, a sample (No. 1) made only of pure Cu was prepared (it was also produced as a comparative example in the evaluation of resistivity).
以藉由膠帶所為的剝離試驗來評估如上所述所得的各試料的密接性。詳言之，在各試料的層積Cu合金膜表面，以截切刀形成1mm間隔的棋盤格狀的切塊(5×5正方形的切塊)。接著，將Nichiban製賽璐玢膠帶(cellophane tape)(製品編號Cellotape(註冊商標)No.405)牢固地黏貼在上述層積Cu合金膜上，一面以上述膠帶的撕離角度成為60°的方式進行保持，一面將上述膠帶一下子撕離，藉由上述膠帶而未剝離的棋盤格的劃區數、以及若棋盤格的一部分剝離時作為經0.5剝離者而將劃區數進行計數，求出 與全劃區的比率(膜殘存率)。進行3次測定，將3次的平均值設為各試料的膜殘存率。The adhesion of each sample obtained as described above was evaluated by a peeling test by an adhesive tape. In detail, in the surface of the Cu alloy film of each sample, a checker-shaped dicing (a 5 × 5 square dicing) having a 1 mm interval was formed by a cutting blade. Next, Nichiban cellophane tape (product number Cellotape (registered trademark) No. 405) was firmly adhered to the laminated Cu alloy film, and the tearing angle of the tape was 60°. While holding the tape, the tape is peeled off at once, the number of the squares of the checkerboard which is not peeled off by the tape, and the number of the zones are counted as 0.5 peeled off when a part of the checkerboard is peeled off. Ratio to full area (membrane residual rate). The measurement was performed three times, and the average value of three times was made into the film residual ratio of each sample.
在本實施例中，將藉由膠帶所致之剝離率為10%以下者判定為○，將超過10%~30%者判定為△，將超過30%者判定為×。In the present embodiment, the peeling rate by the tape is 10% or less, and it is judged as ○, the excess of 10% to 30% is judged as Δ, and the more than 30% is judged as ×.
對上述配線膜的各試料，進行光微影及濕式蝕刻，加工成寬度100μm、長度10mm的陣列狀圖案，而製作出試料。此時，以濕式蝕刻劑而言，係使用由磷酸：硫酸：硝酸：醋酸=75：10：5：10的混酸所成的混合液。Each sample of the wiring film was subjected to photolithography and wet etching, and processed into an array pattern having a width of 100 μm and a length of 10 mm to prepare a sample. At this time, in the case of the wet etchant, a mixed solution of a mixed acid of phosphoric acid: sulfuric acid: nitric acid: acetic acid = 75:10:5:10 was used.
評估所得之各試料的熱處理後的電阻率。詳言之，使用單片式CVD裝置，將上述試料加熱而在350℃下進行30分鐘的真空熱處理，以直流四探針法在室溫下測定該熱處理後的電阻率。以下列基準來評估如此所測定出的熱處理後的電阻率。The resistivity after heat treatment of each of the obtained samples was evaluated. Specifically, the sample was heated by a monolithic CVD apparatus and subjected to vacuum heat treatment at 350 ° C for 30 minutes, and the resistivity after the heat treatment was measured at room temperature by a DC four-probe method. The thus measured heat resistivity after heat treatment was evaluated on the following basis.
○：2.6μΩcm以下○: 2.6 μΩcm or less
△：超過2.6μΩcm~3.0μΩcm以下△: more than 2.6 μΩcm to 3.0 μΩcm or less
×：超過3.0μΩcm×: more than 3.0 μΩcm
將該等結果顯示於表1、表2。其中，表中的綜合評估係將電阻率及密接性的評估均為○者設為○，電阻率及 密接性之中任一者為○、另一者為△者設為△，除此之外則設為×。These results are shown in Tables 1 and 2. Among them, the comprehensive evaluation in the table is that the evaluation of resistivity and adhesion is ○, the resistivity and Any of the adhesions is ○, the other is Δ, and Δ is set, and otherwise, x is set.
由表1、表2，可考察如下。From Table 1 and Table 2, the following can be considered.
首先，No.5~9、11~15、17~21、23~27、29~37係均為將滿足本發明之要件的Cu-Mn-X合金膜作為第一層來使用之例，熱處理後的電阻率低且與基板的密接性亦優異。First, No. 5 to 9, 11 to 15, 17 to 21, 23 to 27, and 29 to 37 are examples in which a Cu-Mn-X alloy film which satisfies the requirements of the present invention is used as the first layer, and heat treatment is employed. The subsequent resistivity is low and the adhesion to the substrate is also excellent.
相對於此，未滿足本發明之要件之下列之例係具有以下之不良情形。On the other hand, the following examples which do not satisfy the requirements of the present invention have the following disadvantages.
首先，No.1為純Cu的習知例，熱處理後的電阻率雖低，但是與半導體層的密接性差。First, No. 1 is a conventional example of pure Cu, and the electrical resistivity after heat treatment is low, but the adhesion to the semiconductor layer is inferior.
No.2係Mn的添加量少且未添加X元素之例，由於Mn含量少且未添加X元素，因此密接性差。In the case where the addition amount of No. 2 Mn is small and X element is not added, since the Mn content is small and X element is not added, the adhesion is inferior.
No.3係Mn及X元素(Ag)的添加量少之例，由於Mn與X元素的添加量少，因此密接性差。In the example in which the amount of addition of Mn and X element (Ag) is small, the amount of addition of Mn and X element is small, and thus the adhesion is inferior.
No.4係Mn的添加量多且未添加X元素之例。No.4由於Mn添加量多，因此密接性良好，但是電阻率上升。No. 4 is an example in which the amount of Mn added is large and X element is not added. In No. 4, since the amount of Mn added was large, the adhesion was good, but the electrical resistivity was increased.
No.10、16、22、28係Mn的添加量適當，但是X元素的添加量多之例。在該等之例中，由於X元素添加量多，因此密接性良好，但是電阻率上升。其中，將密接性評估為△，但是若與Mn或X元素的添加量少之例相比，(No.1、2)的剝離率良好。The addition amount of Mn of No. 10, 16, 22, and 28 is appropriate, but the addition amount of X element is large. In these examples, since the amount of the X element added is large, the adhesion is good, but the electrical resistivity is increased. In the meantime, the adhesion was evaluated as Δ, but the peeling ratio of (No. 1, 2) was good as compared with the case where the amount of Mn or X added was small.
No.38係添加在本發明中所規定之X元素以外的元素(Bi)之例，雖然含有預定量的Mn量，但是密接性差，且熱處理後的電阻率上升。No. 38 is an example in which an element (Bi) other than the X element defined in the present invention is added, and although a predetermined amount of Mn is contained, the adhesion is inferior and the electrical resistivity after heat treatment is increased.
No.39係Cu-Mn-X合金層(第一層)的膜厚薄之例，雖 然含有預定量的Mn及X元素，但是由於Cu-Mn-X合金層(第一層)的膜厚薄，因此未發揮密接性提升效果。An example of the film thickness of the No. 39-based Cu-Mn-X alloy layer (first layer), although Although a predetermined amount of Mn and X elements are contained, since the Cu-Mn-X alloy layer (first layer) has a small film thickness, the adhesion improving effect is not exhibited.
No.40係Cu-Mn-X合金層(第一層)的膜厚厚之例，雖然含有預定量的Mn及X元素，但是由於Cu-Mn-X合金層(第一層)的膜厚厚，因此熱處理後的電阻率上升。An example of the film thickness of the No. 40-based Cu-Mn-X alloy layer (first layer) contains a predetermined amount of Mn and X elements, but the film thickness of the Cu-Mn-X alloy layer (first layer) It is thick, so the resistivity after heat treatment rises.
以上詳細地參照特定的實施態樣來說明本申請案，惟可在未脫離本發明之精神與範圍的情形下施加各種變更或修正，此乃為所屬技術領域熟習該項技術者清楚可知。The present invention has been described in detail with reference to the specific embodiments thereof, and various modifications and changes can be made without departing from the spirit and scope of the invention, which is apparent to those skilled in the art.
本申請案係根據2011年3月31日申請的日本專利申請案(日本特願2011-078281)，其內容作為參考而被編入於此。The present application is based on Japanese Patent Application No. 2011-078281, filed on March 31, 2011, the content of which is hereby incorporated by reference.
本發明，可提供一種即使與基板及/或絕緣膜直接連接，亦為與該等之密接性優異的顯示裝置用或電子裝置用的Cu合金膜。此外，藉由本發明，可提供一種即使未施行特別的熱處理，亦可在顯示裝置或電子裝置等之製造過程中的熱履歷後實現屬於Cu系材料之特徵的低電阻率的Cu合金膜。According to the present invention, it is possible to provide a Cu alloy film for a display device or an electronic device which is excellent in adhesion to the substrate and/or the insulating film. Further, according to the present invention, it is possible to provide a low-resistivity Cu alloy film which is characterized by a Cu-based material after the heat history in the manufacturing process of a display device or an electronic device, without performing a special heat treatment.
2‧‧‧第二層2‧‧‧ second floor
2a‧‧‧第一層2a‧‧‧ first floor
3‧‧‧閘極絕緣膜3‧‧‧gate insulating film
4‧‧‧Si半導體層4‧‧‧Si semiconductor layer
5‧‧‧Al層5‧‧‧Al layer
6‧‧‧汲極電極6‧‧‧汲electrode
7、8、9‧‧‧透明像素電極7, 8, 9‧‧ transparent pixel electrode
10‧‧‧保護層10‧‧‧Protective layer
11‧‧‧Mo層11‧‧‧Mo layer
20‧‧‧基板20‧‧‧Substrate
第1圖係顯示本發明之具代表性的配線構造的概略剖面說明圖。Fig. 1 is a schematic cross-sectional explanatory view showing a typical wiring structure of the present invention.
2‧‧‧第二層2‧‧‧ second floor
2a‧‧‧第一層2a‧‧‧ first floor
3‧‧‧閘極絕緣膜3‧‧‧gate insulating film
4‧‧‧Si半導體層4‧‧‧Si semiconductor layer
5‧‧‧Al層5‧‧‧Al layer
6‧‧‧汲極電極6‧‧‧汲electrode
7、8、9‧‧‧透明像素電極7, 8, 9‧‧ transparent pixel electrode
10‧‧‧保護層10‧‧‧Protective layer
11‧‧‧Mo層11‧‧‧Mo layer
20‧‧‧基板20‧‧‧Substrate
Claims (9)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011078281A JP2012211378A (en) | 2011-03-31 | 2011-03-31 | Cu ALLOY FILM, AND DISPLAY DEVICE OR ELECTRONIC DEVICE EACH EQUIPPED WITH THE SAME |
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| TW201307586A TW201307586A (en) | 2013-02-16 |
| TWI504765B true TWI504765B (en) | 2015-10-21 |
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| JP (1) | JP2012211378A (en) |
| KR (1) | KR20130126996A (en) |
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| WO2014136673A1 (en) * | 2013-03-07 | 2014-09-12 | Jx日鉱日石金属株式会社 | Copper alloy sputtering target |
| JP6250614B2 (en) * | 2015-02-19 | 2017-12-20 | 株式会社神戸製鋼所 | Cu laminated film and Cu alloy sputtering target |
| CN104962871B (en) * | 2015-05-25 | 2018-04-27 | 同济大学 | A kind of high conductivity aluminum alloy films and preparation method thereof |
| JP2018032601A (en) * | 2016-08-26 | 2018-03-01 | 株式会社神戸製鋼所 | REFLECTION ELECTRODE AND Al ALLOY SPUTTERING TARGET |
| JP6350754B1 (en) * | 2017-01-20 | 2018-07-04 | 凸版印刷株式会社 | Display device and display device substrate |
| TWI630534B (en) * | 2017-01-23 | 2018-07-21 | 日商凸版印刷股份有限公司 | Display device and display device substrate |
| JP2018180297A (en) * | 2017-04-13 | 2018-11-15 | 株式会社アルバック | Target, wiring film, semiconductor element, and display device |
| KR20190132342A (en) | 2017-04-13 | 2019-11-27 | 가부시키가이샤 알박 | Liquid crystal display device, organic electroluminescence display, semiconductor element, wiring film, wiring board, target |
| WO2018225114A1 (en) * | 2017-06-05 | 2018-12-13 | 凸版印刷株式会社 | Semiconductor device, display device and sputtering target |
| CN111463168A (en) * | 2019-09-24 | 2020-07-28 | 夏泰鑫半导体(青岛)有限公司 | Metal interconnection structure and preparation method thereof |
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| TW201307586A (en) | 2013-02-16 |
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