JP2011049542A - Wiring structure, method for manufacturing the same and display device with the wiring structure - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring structure having an Al alloy film for a display device having an Al alloy film and an oxide semiconductor layer of a thin film transistor directly connected to the Al alloy film sequentially from a substrate side, and obtaining low contact resistance even if the Al alloy film is directly connected to the oxide semiconductor layer by omitting a high melting point metal such as Ti or Mo. <P>SOLUTION: In the wiring structure, a semiconductor layer is formed of an oxide semiconductor, and the Al alloy film contains Ni and/or Co and is directly connected to a transparent conductive film configuring a pixel electrode on the same plane directly connected to the semiconductor layer. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention is a wiring structure including an Al alloy film and a semiconductor layer of a thin film transistor directly connected to the Al alloy film in order from the substrate side, and the semiconductor layer is an oxide semiconductor layer made of an oxide semiconductor And a manufacturing method thereof, and a display device including the wiring structure. The wiring structure of the present invention is typically used for flat panel displays such as liquid crystal displays (liquid crystal display devices) and organic EL displays. In the following, a liquid crystal display device will be typically taken up and described, but the present invention is not limited to this.

  A liquid crystal display device used in various fields ranging from a small mobile phone to a large-sized television exceeding 30 inches uses a thin film transistor (hereinafter referred to as “TFT”) as a switching element, and constitutes a pixel electrode. TFT having a transparent conductive film (oxide conductive film) to be formed, wiring portions such as gate wiring and source-drain wiring, and Si semiconductor layers such as amorphous silicon (a-Si) and polycrystalline silicon (p-Si) The substrate is composed of a substrate, a counter substrate disposed facing the TFT substrate at a predetermined interval and provided with a common electrode, and a liquid crystal layer filled between the TFT substrate and the counter substrate.

  Currently, as described above, a-Si is often used in the semiconductor layer of the liquid crystal TFT. However, the next generation display is required to have a large size, high resolution, and high speed drive, and the conventional a-Si has low carrier mobility, so that this required specification cannot be satisfied. Therefore, in recent years, oxide semiconductors have attracted attention. An oxide semiconductor has higher carrier mobility than a-Si. Furthermore, since an oxide semiconductor can be formed in a large area at a low temperature by a sputtering method, a resin substrate having low heat resistance can be used, and as a result, a flexible display can be realized.

  As an example of using such an oxide semiconductor for a semiconductor device, for example, Patent Document 1 discloses a compound obtained by adding IIB element, IIA element, or VIB element to zinc oxide (ZnO) or cadmium oxide (CdO), or Using any of the mixtures, 3d transition metal elements; or rare earth elements; or doped with impurities that make high resistance without losing the transparency of the transparent semiconductor are used. Among oxide semiconductors, oxides (IGZO, ZTO, IZO, ITO, ZnO, AZTO, GZTO) containing at least one element selected from the group consisting of In, Ga, Zn, and Sn are very Since it has high carrier mobility, it is preferably used.

  By the way, in a TFT substrate using an oxide semiconductor typified by IGZO or the like, as a wiring material such as a gate wiring or a source-drain wiring, a Mo or Ti single layer, or an Al alloy such as pure Al or Al—Nd (hereinafter referred to as “aluminum alloy”). These materials are sometimes collectively referred to as “Al-based alloys”.) A laminated material in which a refractory metal (barrier metal layer) such as Ti or Mo is interposed above and / or below is mainly used. Al-based alloys have been adopted for reasons such as low electrical resistance and easy microfabrication. The main reason for using a refractory metal as a wiring material is that Al is very easy to oxidize. If an Al-based alloy wiring is directly connected to an oxide semiconductor layer, oxygen and film formation in the liquid crystal display film formation process will occur. Oxygen that is sometimes added generates a high-resistance Al oxide insulating layer at the interface between the Al-based alloy wiring and the oxide semiconductor layer, which increases the connection resistance (contact resistance) with the oxide semiconductor layer. This is because the display quality deteriorates. However, the use of a refractory metal leads to an increase in cost and a decrease in productivity, so that considering the mass production of liquid crystal displays, it is desired to omit the refractory metal. That is, it is desired to provide a novel wiring material that can reduce the contact resistance even when the barrier metal layer is omitted and the Al-based alloyed wiring is directly connected to the oxide semiconductor layer.

On the other hand, paying attention to the wiring structure of a TFT substrate provided with an oxide semiconductor layer, the wiring structure shown in FIG. 2 (hereinafter sometimes referred to as a conventional structure for convenience of description) is widely used as a TFT structure. ing. In FIG. 2, a gate electrode, a gate insulating film, a semiconductor film, and a source-drain electrode are formed in order from the substrate side. FIG. 2 shows an example of “bottom gate type” in which the gate electrode is on the lower side, but “top gate type” in which the gate electrode is on the upper side is also included. In the case of using an oxide semiconductor, SiO ₂ or SiON is often used as the gate insulating film instead of the SiN film. This is because an oxide semiconductor loses its excellent characteristics in a reducing atmosphere, and therefore it is recommended to use SiO ₂ (SiON) which can be formed in an oxidizing atmosphere.

  However, a conventional TFT substrate using an oxide semiconductor such as IGZO has the following problems. First, when forming a wiring pattern by wet-etching a metal electrode (Al-based wiring material) such as a source-drain electrode formed on the upper layer of IGZO using an acid-based etching solution or the like, IGZO and Al There is no etching selection ratio with the system wiring material (in other words, the etching selectivity is low that only the upper layer Al system wiring material is selectively etched and the lower layer IGZO is not etched). There is a problem of receiving. As a countermeasure for this, for example, a method of providing an etch stopper layer as a protective layer on the channel layer of IGZO has been proposed, but the process becomes complicated and the production cost increases. Second, the conventional structure has a problem that contact resistance between the source / drain electrode and the oxide semiconductor increases when a thermal history of about 250 ° C. or higher is received. In this regard, when a refractory metal such as Ti is interposed, an increase in contact resistance can be suppressed. However, as described above, omission of a refractory metal (barrier metal layer) is strongly desired from the viewpoint of cost and productivity. ing. Ti is formed by dry etching using plasma, but is difficult to apply to wiring materials that are difficult to dry etch, such as Cu.

  Therefore, recently, the wiring structure shown in FIG. 1 in which the order of the oxide semiconductor film and the source-drain electrode is reversed from the conventional structure of FIG. 2 (for the sake of convenience of explanation, the structure of the present invention is different from the conventional structure of FIG. 2). Have been proposed). This has a structure in which a gate electrode, a gate insulating film, a source-drain electrode, and an oxide semiconductor film are formed in this order from the substrate side. As shown in FIG. 1, an oxide semiconductor and a transparent conductive film (ITO in the figure) constituting the pixel electrode are on substantially the same plane as the wiring material constituting the source-drain. FIG. 1 shows an example of a “bottom gate type” in which the gate electrode is on the lower side, but a “top gate type” in which the gate electrode is on the upper side is included as in the conventional structure shown in FIG. The

  If the structure of the present invention shown in FIG. 1 is adopted, it is considered that the problems of the conventional structure of FIG. 2 described above can be solved. However, the structure of the present invention has a problem that the effective channel length cannot be determined if a refractory metal (barrier metal layer) such as Ti or Mo is interposed in a material such as pure Al that cannot directly contact an oxide semiconductor. Yes. That is, when a refractory metal such as Ti or Mo is interposed above and below pure Al, the current flowing between the source-drain electrode and IGZO (for example, since it cannot be electrically connected between pure Al and IGZO) There is a problem that it is difficult to easily determine which one of the upper side and the lower side) should be determined as the effective channel length.

  Therefore, even if the novel Al alloy film applicable to the structure of the present invention shown in FIG. 1 is used and the barrier metal layer is omitted and the Al alloy film is directly connected to the oxide semiconductor layer, the contact resistance is kept low. It is strongly desired to provide a wiring structure provided with the Al alloy film.

JP 2002-76356 A

  The present invention has been made in view of the above circumstances, and an object thereof is to have, in order from the substrate side, an Al alloy film and an oxide semiconductor layer of a thin film transistor connected to the Al alloy film. Wiring structure having a novel Al alloy film for a display device that can realize a low contact resistance even when an Al alloy film is directly connected to an oxide semiconductor layer by omitting a refractory metal (barrier metal layer) such as A method and a display device including the wiring structure are provided.

  The wiring structure of the present invention capable of solving the above-described problems has, on the substrate, in order from the substrate side, an Al alloy film, and a semiconductor layer of a thin film transistor directly connected to the Al alloy film, The semiconductor layer is made of an oxide semiconductor, and the Al alloy film has a gist in that it contains Ni and / or Co.

  In a preferred embodiment, the Al alloy film is directly connected to the transparent conductive film constituting the pixel electrode on the same plane directly connected to the semiconductor layer.

  In a preferred embodiment, the Al alloy film contains 0.10 to 2 atomic% of Ni and / or Co.

  In a preferred embodiment, a part of Ni and / or Co is precipitated and / or concentrated at the interface between the Al alloy film and the oxide semiconductor layer.

  In a preferred embodiment, the Al alloy film further contains 0.05 to 2 atomic% of Cu and / or Ge.

  In a preferred embodiment, the Al alloy film further contains 0.05 to 1 atomic% of a rare earth element.

  In a preferred embodiment, the rare earth element is at least one selected from the group consisting of Nd, La, and Gd.

  In a preferred embodiment, the surface of the Al alloy film that is directly connected to the oxide semiconductor layer is formed with irregularities of 5 nm or more at the maximum height Rz.

  In a preferred embodiment, the surface of the Al alloy film directly connected to the transparent conductive film is formed with irregularities of 5 nm or more at the maximum height Rz.

  In a preferred embodiment, the oxide semiconductor is made of an oxide containing at least one element selected from the group consisting of In, Ga, Zn, Ti, and Sn.

  In a preferred embodiment, the transparent conductive film is made of an oxide containing at least one element selected from the group consisting of In, Ga, Zn, and Sn.

  In a preferred embodiment, the transparent conductive film is ITO or IZO.

  In a preferred embodiment, the thin film transistor has a bottom gate type, and the Al alloy film is used for a source electrode and / or a drain electrode of the thin film transistor.

  The present invention includes a display device having any one of the wiring structures described above.

  Moreover, the manufacturing method of the wiring structure according to the present invention that can solve the above-described problems is the method of forming the Al alloy film, performing a heat treatment at a heating temperature of 200 ° C. or higher after the film formation, and performing an alkali treatment. The oxide semiconductor layer is formed; or the Al alloy film is formed at a substrate temperature of 200 ° C. or higher and then subjected to an alkali treatment, and then the oxide semiconductor layer is formed. The gist is that a part of Ni and / or Co is precipitated and / or concentrated at the interface between the alloy film and the oxide semiconductor layer.

  According to the present invention, in order from the substrate side, in an interconnect structure including an Al alloy film and an oxide semiconductor layer of a thin film transistor connected to the Al alloy film, the Al alloy film is directly connected to the oxide semiconductor layer. However, it was possible to provide a wiring structure capable of realizing a low contact resistance. According to the present invention, since a refractory metal (barrier metal layer) such as Ti or Mo can be omitted, problems with the wiring structure shown in FIG. 1 (for example, the effective channel length is not determined) can be solved.

FIG. 1 is a schematic cross-sectional explanatory view showing a typical wiring structure of the present invention. FIG. 2 is a schematic cross-sectional explanatory view showing a conventional wiring structure. FIG. 3 is a diagram showing an electrode pattern used for measurement of contact resistivity with ITO or IZO in Examples. FIG. 4 is a diagram showing an electrode pattern used for measurement of contact resistivity with IGZO or ZTO in Examples. FIG. 46 TEM images. FIG. 6 is a TEM image of a sample prepared for comparison.

  The present inventors used an oxide semiconductor such as IGZO as a semiconductor layer of a TFT, the structure shown in FIG. 1 (in order from the substrate side, an Al alloy film, an oxide semiconductor layer of a thin film transistor connected to the Al alloy film, and Wiring structure with a low contact resistance even if the Al alloy film is directly connected to the oxide semiconductor layer by omitting refractory metals such as Ti and Mo (barrier metal layer) In order to provide a wiring structure provided with a novel Al alloy film for display devices (hereinafter sometimes referred to as an Al alloy film for direct contact), studies have been made repeatedly. As a result, the inventors have found that the intended purpose can be achieved if an Al alloy film containing Ni and / or Co is used, and the present invention has been completed.

  The Al alloy film is preferably directly connected to a transparent conductive film (typically ITO, IZO, etc.) constituting the pixel electrode (see FIG. 1). Further, an Al alloy film further containing Cu and / or Ge for further reduction of contact resistance, and a rare earth element (typically at least one of Nd, La, and Gd) for further improving heat resistance An Al alloy film is preferably used. Further, in order to form a precipitate and concentrated layer of Ni and / or Co, which are considered to contribute to the realization of a low contact resistance, the surface of the Al alloy film directly connected to the oxide semiconductor layer (and further transparent conductive material). The surface of the Al alloy film directly connected to the film is preferably 5 nm or more at the maximum height Rz. In order to obtain such Ni and / or Co precipitates or concentrated layers, control of the substrate temperature (hereinafter sometimes referred to as film formation temperature) during the formation of an Al alloy (about 200 ° C. or higher) It is effective to appropriately combine the heat treatment) and / or the heat treatment after the Al film formation (heat treatment at about 200 ° C. or higher) and a predetermined alkali treatment. For example, (a) the substrate temperature during film formation is increased to about 200 ° C. or higher, heat treatment is performed, and a predetermined alkali treatment is performed, and then an oxide semiconductor film is formed (in this case, heat treatment after film formation) Is not essential and may or may not be performed), or (b) Regardless of the substrate temperature (the substrate temperature may remain at room temperature without heating, for example, heated to 200 ° C. or higher) Or a method of performing a heat treatment after the Al alloy film formation at a temperature of about 200 ° C. or more, performing a predetermined alkali treatment, and then forming an oxide semiconductor film.

  Hereinafter, preferred embodiments of the wiring structure and the manufacturing method thereof according to the present invention will be described with reference to FIG. 1 described above, but the present invention is not limited thereto. Note that FIG. 1 shows an example of a bottom gate type, but the invention is not limited to this, and a top gate type is also included. In FIG. 1, IGZO is used as a typical example of the oxide semiconductor layer; however, the present invention is not limited thereto, and any oxide semiconductor used for a display device such as a liquid crystal display device can be used.

The TFT substrate shown in FIG. 1 has, in order from the substrate side, a gate electrode (Al alloy in the figure), a gate insulating film (SiO _{2 in the} figure), a source electrode / drain electrode (Al alloy in the figure, details will be described later), It has a wiring structure (bottom gate type) in which a channel layer (oxide semiconductor layer, IGZO in the figure) and a protective layer (SiO _{2 in the} figure) are sequentially laminated. Here, the protective layer of FIG. 1 may be SiON, and similarly, the gate insulating film may be SiON. This is because it is recommended to use a silicon oxide film (SiO ₂ ) or silicon oxynitride film (SiON), which is formed in an oxidizing atmosphere, because the excellent characteristics of oxide semiconductors deteriorate in a reducing atmosphere. Because it is done. Alternatively, either the protective layer or the gate insulating film may be SiN.

  And the characteristic part of this invention exists in the place which used Al alloy containing Ni and / or Co as said Al alloy. By adding Ni and / or Co, the contact electrical resistance (contact resistance) between the Al alloy film constituting the source electrode and / or the drain electrode and the oxide semiconductor layer can be reduced. That is, the Al alloy is extremely useful as an Al alloy for direct contact. Ni and Co may be included singly or both.

  In order to sufficiently exhibit such an effect, the content of the above elements (when Ni or Co is contained alone, it is a single content, and when both are included, it is the total amount) is generally about 0. It is preferable to set it to 10 atomic% or more. The contact resistance can be reduced if the content of the above elements is constant (since addition of a certain amount saturates the contact resistance), more preferably 0.2 atomic% or more, and even more preferably 0.5. It is at least atomic percent. On the other hand, if the content of the element is too large, the electrical resistivity of the Al alloy film increases, so the upper limit is preferably 2 atomic%, and more preferably 1 atomic%.

  The Al alloy film used in the present invention contains Ni and / or Co as described above, and the balance is Al and inevitable impurities.

  The Al alloy film may further contain 0.05 to 2 atomic% of Cu and / or Ge. These are elements that contribute to further reduction in contact resistance, and may be added alone or in combination. In order to sufficiently exhibit such an effect, the content of the above-described elements (when Cu and Ge are contained alone, it is a single content, and when both are contained, the total amount is included) is generally about 0. It is preferable to set it to 05 atomic% or more. The effect of reducing the contact resistance is sufficient if the content of the above elements is a certain amount or more, more preferably 0.1 atomic% or more, still more preferably 0.2 atomic% or more. On the other hand, if the content of the element is too large, the electrical resistivity of the Al alloy film increases, so the upper limit is preferably 2 atomic%, and more preferably 1 atomic%.

  The Al alloy film may further contain 0.05 to 1 atomic% of a rare earth element. These are elements useful for improving heat resistance, and may contain one kind of rare earth element, or two or more kinds may be used in combination. More preferable content of the above-mentioned elements (in the case of including alone, the content is independent, and in the case of including two or more types, the total amount) is 0.1 to 0.5 atomic%, more preferably 0.2. ~ 0.35 atomic%. Here, the rare earth element is an element group in which Sc (scandium) and Y (yttrium) are added to a lanthanoid element (a total of 15 elements from La with atomic number 57 to Lu with atomic number 71 in the periodic table). means. Of these, for example, La, Nd, Y, Gd, Ce, and Dy are preferably used, more preferably La, Nd, and Gd, and still more preferably La and Nd.

  The content of each alloy element in the Al alloy film can be determined by, for example, an ICP emission analysis (inductively coupled plasma emission analysis) method.

  In the present invention, it is only necessary that at least the source electrode and / or the drain electrode are made of the Al alloy film, and the component composition of other wiring portions (for example, the gate electrode) is not particularly limited. For example, in FIG. 1, the gate electrode, the scanning line (not shown), and the drain wiring part (not shown) in the signal line may also be constituted by the Al alloy film. In this case, the Al alloy in the TFT substrate is used. All of the wirings can have the same component composition.

  As demonstrated in the examples described later, according to the present invention, the contact resistance between the oxide semiconductor and the Al alloy film can be kept low. This is because (a) Ni and / or Co formed at the interface thereof. And / or (b) a concentrated layer containing Ni and / or Co is presumed to be deeply involved. In the case where the Al alloy film further contains Cu and / or Ge or a rare earth element, it is considered that a precipitate or a concentrated layer further containing these elements is formed at the interface. Such precipitates and concentrated layers have high conductivity unlike Al oxides, and are formed partially or entirely at the interface between the oxide semiconductor and the Al alloy film as a region with low electrical resistance. Thus, the contact resistance is expected to be greatly reduced.

  The precipitation and / or concentration of Ni and / or Co is preferably performed by combining a predetermined heat treatment and a predetermined alkali treatment. Ni or the like contained in the Al alloy is precipitated on the surface by the heat treatment, and the precipitate can be exposed and the oxide film can be removed by the alkali treatment. By performing both treatments in this way, contact resistance can be reduced. It can be significantly reduced. Typically, the alkali treatment includes a method of immersing in an about 0.4 mass% aqueous solution of TMAH (tetramethylammonium hydroxide) for about 60 seconds. In addition, treatment with an acid or physical oxide film removal by Ar plasma irradiation is also applicable. Details of the alkali treatment applicable to the present invention will be described in the explanation section of Rz described later.

  Specifically, the heat treatment is performed by controlling the substrate temperature (film formation temperature) during the Al alloy film formation by sputtering (heat treatment at about 200 ° C. or higher) and / or the heat treatment after the Al film formation (about about It is effective to appropriately combine the heat treatment at 200 ° C. or higher. Details of the sputtering method will be described later. Specifically, (a) the film formation temperature is increased to about 200 ° C. or higher, heat treatment is performed, and a predetermined alkali treatment is performed, and then an oxide semiconductor film is formed (in this case, the heat treatment after film formation is (B) Regardless of the film formation temperature (the substrate may be left at room temperature without being heated, for example, heated to 200 ° C. or higher). Or a method of forming an oxide semiconductor film by performing a predetermined alkali treatment after performing the heat treatment after the Al alloy film formation at a temperature of about 200 ° C. or higher. Note that, in the wiring structure having an oxide semiconductor on an Al alloy film as in the present invention, the heat treatment method of (a) above (a) is performed after film formation without heating the substrate. It is recommended to adopt an alkali treatment method after treatment. As a result, it is possible to effectively prevent the contact resistance from being increased by forming a natural oxide film such as alumina on the surface after the Al alloy film is formed.

  In any of the above (a) and (b), the heat treatment time at 200 ° C. or higher is preferably 5 minutes or longer and 60 minutes or shorter. The upper limit of the substrate temperature (a) is preferably 250 ° C. On the other hand, the post-deposition heating temperature in (a) is preferably 250 ° C. or higher. In consideration of the heat-resistant temperature of the substrate, hillock resistance, etc., it is preferable that the heating temperature after film formation in (a) is about 350 ° C. or less.

  The heat treatment performed after the formation of the Al alloy film may be performed for the purpose of the precipitation / concentration, or a thermal history after the formation of the Al alloy film (for example, a SiN film is formed). Step) may satisfy the temperature and time.

  The Al alloy film is desirably formed by a sputtering method using a sputtering target (hereinafter also referred to as “target”). This is because a thin film having excellent in-plane uniformity of components and film thickness can be easily formed as compared with a thin film formed by ion plating, electron beam vapor deposition or vacuum vapor deposition. In order to form the Al alloy film by sputtering, Al having the same composition as the Al- (Ni / Co) alloy (preferably further containing Cu / Ge or a rare earth element) is used as the target. If an alloy sputtering target is used, there is no fear of composition deviation, and an Al alloy film having a desired component composition can be formed. The shape of the target includes those processed into an arbitrary shape (such as a square plate shape, a circular plate shape, or a donut plate shape) according to the shape or structure of the sputtering apparatus. As a method for producing the above target, a method of producing an ingot made of an Al-based alloy by a melt casting method, a powder sintering method, or a spray forming method, or a preform made of an Al-based alloy (the final dense body is prepared) Examples thereof include a method obtained by producing an intermediate before being obtained) and then densifying the preform by a densification means.

Moreover, it is preferable that the surface of the Al alloy film directly connected to the oxide semiconductor layer has irregularities with a maximum height Rz of 5 nm or more. This is because, before the Al alloy film formed as described above is directly connected to the oxide semiconductor layer, the surface of the Al alloy film is wet-etched with an alkali solution or with a mixed gas of SF ₆ and Ar. It can be obtained by dry etching the surface of the Al alloy film. As a result, Al is eluted, and Ni and Co, which are noble alloy elements than Al, are included in the intermetallic compound and are deposited on the surface of the Al alloy film, and remain as irregularities on the surface of the Al alloy. And when this unevenness | corrugation is 5 nm or more by maximum height Rz, contact resistance is reduced. Here, the maximum height Rz is based on JIS B0601 (JIS standard after 2001 revision) (evaluation length is 4 mm).

  When the unevenness as described above is formed on the surface of the Al alloy film, an oxide (AlOx) that has a high contact electric resistance is hardly formed even if it is in direct contact with the oxide semiconductor layer thereafter. In some cases, a precipitate containing a metal element nobler than Al is in direct contact with the transparent conductive film. By realizing such a situation, low contact electric resistance in the oxide semiconductor layer and the Al alloy film can be realized. The larger the maximum height Rz is, the better. In general, it is preferably 8 nm or more, and more preferably 10 nm or more. Considering improvement in production efficiency and product quality maintenance such as prevention of disconnection of the transparent conductive film, the upper limit of the maximum height Rz is preferably about 100 nm, more preferably about 50 nm.

  In forming the irregularities as described above in the Al alloy film, the Al alloy film surface may be wet-etched or dry-etched with an alkaline solution prior to directly connecting the Al alloy film and the oxide semiconductor layer. The etching amount (etching depth) at this time is preferably 5 nm or more in order to realize 5 nm or more in the maximum height Rz of the unevenness to be formed. In addition, the etching process may be performed before the Al alloy film and the oxide semiconductor layer are physically directly connected, for example, before an interlayer insulating film such as silicon nitride (SiNx) is formed. The same effect is exhibited.

  Alkaline solution for wet etching as described above is generally about pH 9 to 13 (preferably about pH 10.5 to 12.8) and elutes Al but elutes metal elements that are more precious than Al. Not alkaline solution. Specifically, for example, an aqueous solution of a resist stripping solution “TOK106” (trade name: manufactured by Tokyo Ohka Kogyo Co., Ltd.) having a pH of about 9 to 13, or an alkaline solution (AZ 300MIF manufactured by AZ Electronic Materials Co., Ltd.) used in Examples described later Developer), a developer stock solution containing TMAH (tetramethylammonium hydroxide), a solution obtained by diluting the stock solution for pH adjustment (pH of about 10.5 to 13.5), a sodium hydroxide aqueous solution, and the like. The above “TOK106” is a mixed solution of monoethanolamine and dimethylsulfoxide (DMSO), and the pH range can be adjusted by the mixing ratio thereof. The preferred temperature and time for wet etching may be appropriately determined according to the alkaline solution used or the composition of the Al alloy, etc., so that the desired maximum height Rz can be obtained. It is preferably 5 to 180 seconds (preferably 10 to 120 seconds at 30 to 60 ° C.).

As a gas for dry etching, a mixed gas of SF ₆ and Ar (for example, SF ₆ : 60%, Ar: 40% (both volume%)) can be used. Generally, a mixed gas of SF ₆ , Ar, and O ₂ is used as a mixed gas when dry-etching the silicon nitride film after the silicon nitride film is formed. The object of the invention cannot be achieved. The preferable conditions for dry etching may be appropriately determined according to the type of mixed gas used, the composition of the Al alloy, and the like so that the desired maximum height Rz can be obtained.

  By performing the etching process using the alkali solution or mixed gas as described above, the precipitate containing the metal element as described above is concentrated on the surface of the Al alloy film.

  The Al alloy film used in the present invention may preferably be directly connected to a transparent conductive film such as ITO or IZO. In this case, the surface of the Al alloy film directly connected to the transparent conductive film is Similar to the above, it is preferable that irregularities of 5 nm or more are formed at the maximum height Rz. Thereby, low contact resistance with a transparent conductive film is achieved. A preferable range of Rz and a control method thereof may be performed in the same manner as described above.

  The Al alloy film that characterizes the present invention has been described in detail above.

  The present invention is characterized by the above-mentioned Al alloy film, and other constituent requirements are not particularly limited.

  The oxide semiconductor layer is not particularly limited as long as it is an oxide semiconductor used for a liquid crystal display device or the like. For example, at least one element selected from the group consisting of In, Ga, Zn, Ti, and Sn A material made of an oxide containing is used. Specifically, as the above oxide, In oxide, In—Sn oxide, In—Zn oxide, In—Sn—Zn oxide, In—Ga oxide, Zn—Sn oxide, Zn—Ga oxide AZTO and GZTO in which Al or Ga is doped into a transparent oxide such as In—Ga—Zn oxide, Zn oxide, or Ti oxide, or Zn—Sn oxide.

  In addition, as the transparent conductive film constituting the pixel electrode, an oxide conductive film usually used in a liquid crystal display device or the like can be given. For example, at least one element selected from the group consisting of In, Ga, Zn, and Sn A material made of an oxide containing is used. Typically, amorphous ITO, poly-ITO, IZO, ZnO and the like are exemplified.

Further, an insulating film such as a gate insulating film or a protective film formed on the oxide semiconductor (hereinafter, may be represented by an insulating film) is not particularly limited, and is usually used, for example, SiN, Examples thereof include SiO ₂ and SiON. However, from the viewpoint of effectively exhibiting the characteristics of the oxide semiconductor, it is preferable to use SiO ₂ or SiON that can be formed in an acidic atmosphere. Specifically, the insulating film does not necessarily need to be composed of only SiO ₂ , and any insulating film containing at least oxygen that can effectively exhibit the characteristics of the oxide semiconductor is used in the present invention. be able to. For example, a material in which only the surface of SiO ₂ is nitrided or a material in which only the surface of Si is oxidized may be used. When the insulating film contains oxygen, the thickness of the insulating film is preferably approximately 0.17 nm to 3 nm. In addition, the maximum value of the ratio ([O] / [Si]) of the number of oxygen atoms ([O]) and the number of Si atoms ([Si]) in the oxygen-containing insulating film is generally 0.3 or more. It is preferably within the range of 0 or less.

  The substrate is not particularly limited as long as it is used for a liquid crystal display device or the like. Typically, a transparent substrate represented by a glass substrate or the like can be given. The material of the glass substrate is not particularly limited as long as it is used for a display device, and examples thereof include alkali-free glass, high strain point glass, and soda lime glass. Further, a metal foil, a heat-resistant resin substrate such as an imide resin, or the like is also used.

  In manufacturing a display device having the above wiring structure, there is no particular limitation, except that the conditions of the present invention are satisfied and the heat treatment / thermal history conditions of the Al alloy film are set to the recommended conditions described above. What is necessary is just to employ | adopt the general process of an apparatus.

  EXAMPLES Hereinafter, the present invention will be described more specifically with reference to examples. However, the present invention is not limited by the following examples, and may be implemented with appropriate modifications within a range that can meet the above and the following purposes. All of these are possible within the scope of the present invention.

Example 1
An alkali-free glass plate (thickness: 0.7 mm) is used as a substrate, and an Al alloy film (residue: Al and unavoidable impurities) having various alloy compositions shown in Table 1 is formed on the surface by DC magnetron sputtering. Filmed. The film forming conditions are as follows. In addition, as a sputtering target, the Al alloy target of the various composition produced with the vacuum melting method was used.
(Al film deposition conditions)
・ Atmosphere gas = Argon ・ Pressure = 2 mTorr
・ Substrate temperature = 25 ° C. (room temperature) or 200 ° C. for 30 minutes ・ Film thickness = 300 nm

  The content of each alloy element in the Al alloy film was determined by an ICP emission analysis (inductively coupled plasma emission analysis) method.

  Using the Al alloy film formed as described above, the electrical resistivity of the Al alloy film itself after the heat treatment, and the Al alloy film directly on the transparent pixel electrode (ITO, IZO) and oxide semiconductor (IGZO, ZTO). The direct contact resistance (contact resistance with ITO, contact resistance with ZTO, contact resistance with IGZO, or contact resistance with IZO) at the time of connection was measured by the following methods.

(1) Electrical resistivity of the Al alloy film itself after heat treatment The Al alloy film was subjected to a heat treatment at 250 ° C. for 15 minutes in an inert gas atmosphere, and then the electrical resistivity was measured by a four-probe method. . And the quality of the electrical resistivity of Al alloy film itself after heat processing was determined on the following reference | standard.
(Criteria)
○: Less than 5.0 μΩ · cm ×: 5.0 μΩ · cm or more

(2) Contact resistance with transparent pixel electrode (ITO) The Al alloy film formed as described above was sequentially subjected to photolithography and etching to form the electrode pattern shown in FIG. Next, a silicon nitride (SiNx) film having a film thickness of 300 nm was formed by a CVD apparatus. The film formation temperature at this time was 250 ° C. or 320 ° C. as shown in Table 1. The film formation time is 15 minutes. Based on the thermal history at this time, alloy elements were deposited as precipitates. Subsequently, photolithography and etching using a RIE (Reactive Ion Etching) apparatus were performed to form contact holes in the silicon nitride film. After the contact hole is formed, the resist is removed, and the Al alloy thin film surface is wet-treated at room temperature with an alkaline solution (aqueous solution obtained by diluting AZ 300MIF developer (2.38 wt%) of AZ Electronic Materials Co., Ltd. to 0.4%). Etching was performed. Next, the height Rz [maximum height Rz based on JIS B0601 (2001)] of the convex portion of the Al alloy thin film was measured. The maximum height Rz was measured using a Mitutoyo surface roughness measuring instrument SJ-301. The evaluation length was 4 mm, and the quality of the maximum height Rz was determined according to the following criteria.
(Criteria)
○: 5 nm or more ×: less than 5 nm

After that, an ITO film (transparent conductive film) was formed by sputtering under the following conditions, photolithography and patterning were performed, and a contact chain pattern in which 50 10 μm square contact portions were connected in series (see FIG. 3). ) Was formed. In FIG. 3, the line width of the Al alloy and ITO is 80 μm.
(ITO film formation conditions)
・ Atmosphere gas = Argon ・ Pressure = 0.8 mTorr
-Substrate temperature = 25 ° C (room temperature)
・ Film thickness = 200 nm

Using the Precision Semiconductor Parameter Analyzer of HEWLETT PACKARD 4156A and Agilent Technologies 4156C, the probe is brought into contact with the pads at both ends of the contact chain pattern. It was obtained by measuring the IV characteristics. And the contact resistance value converted into one contact was calculated | required, and the quality of the direct contact resistance (ITO contact resistance with ITO) was determined by the following reference | standard. In this example, ○ or Δ was accepted.
(Criteria)
○: Less than 1000Ω Δ: 1000Ω or more and less than 3000Ω ×: 3000Ω or more

(3) Contact resistance with transparent pixel electrode (IZO) Except that IZO was used instead of ITO, (2) Various heat treatments were performed on the Al alloy film in the same manner as in the case of (2) Contact resistance with ITO. Then, wet treatment was performed and etching was performed, and the maximum height Rz of the convex portion of the Al alloy thin film was measured.

After that, an IZO film (transparent conductive film) was formed by sputtering under the following conditions, photolithography and patterning were performed, and a contact chain pattern in which 50 10 μm square contact portions were connected in series (see FIG. 3). ) Was formed. In FIG. 3, the line width of the Al alloy and IZO is 80 μm.
(IZO film formation conditions)
・ Atmosphere gas = Argon ・ Pressure = 0.8 mTorr
-Substrate temperature = 25 ° C (room temperature)
・ Film thickness = 200 nm

The total resistance (contact resistance, connection resistance) of the contact chain is measured in the same manner as (2) described above, the contact resistance value converted into one contact is obtained, and the direct contact resistance ( The quality of contact resistance with IZO was determined. In this example, ○ or Δ was accepted.
(Criteria)
○: Less than 1000Ω Δ: 1000Ω or more and less than 3000Ω ×: 3000Ω or more

(4) Contact resistance with oxide semiconductor (IGZO) Except for using the electrode pattern shown in FIG. Heat treatment was performed, wet treatment was performed, etching was performed, and the maximum height Rz of the convex portion of the Al alloy thin film was measured.

Thereafter, an IGZO film was formed by sputtering under the following conditions, and photolithography and patterning were performed to form a contact chain pattern in which 100 80 μm square contacts were connected in series. In FIG. 4, the line width of Al alloy and IGZO is 80 μm. In this embodiment, as shown in the table, IGZO films having different atomic ratios are manufactured. Specifically, as a sputtering target for the IGZO film, a target of In: Ga: Zn = 1: 1: 1 and 2: A 2: 1 target was used.
(Oxide semiconductor deposition conditions)
・ Atmosphere gas = Argon ・ Pressure = 5 mTorr
-Substrate temperature = 25 ° C (room temperature)
・ Film thickness = 100 nm

The total resistance (contact resistance, connection resistance) of the contact chain is measured in the same manner as (2) described above, the contact resistance value converted into one contact is obtained, and the direct contact resistance with IGZO ( The quality of contact resistance with IGZO was determined. In this example, ○ or Δ was accepted.
(Criteria)
○: Less than 1000Ω Δ: 1000Ω or more and less than 3000Ω ×: 3000Ω or more

(5) Contact resistance with oxide semiconductor (ZTO) Except for using the electrode pattern shown in FIG. Heat treatment was performed, wet treatment was performed, etching was performed, and the maximum height Rz of the convex portion of the Al alloy thin film was measured.

Thereafter, a ZTO film was formed by sputtering under the following conditions, and photolithography and patterning were performed to form a contact chain pattern in which 100 80 μm square contacts were connected in series. In FIG. 4, the line width of Al alloy and ZTO is 80 μm. The composition used for the sputtering target of ZTO was Zn: Sn = 2: 1.
(Oxide semiconductor deposition conditions)
・ Atmosphere gas = Argon ・ Pressure = 5 mTorr
-Substrate temperature = 25 ° C (room temperature)
・ Film thickness = 100 nm

The total resistance (contact resistance, connection resistance) of the contact chain is measured in the same manner as (2) described above, the contact resistance value converted into one contact is obtained, and the direct contact resistance with ZTO ( The quality of contact resistance with ZTO was determined. In this example, ○ or Δ was accepted.
(Criteria)
○: Less than 1000Ω Δ: 1000Ω or more and less than 3000Ω ×: 3000Ω or more

(6) Precipitate density The density of the precipitate was determined using a backscattered electron image of a scanning electron microscope. Specifically, the number of precipitates in one field of view (100 μm ² ) was measured, the average value of the three fields of view was determined, and the quality of the precipitate density was determined according to the following criteria. In this example, ○ or Δ was accepted.
(Criteria)
○: 40 or more △: 30 or more and less than 40 ×: less than 30

  These results are summarized in Tables 1 and 2.

  In Table 1, the column of “Heating film formation (200 ° C.)” means the substrate temperature at the time of Al alloy film formation, “◯” is an example in which the substrate temperature is 200 ° C., and “−” is the substrate temperature is room temperature. This is an example.

  In Table 1, in the column of “maximum height Rz of Al alloy film”, the results of Rz of the Al alloy film directly connected to ITO, IZO, ZTO, and IGZO are collectively shown. Both determination results mean ◯ (Rz 5 nm or more), and “x” means that both determination results are x (less than Rz 5 nm).

  From the results shown in Tables 1 and 2, it can be considered as follows.

  First, when an Al alloy (Ni and / or Co, further Cu and / or Ge, and further a rare earth element) defined in the present invention is used, pure Al (No. 1) is obtained while maintaining a low electrical resistivity. Compared with the case where it used, contact resistance with IGZO (oxide semiconductor), ZTO (oxide semiconductor), ITO (transparent conductive film), and IZO (transparent conductive film) was able to be reduced (No. 3- 5, 8-10, 13-19, 22-25, 27, 28, 31-34, 37-40, 42-44, 46, 48-50).

  Specifically, a precipitate / concentrated layer of Ni and / or Co is formed at the interface between these Al alloy films and IGZO, ZTO, ITO, or IZO, and the maximum height Rz of the Al alloy film is All were 5 nm or more. Speaking of heat treatment conditions, no. When the substrate temperature at the time of forming the Al alloy film is heated to 200 ° C. (heated film formation) as shown in FIG. 3-5, 8-10, 14, 16, 24, 25, 27 or no. No. 28, when the heating temperature after film formation of the Al alloy was increased to 250 ° C. or 320 ° C. without heating the substrate (with room temperature); 15 or No. In any case where the substrate temperature is heated to 200 ° C. (heating film formation) as in 17 and the heating temperature after the Al alloy film formation is increased to 250 ° C. or 320 ° C., the maximum height Rz of the Al alloy film is The contact resistance was kept low because the thickness was 5 nm or more. In addition, No. In the example in which the thermal film formation was performed as shown in No. 13, the contact resistance with IGZO, ZTO, ITO, and IZO slightly increased (Δ) as shown in Table 1, but there is no practical problem. No. In Nos. 3 and 8, the amount of Ni or Co added is small, the precipitate density is low (Δ), and the contact resistance is slightly increased (Δ), but there is no practical problem.

  FIG. Although it is a TEM image which shows the state of the interface of 46 Al alloy (Al-2 atomic% Ni-0.35 atomic% La) and IGZO (In: Ga: Zn (atomic ratio) = 1: 1: 1). (Example of wet treatment and heat treatment) As shown in FIG. 5, precipitates containing Ni were formed at the interface between the Al alloy and IGZO, and it was confirmed that they were in direct contact with IGZO. For comparison, FIG. 46 is a TEM image showing the state of the interface between the Al alloy having the same alloy composition as IGZO and IGZO. In this comparative example, neither wet treatment nor heat treatment was performed, and the interface between the Al alloy and IGZO as shown in FIG. It was confirmed that a precipitate containing Ni and / or a concentrated layer containing Ni was not formed.

  In contrast, no. No. 12 is an example in which neither the heat film formation nor the heat treatment after the Al alloy film formation was performed, and the maximum height Rz of the Al alloy film was less than 5 nm, and the contact resistance with IGZOZTO, ITO, and IZO Rose.

  No. 6, 20, 26 and no. No. 41 is an example with a large amount of Ni. 11, 29, 35 and no. No. 51 is an example in which the amount of Co is large, and in all cases, the electrical resistivity increased.

  On the other hand, no. 2, 21 and no. No. 36 is an example in which the amount of Ni is small. 7, 30 and no. No. 47 is an example in which the amount of Co is small. In all cases, the precipitate density is not sufficient, and the contact resistance with IGZO, ZTO, ITO, and IZO is increased.

  No. No. 45 was an example in which the wet treatment was not performed, and the maximum height Rz of the Al alloy film was less than 5 nm, the precipitate density was not sufficient, and the contact resistance with IGZO, ZTO, ITO, and IZO was increased.

  In each alloy composition in Table 1, Nd and La do not adversely affect the reduction of contact resistance with IGZO, ZTO, ITO, and IZO, and La is used instead of Nd and Nd is used instead of La. However, it has been confirmed by experiments that similar results can be obtained. Similarly, it has been confirmed by experiments that the same result can be obtained even if Gd is used instead of Nd or La.

Claims (14)

On the substrate, in order from the substrate side, an Al alloy film, and a thin film transistor semiconductor layer directly connected to the Al alloy film,
The semiconductor layer is made of an oxide semiconductor,
The Al alloy film includes Ni and / or Co.   The wiring structure according to claim 1, wherein the Al alloy film is directly connected to a transparent conductive film constituting a pixel electrode on the same plane directly connected to the semiconductor layer.   The wiring structure according to claim 1, wherein the Al alloy film contains 0.10 to 2 atomic% of Ni and / or Co.   The wiring structure according to claim 1, wherein a part of Ni and / or Co is precipitated and / or concentrated at an interface between the Al alloy film and the oxide semiconductor layer.   The wiring structure according to claim 1, wherein the Al alloy film further contains 0.05 to 2 atomic% of Cu and / or Ge.   The wiring structure according to claim 1, wherein the Al alloy film further contains 0.05 to 1 atom% of a rare earth element.   The wiring structure according to claim 6, wherein the rare earth element is at least one selected from the group consisting of Nd, La, and Gd.   The wiring structure according to any one of claims 1 to 7, wherein a surface of the Al alloy film directly connected to the oxide semiconductor layer is formed with irregularities of 5 nm or more at a maximum height Rz.   The wiring structure according to any one of claims 2 to 8, wherein the surface of the Al alloy film directly connected to the transparent conductive film is formed with irregularities of 5 nm or more at a maximum height Rz.   The wiring structure according to claim 1, wherein the oxide semiconductor is made of an oxide containing at least one element selected from the group consisting of In, Ga, Zn, Ti, and Sn. .   The wiring structure according to claim 2, wherein the transparent conductive film is made of an oxide containing at least one element selected from the group consisting of In, Ga, Zn, and Sn.   The wiring structure according to claim 2, wherein the transparent conductive film is ITO or IZO.   A display device comprising the wiring structure according to claim 1. A method for manufacturing a wiring structure according to any one of claims 4 to 12,
The Al alloy film is formed and heat-treated at a heating temperature of 200 ° C. or higher after the film formation, and then the oxide semiconductor layer is formed after alkali treatment, or the Al alloy film is heated to 200 ° C. or higher. After forming the film at the substrate temperature, the oxide semiconductor layer is formed by performing an alkali treatment, whereby a part of Ni and / or Co is formed at the interface between the Al alloy film and the oxide semiconductor layer. A method of manufacturing a wiring structure, characterized by depositing and / or concentrating.