JP2011091364A - Wiring structure and method of manufacturing the same, as well as display apparatus with wiring structure - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring structure, which includes an insulation film, a Cu alloy film, and a thin-film transistor oxide semiconductor layer formed sequentially from a substrate side, exhibits excellent adhesiveness even when the Cu alloy film is electrically and directly connected to the substrate and/or insulation film while omitting a barrier metal layer of such as Ti and Mo, and achieves low electric resistance as a characteristic of Cu material, and low contact resistance with a transparent conductive film for structuring the oxide semiconductor layer and/or pixel electrode. <P>SOLUTION: The Cu alloy film includes a lamination structure having a first layer (Y) formed of Cu alloy containing a total of 2-20 at% at least one element selected from a group of Zn, Ni, Ti, Al, Mg, Ca, W, Nb, and Mn, and a second layer (X) formed of pure Cu or Cu alloy which mainly contains Cu and has low electrical resistivity than the first layer (Y). The first layer (Y) is directly connected to the substrate and/or the insulation film. The second layer (X) is directly connected to the semiconductor layer. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention is a wiring structure including an insulating film, a Cu alloy film, and a semiconductor layer of a thin film transistor in order from the substrate side, and the semiconductor layer includes an oxide semiconductor layer made of an oxide semiconductor. The present invention relates to a wiring structure, a manufacturing method thereof, and a display device including the wiring structure. The wiring structure of the present invention is typically used for flat panel displays such as liquid crystal displays (liquid crystal display devices) and organic EL displays. In the following, a liquid crystal display device will be typically taken up and described, but the present invention is not limited to this.

  A liquid crystal display device used in various fields ranging from a small mobile phone to a large-sized television exceeding 30 inches uses a thin film transistor (hereinafter referred to as “TFT”) as a switching element, and constitutes a pixel electrode. TFT having a transparent conductive film (oxide conductive film) to be formed, wiring portions such as gate wiring and source-drain wiring, and Si semiconductor layers such as amorphous silicon (a-Si) and polycrystalline silicon (p-Si) The substrate is composed of a substrate, a counter substrate disposed facing the TFT substrate at a predetermined interval and provided with a common electrode, and a liquid crystal layer filled between the TFT substrate and the counter substrate.

  Currently, as described above, a-Si is often used in the semiconductor layer of the liquid crystal TFT. However, the next generation display is required to have a large size, high resolution, and high speed drive, and the conventional a-Si has low carrier mobility, so that this required specification cannot be satisfied. Therefore, in recent years, oxide semiconductors have attracted attention. An oxide semiconductor has higher carrier mobility than a-Si. Furthermore, since an oxide semiconductor can be formed in a large area at a low temperature by a sputtering method, a resin substrate having low heat resistance can be used, and as a result, a flexible display can be realized.

  As an example of using such an oxide semiconductor for a semiconductor device, for example, Patent Document 1 discloses that zinc oxide (ZnO), cadmium oxide (CdO), zinc oxide (ZnO), IIB element, IIA element, or VIB element Any one of a compound added with a compound or a mixture is used, which is doped with an impurity that makes a high resistance without losing transparency of a 3d transition metal element; or a rare earth element; or a transparent semiconductor. Among oxide semiconductors, oxides (IGZO, ZTO, IZO, ITO, ZnO, AZTO, GZTO) containing at least one element selected from the group consisting of In, Ga, Zn, and Sn are very Since it has high carrier mobility, it is preferably used.

By the way, in a display device typified by a liquid crystal display device or the like, an Al-based alloy such as pure Al or Al—Nd, which has a relatively small electrical resistance and is easily finely processed, is used as a wiring material such as a gate wiring and a source-drain wiring. Many are used. However, problems such as signal delay and power loss due to a large wiring resistance are becoming apparent as the display device is increased in size and image quality. Therefore, copper (Cu) having a lower resistance than Al is attracting attention as a wiring material. The electrical resistivity of the Al thin film is 3.0 × 10 ⁻⁶ Ω · cm, whereas the electrical resistivity of the Cu thin film is as low as 2.0 × 10 ⁻⁶ Ω · cm.

  However, Cu has a problem in that it has low adhesion to a glass substrate and an insulating film (such as a gate insulating film) formed thereon and peels off. Moreover, since Cu has low adhesion to a glass substrate or the like, there is a problem that it is difficult to perform wet etching or dry etching for processing into a wiring shape. Therefore, various techniques for improving the adhesion between Cu and the glass substrate have been proposed.

For example, Patent Documents 2 to 4 disclose techniques for improving adhesion by interposing a refractory metal layer such as molybdenum (Mo) or chromium (Cr) between a Cu wiring and a glass substrate. However, these techniques increase the number of steps for forming a refractory metal layer and increase the manufacturing cost of the display device. Further, since different metals such as Cu and a refractory metal (Mo or the like) are laminated, there is a possibility that corrosion occurs at the interface between Cu and the refractory metal during wet etching. In addition, since these different kinds of metals have different etching rates, there is a problem that the wiring cross section cannot be formed into a desired shape (for example, a shape having a taper angle of about 45 to 60 °). Furthermore, the electrical resistivity (about 15 × 10 ⁻⁶ Ω · cm) of a refractory metal such as Cr is higher than that of Cu, and signal delay and power loss due to wiring resistance are problematic.

  On the other hand, paying attention to the wiring structure of a TFT substrate provided with an oxide semiconductor layer, the wiring structure shown in FIG. 2 (hereinafter sometimes referred to as a conventional structure for convenience of description) is widely used as a TFT structure. ing. In FIG. 2, a gate electrode, a gate insulating film, an oxide semiconductor film, and a source-drain electrode are formed in order from the substrate side, and a metal electrode such as a source-drain electrode is formed in an upper layer of IGZO. The semiconductor device described in Patent Document 1 described above also has this conventional structure. FIG. 2 shows an example of “bottom gate type” in which the gate electrode is on the lower side, but “top gate type” in which the gate electrode is on the upper side is also included. In the case of using an oxide semiconductor, silicon oxide or silicon oxynitride is often used as a gate insulating film instead of a silicon nitride film. This is because the use of silicon oxide (silicon oxynitride) that can form a film in an oxidizing atmosphere is recommended because an oxide semiconductor loses its excellent characteristics in a reducing atmosphere.

  However, a conventional TFT substrate using an oxide semiconductor such as IGZO has the following problems. First, when forming a wiring pattern by wet-etching a metal electrode (Cu-based wiring material) such as a source-drain electrode formed on the upper layer of IGZO using an acid-based etching solution or the like, IGZO and Cu There is no etching selectivity with the system wiring material (in other words, the etching selectivity is low that only the upper layer Cu system wiring material is selectively etched and the lower layer IGZO is not etched). There is a problem of receiving. As a countermeasure for this, for example, a method of providing an etch stopper layer as a protective layer on the channel layer of IGZO has been proposed, but the process becomes complicated and the production cost increases. Second, the conventional structure has a problem that contact resistance between the source / drain electrode and the oxide semiconductor increases when a thermal history of about 250 ° C. or higher is received. In this regard, when a refractory metal such as Ti is interposed, an increase in contact resistance can be suppressed. However, as described above, omission of a refractory metal (barrier metal layer) is strongly desired from the viewpoint of cost and productivity. ing. Ti is formed by dry etching using plasma, but is difficult to apply to wiring materials that are difficult to dry etch, such as Cu.

  Therefore, recently, the wiring structure shown in FIG. 1 in which the order of the oxide semiconductor film and the source-drain electrode is reversed from the conventional structure of FIG. 2 (for the sake of convenience of explanation, the structure of the present invention is different from the conventional structure of FIG. 2). Have been proposed (for example, Non-Patent Document 1). This has a structure in which a gate electrode, a gate insulating film, a source-drain electrode, and an oxide semiconductor film are formed in this order from the substrate side. As shown in FIG. 1, an oxide semiconductor and a transparent conductive film (ITO in the figure) constituting the pixel electrode are on substantially the same plane as the wiring material constituting the source-drain. FIG. 1 shows an example of a “bottom gate type” in which the gate electrode is on the lower side, but a “top gate type” in which the gate electrode is on the upper side is included as in the conventional structure shown in FIG. The

  If the structure of the present invention shown in FIG. 1 is adopted, it is considered that the problems of the conventional structure of FIG. 2 described above can be solved. However, in the structure of the present invention, when a high melting point metal (barrier metal layer) such as Ti or Mo and a different material such as pure Cu are stacked, the contact resistance with the oxide semiconductor may be different. There is a problem that the channel length is not easily determined. That is, when a refractory metal such as Ti or Mo is interposed above or below pure Cu, when the contact resistance between Ti or Mo and an oxide semiconductor is larger than the value of pure Cu, or vice versa. There is a problem that it is difficult to easily determine which of the currents flowing between the source / drain electrodes and the IGZO should be determined as the effective channel length.

  Therefore, a novel Cu alloy film applicable to the wiring structure shown in FIG. 1, in which a barrier metal layer is omitted and a Cu alloy film is formed on a substrate and / or silicon oxide or silicon oxynitride provided on the substrate. Even if it is electrically connected directly to an insulating film composed of, etc., it has excellent adhesiveness with these, and has a low electrical resistance characteristic of a Cu-based material, an oxide semiconductor layer and / or a pixel electrode It is strongly desired to provide a wiring structure including a Cu alloy film in which a low contact resistance with the transparent conductive film constituting the film is maintained.

JP 2002-76356 A JP-A-7-66423 JP-A-8-8498 JP-A-8-138461

Takeshi Osada et al., "Development of Driver-Integrated Panel using Amorphous In-Ga-Zn-Oxide TFT", THE PROCEEDING OF AM-FPD '09, p. 33-36, July 1-3, 2009

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a wiring structure including an insulating film, a Cu alloy film, and an oxide semiconductor layer of a thin film transistor in order from the substrate side. Even if the refractory metal (barrier metal layer) such as Mo and Mo is omitted and the Cu alloy film is electrically connected directly to the substrate and / or the insulating film, it has excellent adhesion to these, and Cu-based A wiring structure having a novel Cu alloy film for a display device capable of realizing low electrical resistance and low contact resistance (contact electrical resistance with an oxide semiconductor layer and / or a transparent conductive film constituting a pixel electrode), which are characteristic of the material, Another object of the present invention is to provide a display device provided with the wiring structure.

  The wiring structure of the present invention that has solved the above problems is a wiring structure comprising an insulating film, a Cu alloy film, and a semiconductor layer of a thin film transistor on a substrate in this order from the substrate side. The layer is made of an oxide semiconductor, and the Cu alloy film contains 2 to 20 in total of at least one element selected from the group consisting of Zn, Ni, Ti, Al, Mg, Ca, W, Nb, and Mn. A first layer (Y) made of a Cu alloy containing atomic% and a second alloy made of pure Cu or a Cu alloy containing Cu as a main component and having a lower electrical resistivity than the first layer (Y). Layer (X), wherein the first layer (Y) is directly connected to the substrate and / or the insulating film, and the second layer (X) The main point is that it is directly connected to the semiconductor layer.

  In a preferred embodiment, the Cu alloy film is directly connected to the transparent conductive film constituting the pixel electrode on the same plane directly connected to the semiconductor layer.

  In a preferred embodiment, the film thickness of the first layer (Y) is 10 nm or more and 100 nm or less, and 60% or less with respect to the total film thickness of the Cu alloy film.

  In a preferred embodiment, a part of Mn is precipitated and / or concentrated at the interface between the substrate and / or the insulating film and the Cu alloy film.

  In a preferred embodiment, the oxide semiconductor is made of an oxide containing at least one element selected from the group consisting of In, Ga, Zn, Ti, and Sn.

  In a preferred embodiment, the insulating film is made of silicon oxide and / or silicon oxynitride.

  In a preferred embodiment, the transparent conductive film is made of an oxide containing at least one element selected from the group consisting of In, Ga, Zn, and Sn.

  The present invention includes a display device having the above wiring structure.

  In addition, in the method for manufacturing the wiring structure that can solve the above problems, a Cu alloy film is formed, and after the film formation, the substrate and / or the insulating film are heated by heating at a temperature of 250 ° C. or more for 30 minutes or more. The main point is that a part of Mn is precipitated and / or concentrated at the interface with the Cu alloy film.

  According to the present invention, in the wiring structure including the insulating film mainly composed of silicon oxide, silicon oxynitride, or the like, the Cu alloy film, and the oxide semiconductor layer of the thin film transistor in order from the substrate side, Even if the alloy film is directly connected to the substrate and / or the insulating film, it has excellent adhesion to them; and, furthermore, the low electrical resistance characteristic of the Cu-based material, the oxide semiconductor layer and / or the pixel electrode The wiring structure which can implement | achieve low contact resistance with the transparent conductive film which comprises was able to be provided. According to the present invention, since a high melting point metal (barrier metal layer) such as Ti or Mo can be omitted, problems with the conventional wiring structure shown in FIG. 2 (for example, the effective channel length is not determined) can be solved. it can.

FIG. 1 is a schematic cross-sectional explanatory view showing a typical wiring structure of the present invention. FIG. 2 is a schematic cross-sectional explanatory view showing a conventional wiring structure. FIG. 3 is a diagram showing an electrode pattern used for measurement of contact resistivity with ITO or IZO in Examples. FIG. 4 is a diagram showing an electrode pattern used for measurement of contact resistivity with IGZO or ZTO in Examples. FIG. 5 is a cross-sectional TEM image near the interface between the Cu alloy film and the glass substrate. FIG. 6 is a partially enlarged image of FIG. FIG. 7 is a graph showing the result of EDX line analysis from a cross-sectional TEM image.

The present inventors used an oxide semiconductor such as IGZO as a semiconductor layer of TFT, and has a structure shown in FIG. 1 (in order from the substrate side, an insulating film, a Cu alloy film, and an oxide semiconductor layer of a thin film transistor). Even if the Cu alloy film is electrically connected directly to the substrate and / or the insulating film by omitting the refractory metal (barrier metal layer) such as Ti or Mo. In addition, a novel Cu alloy film for a display device having a low electrical resistance of the film itself and a low contact resistance with the transparent conductive film constituting the oxide semiconductor layer and the pixel electrode ( Hereinafter, in order to provide a wiring structure provided with a Cu alloy film for direct contact. As a result, as a Cu alloy film used in the wiring structure,
A first layer (Y) made of a Cu alloy containing in total 2 to 20 atomic% of at least one element selected from the group consisting of Zn, Ni, Ti, Al, Mg, Ca, W, Nb, and Mn; ,
A second layer (X) made of pure Cu or a Cu alloy containing Cu as a main component and having a lower electrical resistivity than the first layer (Y);
Has a laminated structure including
The first layer (Y) is directly connected to the substrate and / or the insulating film, and the second layer (X) is formed by using a Cu alloy directly connected to the semiconductor layer. The present invention was completed by finding that the object was achieved.

  The Cu alloy film is preferably directly connected to a transparent conductive film (typically ITO, IZO, etc.) constituting the pixel electrode (see FIG. 1). The film thickness of the first layer (Y) constituting the laminated Cu alloy film described above is preferably 10 nm or more and 100 nm or less, and 60% or less with respect to the total film thickness of the Cu alloy film. Moreover, the preferable alloy element contained in the first layer (Y) is Mn, which is very excellent in adhesion to the substrate and / or the insulating film. This is presumably because a Cu—Mn reaction layer in which a part of Mn is precipitated and / or concentrated is formed at the interface with the substrate and / or the insulating film. Such a laminated Cu alloy film having excellent adhesion is preferably produced by performing a heat treatment at a temperature of about 250 ° C. or more for 30 minutes or more after the formation of the Cu alloy film. However, from the viewpoint of ensuring low contact resistance between the Cu alloy film and the oxide semiconductor layer with good reproducibility, the heat treatment after the Cu alloy film is formed is generally over about 300 ° C. to about 500 ° C. It is effective to carry out the control within the above range, and it has been found that when the heat treatment is performed at a temperature of 300 ° C. or less, the contact resistance with the oxide semiconductor layer varies (see Example 2 described later). ).

  Hereinafter, preferred embodiments of the wiring structure and the manufacturing method thereof according to the present invention will be described with reference to FIG. 1 described above, but the present invention is not limited thereto. Note that FIG. 1 shows an example of a bottom gate type, but the invention is not limited to this, and a top gate type is also included. In FIG. 1, IGZO is used as a typical example of the oxide semiconductor layer; however, the present invention is not limited thereto, and any oxide semiconductor used for a display device such as a liquid crystal display device can be used.

The TFT substrate shown in FIG. 1 has, in order from the substrate side, a gate electrode (Cu alloy in the figure), a gate insulating film (SiO _{2 in the} figure), a source electrode / drain electrode (Cu alloy in the figure, details will be described later), It has a wiring structure (bottom gate type) in which a channel layer (oxide semiconductor layer, IGZO in the figure) and a protective layer (SiO _{2 in the} figure) are sequentially laminated. Here, the protective layer in FIG. 1 may be silicon oxynitride, and similarly, the gate insulating film may be silicon oxynitride. As described above, an oxide semiconductor loses its excellent characteristics in a reducing atmosphere, and therefore it is recommended to use silicon oxide (silicon oxynitride) that can be formed in an oxidizing atmosphere. Alternatively, either the protective layer or the gate insulating film may be silicon nitride.

  And the characteristic part of this invention exists in the place which used the laminated Cu alloy mentioned above as said Cu alloy. In the present invention, the first layer (Y) that is in direct contact with the substrate and / or the insulating film is made of a Cu alloy containing an alloy element that contributes to improving the adhesion, whereby the substrate and / or the insulating film Improved adhesion. On the other hand, the second layer (X) stacked on the first layer (Y) is directly connected to the oxide semiconductor layer, and has an element with low electrical resistivity (pure Cu or pure Cu). Cu alloy having a low electrical resistivity), thereby reducing the electrical resistivity of the entire Cu alloy film. That is, by using the laminated structure defined in the present invention, (a) the electrical resistivity is lower than that of Al, and the contact resistance with the transparent conductive film constituting the oxide semiconductor layer and / or the pixel electrode is also kept low. (I) Low adhesion to the substrate and / or insulating film, which has been a defect of Cu, can be remarkably enhanced while effectively maximizing the original characteristics of Cu. That is, the Cu alloy is extremely useful as a Cu alloy for direct contact, and is particularly preferably used as a wiring material for a source electrode and / or a drain electrode.

  In the present invention, the second layer (X) is formed on (directly above) the first layer (Y), and is mainly made of pure Cu or Cu having a lower electrical resistivity than the first layer (Y). It is composed of a Cu alloy as a component. By providing such a second layer (X), the electrical resistivity of the entire Cu alloy film can be kept low. Here, the “Cu alloy having a lower electrical resistivity than the first layer (Y)” used for the second layer (X) means the first layer (Y ) And the content and / or content of the alloy elements may be appropriately controlled so that the electrical resistivity is lower than that of the above. Elements with low electrical resistivity (generally, elements as low as pure Cu alloys) can be easily selected from known elements with reference to numerical values described in the literature. However, even if it is an element with a high electrical resistivity, if the content is reduced (generally, about 0.05 to 1 atomic%), the electrical resistivity can be reduced, so that the above can be applied to the second layer (X). The alloy element is not necessarily limited to an element having a low electrical resistivity. Specifically, for example, Cu-0.5 atomic% Ni, Cu-0.5 atomic% Zn, Cu-0.3 atomic% Mn and the like are preferably used. Moreover, the said alloy element applicable to 2nd layer (X) may contain the gas component of oxygen gas or nitrogen gas, for example, Cu-O, Cu-N, etc. can be used.

  Hereinafter, the first layer (Y) that characterizes the present invention will be described in detail. Hereinafter, for convenience of explanation, “substrate and / or insulating film” may be referred to as “substrate and the like”.

[About the first layer (Y)]
In the Cu alloy film, the first layer (Y) is in direct contact with the substrate and / or the insulating film, and is selected from the group consisting of Zn, Ni, Ti, Al, Mg, Ca, W, Nb, and Mn. It is composed of a Cu alloy containing at least one element (adhesion improving element) in a total of 2 to 20 atomic%. These elements may be contained alone or in combination of two or more. In the case of containing alone, the single amount may satisfy the above range, and in the case of containing two or more types, the total amount may satisfy the above range. These elements are selected as elements that dissolve in Cu metal but not in Cu oxide film. When a Cu alloy in which these elements are dissolved is oxidized by heat treatment or the like during the film formation process, the elements do not dissolve in the Cu oxide film, so that the elements are placed under the interface of the Cu oxide film generated by oxidation. Sweeped out and concentrated, and the concentrated layer is considered to improve the adhesion to the substrate and / or the insulating film. By forming such a concentrated layer, sufficient adhesion can be ensured even if the Cu alloy film is directly connected to a substrate or the like without interposing a barrier metal. As a result, it is possible to prevent deterioration of display performance such as gradation display of the liquid crystal display. The concentrated layer is a layer in which the above-mentioned adhesion improving element is present at a high concentration, specifically, the above-mentioned adhesion improving element at a concentration of 1.1 times or more in the matrix of the first layer (Y). It is a layer that exists.

  5 and 6 are TEM images (magnification: 150,000 times) in the vicinity of the interface between the Cu alloy film (4 atomic% Mn—Cu alloy: film thickness 50 nm) and the glass substrate (FIG. 6 is a part of FIG. 5). FIG. 7 is a graph showing the results of EDX line analysis of the cross-sectional TEM image. FIG. 7 also shows that the Mn concentrated layer is formed at the interface between the Cu alloy film and the glass substrate.

Among the above-mentioned adhesion improving elements, Mn and Ni are preferable, and Mn is more preferable. This is because Mn is an element in which the concentration phenomenon at the interface described above is expressed very strongly. That is, Mn is formed from the inner side to the outer side (insulated by heat treatment in the manufacturing process of a display device such as a process of forming an insulating film of SiO ₂ film) during or after the Cu alloy film formation. Move toward the interface). The movement of Mn to the interface is further accelerated by the driving force of Mn oxide generated by oxidation by heat treatment. As a result, a Cu—Mn reaction layer (hereinafter referred to as “Mn reaction layer”) is formed on the entire surface with good adhesion at the interface with the insulating film, etc., and the adhesion with the insulating film etc. is remarkably improved. it is conceivable that.

  Such a concentrated layer (including precipitates) such as a Mn reaction layer is preferably obtained by performing a predetermined heat treatment after forming a Cu alloy film by a sputtering method (details will be described later). Here, “predetermined heat treatment” means a heat treatment at about 250 ° C. or higher for 30 minutes or more considering adhesion, as described above; and a low resistance to the oxide semiconductor layer. From the viewpoint of ensuring with good reproducibility, this means that the temperature range of the heat treatment is controlled to be more than about 300 ° C. and 500 ° C. or less. By such heat treatment, the alloy element is easily diffused and concentrated at the interface with the insulating film or the like. After that, an oxide semiconductor film may be formed.

  The heat treatment may be performed for the purpose of forming the concentrated layer such as a Mn reaction layer, or a heat history (for example, a protective film such as a silicon nitride film) after the Cu alloy film is formed. The film forming step) may satisfy the temperature and time.

  The content of the above elements is 2 atomic% or more. If the content of the element is less than 2 atomic%, the adhesiveness with the substrate and / or the insulating film is insufficient and satisfactory characteristics cannot be obtained. For example, when the content of the element is as low as about 0.5%, good adhesion may be obtained depending on conditions, but reproducibility is lacking. Therefore, in the present invention, considering the reproducibility, the lower limit of the content of the element is set to 2 atomic% or more. As a result, good adhesion can always be obtained regardless of the measurement conditions. On the other hand, if the content of the above elements exceeds 20 atomic%, the Cu alloy film (wiring film) itself (first layer + second layer) has an increased electrical resistivity, and residues are generated during wiring etching. Fine processing becomes difficult. The preferable lower limit of the content of the element is 3 atomic%, more preferably 4 atomic%. Moreover, a preferable upper limit is 12 atomic%, More preferably, it is 10 atomic%.

  Strictly speaking, the preferable content of the above elements may vary depending on the kind of the element. This is because the load (influence) on adhesion and electrical resistance differs depending on the type of element. For example, Mn is preferably 3 atom% or more and 12 atom% or less, more preferably 4 atom% or more and 10 atom% or less.

  The Cu alloy film used in the present invention contains the above elements, and the remainder: Cu and inevitable impurities.

  The Cu alloy constituting the first layer (Y) may further contain Fe and / or Co in a total amount (in the case of a single substance) in a range of 0.02 to 1.0 atomic%. Thus, the low electrical resistivity and the high adhesion with the transparent substrate are further improved. The preferable content is 0.05 atomic percent or more and 0.8 atomic percent or less, and more preferably 0.1 atomic percent or more and 0.5 atomic percent or less.

  In the Cu alloy film, the second layer (X) is formed on (directly above) the first layer (Y) and has a lower electrical resistivity than pure Cu or the first layer (Y). And a Cu alloy containing Cu as a main component. By providing such a second layer (X), the electrical resistivity of the entire Cu alloy film can be kept low. In addition, the alloy which has Cu as a main component means that Cu is most contained in Cu alloy.

  As described above, the Cu alloy film used in the present invention exhibits desired characteristics by adopting a laminated structure of the second layer (X) and the first layer (Y) having different compositions. In particular, it is effective to control the film thickness of the first layer (Y) in order to exhibit the effect more effectively. Specifically, the film thickness of the first layer (Y) is 10 nm or more, and 60% of the total film thickness of the Cu alloy film [film thickness of the second layer (X) and the first layer (Y)]. The following is preferable. Thereby, low electrical resistivity and high adhesion are obtained, and fine workability is more effectively exhibited. More preferably, the film thickness of the first layer (Y) is 20 nm or more and 50% or less with respect to the total film thickness of the Cu alloy film.

  The upper limit of the film thickness of the first layer (Y) may be determined as appropriate mainly considering the electrical resistivity of the wiring film itself, preferably 100 nm or less, and more preferably 80 nm or less. Further, the lower limit of the ratio of the first layer (Y) to the total thickness of the Cu alloy film is not particularly limited, but is preferably about 15% in consideration of improvement in adhesion to the transparent substrate.

  Strictly speaking, the film thickness of the first layer (Y) may vary depending on the type of element contained in the first layer (Y). This is because the influence on adhesion and electrical resistance differs depending on the type of element. For example, in the case of Mn, the lower limit of the film thickness is preferably 10 nm or more, more preferably 20 nm or more. In the case of Mn, the upper limit of the film thickness is preferably 80 nm or less, and more preferably 50 nm or less. In the case of Ni or Zn, the lower limit of the film thickness is preferably 20 nm or more, more preferably 30 nm or more, and the upper limit is preferably 100 nm or less, more preferably 80 nm or less. In the case of an element other than Mn, Ni, and Zn, it is preferably 10 nm or more and 100 nm or less as described above.

  The film thickness of the entire Cu alloy film (second layer (X) + first layer (Y)) is generally preferably from 200 nm to 500 nm, and more preferably from 250 nm to 400 nm.

  In order to further improve adhesion to a substrate or the like, the first layer (Y) may further contain oxygen. By introducing an appropriate amount of oxygen into the first layer (Y) in contact with the substrate and / or the insulation, an oxygen-containing layer containing a predetermined amount of oxygen is interposed at the interface, and a strong bond ( It is thought that chemical bonds are formed and adhesion is improved.

  In order to sufficiently exhibit the above-described action, the preferable amount of oxygen contained in the first layer (Y) is 0.5 atomic% or more, more preferably 1 atomic% or more, still more preferably 2 atomic% or more, Even more preferably, it is 4 atomic% or more. On the other hand, if the amount of oxygen becomes excessive and the adhesiveness is excessively improved, a residue remains after wet etching and the wet etching property is lowered. Moreover, when the amount of oxygen becomes excessive, the electrical resistance of the entire Cu alloy film is improved. Considering these viewpoints, the amount of oxygen contained in the first layer (Y) is preferably 30 atomic% or less, more preferably 20 atomic% or less, still more preferably 15 atomic% or less, and still more preferably 10 Atomic% or less.

Such an oxygen-containing first layer (Y) can be obtained by supplying oxygen gas when the first layer (Y) is formed by sputtering. As an oxygen gas supply source, in addition to oxygen (O ₂ ), an oxidizing gas containing oxygen atoms (for example, O ₃ ) can be used. Specifically, when forming the first layer (Y), a mixed gas obtained by adding oxygen to a process gas usually used in the sputtering method is used. When forming the second layer (X), oxygen is not added. Sputtering may be performed using a process gas. This is because the second layer (X) preferably contains no oxygen from the viewpoint of reducing electrical resistivity. As the process gas, a rare gas (for example, xenon gas or argon gas) is typically mentioned, and argon gas is preferable. Further, if the amount of oxygen gas in the process gas is changed during the formation of the first layer (Y), a plurality of underlayers having different oxygen contents can be formed.

  Since the amount of oxygen in the first layer (Y) can vary depending on the mixing ratio of oxygen gas in the process gas, the mixing ratio may be appropriately changed according to the amount of oxygen to be introduced. For example, when it is desired to introduce 1 atomic% of oxygen into the first layer (Y), approximately 10 times the amount of oxygen is mixed in the process gas, and the ratio of the oxygen gas in the process gas Is preferably about 10% by volume.

  Since the Cu alloy film used in the present invention is excellent in adhesion to the substrate and / or the insulating film, it is suitably used as a wiring film and an electrode film in direct contact with them. In the present invention, the source electrode and / or the drain electrode are preferably made of the Cu alloy film, and the component composition of other wiring portions (for example, the gate electrode) is not particularly limited. For example, in FIG. 1, the gate electrode, the scanning line (not shown), and the drain wiring portion (not shown) in the signal line may also be constituted by the Cu alloy film, and in this case, the Cu alloy in the TFT substrate. All of the wirings can have the same component composition.

  The Cu alloy film having the above laminated structure is preferably formed by a sputtering method. Specifically, the material constituting the first layer (Y) is formed by sputtering to form the first layer (Y), and then the second layer (X) is formed thereon. A material to be formed may be formed by a sputtering method to form the second layer (X) to have a stacked structure. After forming the Cu alloy laminated film in this way, it is preferable to perform predetermined patterning and then process the cross-sectional shape into a taper shape with a taper angle of about 45 to 60 ° from the viewpoint of coverage.

  If the sputtering method is used, a Cu alloy film having almost the same composition as the sputtering target can be formed. Therefore, the composition of the Cu alloy film can be adjusted by adjusting the composition of the sputtering target. The composition of the sputtering target may be adjusted by using a Cu alloy target having a different composition, or may be adjusted by chip-oning an alloy element metal on a pure Cu target.

  In the sputtering method, a slight deviation may occur between the composition of the formed Cu alloy film and the composition of the sputtering target. However, the deviation is within a few atomic percent. Therefore, if the composition of the sputtering target is controlled within a range of ± 10 atomic% at the maximum, a Cu alloy film having a desired composition can be formed.

  The Cu alloy film that best characterizes the present invention has been described above.

  The present invention is characterized by the Cu alloy film, and other constituent elements are not particularly limited.

  The oxide semiconductor layer is not particularly limited as long as it is an oxide semiconductor used for a liquid crystal display device or the like. For example, at least one element selected from the group consisting of In, Ga, Zn, Ti, and Sn A material made of an oxide containing is used. Specifically, as the above oxide, In oxide, In—Sn oxide, In—Zn oxide, In—Sn—Zn oxide, In—Ga oxide, Zn—Sn oxide, Zn—Ga oxide AZTO and GZTO in which transparent oxides such as In—Ga—Zn oxide, Zn oxide, and Ti oxide, and Zn—Sn oxide are doped with Al or Ga.

  In addition, examples of the transparent conductive film that forms the pixel electrode include an oxide conductive film that is usually used in a liquid crystal display device, for example, at least one selected from the group consisting of In, Ga, Zn, and Sn. A conductive film made of an oxide containing an element can be given. Typically, amorphous ITO, poly-ITO, IZO, ZnO and the like are exemplified.

  Further, an insulating film such as a gate insulating film or a protective film formed on the oxide semiconductor (hereinafter, may be represented by an insulating film) is not particularly limited, and is usually used, for example, silicon nitride , Silicon oxide, silicon oxynitride, and the like. However, from the viewpoint of effectively exhibiting the characteristics of the oxide semiconductor, it is preferable to use silicon oxide or silicon oxynitride that can be formed in an acidic atmosphere. Specifically, the insulating film does not necessarily need to be composed only of silicon oxide, and any insulating film containing at least oxygen that can effectively exhibit the characteristics of the oxide semiconductor is used in the present invention. be able to. For example, a material obtained by nitriding only the surface of silicon oxide or a material obtained by oxidizing only the surface of Si may be used. When the insulating film contains oxygen, the thickness of the insulating film is preferably approximately 0.17 nm to 3 nm. In addition, the maximum value of the ratio ([O] / [Si]) of the number of oxygen atoms ([O]) and the number of Si atoms ([Si]) in the oxygen-containing insulating film is generally 0.3 or more. It is preferably within the range of 0 or less.

  The substrate is not particularly limited as long as it is used for a liquid crystal display device or the like. Typically, a transparent substrate represented by a glass substrate or the like can be given. The material of the glass substrate is not particularly limited as long as it is used for a display device, and examples thereof include alkali-free glass, high strain point glass, and soda lime glass. Or a flexible resin film, a metal foil, etc. can also be used.

  In manufacturing a display device having the above wiring structure, there is no particular limitation, except that the conditions of the present invention are satisfied and the heat treatment / thermal history conditions of the Cu alloy film are set to the recommended conditions described above. What is necessary is just to employ | adopt the general process of an apparatus.

  EXAMPLES Hereinafter, the present invention will be described more specifically with reference to examples. However, the present invention is not limited by the following examples, and may be implemented with appropriate modifications within a range that can meet the above and the following purposes. All of these are possible within the scope of the present invention.

Example 1
In this embodiment, a sample manufactured by the following method is used, and adhesion to an insulating film on a substrate (in this embodiment, a silicon oxide film or a silicon oxynitride film is manufactured by simulating a gate insulating film) Contact resistance with an oxide semiconductor (IGZO, ZTO) and contact resistance with a transparent conductive film (ITO, IZO) were measured.

(Sample preparation)
First, a glass substrate (Corning Eagle 2000, size is 50.8 mm diameter × 0.7 mm thickness) is prepared, and a silicon oxide film or a silicon oxynitride film (both film thickness is 300 nm) is formed by plasma CVD. A film was formed. Silane gas and N ₂ O were used to form the silicon oxide film, while silane gas and ammonia gas were used to form the silicon oxynitride film.

Next, various Cu alloy films (constant at a total film thickness of 300 nm) shown in Table 1 were formed on the above insulating film by a DC magnetron sputtering method. Specifically, the product name “HSM-552” manufactured by Shimadzu Corporation is used as the sputtering apparatus, and the DC magnetron sputtering method [back pressure: 0.27 × 10 ⁻³ Pa or less, atmospheric gas: Ar, Ar gas pressure: 2 mTorr , Ar gas flow rate: 30 sccm, sputtering power: DC 260 W, distance between electrodes: 50.4 mm, substrate temperature: 25 ° C. (room temperature)], a Cu alloy film of the first layer (Y) on the silicon oxide film, and A pure Cu metal film of the second layer (X) was sequentially formed to obtain a sample of a laminated wiring film.

  In addition, pure Cu was used for the sputtering target for the formation of the pure Cu film. Moreover, the sputtering target produced by the vacuum melting method was used for formation of Cu alloy film of various alloy components.

  The composition of the Cu alloy film formed as described above was confirmed by quantitative analysis using an ICP emission spectrometer (ICP emission spectrometer “ICP-8000 type” manufactured by Shimadzu Corporation).

  For comparison, a sample (No. 1 in Table 1) consisting only of pure Cu was prepared. In addition, although the sample in which the amount of additive elements such as Mn exceeded 20% was prepared, the following test was not performed because there was a problem that undercut would increase during the following etching if the amount of added elements exceeded 20%. It was.

(Adhesion test with insulating film)
Each sample obtained as described above was subjected to various heat treatments described in Table 1. Specifically, the heat treatment was performed at 350 ° C. or 250 ° C. for 30 minutes in a vacuum in a CVD apparatus.

  The adhesion of each sample after the heat treatment was evaluated by a tape peel test based on a JIS standard tape peel test. Specifically, a grid-like cut (5 × 5 grid cut) with a 1 mm interval was made on the surface of each sample with a cutter knife. Next, a black polyester tape (product number 8422B) manufactured by Sumitomo 3M is firmly attached onto the surface, and the tape is peeled off at once while holding the tape at a peeling angle of 60 °. The number of sections of the grid that were not peeled off by the tape was counted, and the ratio (film residual ratio) with respect to all sections was determined. The measurement was performed three times, and the average value of the three times was used as the film remaining rate of each sample.

  In this example, the case where the peeling rate by the tape was 0 to less than 10% was judged as “good”, and the case where the peeling rate was 10% or more was judged as “poor”, and “good” was judged as pass (adhesion with the silicon oxide film was good).

(Presence or absence of a concentrated layer at the interface between the insulating film and the Cu alloy film)
Before performing the adhesion test, it was confirmed whether a concentrated layer was formed on each sample. Specifically, each sample was confirmed to have a concentrated layer at the interface with the substrate by TEM image and EDX line analysis of the interface.

  In this example, a case where the thickened layer could be confirmed was judged as ◯, a case where the thickened layer could not be confirmed was judged as ×, and a pass was judged as acceptable (a thickened layer was formed).

(Measurement of contact resistance with IGZO)
Each sample obtained as described above was sequentially subjected to photolithography and etching to form the electrode pattern shown in FIG. 4, and then subjected to various heat treatments described in Table 1. Specifically, the heat treatment was performed at 350 ° C. or 250 ° C. for 30 minutes in a vacuum in a CVD apparatus.

Next, an IGZO film (oxide semiconductor) is formed by sputtering under the following conditions, photolithography and patterning are performed, and a contact chain pattern in which 100 80 μm square contact portions are connected in series (see FIG. 4). Reference) was formed. In FIG. 4, the line width of Cu alloy and IGZO is 80 μm. In this embodiment, two types of IGZO films are used. Specifically, as shown in the table, the sputtering target for the IGZO film has an atomic ratio of In: Ga: Zn = 1: 1: 1. , In: Ga: Zn = 2: 2: 1 target was used.
(Oxide semiconductor deposition conditions)
・ Atmosphere gas = Argon ・ Pressure = 5 mTorr
-Substrate temperature = 25 ° C (room temperature)
・ Film thickness = 100 nm

  Probe needles are brought into contact with pads arranged at both ends of the contact chain pattern, and a voltage of −0.1 V to +0.1 V is applied using an HP4156A semiconductor parameter analyzer, and IV characteristics are measured by two-terminal measurement. Thus, the contact chain resistance was obtained.

Then, a contact resistance value per contact was calculated, and converted into a unit area to obtain a contact resistivity with IGZO. The measurement was performed only once. The quality of contact resistance with IGZO after one measurement was determined based on the following criteria. In this example, ○ or Δ was accepted.
(Criteria)
○ · · · the contact resistivity of 10 ^-2 [Omega] cm less than ² △ · · · contact resistivity of 10 ^-2 [Omega] cm ² or more 10 ⁰ [Omega] cm ² or less × · · · the contact resistivity of 10 ⁰ [Omega] cm ² than

(Measurement of contact resistance with ZTO)
Each sample obtained as described above was sequentially subjected to photolithography and etching to form the electrode pattern shown in FIG. 4, and then subjected to various heat treatments described in Table 1. Specifically, the heat treatment was performed at 350 ° C. or 250 ° C. for 5 minutes in a vacuum in a CVD apparatus.

Next, a ZTO film (oxide semiconductor) is formed by sputtering under the following conditions, photolithography and patterning are performed, and a contact chain pattern in which 100 80 μm square contact portions are connected in series (see FIG. 4). Reference) was formed. In FIG. 4, the line width of Cu alloy and ZTO is 80 μm. As a sputtering target of ZTO, an atomic ratio of Zn: Sn = 2: 1 was used.
(Oxide semiconductor deposition conditions)
・ Atmosphere gas = Argon ・ Pressure = 5 mTorr
-Substrate temperature = 25 ° C (room temperature)
・ Film thickness = 100 nm

  Probe needles are brought into contact with pads arranged at both ends of the contact chain pattern, and a voltage of −0.1 V to +0.1 V is applied using an HP4156A semiconductor parameter analyzer, and IV characteristics are measured by two-terminal measurement. Thus, the contact chain resistance was obtained. Furthermore, heat treatment at the time of forming the protective layer is simulated, and a heat treatment is performed at 250 ° C., 300 ° C., or 350 ° C. for 30 minutes in a vacuum atmosphere using a CVD apparatus (see Table 1). Contact chain resistance was measured.

Then, a contact resistance value per contact was calculated, and converted into a unit area to obtain a contact resistivity with ZTO. The quality of contact resistance with ZTO was determined based on the following criteria. In this example, ○ or Δ was accepted.
(Criteria)
○ · · · the contact resistivity of 10 ^-2 [Omega] cm less than ² △ · · · contact resistivity of 10 ^-2 [Omega] cm ² or more 10 ⁰ [Omega] cm ² or less × · · · the contact resistivity of 10 ⁰ [Omega] cm ² than

(Contact resistance with ITO)
The Cu alloy film formed as described above was sequentially subjected to photolithography and etching to form the electrode pattern shown in FIG. Next, a silicon nitride (SiNx) film having a film thickness of 300 nm was formed by a CVD apparatus. The film formation temperature at this time was 250 ° C. or 320 ° C. as shown in Table 1. In addition, the film formation time is 30 minutes. Based on the thermal history at this time, alloy elements were deposited as precipitates. Subsequently, photolithography and etching using a RIE (Reactive Ion Etching) apparatus were performed to form contact holes in the silicon nitride film.

Next, an ITO film (transparent conductive film) is formed by sputtering under the following conditions, photolithography and patterning are performed, and a contact chain pattern in which 50 10 μm square contact portions are connected in series (see FIG. 3). ) Was formed. In FIG. 3, the line width of Cu alloy and ITO is 80 μm.
(ITO film formation conditions)
・ Atmosphere gas = Argon ・ Pressure = 0.8 mTorr
-Substrate temperature = 25 ° C (room temperature)
・ Film thickness = 200 nm

Using the Precision Semiconductor Parameter Analyzer of HEWLETT PACKARD 4156A and Agilent Technologies 4156C, the probe is brought into contact with the pads at both ends of the contact chain pattern. It was obtained by measuring the IV characteristics. And the contact resistance value converted into one contact was calculated | required, and the quality of the direct contact resistance (ITO contact resistance with ITO) was determined by the following reference | standard. In this example, ○ or Δ was accepted.
(Criteria)
○ · · · the contact resistivity of 10 ^-2 [Omega] cm less than ² △ · · · contact resistivity of 10 ^-2 [Omega] cm ² or more 10 ⁰ [Omega] cm ² or less × · · · the contact resistivity of 10 ⁰ [Omega] cm ² than

(Contact resistance with IZO)
In the same manner as ITO, the Cu alloy film thus formed is sequentially subjected to photography and etching to form the electrode pattern shown in FIG. 3, and a silicon nitride (SiNx) film is formed. Thus, the alloy element was deposited as a precipitate. Subsequently, contact holes are formed in the silicon nitride film, IZO (transparent conductive film) is formed by sputtering under the following conditions, photolithography and patterning are performed, and 50 10 μm square contact portions are connected in series. A connected contact chain pattern (see FIG. 3) was formed. In FIG. 3, the line width of Cu alloy and IZO is 80 μm.
(IZO film formation conditions)
・ Atmosphere gas = Argon ・ Pressure = 0.8 mTorr
-Substrate temperature = 25 ° C (room temperature)
・ Film thickness = 200 nm

The total resistance (contact resistance, connection resistance) of the contact chain was determined in the same manner as the ITO film. Then, the contact resistance value converted into one contact was obtained, and the quality of the direct contact resistance with IZO (contact resistance with IZO) was determined based on the following criteria. In this example, ○ or Δ was accepted.
(Criteria)
○ · · · the contact resistivity of 10 ^-2 [Omega] cm less than ² △ · · · contact resistivity of 10 ^-2 [Omega] cm ² or more 10 ⁰ [Omega] cm ² or less × · · · the contact resistivity of 10 ⁰ [Omega] cm ² than

  These results are summarized in Tables 1 and 2.

  From Tables 1 and 2, it can be considered as follows.

  First, as shown in Table 1, for adhesion to the insulating film, No. 1 using a laminated Cu alloy film defined in the present invention was used. All of Nos. 2 to 36 (examples of the present invention) improved adhesion with the insulating film as compared with the pure Cu film (No. 1). Specifically, it is presumed that the adhesion with the insulating film was improved because the alloy element diffused in the vicinity of the insulating film by performing a heat treatment at 250 ° C. or higher after forming the Cu alloy film. Such high adhesion to the insulating film was confirmed when either silicon oxide or silicon oxynitride was used.

  Furthermore, as shown in Table 2, the contact resistances with IGZO, ZTO, ITO, and IZO were all kept low as in the case of pure Cu. Further, although not shown in the table, the electrical resistivity (wiring resistance of the Cu alloy film itself) of the present invention example was as low as that of pure Cu (generally 2.1 to 2.5 μΩ).・ About cm).

  From the above results, using the laminated Cu alloy film defined in the present invention, while maintaining the low electrical resistivity of Cu and the low contact resistance between the conductive oxide film constituting the oxide semiconductor and the pixel electrode, A wiring structure having excellent adhesion to an insulating film could be provided without using a refractory metal barrier metal layer as in the prior art.

(Example 2)
In this example, the contact resistance between the Cu alloy film and the oxide semiconductor fluctuates depending on the heating temperature after the Cu alloy film is formed, resulting in variations in measured values; In order to keep it low, it is demonstrated that it is effective to control the heating temperature within a predetermined range.

  First, No. 1 in Table 1 described above. Table 3 shows the heat treatment temperature after the electrode pattern shown in FIG. 3 was formed using a sample having the same composition as 5 and 6 (pure Cu-10 atomic% Mn, laminated Cu alloy film defined in the present invention). The oxide semiconductor (IGZO (In: Ga: Zn (atomic ratio) = 1: 1: 1, atomic ratio = 2: 2: 1) is the same as in Example 1 except that it is controlled in various ranges. And contact resistance with ZTO (Zn: Sn (atomic ratio) = 2: 1)). The measurement was performed 5 times in total, and the average value was calculated. Whether the contact resistance with the oxide semiconductor was good or bad was evaluated based on the same criteria as in Example 1, and the result was ○. In the first embodiment, the quality is determined by the contact resistance (n = 1) with the oxide semiconductor at one measurement, whereas in this embodiment, the contact resistance with the oxide semiconductor at five measurements. It is different in that the quality is judged by (average value of n = 5), and only ◯ is strictly judged as acceptable.

  These results are shown in Table 3.

  From Table 3, if the heating temperature after forming the Cu alloy film is controlled to a temperature exceeding 300 ° C., a low contact resistance with the oxide semiconductor can be reliably achieved even if the number of measurements is increased. When the temperature was set to 300 ° C. or lower, it was found that the measured values of contact resistance varied and the reproducibility was poor. Although not shown in Table 3, a low contact resistance with the oxide semiconductor could be maintained even when the heating temperature was increased to the upper limit of about 450 ° C. used in the process steps of a normal flat panel display. .

  Here, No. of Table 1 mentioned above. 5 (heat treatment temperature 250 ° C.) and No. 5 6 (heat treatment temperature 350 ° C.) has the same composition as the Cu alloy film used in this example. As shown in Table 2, the contact resistance with the oxide semiconductor at the number of measurements of 1 is all ◯, and no significant difference was seen, whereas when the number of measurements is increased as in this example, A significant difference was observed, and Δ was obtained at a heat treatment temperature of 250 ° C. (No. 2 in Table 3) and ◯ at a heat treatment temperature of 350 ° C. (No. 4 in Table 3).

  From the above results, in order to ensure a low contact resistance between the Cu alloy film and the oxide semiconductor with good reproducibility, the heating temperature after the Cu alloy film formation is generally over 300 ° C. and 450 ° C. or less. It was found that it is effective to control the

Claims (9)

A wiring structure including an insulating film, a Cu alloy film, and a semiconductor layer of a thin film transistor in order from the substrate side on the substrate,
The semiconductor layer is made of an oxide semiconductor,
The Cu alloy film is
A first layer (Y) made of a Cu alloy containing in total 2 to 20 atomic% of at least one element selected from the group consisting of Zn, Ni, Ti, Al, Mg, Ca, W, Nb, and Mn; ,
Pure Cu, or a Cu alloy containing Cu as a main component, and having a multilayer structure including a second layer (X) made of a Cu alloy having a lower electrical resistivity than the first layer (Y),
The first layer (Y) is directly connected to the substrate and / or the insulating film,
The wiring structure, wherein the second layer (X) is directly connected to the semiconductor layer.   The wiring structure according to claim 1, wherein the Cu alloy film is directly connected to a transparent conductive film constituting a pixel electrode on the same plane directly connected to the semiconductor layer.   The wiring structure according to claim 1 or 2, wherein the film thickness of the first layer (Y) is not less than 10 nm and not more than 100 nm, and is not more than 60% with respect to the total film thickness of the Cu alloy film.   The wiring structure according to claim 1, wherein a part of Mn is precipitated and / or concentrated at an interface between the substrate and / or the insulating film and the Cu alloy film.   The wiring structure according to claim 1, wherein the oxide semiconductor is made of an oxide containing at least one element selected from the group consisting of In, Ga, Zn, Ti, and Sn. .   The wiring structure according to claim 1, wherein the insulating film is made of silicon oxide and / or silicon oxynitride.   The wiring structure according to claim 2, wherein the transparent conductive film is made of an oxide containing at least one element selected from the group consisting of In, Ga, Sn, and Zn.   A display device comprising the wiring structure according to claim 1. It is a manufacturing method of the wiring structure in any one of Claims 4-7,
The Cu alloy film is formed and heated at a temperature of 250 ° C. or higher for 30 minutes or more after the film formation, whereby a part of Mn is formed at the interface between the substrate and / or the insulating film and the Cu alloy film. A method of manufacturing a wiring structure, characterized by depositing and / or concentrating.