JP2011091365A - Wiring structure and method of manufacturing the same, and display device with wiring structure - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a new wiring structure in which a film for structuring a metal electrode such as a source-drain electrode is formed under a thin-film transistor oxide semiconductor layer, especially a wiring structure that reliably achieves low electric resistance to the oxide semiconductor layer with high reproducibility. <P>SOLUTION: The wiring structure includes the insulation film, a Cu film, and the thin-film transistor semiconductor layer formed on a substrate sequentially from a substrate side. The semiconductor layer is formed of an oxide semiconductor. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention is a wiring structure including an insulating film, a Cu film, and a semiconductor layer of a thin film transistor in order from the substrate side, and the semiconductor layer is formed of an oxide semiconductor layer made of an oxide semiconductor. The present invention relates to a wiring structure and a manufacturing method thereof; and a display device having the wiring structure. The wiring structure of the present invention is typically used for flat panel displays such as liquid crystal displays (liquid crystal display devices) and organic EL displays. In the following, a liquid crystal display device will be typically taken up and described, but the present invention is not limited to this.

  A liquid crystal display device used in various fields ranging from a small mobile phone to a large-sized television exceeding 30 inches uses a thin film transistor (hereinafter referred to as “TFT”) as a switching element, and constitutes a pixel electrode. TFT having a transparent conductive film (oxide conductive film) to be formed, wiring portions such as gate wiring and source-drain wiring, and Si semiconductor layers such as amorphous silicon (a-Si) and polycrystalline silicon (p-Si) The substrate is composed of a substrate, a counter substrate disposed facing the TFT substrate at a predetermined interval and provided with a common electrode, and a liquid crystal layer filled between the TFT substrate and the counter substrate.

In display devices typified by liquid crystal display devices and the like, Al-based alloys such as pure Al or Al—Nd, which have a relatively small electrical resistance and are easily finely processed, are often used as wiring materials such as gate wiring and source-drain wiring. It has been. However, problems such as signal delay and power loss due to a large wiring resistance are becoming apparent as the display device is increased in size and image quality. Therefore, copper (Cu) having a lower resistance than Al is attracting attention as a wiring material. The electrical resistivity of the Al thin film is 3.0 × 10 ⁻⁶ Ω · cm, whereas the electrical resistivity of the Cu thin film is as low as 2.0 × 10 ⁻⁶ Ω · cm.

  However, Cu has a problem in that it has low adhesion to a glass substrate and an insulating film (such as a gate insulating film) formed thereon and peels off. Moreover, since Cu has low adhesion to a glass substrate or the like, there is a problem that it is difficult to perform wet etching or dry etching for processing into a wiring shape. Therefore, in order to improve the adhesion between Cu and the glass substrate, for example, in Patent Documents 1 to 3, a refractory metal layer such as molybdenum (Mo) or chromium (Cr) is provided between the Cu wiring and the glass substrate. A technique for improving the adhesion by interposing is disclosed.

  By the way, as described above, a-Si is often used in the semiconductor layer of the liquid crystal TFT. However, the next generation display is required to have a large size, high resolution, and high speed drive, and the conventional a-Si has low carrier mobility, so that this required specification cannot be satisfied. Therefore, in recent years, oxide semiconductors have attracted attention. An oxide semiconductor has higher carrier mobility than a-Si. Furthermore, since an oxide semiconductor can be formed in a large area at a low temperature by a sputtering method, a resin substrate having low heat resistance can be used, and as a result, a flexible display can be realized.

  As an example of using such an oxide semiconductor in a semiconductor device, for example, Patent Document 1 discloses zinc oxide (ZnO), cadmium oxide (CdO); zinc oxide (ZnO), IIB element, IIA element, or VIB element. A compound doped with an impurity or a mixture of a 3d transition metal element, a rare earth element, or an impurity that makes high resistance without losing transparency of a transparent semiconductor is used. Among oxide semiconductors, oxides (IGZO, ZTO, IZO, ITO, ZnO, AZTO, GZTO) containing at least one element selected from the group consisting of In, Ga, Zn, and Sn are very high. Since it has carrier mobility, it is preferably used.

  On the other hand, paying attention to the wiring structure of a TFT substrate provided with an oxide semiconductor layer, the wiring structure shown in FIG. 2 (hereinafter sometimes referred to as a conventional structure for convenience of description) is widely used as a TFT structure. ing. In FIG. 2, a gate electrode, a gate insulating film, an oxide semiconductor film, and a source-drain electrode are formed in order from the substrate side, and a metal electrode such as a source-drain electrode is formed in an upper layer of IGZO. The semiconductor device described in Patent Document 4 also has this conventional structure. FIG. 2 shows an example of “bottom gate type” in which the gate electrode is on the lower side, but “top gate type” in which the gate electrode is on the upper side is also included. In the case of using an oxide semiconductor, silicon oxide or silicon oxynitride is often used as a gate insulating film instead of a silicon nitride film. This is because the use of silicon oxide (silicon oxynitride) that can form a film in an oxidizing atmosphere is recommended because an oxide semiconductor loses its excellent characteristics in a reducing atmosphere.

  However, a conventional TFT substrate using an oxide semiconductor such as IGZO has the following problems. First, when forming a wiring pattern by wet-etching a metal electrode (Cu-based wiring material) such as a source-drain electrode formed on the upper layer of IGZO using an acid-based etching solution or the like, IGZO and Cu There is no etching selectivity with the system wiring material (in other words, the etching selectivity is low that only the upper layer Cu system wiring material is selectively etched and the lower layer IGZO is not etched). There is a problem of receiving. As a countermeasure for this, for example, a method of providing an etch stopper layer as a protective layer on the channel layer of IGZO has been proposed, but the process becomes complicated and the production cost increases. Second, the conventional structure has a problem that contact resistance between the source / drain electrode and the oxide semiconductor increases when a thermal history of about 250 ° C. or higher is received.

  Therefore, recently, the wiring structure shown in FIG. 1 in which the order of the oxide semiconductor film and the source-drain electrode is reversed from the conventional structure of FIG. 2 (for the sake of convenience of explanation, the structure of the present invention is different from the conventional structure of FIG. 2). Have been proposed (for example, Non-Patent Document 1). This has a structure in which a gate electrode, a gate insulating film, a source-drain electrode, and an oxide semiconductor film are formed in this order from the substrate side. As shown in FIG. 1, an oxide semiconductor and a transparent conductive film (ITO in the figure) constituting the pixel electrode are on substantially the same plane as the wiring material constituting the source-drain. FIG. 1 shows an example of a “bottom gate type” in which the gate electrode is on the lower side, but a “top gate type” in which the gate electrode is on the upper side is included as in the conventional structure shown in FIG. The

  If the structure of the present invention shown in FIG. 1 is adopted, it is considered that the problems of the conventional structure of FIG. 2 described above can be solved. However, the non-patent document 1 discloses a wiring structure in which Al is used as the wiring material of the source-drain wiring, and Ti is interposed above and below the wiring material. Cu has a lower electrical resistivity than Al. The structure of the present invention in which is used as a wiring material has not been disclosed so far.

JP-A-8-8498 JP-A-8-138461 JP 2002-76356 A JP-A-7-66423

Takeshi Osada et al., "Development of Driver-Integrated Panel using Amorphous In-Ga-Zn-Oxide TFT", THE PROCEEDING OF AM-FPD '09, p. 33-36, July 1-3, 2009

  The present invention has been made in view of the above circumstances, and an object thereof is a novel wiring structure in which a film constituting a metal electrode such as a source-drain electrode is formed under an oxide semiconductor layer of a thin film transistor. In particular, it is an object of the present invention to provide a wiring structure capable of realizing low electrical resistance with an oxide semiconductor layer with high reproducibility, a manufacturing method thereof, and a display device including the wiring structure.

  The wiring structure of the present invention that has solved the above problems is a wiring structure comprising an insulating film, a Cu film, and a semiconductor layer of a thin film transistor on a substrate in this order from the substrate side. Has a gist of an oxide semiconductor.

  In a preferred embodiment, the Cu film is directly connected to the transparent conductive film constituting the pixel electrode on the same plane directly connected to the semiconductor layer.

  In a preferred embodiment, the oxide semiconductor is made of an oxide containing at least one element selected from the group consisting of In, Ga, Zn, Ti, and Sn.

  In a preferred embodiment, the insulating film is made of silicon oxide and / or silicon oxynitride.

  In a preferred embodiment, the transparent conductive film is made of an oxide containing at least one element selected from the group consisting of In, Ga, Zn, and Sn.

  The present invention includes a display device having the above wiring structure.

  The manufacturing method of the wiring structure that can solve the above problems has a gist in that a Cu film is formed and heated at a temperature of more than 300 ° C. and not more than 450 ° C. for 5 minutes or more after the film formation.

  Since the wiring structure of the present invention is configured as described above, a low contact resistance between the Cu film and the oxide semiconductor layer formed thereon can be ensured with good reproducibility.

FIG. 1 is a schematic cross-sectional explanatory view showing a typical wiring structure of the present invention. FIG. 2 is a schematic cross-sectional explanatory view showing a conventional wiring structure. FIG. 3 is a diagram showing an electrode pattern used for measurement of contact resistivity with IGZO and ZTO in Examples. 4 shows No. 1 in Table 1. 4 (heat treatment temperature 350 ° C.) is a TEM photograph (magnification 1.5 million times) after heat treatment. FIG. 5 is a diagram showing an electrode pattern used for measurement of contact resistivity with ITO or IZO in Examples.

  The wiring structure of the present invention includes, in order from the substrate side, an insulating film mainly composed of silicon oxide, silicon oxynitride, or the like, a Cu film, and an oxide semiconductor layer of a thin film transistor. In the present invention, unlike Non-Patent Document 1 (using an Al material for the source-drain electrode) described above, Cu having a low electrical resistivity is used as the material for the source-drain electrode. The contact resistance with the transparent conductive film constituting the oxide semiconductor layer and the pixel electrode is also low. In particular, in the present invention, since the heating temperature after Cu film formation is controlled within a predetermined range, a low contact resistance with the oxide semiconductor layer can be ensured with good reproducibility.

  In this specification, the “Cu film” means a film made of pure Cu, and the pure Cu means that the content of Cu is generally 99% or more. As long as the above requirements are satisfied, pure Cu may contain, for example, Fe and / or Co in total (in the case of a single substance) in a range of 0.02 to 1.0 atomic%.

  The Cu film is preferably directly connected to the oxide semiconductor layer.

  The Cu film is preferably directly connected to a transparent conductive film (typically ITO, IZO, etc.) constituting the pixel electrode (see FIG. 1).

  Hereinafter, preferred embodiments of the wiring structure and the manufacturing method thereof according to the present invention will be described with reference to FIG. 1 described above, but the present invention is not limited thereto. Note that FIG. 1 shows an example of a bottom gate type, but the invention is not limited to this, and a top gate type is also included. In FIG. 1, IGZO is used as a typical example of the oxide semiconductor layer; however, the present invention is not limited thereto, and any oxide semiconductor used for a display device such as a liquid crystal display device can be used.

The TFT substrate shown in FIG. 1 includes, in order from the substrate side, a gate electrode, a gate insulating film (SiO _{2 in the} figure), a source electrode / drain electrode, a channel layer (oxide semiconductor layer, IGZO in the figure), and a protective layer (in the figure). It has a wiring structure (bottom gate type) in which SiO ₂ ) is sequentially laminated. The wiring film constituting the gate electrode and the source / drain electrodes is made of Cu. Here, the protective layer in FIG. 1 may be silicon oxynitride, and similarly, the gate insulating film may be silicon oxynitride. As described above, an oxide semiconductor loses its excellent characteristics in a reducing atmosphere, and therefore it is recommended to use silicon oxide (silicon oxynitride) that can be formed in an oxidizing atmosphere. Alternatively, either the protective layer or the gate insulating film may be silicon nitride.

  In FIG. 1, since the Cu film constituting the source electrode / drain electrode is in contact with the substrate and / or the insulating film via a refractory metal such as Mo or Cr, the adhesion between them is improved. On the other hand, the Cu film is directly connected to the oxide semiconductor layer. According to the present invention, the original characteristics of Cu are exhibited, in which the electrical resistivity is lower than that of Al, and the contact resistance with the transparent conductive film constituting the oxide semiconductor layer and / or the pixel electrode can be kept low. Furthermore, in the present invention, the heat treatment after the Cu film formation is generally controlled within the range of more than 300 ° C. and less than 450 ° C., so that the low contact resistance between the Cu film and the oxide semiconductor layer is ensured with good reproducibility. Can be secured. As demonstrated in the examples described later, it has been found that when the heat treatment is performed at a temperature of 300 ° C. or lower, the contact resistance with the oxide semiconductor layer varies.

  The oxide semiconductor layer used in the present invention is not particularly limited as long as it is an oxide semiconductor used in a liquid crystal display device or the like. For example, at least selected from the group consisting of In, Ga, Zn, Ti, and Sn Those made of an oxide containing one or more elements are used. Specifically, as the above oxide, In oxide, In—Sn oxide, In—Zn oxide, In—Sn—Zn oxide, In—Ga oxide, Zn—Sn oxide, Zn—Ga oxide AZTO and GZTO in which transparent oxides such as In—Ga—Zn oxide, Zn oxide, and Ti oxide, and Zn—Sn oxide are doped with Al or Ga.

  In addition, examples of the transparent conductive film that forms the pixel electrode include an oxide conductive film that is usually used in a liquid crystal display device, for example, at least one selected from the group consisting of In, Ga, Zn, and Sn. A conductive film made of an oxide containing an element can be given. Typically, amorphous ITO, poly-ITO, IZO, ZnO and the like are exemplified.

  Further, an insulating film such as a gate insulating film or a protective film formed on the oxide semiconductor (hereinafter, may be represented by an insulating film) is not particularly limited, and is usually used, for example, silicon nitride , Silicon oxide, silicon oxynitride, and the like. However, from the viewpoint of effectively exhibiting the characteristics of the oxide semiconductor, it is preferable to use silicon oxide or silicon oxynitride that can be formed in an acidic atmosphere. Specifically, the insulating film does not necessarily need to be composed only of silicon oxide, and any insulating film containing at least oxygen that can effectively exhibit the characteristics of the oxide semiconductor is used in the present invention. be able to. For example, a material obtained by nitriding only the surface of silicon oxide or a material obtained by oxidizing only the surface of Si may be used. When the insulating film contains oxygen, the thickness of the insulating film is preferably approximately 0.17 nm to 3 nm. In addition, the maximum value of the ratio ([O] / [Si]) of the number of oxygen atoms ([O]) and the number of Si atoms ([Si]) in the oxygen-containing insulating film is generally 0.3 or more. It is preferably within the range of 0 or less.

  The substrate is not particularly limited as long as it is used for a liquid crystal display device or the like. Typically, a transparent substrate represented by a glass substrate or the like can be given. The material of the glass substrate is not particularly limited as long as it is used for a display device, and examples thereof include alkali-free glass, high strain point glass, and soda lime glass. Or a flexible resin film, a metal foil, etc. can also be used.

  In manufacturing a display device having the above wiring structure, the display device is not particularly limited, except that the provisions of the present invention are satisfied and the heat treatment / thermal history conditions of the Cu film are set to the recommended conditions described above. The general process may be adopted.

  EXAMPLES Hereinafter, the present invention will be described more specifically with reference to examples. However, the present invention is not limited by the following examples, and may be implemented with appropriate modifications within a range that can meet the above and the following purposes. All of these are possible within the scope of the present invention.

Example 1
In this example, contact resistance with an oxide semiconductor (IGZO, ZTO) and a transparent conductive film (ITO or IZO) was measured using a sample manufactured by the following method. In particular, in this example, the contact resistance between the Cu film and the oxide semiconductor varies depending on the heating temperature after the Cu film formation, and the measured value varies. Therefore, the contact resistance is reliably reduced with good reproducibility. In order to suppress it, it is demonstrated that it is effective to control the heating temperature within a predetermined range. It is also demonstrated that the contact resistance of the transparent conductive film does not vary as much as the oxide semiconductor depending on the heating temperature after Cu film formation.

(Sample preparation)
First, a glass substrate (Corning Eagle 2000, size: diameter 50.8 mm × thickness 0.7 mm) was prepared, and a silicon oxide film (film thickness: 300 nm) was formed by plasma CVD. Silane gas and N ₂ O were used for forming the silicon oxide film.

  Next, Mo was used as a sputtering target, and a Mo film (thickness 20 nm) was formed on the insulating film by a DC magnetron sputtering method. Specifically, the product name “HSM-552” manufactured by Shimadzu Corporation is used as the sputtering apparatus, and the DC magnetron sputtering method [back pressure: 0.27 × 10 −3 Pa or less, atmospheric gas: Ar, Ar gas pressure: 2 mTorr, Mo was formed by Ar gas flow rate: 30 sccm, sputtering power: DC 260 W, distance between electrodes: 50.4 mm, substrate temperature: 25 ° C. (room temperature)], and a pure Cu film was formed thereon to obtain a sample. . In addition, pure Cu was used for the sputtering target for the formation of the pure Cu film.

(Measurement of contact resistance with IGZO)
The sample obtained as described above was sequentially subjected to photolithography and etching to form the electrode pattern shown in FIG. 3, and then subjected to various heat treatments described in Table 1 in a vacuum in a CVD apparatus. . The heating time was 5 minutes in all cases.

Next, an IGZO film (oxide semiconductor) is formed by sputtering under the following conditions, photolithography and patterning are performed, and a contact chain pattern in which 100 80 μm square contact portions are connected in series (see FIG. 3). Reference) was formed. In FIG. 3, the line width of Cu and IGZO is 80 μm. In this embodiment, as shown in the table, two types of IGZO films are used. Specifically, a sputtering target for the IGZO film is an atomic ratio of In: Ga: Zn = 1: 1: 1. , In: Ga: Zn = 2: 2: 1 target was used.
(Oxide semiconductor deposition conditions)
・ Atmosphere gas = Argon ・ Pressure = 5 mTorr
-Substrate temperature = 25 ° C (room temperature)
・ Film thickness = 100 nm

  Probe needles are brought into contact with pads arranged at both ends of the contact chain pattern, and a voltage of −0.1 V to +0.1 V is applied using an HP4156A semiconductor parameter analyzer, and IV characteristics are measured by two-terminal measurement. Thus, the contact chain resistance was obtained.

Then, a contact resistance value per contact was calculated, and converted into a unit area to obtain a contact resistivity with IGZO. The measurement was performed 5 times, and the average value was calculated. The quality of contact resistance with IGZO was evaluated according to the following criteria, and ○ was accepted.
(Criteria)
○ · · · the contact resistivity of 10 ^-2 [Omega] cm less than ² △ · · · contact resistivity of 10 ^-2 [Omega] cm ² or more 10 ⁰ [Omega] cm ² or less × · · · the contact resistivity of 10 ⁰ [Omega] cm ² than

(Measurement of contact resistance with ZTO)
The sample obtained as described above was sequentially subjected to photolithography and etching to form the electrode pattern shown in FIG. 3, and then subjected to various heat treatments described in Table 1 in a vacuum in a CVD apparatus. . The heating time was 5 minutes in all cases.

Next, a ZTO film (oxide semiconductor) is formed by sputtering under the following conditions, photolithography and patterning are performed, and a contact chain pattern in which 100 80 μm square contact portions are connected in series (see FIG. 3). Reference) was formed. In FIG. 3, the line width of Cu and ZTO is 80 μm. The composition used for the sputtering target of ZTO was Zn: Sn = 2: 1.
(Oxide semiconductor deposition conditions)
・ Atmosphere gas = Argon ・ Pressure = 5 mTorr
-Substrate temperature = 25 ° C (room temperature)
・ Film thickness = 100 nm

  Probe needles are brought into contact with pads arranged at both ends of the contact chain pattern, and a voltage of −0.1 V to +0.1 V is applied using an HP4156A semiconductor parameter analyzer, and IV characteristics are measured by two-terminal measurement. Thus, the contact chain resistance was obtained.

Then, a contact resistance value per contact was calculated, and converted into a unit area to obtain a contact resistivity with ZTO. The measurement was performed 5 times, and the average value was calculated. The quality of contact resistance with ZTO was evaluated according to the following criteria, and ○ was accepted.
(Criteria)
○ · · · the contact resistivity of 10 ^-2 [Omega] cm less than ² △ · · · contact resistivity of 10 ^-2 [Omega] cm ² or more 10 ⁰ [Omega] cm ² or less × · · · the contact resistivity of 10 ⁰ [Omega] cm ² than

(Contact resistance with ITO)
The pure Cu film formed as described above was sequentially subjected to photolithography and etching to form the electrode pattern shown in FIG. Next, a silicon nitride (SiNx) film having a film thickness of 300 nm was formed by a CVD apparatus. The film forming temperature at this time was 200 to 400 ° C. as shown in Table 1. The film formation time is 15 minutes. Subsequently, photolithography and etching using a RIE (Reactive Ion Etching) apparatus were performed to form contact holes in the silicon nitride film.

Next, an ITO film (transparent conductive film) is formed by sputtering under the following conditions, photolithography and patterning are performed, and a contact chain pattern in which 50 10 μm square contact portions are connected in series (see FIG. 5). ) Was formed. In FIG. 5, the line width of Cu alloy and ITO is 80 μm.
(ITO film formation conditions)
・ Atmosphere gas = Argon ・ Pressure = 0.8 mTorr
-Substrate temperature = 25 ° C (room temperature)
・ Film thickness = 200 nm

Using the Precision Semiconductor Parameter Analyzer of HEWLETT PACKARD 4156A and Agilent Technologies 4156C, the probe is brought into contact with the pads at both ends of the contact chain pattern. It was obtained by measuring the IV characteristics. And the contact resistance value converted into one contact was calculated | required, and the quality of the direct contact resistance (ITO contact resistance with ITO) was determined by the following reference | standard. In this example, ○ or Δ was accepted.
(Criteria)
○ · · · the contact resistivity of 10 ^-2 [Omega] cm less than ² △ · · · contact resistivity of 10 ^-2 [Omega] cm ² or more 10 ⁰ [Omega] cm ² or less × · · · the contact resistivity of 10 ⁰ [Omega] cm ² than

(Contact resistance with IZO)
In the same manner as the ITO, the formed pure Cu film was sequentially subjected to photography and etching to form an electrode pattern shown in FIG. 5 and a silicon nitride (SiNx) film. Subsequently, contact holes are formed in the silicon nitride film, IZO (transparent conductive film) is formed by sputtering under the following conditions, photolithography and patterning are performed, and 50 10 μm square contact portions are connected in series. A connected contact chain pattern (see FIG. 5) was formed. In FIG. 5, the line width of Cu alloy and IZO is 80 μm.
(IZO film formation conditions)
・ Atmosphere gas = Argon ・ Pressure = 0.8 mTorr
-Substrate temperature = 25 ° C (room temperature)
・ Film thickness = 200 nm

The total resistance (contact resistance, connection resistance) of the contact chain was determined in the same manner as the ITO film. Then, the contact resistance value converted into one contact was obtained, and the quality of the direct contact resistance with IZO (contact resistance with IZO) was determined based on the following criteria. In this example, ○ or Δ was accepted.
(Criteria)
○ · · · the contact resistivity of 10 ^-2 [Omega] cm less than ² △ · · · contact resistivity of 10 ^-2 [Omega] cm ² or more 10 ⁰ [Omega] cm ² or less × · · · the contact resistivity of 10 ⁰ [Omega] cm ² than

  These results are shown in Table 1.

  From Table 1, if the heating temperature after Cu film formation is controlled to a temperature exceeding 300 ° C., a low contact resistance with IGZO and ZTO can be reliably achieved even if the number of measurements is increased, whereas the heating temperature is When the temperature was set to 300 ° C. or lower, variations in the measured contact resistance were observed, indicating that the reproducibility was poor. Although not shown in Table 1, low contact resistance with IGZO and ZTO could be maintained even when the upper limit of 450 ° C. used in a normal flat panel display process step was increased.

  From the above results, in order to ensure low contact resistance between the Cu film and IGZO and ZTO with good reproducibility, the heating temperature after Cu film formation is generally over 300 ° C and controlled to 450 ° C or less. It turned out to be effective.

  On the other hand, oxides such as ITO and IZO were able to maintain low contact resistance regardless of the heating temperature after Cu film formation.

  For reference, FIG. 4 (IGZO (In: Ga: Zn (atomic ratio) = 1: 1: 1)) is shown in FIG. 4 (heat treatment temperature 350 ° C.) shows a TEM photograph (magnification 1.5 million times) after the heat treatment. By EDX analysis, it was confirmed that Cu was diffused by about 20 nm on the IGZO side.

Claims (7)

A wiring structure including an insulating film, a Cu film, and a semiconductor layer of a thin film transistor in order from the substrate side on the substrate,
The wiring structure, wherein the semiconductor layer is made of an oxide semiconductor.   The wiring structure according to claim 1, wherein the Cu film is directly connected to a transparent conductive film constituting a pixel electrode on the same plane directly connected to the semiconductor layer.   The wiring structure according to claim 1, wherein the oxide semiconductor is made of an oxide containing at least one element selected from the group consisting of In, Ga, Zn, Ti, and Sn.   The wiring structure according to claim 1, wherein the insulating film is made of silicon oxide and / or silicon oxynitride.   The wiring structure according to claim 2, wherein the transparent conductive film is made of an oxide containing at least one element selected from the group consisting of In, Ga, Sn, and Zn.   A display device comprising the wiring structure according to claim 1. A method for manufacturing the wiring structure according to claim 1,
A method of manufacturing a wiring structure, comprising: forming the Cu film;