WO2016035503A1

WO2016035503A1 - Thin film transistor

Info

Publication number: WO2016035503A1
Application number: PCT/JP2015/072326
Authority: WO
Inventors: 元隆越智; 泰幸高梨; 綾三木; 後藤　裕史; 釘宮　敏洋
Original assignee: 株式会社神戸製鋼所
Priority date: 2014-09-02
Filing date: 2015-08-06
Publication date: 2016-03-10

Abstract

This thin film transistor has a gate electrode, a gate insulating film, an oxide semiconductor thin film, an etch stop layer for protecting the oxide semiconductor thin film, a source and drain electrodes, and a protection film in this order on a substrate. The oxide semiconductor thin film is formed of an oxide configured from In, Ga and Sn as metal elements, and O, and has an amorphous structure, and the etch stop layer and/or the protection film includes SiNx. The thin film transistor has an extremely high mobility of approximately 40 cm²/Vs or more.

Description

Thin film transistor

The present invention relates to a thin film transistor having an oxide semiconductor thin film. The thin film transistor of the present invention is suitably used for display devices such as a liquid crystal display and an organic EL display. Hereinafter, the thin film transistor may be referred to as a TFT (Thin Film Transistor).

An amorphous oxide semiconductor has higher carrier mobility than general-purpose amorphous silicon. Amorphous oxide semiconductors have a large optical band gap and can be deposited at low temperatures, so they are expected to be applied to next-generation displays that require large size, high resolution, and high-speed driving, and resin substrates with low heat resistance. Yes.

When the oxide semiconductor is used as a semiconductor layer of a TFT, it is required that the TFT has excellent switching characteristics. Specifically, (1) the on-current, that is, the maximum drain current when a positive voltage is applied to the gate electrode and the drain electrode is high, and (2) the off-current, ie, the negative voltage is applied to the gate electrode. When the positive voltage is applied, the drain current is low, (3) the S value (Subthreshold Swing), that is, the gate voltage required to increase the drain current by 10 times is low, and (4) the threshold voltage, The voltage at which the drain current begins to flow when a positive voltage is applied to the drain electrode and a positive or negative voltage is applied to the gate electrode is stable without changing over time, and (5) field-effect mobility , It may be simply referred to as mobility).

As the oxide semiconductor, for example, as shown in Patent Documents 1 to 3, an In—Ga—Zn amorphous oxide semiconductor (IGZO) made of indium, gallium, zinc, and oxygen is well known. However, the field-effect mobility when a TFT is manufactured using the above oxide semiconductor is 10 cm ² / Vs or less. However, in order to cope with the recent increase in screen size, definition and speed of display devices, materials with higher mobility are required.

JP 2010-219538 A JP 2011-174134 A JP 2013-249537 A

The present invention has been made in view of the above circumstances, and an object thereof is to provide a thin film transistor having an extremely high mobility of about 40 cm ² / Vs or more.

The thin film transistor according to the present invention that has solved the above problems includes a gate electrode, a gate insulating film, an oxide semiconductor thin film, an etch stop layer for protecting the oxide semiconductor thin film, a source / drain electrode, A thin film transistor having a protective film in this order, wherein the oxide semiconductor thin film is made of an oxide composed of In, Ga and Sn; and O as metal elements, has an amorphous structure, and The gist is that the atomic ratio of each metal element to the total of In, Ga and Sn satisfies all of the following formulas (1) to (3), and at least one of the etch stop layer and the protective film contains SiNx. .
0.30 ≦ In / (In + Ga + Sn) ≦ 0.50 (1)
0.20 ≦ Ga / (In + Ga + Sn) ≦ 0.30 (2)
0.25 ≦ Sn / (In + Ga + Sn) ≦ 0.45 (3)

Hereinafter, a thin film transistor including SiNx only in the protective film is referred to as a first thin film transistor (TFT), and a thin film transistor including SiNx only in the etch stop layer and SiNx in each of the etch stop layer and the protective film. The thin film transistor may be referred to as a second thin film transistor (TFT).

In a preferred embodiment of the present invention, at least a part of the oxide semiconductor thin film is crystallized.

In a preferred embodiment of the present invention, the protective film contains SiNx, and both ends of the oxide semiconductor thin film in the channel length direction and the channel width direction are in contact with the etch stop layer.

According to the present invention, a TFT having extremely high mobility of about 40 cm ² / Vs or more can be provided.

FIG. 1 is a schematic cross-sectional view for explaining a first thin film transistor according to the present invention. FIG. 2 is a schematic cross-sectional view for explaining a conventional thin film transistor. FIG. FIG. 11 is a diagram showing Id-Vg characteristics in 1-1. 4 shows No. 1 in Table 1. It is a figure which shows the TEM observation result of the oxide semiconductor thin film cross section in 1-1. FIG. 5 is a diagram showing a TEM observation result of the cross section of the oxide semiconductor thin film from after the formation of the In—Ga—Sn-based oxide semiconductor to the completion of the TFT. FIG. 6 is a diagram illustrating a TEM observation result of the planar surface of the oxide semiconductor thin film after the film formation of the In—Ga—Zn-based oxide semiconductor and after the pre-annealing. FIG. 7 is a diagram illustrating a TEM observation result of the oxide semiconductor thin film plane after the In—Ga—Zn-based oxide semiconductor is formed and after the pre-annealing. FIG. 8 is a graph showing a result of measuring X-ray diffraction of an In—Ga—Sn-based oxide semiconductor thin film. FIG. 9 is a schematic view of the TFTs with patterns (i) to (iv) used in Example 2 as viewed from above. FIG. 10 is a cross-sectional view taken along the line A-A ′ of FIG. FIG. 11 is a cross-sectional view taken along line B-B ′ of FIG. FIG. 12 is a schematic cross-sectional view for explaining a second thin film transistor according to the present invention. FIG. 13 is a schematic cross-sectional view illustrating the manufacturing process of the second thin film transistor according to the present invention. FIG. 14 is a schematic cross-sectional view for explaining different aspects of the second thin film transistor according to the present invention. FIG. 15 is a schematic cross-sectional view illustrating a manufacturing process of the thin film transistor of FIG.

The present inventors have repeatedly studied in order to improve mobility when an In—Ga—Sn-based oxide containing In, Ga, and Sn as metal elements is used for a semiconductor layer of a TFT. As a result, in the oxide semiconductor thin film including In—Ga—Sn-based oxide, the atomic ratio of each metal element in the In—Ga—Sn-based oxide is appropriately controlled, and the protective film including SiNx and SiNx It has been found that at least one of the etch stop layers containing can be used. Hereinafter, the protective film containing SiNx and the etch stop layer containing SiNx may be collectively referred to as a SiNx-containing layer.

In order to further improve the mobility of the TFT, the present inventors use an In—Ga—Sn-based oxide in which at least a part of the oxide is crystallized as the oxide semiconductor thin film. It was also found that when the protective film contains SiNx, a TFT configured so that both ends of the oxide semiconductor thin film in the channel length direction and the channel width direction are in contact with the etch stop layer may be used.

Hereinafter, the TFT of the present invention will be described in detail.

First, the oxide semiconductor thin film used in the present invention will be described. The oxide semiconductor thin film is made of an oxide composed of In, Ga, and Sn as metal elements; and O, and the atomic ratio of each metal element to the total of In, Ga, and Sn is represented by the following formula (1 ) To (3) are all satisfied.
0.30 ≦ In / (In + Ga + Sn) ≦ 0.50 (1)
0.20 ≦ Ga / (In + Ga + Sn) ≦ 0.30 (2)
0.25 ≦ Sn / (In + Ga + Sn) ≦ 0.45 (3)

Hereinafter, the In content (atomic%) with respect to the total of all metal elements In, Ga, and Sn represented by the above formula (1) may be referred to as In atomic ratio. Similarly, the Ga content (atomic%) relative to the total of all metal elements In, Ga, and Sn represented by the above formula (2) may be referred to as a Ga atomic ratio. Similarly, the Sn content (atomic%) with respect to the total of all metal elements In, Ga and Sn represented by the above formula (3) may be referred to as the Sn atomic ratio.

About In atomic ratio In is an element contributing to the improvement of electrical conductivity. As the In atom number ratio represented by the above formula (1) increases, that is, as the amount of In occupying the metal element increases, the conductivity of the oxide semiconductor thin film improves and the mobility increases. In order to effectively exhibit the above action, the In atom number ratio needs to be 0.30 or more. The In atom number ratio is preferably 0.31 or more, more preferably 0.35 or more, and further preferably 0.40 or more. However, if the In atom number ratio is too large, there is a problem that the carrier density increases excessively and the threshold voltage decreases, so the upper limit is made 0.50 or less. The In atom number ratio is preferably 0.48 or less, more preferably 0.45 or less.

Ga atom number ratio Ga is an element that contributes to reduction of oxygen deficiency and control of carrier density. As the Ga atom number ratio represented by the above formula (2) is larger, the electrical stability of the oxide semiconductor thin film is improved, and the effect of suppressing the excessive generation of carriers is exhibited. In order to exhibit the above action more effectively, the Ga atom number ratio needs to be 0.20 or more. The Ga atom number ratio is preferably 0.22 or more, more preferably 0.25 or more. However, when the Ga atom number ratio is too large, the conductivity of the oxide semiconductor thin film is lowered and the mobility is easily lowered. Therefore, the Ga atom number ratio is set to 0.30 or less. The Ga atom number ratio is preferably 0.28 or less.

About Sn atomic ratio Sn is an element which contributes to the improvement of acid etching tolerance. The resistance to the inorganic acid etching solution in the oxide semiconductor thin film is improved as the Sn atomic ratio represented by the above formula (3) is larger. In order to exhibit the above action more effectively, the Sn atom number ratio needs to be 0.25 or more. The Sn atom number ratio is preferably 0.30 or more, more preferably 0.31 or more, and still more preferably 0.35 or more. On the other hand, if the Sn atomic ratio is too large, the mobility of the oxide semiconductor thin film is lowered and the resistance to the inorganic acid etching solution is increased more than necessary, making it difficult to process the oxide semiconductor thin film itself. Therefore, the Sn atom number ratio is set to 0.45 or less. The Sn atom number ratio is preferably 0.40 or less, more preferably 0.38 or less.

The above-mentioned oxide semiconductor thin film for TFT usually has an amorphous structure, but it is preferable that at least a part thereof is crystallized (hereinafter, sometimes referred to as having a microcrystalline structure). When at least part of the oxide semiconductor thin film is crystallized, the mobility of the TFT is remarkably improved. Here, the degree of crystallinity of the oxide semiconductor thin film is not particularly limited as long as an extremely excellent mobility improvement effect by the use of the TFT including the oxide semiconductor thin film is effectively exhibited. The fact that the oxide semiconductor thin film of the present invention has a microcrystalline structure can be confirmed, for example, by an electron beam diffraction image described later. Although details will be described later in the column of Examples, the diffraction point becomes clearer as the ratio of the crystal structure increases.

On the other hand, when the oxide semiconductor thin film is crystallized, the mobility is increased, but the etching rate in the wet etching process and the generation of residues are caused, so that productivity and yield are reduced. Therefore, it is more preferable that the oxide semiconductor thin film of the present invention is partially crystallized, which can suppress a decrease in etching rate and generation of residues in the wet etching process. Therefore, the workability of the wet etching process and the high mobility in the TFT can be compatible.

The oxide semiconductor thin film having the microcrystalline structure described above is controlled to a gas pressure in the range of 1 to 5 mTorr during the formation of the oxide semiconductor thin film in the TFT formation process, and after the formation of the SiNx-containing layer, the oxide semiconductor thin film is 200 ° C. It can be obtained by heat treatment (post-annealing) at a temperature. The TFT formation process other than the above is not particularly limited, and a normal method can be adopted.

First, an oxide semiconductor thin film is formed by controlling the gas pressure within a range of 1 to 5 mTorr. When the gas pressure is less than 1 mTorr, the film density is insufficient. A preferable lower limit of the gas pressure is 2 mTorr or more. However, if the gas pressure exceeds 5 mTorr, the desired microcrystalline structure cannot be obtained. A preferable upper limit of the gas pressure is 4 mTorr or less, more preferably 3 mTorr or less.

The concentration of oxygen in the atmospheric gas is preferably 1 to 40% by volume, more preferably 2 to 30% by volume.

A preferable atmosphere when forming the oxide semiconductor thin film is an air atmosphere or a water vapor atmosphere.

It is important that the TFT of the present invention further has a SiNx-containing layer. According to the examination results of the present inventors, hydrogen contained in the SiNx-containing layer diffuses into the oxide semiconductor thin film by using a TFT including an oxide semiconductor thin film having a predetermined composition and a SiNx-containing layer. (Diffusion) has been found to contribute greatly to the development of high mobility. Such a mobility improving effect was found by using the TFT of the present invention. For example, it will be described later that it was not seen when using the IGZO described in Patent Document 1 described above. This is described in the examples.

The amount of hydrogen in the SiNx-containing layer is preferably 20 to 50 atomic%, and more preferably 30 to 40 atomic%. The amount of hydrogen in the SiNx-containing layer can be controlled by the mixing ratio of SiH ₄ and NH ₃ gas, the film formation temperature, or the like.

Furthermore, in the present invention, after the SiNx-containing layer is formed, heat treatment is performed at a temperature of 200 ° C. or higher. Specifically, the heat treatment may be performed after forming an etch stop layer containing SiNx, or the heat treatment may be performed after forming a protective film containing SiNx. Alternatively, the heat treatment may be performed after forming the etch stop layer including SiNx, and then the protective film including SiNx may be formed and the heat treatment may be performed again. When the temperature of the heat treatment is less than 200 ° C., high mobility of the TFT does not appear. The minimum with preferable heat processing temperature is 250 degreeC or more, More preferably, it is 260 degreeC or more. However, if the heat treatment temperature is too high, the TFT becomes a conductor, so the upper limit is preferably 280 ° C. or lower. A more preferable upper limit is 270 ° C. or less.

Furthermore, in the above heat treatment, it is preferable to control the heat treatment time within a range of, for example, 30 to 90 minutes so that a desired microcrystalline structure can be obtained. The atmosphere is not particularly limited, and examples thereof include a nitrogen atmosphere and an air atmosphere.

Furthermore, the TFT of the present invention preferably has a structure in which both ends of the oxide semiconductor thin film in the channel length direction and the channel width direction (hereinafter, simply referred to as both ends) are in contact with the etch stop layer. Thus, the mobility of the TFT is remarkably increased to about 40 cm ² / Vs or more as compared with the general-purpose In—Ga—Zn-based oxide semiconductor thin film described in Patent Documents 1 to 3 described above.

A preferred embodiment of the first TFT according to the present invention having the above structure will be described in detail with reference to FIG. For comparison, FIG. 2 shows a conventional general TFT structure. However, the configuration of the first TFT according to the present invention is not limited to FIG.

As shown in FIG. 1, the first TFT of the above embodiment includes a gate electrode 2, a gate insulating film 3, an oxide semiconductor thin film 4, an etch stop layer 9 for protecting the oxide semiconductor thin film 4 on the substrate 1, The source / drain electrode 5 and the protective film 6 are provided in this order, and the transparent conductive film 8 is electrically connected to the source / drain electrode 5 through the contact hole 7. The first TFT of the above embodiment uses the oxide semiconductor thin film 4 having the above-described composition and microcrystalline structure. On the other hand, the conventional TFT shown in FIG. 2 has the same configuration order except that an amorphous In—Ga—Zn-based oxide semiconductor thin film is used as the oxide semiconductor thin film 4.

However, the first TFT of the above embodiment is configured such that both ends in the channel length direction of the oxide semiconductor thin film 4 are in contact with the etch stop layer 9 as shown in FIG. The etch stop layer 9 is covered so as to cover both ends in the channel length direction), and both ends in the channel length direction of the oxide semiconductor thin film 4 are not in contact with the source / drain electrodes 5. 4 is configured to be in contact with the source / drain electrode 5 (that is, the source / drain electrode 5 is covered so as to cover both ends of the oxide semiconductor thin film 4 in the channel length direction). It is greatly different from the TFT of FIG. Further, when attention is paid to the upper surface of the oxide semiconductor thin film 4 in FIGS. 1 and 2, a part of the etch stop layer 9 is patterned in the example of the present invention in FIG. 1, and a region in contact with the contact hole 7 through the source / drain electrode 5. 2 is different from the conventional example of FIG. 2 in that the etch stop layer 9 is not patterned and does not have a region in contact with the contact hole 7 via the source / drain electrode 5. 1 and 2, both end portions in the channel length direction of the oxide semiconductor thin film 4 are not in direct contact with the protective film 6.

Hereinafter, a preferred method for manufacturing the TFT according to the embodiment will be described with reference to FIG. However, the present invention is not limited to this.

First, the gate electrode 2 and the gate insulating film 3 are formed on the substrate 1. These forming methods are not particularly limited, and commonly used methods can be employed. Further, the types of the gate electrode 2 and the gate insulating film 3 are not particularly limited, and those commonly used can be used. For example, as the gate electrode 2, Al or Cu metal having a low electrical resistivity, refractory metal such as Mo, Cr, or Ti having high heat resistance, or an alloy thereof can be preferably used. The gate insulating film 3 is typically exemplified by a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and the like. In addition, oxides such as Al ₂ O ₃ and Y ₂ O ₃ and those obtained by stacking these can also be used.

Next, the above-described oxide semiconductor thin film 4 is formed. As described above, in the present invention, in particular, when forming an oxide semiconductor thin film, it is important to control the gas pressure in the range of 1 to 5 mTorr and to heat-treat at a temperature of 200 ° C. or higher after forming the protective film. The other steps are not particularly limited, and a normal method can be adopted, but a preferable method is as follows.

For example, the oxide semiconductor thin film 4 is preferably formed by a sputtering target using a sputtering method, for example, by a DC sputtering method or an RF sputtering method. Hereinafter, the sputtering target may be simply referred to as “target”. According to the sputtering method, a thin film having excellent in-plane uniformity of components and film thickness can be easily formed. Alternatively, the oxide may be formed by a chemical film formation method such as a coating method.

As a target used in the sputtering method, it is preferable to use a target containing the above-described elements and having the same composition as the desired oxide, whereby a thin film having a desired component composition can be formed with little compositional deviation. Specifically, a target that is made of an oxide containing In, Ga, and Sn as metal elements and that has an atomic ratio of each metal element to the total of In, Ga, and Sn satisfying the above formulas (1) to (3) is used. Is recommended.

Or you may form into a film using the combinatorial sputtering method which discharges simultaneously two targets from which a composition differs. For example, an oxide target of each element of In, Ga, and Sn, such as In ₂ O ₃ , Ga ₂ O ₃ , and SnO ₂ , or an oxide target of a mixture containing at least two or more of the above elements can be used. One or a plurality of pure metal targets or alloy targets containing the above metal elements may be used, and film formation may be performed while supplying oxygen as an atmospheric gas.

The target can be manufactured by, for example, a powder sintering method.

In the case where a film is formed by sputtering using the above target, in addition to the gas pressure at the time of film formation described above, oxygen partial pressure, power input to the target, substrate temperature, and the distance between the target and the substrate TS It is preferable to appropriately control the distance.

Specifically, for example, it is preferable to form a film under the following sputtering conditions.

In order to operate as a semiconductor, the amount of oxygen added is preferably adjusted so that the carrier density of the oxide semiconductor thin film 4 is in the range of 1 × 10 ¹⁵ to 10 ¹⁷ / cm ³ . The optimum oxygen addition amount may be appropriately controlled according to the sputtering apparatus, the composition of the target, the thin film transistor manufacturing process, and the like. In Examples described later, the addition flow rate ratio was set to 100 × O ₂ / (Ar + O ₂ ) = 4% by volume.

The higher the film formation power density, the better. It is recommended that the DC sputtering method or the RF sputtering method be set to approximately 2.0 W / cm ² or more. However, if the film formation power density is too high, the oxide target may be broken or cracked, and the upper limit is about 50 W / cm ² .

It is recommended that the substrate temperature during film formation is controlled within the range of room temperature to 200 ° C.

Furthermore, since the amount of defects in the oxide semiconductor thin film 4 is also affected by the heat treatment conditions after film formation, it is preferably controlled appropriately. As the heat treatment conditions after the film formation, for example, it is recommended that the heat treatment is generally performed at 250 to 400 ° C. for 10 minutes to 3 hours in an air atmosphere. Examples of the heat treatment include a pre-annealing process (a heat treatment performed immediately after patterning after wet etching of the oxide semiconductor thin film 4).

The preferable film thickness of the oxide semiconductor thin film 4 can be about 10 nm or more, further 20 nm or more, 200 nm or less, and further 100 nm or less.

After the oxide semiconductor thin film 4 is formed, patterning is performed by wet etching. Immediately after the patterning, it is preferable to perform a heat treatment (pre-annealing treatment) for improving the film quality of the oxide semiconductor thin film 4, thereby increasing the on-current and field-effect mobility of the transistor characteristics and improving the transistor performance. It becomes like this. The pre-annealing treatment is preferably performed, for example, in a steam atmosphere or an air atmosphere at 350 to 400 ° C. for 30 to 60 minutes.

Next, an etch stop layer 9 is formed. The method for forming the etch stop layer 9 is not particularly limited, and a commonly used method can be employed.

In the first TFT of the present embodiment, a SiNx film is used only for the protective film 6, and any film normally used in the field of TFT can be used for the etch stop layer 9. For example, as the etch stop layer 9, a film such as a SiOxNy (silicon oxynitride) film, a SiOx (silicon oxide) film, an Al ₂ O ₃ film, or a Ta ₂ O ₅ film can be used. Specifically, as the etch stop layer 9, only one of these films may be used as a single layer, or any one of these films may be used by laminating a plurality of layers. Alternatively, two or more types of films may be stacked.

Next, source / drain electrodes 5 are formed. The type of the source / drain electrode 5 is not particularly limited, and a commonly used one can be used. For example, a metal or alloy such as Al, Mo, or Cu may be used as in the gate electrode.

As a method for forming the source / drain electrodes 5, for example, after forming a metal thin film by a magnetron sputtering method, patterning can be performed by photolithography, and wet etching can be performed to form an electrode.

Before the protective film 6 described later is formed, heat treatment (200 ° C. to 300 ° C.) or N ₂ O plasma treatment may be performed as necessary to recover damage to the oxide surface.

Next, a protective film 6 is formed on the oxide semiconductor thin film 4 by a CVD (Chemical Vapor Deposition) method.

As described above, it is important to use the protective film 6 containing SiNx in the first TFT of this embodiment. By using the protective film 6 containing SiNx, the mobility improving effect by hydrogen diffusion to the oxide semiconductor thin film 4 can be effectively exhibited. As the protective film 6, any film other than the SiNx film may be stacked as long as it has a SiNx film. For example, only a SiNx film may be used as a single layer, or a plurality of SiNx films may be stacked. In addition, a SiNx film and at least one film such as a SiOxNy film, a SiOx film, an Al ₂ O ₃ film, and a Ta ₂ O ₅ film may be laminated. For example, as shown in an embodiment described later, an upper layer is formed. It is preferable to use a laminated film in which a SiNx film and a SiOx film as a lower layer are used.

The film thickness of the SiNx film in the protective film 6 is preferably 50 to 400 nm, and more preferably 100 to 200 nm. In the case of the protective film 6 in which a plurality of SiNx films are stacked, the thickness of the SiNx film indicates the total thickness of all the SiNx films. Further, the ratio of the film thickness of the SiNx film to the film thickness of the entire protective film 6 is preferably 20 to 100%, more preferably 40 to 70%.

Subsequently, a contact hole 7 for probing for transistor characteristic evaluation is formed in the protective film 6. Thereafter, the post-annealing described above is performed.

Next, based on a conventional method, the transparent conductive film 8 is electrically connected to the source / drain electrode 5 through the contact hole 7. The kind of the transparent conductive film 8 is not specifically limited, What is normally used can be used.

Hereinafter, a preferred embodiment of the second TFT according to the present invention will be described in detail with reference to FIGS. However, the configuration of the second TFT according to the present invention is not limited to FIGS. Note that the steps up to the step of forming the oxide semiconductor thin film 4 are the same as the steps described for the first TFT, and thus are omitted.

Next to the oxide semiconductor thin film 4, an etch stop layer 9 is formed. The method for forming the etch stop layer 9 is not particularly limited, and a commonly used method can be employed. In the second TFT of this embodiment, it is important to use the etch stop layer 9 containing SiNx. By using the etch stop layer 9 containing SiNx, it is possible to effectively exert a mobility improving effect by hydrogen diffusion into the oxide semiconductor thin film 4. As the etch stop layer 9, any film other than the SiNx film may be laminated as long as it has a SiNx film. That is, only a SiNx film may be used as a single layer, or a plurality of SiNx films may be stacked and used. For example, a SiNx film and at least one film such as a SiOxNy film, a SiOx film, an Al ₂ O ₃ film, or a Ta ₂ O ₅ film may be laminated, and an upper layer may be formed as shown in an embodiment described later. A laminated film in which the SiNx film 9-2 and the SiOx film 9-1 as the lower layer may be used.

In the second TFT of the present embodiment, both ends of the oxide semiconductor thin film 4 may be in contact with the etch stop layer 9 as shown in FIG. 12 and FIG. As shown, both ends of the oxide semiconductor thin film 4 may be configured not to contact the etch stop layer 9. Therefore, in the second TFT of this embodiment, the etch stop layer 9 can be disposed only in the channel portion of the oxide semiconductor thin film 4.

The film thickness of the SiNx film in the etch stop layer 9 is preferably 50 to 250 nm, and more preferably 100 to 200 nm. In the case of the etch stop layer 9 in which a plurality of SiNx films are stacked, the film thickness of the SiNx film indicates the total film thickness of all the SiNx films. Further, the ratio of the film thickness of the SiNx film to the film thickness of the entire etch stop layer 9 is preferably 30 to 100%, more preferably 40 to 80%.

Subsequently, a contact hole 7 for probing for transistor characteristic evaluation is formed in the etch stop layer 9. Thereafter, the post-annealing described above is performed. As long as the post-annealing is after the formation of the etch stop layer 9, the post-annealing may be performed before the formation of the source / drain electrodes 5 described later or after the formation of the source / drain electrodes 5.

Next, the protective film 6 may be formed over the oxide semiconductor thin film 4 by a CVD method. In the second TFT of the present embodiment, examples of the protective film 6 include SiNx films, SiOxNy films, SiOx films, Al ₂ O ₃ films, Ta ₂ O ₅ films, and any one of these films. Only one of these films may be used as a single layer, or any one of these films may be laminated and used, or two or more kinds of films may be laminated.

As described later, the first and second TFTs of the present invention thus obtained have a mobility of about 40 cm ² / Vs or more when the mobility is measured by Hall measurement that derives the mobility from Id-Vg measurement. Very high mobility.

The present application includes Japanese Patent Application No. 2014-178857 filed on September 2, 2014, Japanese Patent Application No. 2014-245124 filed on December 3, 2014, and July 1, 2015. Claims the benefit of priority based on Japanese Patent Application No. 2015-132533 filed in. Japanese Patent Application No. 2014-178857 filed on September 2, 2014, Japanese Patent Application No. 2014-245124 filed on December 3, 2014, and Japanese Patent Application No. 2014-245124 filed on July 1, 2015 The entire contents of Japanese Patent Application No. 2015-132533 are incorporated herein by reference.

Hereinafter, the present invention will be described in more detail with reference to examples, but the present invention is not limited by the following examples, and can be implemented with modifications within a range that can meet the purpose described above and below. They are all included in the technical scope of the present invention.

Example 1
In this example relating to the first TFT, the influence of the formation conditions of the oxide semiconductor thin film on the mobility of the TFT was examined. In Example 1, a film containing SiNx was used only for the protective film.

First, on a glass substrate 1 (Corning Eagle 2000, diameter: 100 mm × thickness: 0.7 mm), a Mo thin film of 100 nm as the gate electrode 2 and a SiO ₂ (film thickness of 200 nm) as the gate insulating film 3 are sequentially formed. did. The gate electrode 2 was formed by a DC sputtering method using a pure Mo sputtering target. The sputtering conditions were film formation temperature: room temperature, film formation power density: 3.8 W / cm ² , carrier gas: Ar, gas pressure during film formation: 2 mTorr, and Ar gas flow rate: 20 sccm. The gate insulating film 3 uses a plasma CVD method, carrier gas: a mixed gas of SiH ₄ and N ₂ O, film formation power density: 0.96 W / cm ² , film formation temperature: 320 ° C., gas during film formation The film was formed under a pressure of 133 Pa.

Next, an oxide semiconductor thin film 4 (In—Ga—Sn—O film, film thickness: 40 nm) having the following composition was formed under various sputtering conditions shown in Table 1.
In: Ga: Sn = 42.7: 26.7: 30.6 atomic%
Specifically, a sputtering target having the same composition as that of the oxide semiconductor thin film 4 was used, and a film was formed by a sputtering method under the following conditions.
Sputtering equipment: “CS-200” manufactured by ULVAC, Inc.
Substrate temperature: room temperature gas pressure: 1, 3, 5, 10 mTorr
Carrier gas: Ar
Oxygen partial pressure: 100 × O ₂ / (Ar + O ₂ ) = 4, 12, 20% by volume
Deposition power density: 1.27, 2.55, 3.83 W / cm ²
Sputtering target used: In: Ga: Sn = 42.7: 26.7: 30.6 atomic%

In addition, each content of the metal element of the oxide semiconductor thin film was analyzed by separately preparing a sample in which each oxide semiconductor thin film having a film thickness of 40 nm was formed on a glass substrate by the sputtering method in the same manner as described above. The analysis was performed by ICP (Inductively Coupled Plasma) emission spectroscopy using CIROS Mark II (manufactured by Rigaku Corporation).

Moreover, the electrical resistivity was measured as follows using the said sample which formed each 40-nm-thick oxide semiconductor thin film on the glass substrate. The measurement results are shown in Table 1 below. In Table 1 below, “aE + b” means “a × 10 ^b ”.
Manufacturer: Mitsubishi Chemical Analytech Product name: Hiresta (registered trademark) UP
Model number: MCP-HT450 measurement method: Ring electrode method

After forming the oxide semiconductor thin film 4 as described above, patterning was performed by photolithography and wet etching. As a wet etching solution, “ITO-07N” manufactured by Kanto Chemical Co., Inc. was used. In this example, it was confirmed that all oxide semiconductor thin films tested were free from residues due to wet etching and could be properly etched.

As described above, after the oxide semiconductor thin film 4 was patterned, pre-annealing was performed to improve the film quality. Pre-annealing was performed at 350 ° C. for 1 hour in an air atmosphere.

After the pre-annealing, an SiOx film (film thickness: 100 nm) was formed on the oxide semiconductor thin film 4 as the etch stop layer 9. The SiOx film was formed by a plasma CVD method using a mixed gas of N ₂ O and SiH ₄ . The film formation conditions were film formation power density: 0.32 W / cm ² , film formation temperature: 230 ° C., and gas pressure during film formation: 133 Pa. After the formation of the SiOx film, the etch stop layer 9 was patterned by photolithography and dry etching.

Next, in order to form the source / drain electrodes 5, a pure Mo film having a thickness of 200 nm was formed above the oxide semiconductor thin film 4 by sputtering. The pure Mo film was formed under the following conditions: input power: DC 300 W (deposition power density: 3.8 W / cm ² ), carrier gas: Ar, gas pressure: 2 mTorr, substrate temperature: room temperature.

Next, the source / drain electrodes 5 were patterned by photolithography and wet etching. Specifically, a mixed acid etching solution composed of a mixed solution of phosphoric acid: nitric acid: acetic acid = 70: 2: 10 (mass ratio) and having a liquid temperature of 40 ° C. was used.

After forming the source / drain electrodes 5 in this manner, a 100 nm thick SiOx film is formed by plasma CVD as a protective film 6 for protecting the oxide semiconductor thin film transistor, and a 150 nm thick SiNx film is further formed. It formed by plasma CVD method. A mixed gas of SiH ₄ , N ₂ and N ₂ O was used to form the SiOx film, and a mixed gas of SiH ₄ , N ₂ and NH ₃ was used to form the SiNx film. In either case, the film formation conditions were film formation power density: 0.32 W / cm ² , film formation temperature: 150 ° C., and gas pressure during film formation: 133 Pa.

Next, contact holes 7 for probing for transistor characteristic evaluation were formed in the protective film 6 by photolithography and dry etching. Then, as post-annealing, heat treatment was performed at 260 ° C. for 30 minutes in a nitrogen atmosphere.

Finally, an ITO film having a thickness of 80 nm was formed as the transparent conductive film 8 to produce the thin film transistor of FIG. Specifically, an ITO film is formed by DC sputtering using a carrier gas: a mixed gas of argon and oxygen gas, film formation power: 200 W (film formation power density: 2.5 W / cm ² ), and gas pressure: 5 mTorr. A film was formed.

The fabricated thin film transistor had a channel length of 20 μm and a channel width of 200 μm.

The following characteristics were examined for the TFT.

(1) Measurement of transistor characteristics Transistor characteristics (drain current-gate voltage characteristics, Id-Vg characteristics) were measured using a semiconductor parameter analyzer “HP4156C” manufactured by Agilent Technology. Detailed measurement conditions are as follows. No. in Table 1 The Id-Vg characteristic in 1-1 is shown in FIG.
Source voltage: 0V
Drain voltage: 10V
Gate voltage: -30 to 30V (measurement interval: 0.25V)
Substrate temperature: Room temperature

(2) Threshold voltage (Vth)
The threshold voltage is roughly a value of a gate voltage when the transistor shifts from an off state (a state where the drain current is low) to an on state (a state where the drain current is high). In this example, the voltage when the drain current is around 1 nA between the on-current and the off-current is defined as the threshold voltage, and the threshold voltage of each thin film transistor is measured.

(3) Field effect mobility μFE
The field effect mobility μFE is derived from the transistor characteristics in the saturation region where Vg> Vd−Vth, the relational expression of drain current and gate voltage, Id = μFE × Cox × W × (Vg−Vth) ² / 2L. (Vg: gate voltage, Vd: drain voltage, Id: drain current, L: channel length, W: channel width, Cox: capacitance of gate insulating film, μFE: field effect mobility). In this embodiment, the field effect mobility μFE is derived from the slope of the drain current-gate voltage characteristic (Id-Vg characteristic) near the gate voltage that satisfies the linear region. The higher the field effect mobility, the better. In this example, 40 cm ² / Vs was used as a reference, and more than that was accepted.

(4) S value The S value is the minimum value of the gate voltage required to increase the drain current 10 times from the Id-Vg characteristic, and the lower the value, the better the characteristic. Specifically, in this case, the S value was 0.4 V / decade or less under favorable conditions.

These results are also shown in Table 1.

Table 1 shows that when the oxygen partial pressure and the deposition power density are the same, the mobility increases as the gas pressure decreases (see Nos. 1-1, 4, 5, and 6 in Table 1). It was also found that, under the above experimental conditions, when the gas pressure and the deposition power density were the same, the smaller the oxygen partial pressure, the higher the mobility (see Nos. 1-1 to 3 in Table 1). In addition, regarding the film-forming power density, the influence which exerts on mobility was not seen so much.

In order to evaluate the crystal structure of the oxide semiconductor thin film, cross-sectional TEM observation, electron diffraction image observation, and X-ray diffraction measurement were performed.

(Section TEM observation and electron diffraction measurement)
No. in Table 1 With respect to 1-1, the result of TEM observation of the cross section of the oxide semiconductor thin film after the thin film transistor was produced is shown in FIG. An electron diffraction image of a circular region shining in the oxide semiconductor thin film of FIG. 4 is shown on the right side of FIG. From the right diagram in FIG. 4, there are diffraction points in the ring-shaped diffraction pattern. If the amorphous structure is used, the diffraction point is not noticeable. However, the higher the proportion of the oxide semiconductor thin film having the crystal structure, the clearer the diffraction point. FIG. 4 shows that the oxide semiconductor thin film of the present invention has a crystal structure.

Next, the crystal structure of the oxide semiconductor thin film is confirmed immediately after the oxide semiconductor thin film 4 is formed on the gate insulating film 3, and it is demonstrated that the crystal structure is not greatly changed by the thin film transistor manufacturing process.

FIG. 5 shows a TEM observation of the cross section of the oxide semiconductor thin film at each timing of A: after formation of the oxide semiconductor thin film, B: after pre-annealing, C: after contact hole formation, and D: post-annealing. Results are shown.

An electron diffraction image of a circular region shining in the oxide semiconductor thin film 4 shown in FIGS. 5A to 5D is shown on the right side of FIGS. 5A to 5D. From the right diagrams shown in FIGS. 5A to 5D, it can be seen that there is a region in the ring shape that is slightly shining in any state, and the crystal structure is not greatly changed by the thin film transistor manufacturing process.

Next, it will be demonstrated that the crystal structure is not observed when the constituent elements of the thin film change.

FIGS. 6 and 7 are different from the oxide semiconductor thin film 4 in the constituent elements, and after manufacturing the thin film transistor in which the oxide semiconductor thin film formed of the In—Ga—Zn—O film is formed, the oxide semiconductor thin film is formed. The results of TEM observation of the oxide semiconductor thin film plane after pre-annealing are shown. The composition of the In—Ga—Zn—O film is as follows.
In: Ga: Zn = 33.3: 33.3: 33.3 atomic%
Specifically, a sputtering target having the same composition as the above In—Ga—Zn—O film was used, and a film was formed by a sputtering method under the following conditions.
Sputtering equipment: “CS-200” manufactured by ULVAC, Inc.
Substrate temperature: room temperature gas pressure: 1 mTorr or 5 mTorr
Carrier gas: Ar
Oxygen partial pressure: 100 × O ₂ / (Ar + O ₂ ) = 4% by volume
Deposition power density: 2.55 W / cm ²
Sputtering target used: In: Ga: Zn = 33.3: 33.3: 33.3 atomic%

6 shows the result of forming an In—Ga—Zn—O film at a gas pressure of 1 mTorr, FIG. 6A shows the result after forming the In—Ga—Zn—O film, and FIG. 6B shows the result after pre-annealing. Yes. FIG. 7 shows the result of forming an In—Ga—Zn—O film at a gas pressure of 5 mTorr, FIG. 7A shows the result after forming the In—Ga—Zn—O film, and FIG. 7B shows the result after pre-annealing. Yes.

FIG. 6 and FIG. 7 show electron beam diffraction images of a circular region shining in the oxide semiconductor thin film of FIGS. In FIG. 5, spots (diffraction points) are seen while the light shines in the outer ring shape from the point shining in the center, while spots are hardly seen in FIGS. That is, FIG. 5 includes microcrystals, but FIGS. 6 and 7 do not include microcrystals. Therefore, it can be seen from the right diagrams of FIGS. 6 and 7 that there is no significant difference in light emission intensity in the ring shape, and it has an amorphous structure.

(X-ray diffraction measurement)
No. in Table 1 For 1-1, an oxide semiconductor thin film 4 (In—Ga—Sn—O film, film thickness 40 nm) having the following composition was sputtered on a glass substrate (Corning Eagle 2000, diameter 100 mm × thickness 0.7 mm). The film was formed.
In: Ga: Sn = 42.7: 26.7: 30.6 atomic%
Specifically, a sputtering target having the same composition as that of the oxide semiconductor thin film 4 was used, and a film was formed by a sputtering method under the following conditions.
Sputtering equipment: “CS-200” manufactured by ULVAC, Inc.
Substrate temperature: room temperature gas pressure: 1 mTorr
Oxygen partial pressure: 100 × O ₂ / (Ar + O ₂ ) = 4% by volume
Deposition power density: 2.55 W / cm ²
Sputtering target used: In: Ga: Sn = 42.7: 26.7: 30.6 atomic%

After forming an In—Ga—Sn—O film, X-ray diffraction measurement was performed. For X-ray diffraction, a Rigaku Co., Ltd. Smart Lab was used, a Cu target was used, a target output was 45 kV-200 mA, and 2θ scan measurement was performed. The incident angle of X-rays was 0.5 °, and the measurement angle was 10 to 100 °. FIG. 8A shows the result of measuring the X-ray diffraction after forming the In—Ga—Sn—O film.

Next, after forming an In—Ga—Sn—O film, pre-annealing was performed to improve the film quality. Pre-annealing was performed at 350 ° C. for 1 hour in an air atmosphere. After pre-annealing, X-ray diffraction measurement is performed under the same conditions as above, and the measurement results are shown in FIG. 8B. Moreover, the result of having measured the X-ray diffraction of the glass substrate as reference data is shown in FIG. 8C.

As is clear from FIG. 8, according to FIG. 8C in which the X-ray diffraction of the glass substrate was measured, a broad halo pattern was recognized in the vicinity of 2θ = 23 °. On the other hand, according to FIG. 8A measured after depositing the In—Ga—Sn—O film and FIG. 8B measured after pre-annealing, oxides near 31 ° and 55 ° other than the halo pattern derived from the glass substrate Although a halo pattern derived from a semiconductor thin film was observed, no sharp peak based on crystals was observed.

Since the crystallite size measurable by the X-ray diffraction measurement is about 1 nm, the size of the formed crystal grains is considered to be less than 1 nm. That is, it is suggested that most of the film is amorphous, and the size of the formed crystal grains is less than 1 nm.

As described above, a part of the In—Ga—Sn—O film is crystallized, but most of the In—Ga—Sn—O film has an amorphous structure. It is presumed that the etching processability is also excellent, and high mobility due to the formation of very short range order is compatible.

Example 2
In this example relating to the first TFT, TFTs having four types of shapes shown in the following patterns (i) to (iv) were produced, and the transistor characteristics after the formation of the protective film (insulating film) 6 were evaluated. In Example 2, a film containing SiNx was used only for the protective film.

FIGS. 9A to 9D are top views of the thin film transistor in order to clarify the shape of the TFT used in this example. 10A to 10D are cross-sectional views taken along the line A-A 'of FIGS. 9A to 9D. Cross-sectional views taken along the line B-B 'of FIGS. 9A to 9D are shown in FIGS. 11A to 11D. In FIG. 9, ACT is a region corresponding to the oxide semiconductor thin film 4.

Pattern (i): See FIGS. 9A, 10A, and 11A The pattern (i) corresponds to FIG. 1 described above. The source / drain electrodes 5 are not in direct contact with both ends of the oxide semiconductor thin film 4 but are in direct contact with part of the upper surface of the oxide semiconductor thin film 4, and the etch stop layer 9 is formed of the oxide semiconductor thin film 4. 4 is in contact with both ends of the oxide semiconductor thin film 4 and is in direct contact with part of the upper surface of the oxide semiconductor thin film 4.

Pattern (ii): See FIG. 9B, FIG. 10B, and FIG. 11B The source / drain electrode 5 does not directly contact both ends of the oxide semiconductor thin film 4, but directly contacts a part of the upper surface of the oxide semiconductor thin film 4. In addition, the etch stop layer 9 does not contact both end portions of the oxide semiconductor thin film 4 but directly contacts a part of the upper surface of the oxide semiconductor thin film 4.

Pattern (iii): See FIGS. 9C, 10C, and 11C The source / drain electrodes 5 are in direct contact with both ends of the oxide semiconductor thin film 4 in the channel length direction in the cross-sectional view of FIG. In the figure, the oxide semiconductor thin film 4 is not in direct contact but is in direct contact with a part of the upper surface of the oxide semiconductor thin film 4, and the etch stop layer 9 is not in contact with both ends of the oxide semiconductor thin film 4. It is in direct contact with a part of the top surface.

Pattern (iv): See FIGS. 9D, 10D, and 11D The pattern (iv) corresponds to FIG. 2 described above. The source / drain electrodes 5 are in direct contact with both ends of the oxide semiconductor thin film 4 and in direct contact with part of the upper surface of the oxide semiconductor thin film 4, and the etch stop layer 9 is formed of the oxide semiconductor thin film 4. Are in direct contact with a part of the upper surface of the oxide semiconductor thin film 4.

The TFT with the above pattern (iv) was manufactured by designing a mask so as to obtain a desired shape. Hereinafter, as a representative example, a method for forming a TFT having a pattern (i) will be described. Since the shape of the pattern is the same as that of the first embodiment described above, the following description will focus on differences from the first embodiment.

After the gate electrode 2 and the gate insulating film 3 were sequentially formed on the glass substrate 1 in the same manner as in Example 1 described above, an oxide semiconductor thin film (In—Ga—Sn—O, film thickness having the same composition as in Example 1 was formed. 40 nm). The sputtering conditions are the same as in Example 1 except for the following points.
Gas pressure: 1mTorr
Oxygen partial pressure: 100 × O ₂ / (Ar + O ₂ ) = 4% by volume
Deposition power density: 2.55 W / cm ²

For comparison, an In—Ga—Zn—O film (with a thickness of 40 nm) described in Patent Document 1 or the like was formed as an oxide semiconductor thin film. The composition of In—Ga—Zn—O is as follows.
In: Ga: Zn = 33.3: 33.3: 33.3 atomic%

Next, after the etch stop layer 9, the source / drain electrodes 5, the protective film 6, and the contact hole 7 were formed in the same manner as in Example 1, the following heat treatment was performed as post-annealing as shown in Table 2. For reference, a sample without heat treatment was also prepared.
Nitrogen atmosphere, 250 ° C, 260 ° C, 270 ° C, 30 minutes

Finally, an ITO film (film thickness of 80 nm) was formed as the transparent conductive film 8 in the same manner as in Example 1 to produce a thin film transistor having a pattern (i).

For each thin film transistor thus obtained, the S value, threshold voltage Vth, and field effect mobility μFE were measured in the same manner as in Example 1.

These results are also shown in Table 2.

No. Examples 2-1 to 15 are examples in which an In—Ga—Sn-based oxide having a composition defined in the present invention is used as the oxide semiconductor thin film 4. Among these, No. of the example of this invention which has the shape of the pattern (i) which gave the manufacturing conditions prescribed | regulated by this invention. Both 2-5 and 12 have a very high mobility of 40 cm ² / Vs or more. In particular, No. No. 1 treated at 270 ° C. with a higher post-annealing temperature after forming the protective film. In 2-12, the mobility was remarkably high at about 67 cm ² / Vs.

In contrast, the comparative example No. having the shape of the pattern (ii). 2-6, 9, and 13; comparative examples No. 2 having the shape of pattern (iii) Since 2-7, 10 and 14 were made into conductors, various characteristics could not be measured (indicated as “-” in Table 2).

In addition, the comparative example No. having the shape of the pattern (iv) does not have the shape defined in the present invention. In 2-8, 11 and 15, the desired high mobility was not obtained.

The reason why a very high mobility can be obtained by the configuration of the present invention as in the above pattern (i) is unknown in detail, but it is assumed as follows, for example. As described above, in the pattern (i), the upper surface of the oxide semiconductor thin film 4 is in contact with the source / drain electrode 5 through the contact hole 7 of the etch stop layer 9. That is, both end portions of the oxide semiconductor thin film 4 are not in direct contact with the source / drain electrodes 5. An etch stop layer 9 is disposed on the oxide semiconductor thin film 4 except for the contact hole 7. Here, Mo or Al, which is a constituent material of the source / drain electrode 5, is a material in which hydrogen does not easily permeate. The protective film 6 is supplied from SiNx or directly from the etch stop layer 9. Since the amount of hydrogen in the etch stop layer 9 (SiOx) used in this example is about 5.0 atomic% and the amount of hydrogen in the protective film 6 (SiNx) is about 32 atomic%, the protective film 6 There is a very high possibility that the hydrogen contained therein diffuses into the oxide semiconductor thin film 4 and contributes to the expression of high mobility. Probably, hydrogen passivates the bottom level under the conductor, so that defects in the oxide semiconductor thin film 4 are reduced, leading to high mobility.

On the other hand, when both ends of the oxide semiconductor thin film 4 in the channel width direction are in direct contact with the protective film 6 as in the pattern (ii) and the pattern (iii), excessive hydrogen is supplied to the oxide semiconductor thin film 4. Therefore, on the contrary, it is surmised that the carrier becomes excessive and the TFT is made into a conductor.

Further, when the portion other than the channel region of the oxide semiconductor thin film 4 is covered with the source / drain electrodes 5 as in the pattern (iv), the supply of hydrogen is limited, so that the mobility is not likely to increase.

On the other hand, as the oxide semiconductor thin film 4, No. 1 using an In—Ga—Zn-based oxide having a conventional composition is used. In 2-16 to 31, no significantly improved mobility was measured, and the maximum was only 7.1 cm ² / Vs. That is, no improvement in mobility due to post-annealing and no improvement in mobility due to TFT shape control as in the case of using an In—Ga—Sn-based oxide having the composition of the present invention was observed.

Example 3
In this example relating to the second TFT, except that the structure of the etch stop layer is different from that of Example 1, a TFT having the same shape as the pattern (i) was produced, and the transistor characteristics were evaluated. In Tables 3 to 5, the production method described below is represented as production method A. 3-1 to 8 are manufactured by manufacturing method A. Further, in this embodiment, the protective film 6 for protecting the oxide semiconductor transistor is not provided in order to emphasize the usefulness when the layer containing SiNx is used as the etch stop layer 9, but the above-described embodiment 1 is not provided. Similarly to 2 and 2, a protective film 6 may be provided.

Next, an oxide semiconductor thin film 4 (In—Ga—Sn—O film, film thickness: 40 nm) having the following composition was formed under various sputtering conditions shown in Table 3.
In: Ga: Sn = 42.7: 26.7: 30.6 atomic%
Specifically, a sputtering target having the same composition as that of the oxide semiconductor thin film 4 was used, and a film was formed by a sputtering method under the following conditions.
Sputtering equipment: “CS-200” manufactured by ULVAC, Inc.
Substrate temperature: room temperature gas pressure: 1 mTorr
Carrier gas: Ar
Oxygen partial pressure: 100 × O ₂ / (Ar + O ₂ ) = 4% by volume
Deposition power density: 2.55 W / cm ²
Sputtering target used: In: Ga: Sn = 42.7: 26.7: 30.6 atomic%

After the pre-annealing, as shown in Table 3, FIG. 12, and FIG. 13, an SiOx film 9-1 and a SiNx film 9-2 were formed on the oxide semiconductor thin film as an etch stop layer 9 (FIG. 13A). . The SiOx film 9-1 was formed by a plasma CVD method using a mixed gas of N ₂ O and SiH ₄ . The film formation conditions were film formation power density: 0.32 W / cm ² , film formation temperature: 230 ° C., and gas pressure during film formation: 133 Pa. The SiNx film 9-2 was formed by a plasma CVD method using a mixed gas of SiH ₄ , N ₂ , and NH ₃ . The film formation conditions were film formation power density: 0.32 W / cm ² , film formation temperature: 150 ° C., and gas pressure during film formation: 133 Pa. After the formation of the SiOx film 9-1 and the SiNx film 9-2, the etch stop layer 9 was patterned by photolithography and dry etching (FIG. 13B). In Example 3-8, only the SiOx film was formed on the oxide semiconductor thin film for comparison.

Next, the source / drain electrodes 5 were patterned by photolithography and wet etching to form contact holes 7 for probing for transistor characteristic evaluation (FIG. 13C). Specifically, a mixed acid etching solution composed of a mixed solution of phosphoric acid: nitric acid: acetic acid = 70: 2: 10 (mass ratio) and having a liquid temperature of 40 ° C. was used.

After forming the source / drain electrodes 5 in this manner, a heat treatment was performed in a nitrogen atmosphere at 260 ° C. for 30 minutes as post-annealing.

FIG. 12 is a cross-sectional view of the manufactured transistor, and FIG. 13 is a cross-sectional view of the transistor explaining the manufacturing process.

The manufactured thin film transistor has a channel length of 20 μm, a channel width of 200 μm (No. 3-2, 3, 7, 8), a channel length of 10 μm, a channel width of 200 μm (No. 3-4), a channel length of 10 μm, and a channel width of 100 μm (No. 3-5), channel length 10 μm, channel width 50 μm (No. 3-6).

The above-described various characteristics (S value, threshold voltage Vth, and field-effect mobility μFE) were examined for the TFT in the same manner as in Examples 1 and 2.

These results are also shown in Table 3. For reference, the structure, physical properties, and various characteristics of the TFT fabricated by the method of Example 1 are No. Described as 3-1.

From Table 3, when the etch stop layer is formed only of the SiOx film, it is No. As in 3-8, the mobility was comparable to that of a general In—Ga—Zn—O (IGZO) film. On the other hand, when the etch stop layer is a laminated film of a SiOx film and a SiNx film, No. 1 is used. High mobility was obtained as in 3-2 to 7. That is, high mobility was obtained when a SiNx film was provided as an upper layer. Also, the mobility was higher when the ratio of the SiNx film thickness to the entire etch stop layer was higher. In addition, the longer the channel length, the higher the mobility, and the shorter the channel width, the higher the mobility.

Example 4
No. For 4-2 to 3, a second TFT having an etch stop layer structure different from that of Example 1 is manufactured, and a transistor is manufactured by the following manufacturing method (hereinafter referred to as manufacturing method B) different from Example 3. Then, transistor characteristics were evaluated.

In this embodiment, in order to emphasize the usefulness when a layer containing SiNx is used as the etch stop layer 9, for convenience, the protective film 6 for protecting the oxide semiconductor transistor is not provided. A protective film 6 may be provided as in Examples 1 and 2.

Next, an oxide semiconductor thin film 4 (In—Ga—Sn—O film, film thickness 40 nm) having the following composition was formed under various sputtering conditions shown in Table 4.
In: Ga: Sn = 42.7: 26.7: 30.6 atomic%
Specifically, a sputtering target having the same composition as that of the oxide semiconductor thin film 4 was used, and a film was formed by a sputtering method under the following conditions.
Sputtering equipment: “CS-200” manufactured by ULVAC, Inc.
Substrate temperature: room temperature gas pressure: 1 mTorr
Carrier gas: Ar
Oxygen partial pressure: 100 × O ₂ / (Ar + O ₂ ) = 4% by volume
Deposition power density: 2.55 W / cm ²
Sputtering target used: In: Ga: Sn = 42.7: 26.7: 30.6 atomic%

After the pre-annealing, an SiOx film 9-1 and a SiNx film 9-2 were formed on the oxide semiconductor thin film as an etch stop layer 9 as shown in Table 4, FIG. 12, and FIG. 13 (FIG. 13A). . The SiOx film 9-1 was formed by a plasma CVD method using a mixed gas of N ₂ O and SiH ₄ . The film formation conditions were film formation power density: 0.32 W / cm ² , film formation temperature: 230 ° C., and gas pressure during film formation: 133 Pa. The SiNx film 9-2 was formed by a plasma CVD method using a mixed gas of SiH ₄ , N ₂ , and NH ₃ . The film formation conditions were film formation power density: 0.32 W / cm ² , film formation temperature: 150 ° C., and gas pressure during film formation: 133 Pa. Then, as post-annealing, heat treatment was performed at 260 ° C. for 30 minutes in a nitrogen atmosphere. After the formation of the SiOx film 9-1 and the SiNx film 9-2, post-annealing was performed, and the etch stop layer 9 (9-1 and 9-2) was patterned by photolithography and dry etching (FIG. 13B). .

The manufactured thin film transistor had a channel length of 20 μm, a channel width of 200 μm (No. 4-2), a channel length of 10 μm, and a channel width of 50 μm (No. 4-3).

The above-mentioned various characteristics (S value, threshold voltage Vth, and field effect mobility μFE) of the TFT were examined in the same manner as in Examples 1 to 3.

These results are also shown in Table 4. For reference, the structure, physical properties, and various characteristics of the TFT fabricated by the method of Example 1 are No. It is described as 4-1.

From Table 4, when the etch stop layer was formed only of the SiOx film, the mobility was the same value as that of a general In—Ga—Zn—O (IGZO) film. On the other hand, when the etch stop layer is a laminated film of a SiOx film and a SiNx film, a high mobility was obtained because the SiNx film was provided as an upper layer. From Tables 3 and 4, post-annealing may be performed before the formation of the source / drain electrodes 5 or after the formation of the source / drain electrodes 5 as long as the etching stop layer 9 is formed. I understood it.

Example 5
In Example 5, a transistor was produced in substantially the same manner as in Example 3 except that the shape TFT shown in the pattern (iv) was produced instead of the shape shown in the pattern (i) in Example 3, and transistor characteristics were obtained. Evaluated.

First, on a glass substrate 1 (Corning Eagle 2000, diameter: 100 mm × thickness: 0.7 mm), a Mo thin film of 100 nm as the gate electrode 2 and a SiO ₂ (film thickness of 200 nm) as the gate insulating film 3 are sequentially formed. did. The gate electrode 2 was formed by a DC sputtering method using a pure Mo sputtering target. The sputtering conditions were film formation temperature: room temperature, film formation power density: 3.8 W / cm ² , carrier gas: Ar, gas pressure during film formation: 2 mTorr, and Ar gas flow rate: 20 sccm. The gate insulating film 3 uses a plasma CVD method, carrier gas: mixed gas of SiH ₄ and N ₂ O, deposition power density: 1.27 W / cm ² , deposition temperature: 320 ° C., gas during deposition The film was formed under a pressure of 133 Pa.

Next, an oxide semiconductor thin film 4 (In—Ga—Sn—O film, thickness 40 nm) having the following composition was formed under the sputtering conditions shown in Table 5.
In: Ga: Sn = 42.7: 26.7: 30.6 atomic%
Specifically, a sputtering target having the same composition as that of the oxide semiconductor thin film 4 was used, and a film was formed by a sputtering method under the following conditions.
Sputtering equipment: “CS-200” manufactured by ULVAC, Inc.
Substrate temperature: room temperature gas pressure: 1 mTorr
Carrier gas: Ar
Oxygen partial pressure: 100 × O ₂ / (Ar + O ₂ ) = 4% by volume
Deposition power density: 2.55 W / cm ²
Sputtering target used: In: Ga: Sn = 42.7: 26.7: 30.6 atomic%

After the pre-annealing, an SiOx film 9-1 and a SiNx film 9-2 were formed on the oxide semiconductor thin film as an etch stop layer 9 as shown in Table 5, FIG. 14, and FIG. 15 (FIG. 15A). . The SiOx film 9-1 was formed by a plasma CVD method using a mixed gas of N ₂ O and SiH ₄ . The film formation conditions were film formation power density: 0.32 W / cm ² , film formation temperature: 230 ° C., and gas pressure during film formation: 133 Pa. The SiNx film 9-2 was formed by a plasma CVD method using a mixed gas of SiH ₄ , N ₂ , and NH ₃ . The film formation conditions were film formation power density: 0.32 W / cm ² , film formation temperature: 150 ° C., and gas pressure during film formation: 133 Pa. After the formation of the SiOx film 9-1 and the SiNx film 9-2, the etch stop layer 9 was patterned by photolithography and dry etching (FIG. 15B).

Next, the source / drain electrodes 5 were patterned by photolithography and wet etching to form contact holes 7 for probing for transistor characteristic evaluation (FIG. 15C). Specifically, a mixed acid etching solution composed of a mixed solution of phosphoric acid: nitric acid: acetic acid = 70: 2: 10 (mass ratio) and having a liquid temperature of 40 ° C. was used.

FIG. 14 is a cross-sectional view of the manufactured transistor, and FIG. 15 is a cross-sectional view of the transistor illustrating the manufacturing process.

The fabricated thin film transistors had a channel length of 10 μm, a channel width of 200 μm, 100 μm, and 25 μm (No. 5-1 to 3), a channel length of 25 μm, a channel width of 200 μm, 100 μm, and 25 μm (No. 5-4 to 6).

The above TFT characteristics (S value, threshold voltage Vth, and field effect mobility μFE) of the above TFT were examined in the same manner as in Examples 1 to 4.

These results are also shown in Table 5.

As described above, the mobility when the etch stop layer is only the SiOx film is low, but from Table 5, the etch stop layer is a laminated film of the SiOx film and the SiNx film, and the etch stop layer is the oxide semiconductor thin film. Even when arranged only in the channel portion, a high mobility of about 40 cm ² / Vs or more was expressed. In addition, it was found that when the etch stop layer is a laminated film of a SiOx film and a SiNx film and the etch stop layer is disposed only in the channel portion of the oxide semiconductor thin film, the mobility is high regardless of the channel width.

DESCRIPTION OF SYMBOLS 1 Substrate 2 Gate electrode 3 Gate insulating film 4 Oxide semiconductor thin film 5 Source / drain electrode 6 Protective film 7 Contact hole 8 Transparent conductive film 9 Etch stop layer 9-1 SiOx film 9-2 SiNx film

Claims

A thin film transistor having a gate electrode, a gate insulating film, an oxide semiconductor thin film, an etch stop layer for protecting the oxide semiconductor thin film, a source / drain electrode, and a protective film in this order on a substrate,
The oxide semiconductor thin film is made of an oxide composed of In, Ga and Sn; and O as metal elements, has an amorphous structure, and has a metal structure with respect to the total of In, Ga and Sn. The atomic ratio satisfies all of the following formulas (1) to (3),
A thin film transistor, wherein both or one of the etch stop layer and the protective film contains SiNx.
0.30 ≦ In / (In + Ga + Sn) ≦ 0.50 (1)
0.20 ≦ Ga / (In + Ga + Sn) ≦ 0.30 (2)
0.25 ≦ Sn / (In + Ga + Sn) ≦ 0.45 (3)
The thin film transistor according to claim 1, wherein at least a part of the oxide semiconductor thin film is crystallized.
2. The thin film transistor according to claim 1, wherein the protective film includes SiNx, and both ends of the oxide semiconductor thin film in a channel length direction and a channel width direction are in contact with the etch stop layer.
3. The thin film transistor according to claim 2, wherein the protective film includes SiNx, and both ends of the oxide semiconductor thin film in a channel length direction and a channel width direction are in contact with the etch stop layer.