WO2016035503A1 - Transistor a couches minces - Google Patents

Transistor a couches minces Download PDF

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Publication number
WO2016035503A1
WO2016035503A1 PCT/JP2015/072326 JP2015072326W WO2016035503A1 WO 2016035503 A1 WO2016035503 A1 WO 2016035503A1 JP 2015072326 W JP2015072326 W JP 2015072326W WO 2016035503 A1 WO2016035503 A1 WO 2016035503A1
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Prior art keywords
film
thin film
oxide semiconductor
semiconductor thin
etch stop
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PCT/JP2015/072326
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English (en)
Japanese (ja)
Inventor
元隆 越智
泰幸 高梨
綾 三木
後藤　裕史
釘宮　敏洋
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株式会社神戸製鋼所
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Priority claimed from JP2015132533A external-priority patent/JP6659255B2/ja
Application filed by 株式会社神戸製鋼所 filed Critical 株式会社神戸製鋼所
Priority to US15/327,296 priority Critical patent/US20170170029A1/en
Priority to KR1020177005510A priority patent/KR101974754B1/ko
Priority to CN201580035556.7A priority patent/CN106489209B/zh
Publication of WO2016035503A1 publication Critical patent/WO2016035503A1/fr

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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/08—Oxides
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present invention relates to a thin film transistor having an oxide semiconductor thin film.
  • the thin film transistor of the present invention is suitably used for display devices such as a liquid crystal display and an organic EL display.
  • the thin film transistor may be referred to as a TFT (Thin Film Transistor).
  • An amorphous oxide semiconductor has higher carrier mobility than general-purpose amorphous silicon.
  • Amorphous oxide semiconductors have a large optical band gap and can be deposited at low temperatures, so they are expected to be applied to next-generation displays that require large size, high resolution, and high-speed driving, and resin substrates with low heat resistance. Yes.
  • the TFT When the oxide semiconductor is used as a semiconductor layer of a TFT, it is required that the TFT has excellent switching characteristics. Specifically, (1) the on-current, that is, the maximum drain current when a positive voltage is applied to the gate electrode and the drain electrode is high, and (2) the off-current, ie, the negative voltage is applied to the gate electrode.
  • the drain current When the positive voltage is applied, the drain current is low, (3) the S value (Subthreshold Swing), that is, the gate voltage required to increase the drain current by 10 times is low, and (4) the threshold voltage, The voltage at which the drain current begins to flow when a positive voltage is applied to the drain electrode and a positive or negative voltage is applied to the gate electrode is stable without changing over time, and (5) field-effect mobility , It may be simply referred to as mobility).
  • an In—Ga—Zn amorphous oxide semiconductor made of indium, gallium, zinc, and oxygen is well known.
  • the field-effect mobility when a TFT is manufactured using the above oxide semiconductor is 10 cm 2 / Vs or less.
  • materials with higher mobility are required.
  • the present invention has been made in view of the above circumstances, and an object thereof is to provide a thin film transistor having an extremely high mobility of about 40 cm 2 / Vs or more.
  • the thin film transistor according to the present invention that has solved the above problems includes a gate electrode, a gate insulating film, an oxide semiconductor thin film, an etch stop layer for protecting the oxide semiconductor thin film, a source / drain electrode, A thin film transistor having a protective film in this order, wherein the oxide semiconductor thin film is made of an oxide composed of In, Ga and Sn; and O as metal elements, has an amorphous structure, and
  • the gist is that the atomic ratio of each metal element to the total of In, Ga and Sn satisfies all of the following formulas (1) to (3), and at least one of the etch stop layer and the protective film contains SiNx. . 0.30 ⁇ In / (In + Ga + Sn) ⁇ 0.50 (1) 0.20 ⁇ Ga / (In + Ga + Sn) ⁇ 0.30 (2) 0.25 ⁇ Sn / (In + Ga + Sn) ⁇ 0.45 (3)
  • a thin film transistor including SiNx only in the protective film is referred to as a first thin film transistor (TFT), and a thin film transistor including SiNx only in the etch stop layer and SiNx in each of the etch stop layer and the protective film.
  • the thin film transistor may be referred to as a second thin film transistor (TFT).
  • At least a part of the oxide semiconductor thin film is crystallized.
  • the protective film contains SiNx, and both ends of the oxide semiconductor thin film in the channel length direction and the channel width direction are in contact with the etch stop layer.
  • a TFT having extremely high mobility of about 40 cm 2 / Vs or more can be provided.
  • FIG. 1 is a schematic cross-sectional view for explaining a first thin film transistor according to the present invention.
  • FIG. 2 is a schematic cross-sectional view for explaining a conventional thin film transistor.
  • FIG. FIG. 11 is a diagram showing Id-Vg characteristics in 1-1. 4 shows No. 1 in Table 1. It is a figure which shows the TEM observation result of the oxide semiconductor thin film cross section in 1-1.
  • FIG. 5 is a diagram showing a TEM observation result of the cross section of the oxide semiconductor thin film from after the formation of the In—Ga—Sn-based oxide semiconductor to the completion of the TFT.
  • FIG. 1 is a schematic cross-sectional view for explaining a first thin film transistor according to the present invention.
  • FIG. 2 is a schematic cross-sectional view for explaining a conventional thin film transistor.
  • FIG. 11 is a diagram showing Id-Vg characteristics in 1-1. 4 shows No. 1 in Table 1. It is a figure which shows the TEM observation result of the oxide semiconductor thin film cross section in
  • FIG. 6 is a diagram illustrating a TEM observation result of the planar surface of the oxide semiconductor thin film after the film formation of the In—Ga—Zn-based oxide semiconductor and after the pre-annealing.
  • FIG. 7 is a diagram illustrating a TEM observation result of the oxide semiconductor thin film plane after the In—Ga—Zn-based oxide semiconductor is formed and after the pre-annealing.
  • FIG. 8 is a graph showing a result of measuring X-ray diffraction of an In—Ga—Sn-based oxide semiconductor thin film.
  • FIG. 9 is a schematic view of the TFTs with patterns (i) to (iv) used in Example 2 as viewed from above.
  • FIG. 10 is a cross-sectional view taken along the line A-A ′ of FIG. FIG.
  • FIG. 11 is a cross-sectional view taken along line B-B ′ of FIG.
  • FIG. 12 is a schematic cross-sectional view for explaining a second thin film transistor according to the present invention.
  • FIG. 13 is a schematic cross-sectional view illustrating the manufacturing process of the second thin film transistor according to the present invention.
  • FIG. 14 is a schematic cross-sectional view for explaining different aspects of the second thin film transistor according to the present invention.
  • FIG. 15 is a schematic cross-sectional view illustrating a manufacturing process of the thin film transistor of FIG.
  • the present inventors have repeatedly studied in order to improve mobility when an In—Ga—Sn-based oxide containing In, Ga, and Sn as metal elements is used for a semiconductor layer of a TFT.
  • the oxide semiconductor thin film including In—Ga—Sn-based oxide the atomic ratio of each metal element in the In—Ga—Sn-based oxide is appropriately controlled, and the protective film including SiNx and SiNx
  • the protective film containing SiNx and the etch stop layer containing SiNx may be collectively referred to as a SiNx-containing layer.
  • the present inventors use an In—Ga—Sn-based oxide in which at least a part of the oxide is crystallized as the oxide semiconductor thin film. It was also found that when the protective film contains SiNx, a TFT configured so that both ends of the oxide semiconductor thin film in the channel length direction and the channel width direction are in contact with the etch stop layer may be used.
  • the oxide semiconductor thin film used in the present invention is made of an oxide composed of In, Ga, and Sn as metal elements; and O, and the atomic ratio of each metal element to the total of In, Ga, and Sn is represented by the following formula (1 ) To (3) are all satisfied. 0.30 ⁇ In / (In + Ga + Sn) ⁇ 0.50 (1) 0.20 ⁇ Ga / (In + Ga + Sn) ⁇ 0.30 (2) 0.25 ⁇ Sn / (In + Ga + Sn) ⁇ 0.45 (3)
  • the In content (atomic%) with respect to the total of all metal elements In, Ga, and Sn represented by the above formula (1) may be referred to as In atomic ratio.
  • the Ga content (atomic%) relative to the total of all metal elements In, Ga, and Sn represented by the above formula (2) may be referred to as a Ga atomic ratio.
  • the Sn content (atomic%) with respect to the total of all metal elements In, Ga and Sn represented by the above formula (3) may be referred to as the Sn atomic ratio.
  • In is an element contributing to the improvement of electrical conductivity.
  • the In atom number ratio represented by the above formula (1) increases, that is, as the amount of In occupying the metal element increases, the conductivity of the oxide semiconductor thin film improves and the mobility increases.
  • the In atom number ratio needs to be 0.30 or more.
  • the In atom number ratio is preferably 0.31 or more, more preferably 0.35 or more, and further preferably 0.40 or more.
  • the In atom number ratio is preferably 0.48 or less, more preferably 0.45 or less.
  • Ga atom number ratio Ga is an element that contributes to reduction of oxygen deficiency and control of carrier density.
  • the Ga atom number ratio represented by the above formula (2) is larger, the electrical stability of the oxide semiconductor thin film is improved, and the effect of suppressing the excessive generation of carriers is exhibited.
  • the Ga atom number ratio needs to be 0.20 or more.
  • the Ga atom number ratio is preferably 0.22 or more, more preferably 0.25 or more.
  • the Ga atom number ratio is set to 0.30 or less.
  • the Ga atom number ratio is preferably 0.28 or less.
  • Sn is an element which contributes to the improvement of acid etching tolerance.
  • the resistance to the inorganic acid etching solution in the oxide semiconductor thin film is improved as the Sn atomic ratio represented by the above formula (3) is larger.
  • the Sn atom number ratio needs to be 0.25 or more.
  • the Sn atom number ratio is preferably 0.30 or more, more preferably 0.31 or more, and still more preferably 0.35 or more.
  • the Sn atom number ratio is set to 0.45 or less.
  • the Sn atom number ratio is preferably 0.40 or less, more preferably 0.38 or less.
  • the above-mentioned oxide semiconductor thin film for TFT usually has an amorphous structure, but it is preferable that at least a part thereof is crystallized (hereinafter, sometimes referred to as having a microcrystalline structure).
  • the degree of crystallinity of the oxide semiconductor thin film is not particularly limited as long as an extremely excellent mobility improvement effect by the use of the TFT including the oxide semiconductor thin film is effectively exhibited.
  • the fact that the oxide semiconductor thin film of the present invention has a microcrystalline structure can be confirmed, for example, by an electron beam diffraction image described later. Although details will be described later in the column of Examples, the diffraction point becomes clearer as the ratio of the crystal structure increases.
  • the oxide semiconductor thin film of the present invention is partially crystallized, which can suppress a decrease in etching rate and generation of residues in the wet etching process. Therefore, the workability of the wet etching process and the high mobility in the TFT can be compatible.
  • the oxide semiconductor thin film having the microcrystalline structure described above is controlled to a gas pressure in the range of 1 to 5 mTorr during the formation of the oxide semiconductor thin film in the TFT formation process, and after the formation of the SiNx-containing layer, the oxide semiconductor thin film is 200 ° C. It can be obtained by heat treatment (post-annealing) at a temperature.
  • the TFT formation process other than the above is not particularly limited, and a normal method can be adopted.
  • an oxide semiconductor thin film is formed by controlling the gas pressure within a range of 1 to 5 mTorr.
  • the gas pressure is less than 1 mTorr, the film density is insufficient.
  • a preferable lower limit of the gas pressure is 2 mTorr or more.
  • a preferable upper limit of the gas pressure is 4 mTorr or less, more preferably 3 mTorr or less.
  • the concentration of oxygen in the atmospheric gas is preferably 1 to 40% by volume, more preferably 2 to 30% by volume.
  • a preferable atmosphere when forming the oxide semiconductor thin film is an air atmosphere or a water vapor atmosphere.
  • the TFT of the present invention further has a SiNx-containing layer.
  • hydrogen contained in the SiNx-containing layer diffuses into the oxide semiconductor thin film by using a TFT including an oxide semiconductor thin film having a predetermined composition and a SiNx-containing layer. (Diffusion) has been found to contribute greatly to the development of high mobility.
  • Such a mobility improving effect was found by using the TFT of the present invention. For example, it will be described later that it was not seen when using the IGZO described in Patent Document 1 described above. This is described in the examples.
  • the amount of hydrogen in the SiNx-containing layer is preferably 20 to 50 atomic%, and more preferably 30 to 40 atomic%.
  • the amount of hydrogen in the SiNx-containing layer can be controlled by the mixing ratio of SiH 4 and NH 3 gas, the film formation temperature, or the like.
  • heat treatment is performed at a temperature of 200 ° C. or higher.
  • the heat treatment may be performed after forming an etch stop layer containing SiNx, or the heat treatment may be performed after forming a protective film containing SiNx.
  • the heat treatment may be performed after forming the etch stop layer including SiNx, and then the protective film including SiNx may be formed and the heat treatment may be performed again.
  • the minimum with preferable heat processing temperature is 250 degreeC or more, More preferably, it is 260 degreeC or more.
  • the upper limit is preferably 280 ° C. or lower. A more preferable upper limit is 270 ° C. or less.
  • the heat treatment time it is preferable to control the heat treatment time within a range of, for example, 30 to 90 minutes so that a desired microcrystalline structure can be obtained.
  • the atmosphere is not particularly limited, and examples thereof include a nitrogen atmosphere and an air atmosphere.
  • the TFT of the present invention preferably has a structure in which both ends of the oxide semiconductor thin film in the channel length direction and the channel width direction (hereinafter, simply referred to as both ends) are in contact with the etch stop layer.
  • the mobility of the TFT is remarkably increased to about 40 cm 2 / Vs or more as compared with the general-purpose In—Ga—Zn-based oxide semiconductor thin film described in Patent Documents 1 to 3 described above.
  • FIG. 2 shows a conventional general TFT structure.
  • the configuration of the first TFT according to the present invention is not limited to FIG.
  • the first TFT of the above embodiment includes a gate electrode 2, a gate insulating film 3, an oxide semiconductor thin film 4, an etch stop layer 9 for protecting the oxide semiconductor thin film 4 on the substrate 1,
  • the source / drain electrode 5 and the protective film 6 are provided in this order, and the transparent conductive film 8 is electrically connected to the source / drain electrode 5 through the contact hole 7.
  • the first TFT of the above embodiment uses the oxide semiconductor thin film 4 having the above-described composition and microcrystalline structure.
  • the conventional TFT shown in FIG. 2 has the same configuration order except that an amorphous In—Ga—Zn-based oxide semiconductor thin film is used as the oxide semiconductor thin film 4.
  • the first TFT of the above embodiment is configured such that both ends in the channel length direction of the oxide semiconductor thin film 4 are in contact with the etch stop layer 9 as shown in FIG.
  • the etch stop layer 9 is covered so as to cover both ends in the channel length direction), and both ends in the channel length direction of the oxide semiconductor thin film 4 are not in contact with the source / drain electrodes 5.
  • 4 is configured to be in contact with the source / drain electrode 5 (that is, the source / drain electrode 5 is covered so as to cover both ends of the oxide semiconductor thin film 4 in the channel length direction). It is greatly different from the TFT of FIG. Further, when attention is paid to the upper surface of the oxide semiconductor thin film 4 in FIGS.
  • etch stop layer 9 is patterned in the example of the present invention in FIG. 1, and a region in contact with the contact hole 7 through the source / drain electrode 5.
  • 2 is different from the conventional example of FIG. 2 in that the etch stop layer 9 is not patterned and does not have a region in contact with the contact hole 7 via the source / drain electrode 5. 1 and 2, both end portions in the channel length direction of the oxide semiconductor thin film 4 are not in direct contact with the protective film 6.
  • the present invention is not limited to this.
  • the gate electrode 2 and the gate insulating film 3 are formed on the substrate 1. These forming methods are not particularly limited, and commonly used methods can be employed. Further, the types of the gate electrode 2 and the gate insulating film 3 are not particularly limited, and those commonly used can be used. For example, as the gate electrode 2, Al or Cu metal having a low electrical resistivity, refractory metal such as Mo, Cr, or Ti having high heat resistance, or an alloy thereof can be preferably used.
  • the gate insulating film 3 is typically exemplified by a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and the like. In addition, oxides such as Al 2 O 3 and Y 2 O 3 and those obtained by stacking these can also be used.
  • the above-described oxide semiconductor thin film 4 is formed.
  • the other steps are not particularly limited, and a normal method can be adopted, but a preferable method is as follows.
  • the oxide semiconductor thin film 4 is preferably formed by a sputtering target using a sputtering method, for example, by a DC sputtering method or an RF sputtering method.
  • the sputtering target may be simply referred to as “target”.
  • the oxide may be formed by a chemical film formation method such as a coating method.
  • a target used in the sputtering method it is preferable to use a target containing the above-described elements and having the same composition as the desired oxide, whereby a thin film having a desired component composition can be formed with little compositional deviation.
  • a target that is made of an oxide containing In, Ga, and Sn as metal elements and that has an atomic ratio of each metal element to the total of In, Ga, and Sn satisfying the above formulas (1) to (3) is used. Is recommended.
  • an oxide target of each element of In, Ga, and Sn such as In 2 O 3 , Ga 2 O 3 , and SnO 2
  • an oxide target of a mixture containing at least two or more of the above elements can be used.
  • One or a plurality of pure metal targets or alloy targets containing the above metal elements may be used, and film formation may be performed while supplying oxygen as an atmospheric gas.
  • the target can be manufactured by, for example, a powder sintering method.
  • a film under the following sputtering conditions.
  • the amount of oxygen added is preferably adjusted so that the carrier density of the oxide semiconductor thin film 4 is in the range of 1 ⁇ 10 15 to 10 17 / cm 3 .
  • the higher the film formation power density the better. It is recommended that the DC sputtering method or the RF sputtering method be set to approximately 2.0 W / cm 2 or more. However, if the film formation power density is too high, the oxide target may be broken or cracked, and the upper limit is about 50 W / cm 2 .
  • the substrate temperature during film formation is controlled within the range of room temperature to 200 ° C.
  • the amount of defects in the oxide semiconductor thin film 4 is also affected by the heat treatment conditions after film formation, it is preferably controlled appropriately.
  • the heat treatment conditions after the film formation for example, it is recommended that the heat treatment is generally performed at 250 to 400 ° C. for 10 minutes to 3 hours in an air atmosphere.
  • the heat treatment include a pre-annealing process (a heat treatment performed immediately after patterning after wet etching of the oxide semiconductor thin film 4).
  • the preferable film thickness of the oxide semiconductor thin film 4 can be about 10 nm or more, further 20 nm or more, 200 nm or less, and further 100 nm or less.
  • pre-annealing treatment for improving the film quality of the oxide semiconductor thin film 4, thereby increasing the on-current and field-effect mobility of the transistor characteristics and improving the transistor performance. It becomes like this.
  • the pre-annealing treatment is preferably performed, for example, in a steam atmosphere or an air atmosphere at 350 to 400 ° C. for 30 to 60 minutes.
  • an etch stop layer 9 is formed.
  • the method for forming the etch stop layer 9 is not particularly limited, and a commonly used method can be employed.
  • a SiNx film is used only for the protective film 6, and any film normally used in the field of TFT can be used for the etch stop layer 9.
  • a film such as a SiOxNy (silicon oxynitride) film, a SiOx (silicon oxide) film, an Al 2 O 3 film, or a Ta 2 O 5 film can be used.
  • the etch stop layer 9 only one of these films may be used as a single layer, or any one of these films may be used by laminating a plurality of layers. Alternatively, two or more types of films may be stacked.
  • source / drain electrodes 5 are formed.
  • the type of the source / drain electrode 5 is not particularly limited, and a commonly used one can be used.
  • a metal or alloy such as Al, Mo, or Cu may be used as in the gate electrode.
  • the source / drain electrodes 5 for example, after forming a metal thin film by a magnetron sputtering method, patterning can be performed by photolithography, and wet etching can be performed to form an electrode.
  • heat treatment 200 ° C. to 300 ° C.
  • N 2 O plasma treatment may be performed as necessary to recover damage to the oxide surface.
  • a protective film 6 is formed on the oxide semiconductor thin film 4 by a CVD (Chemical Vapor Deposition) method.
  • the protective film 6 containing SiNx in the first TFT of this embodiment.
  • the protective film 6 containing SiNx By using the protective film 6 containing SiNx, the mobility improving effect by hydrogen diffusion to the oxide semiconductor thin film 4 can be effectively exhibited.
  • any film other than the SiNx film may be stacked as long as it has a SiNx film.
  • a SiNx film may be used as a single layer, or a plurality of SiNx films may be stacked.
  • a SiNx film and at least one film such as a SiOxNy film, a SiOx film, an Al 2 O 3 film, and a Ta 2 O 5 film may be laminated.
  • an upper layer is formed. It is preferable to use a laminated film in which a SiNx film and a SiOx film as a lower layer are used.
  • the film thickness of the SiNx film in the protective film 6 is preferably 50 to 400 nm, and more preferably 100 to 200 nm. In the case of the protective film 6 in which a plurality of SiNx films are stacked, the thickness of the SiNx film indicates the total thickness of all the SiNx films. Further, the ratio of the film thickness of the SiNx film to the film thickness of the entire protective film 6 is preferably 20 to 100%, more preferably 40 to 70%.
  • a contact hole 7 for probing for transistor characteristic evaluation is formed in the protective film 6. Thereafter, the post-annealing described above is performed.
  • the transparent conductive film 8 is electrically connected to the source / drain electrode 5 through the contact hole 7.
  • the kind of the transparent conductive film 8 is not specifically limited, What is normally used can be used.
  • the configuration of the second TFT according to the present invention is not limited to FIGS. Note that the steps up to the step of forming the oxide semiconductor thin film 4 are the same as the steps described for the first TFT, and thus are omitted.
  • an etch stop layer 9 is formed.
  • the method for forming the etch stop layer 9 is not particularly limited, and a commonly used method can be employed.
  • the etch stop layer 9 containing SiNx By using the etch stop layer 9 containing SiNx, it is possible to effectively exert a mobility improving effect by hydrogen diffusion into the oxide semiconductor thin film 4.
  • any film other than the SiNx film may be laminated as long as it has a SiNx film. That is, only a SiNx film may be used as a single layer, or a plurality of SiNx films may be stacked and used.
  • a SiNx film and at least one film such as a SiOxNy film, a SiOx film, an Al 2 O 3 film, or a Ta 2 O 5 film may be laminated, and an upper layer may be formed as shown in an embodiment described later.
  • a laminated film in which the SiNx film 9-2 and the SiOx film 9-1 as the lower layer may be used.
  • both ends of the oxide semiconductor thin film 4 may be in contact with the etch stop layer 9 as shown in FIG. 12 and FIG. As shown, both ends of the oxide semiconductor thin film 4 may be configured not to contact the etch stop layer 9. Therefore, in the second TFT of this embodiment, the etch stop layer 9 can be disposed only in the channel portion of the oxide semiconductor thin film 4.
  • the film thickness of the SiNx film in the etch stop layer 9 is preferably 50 to 250 nm, and more preferably 100 to 200 nm. In the case of the etch stop layer 9 in which a plurality of SiNx films are stacked, the film thickness of the SiNx film indicates the total film thickness of all the SiNx films. Further, the ratio of the film thickness of the SiNx film to the film thickness of the entire etch stop layer 9 is preferably 30 to 100%, more preferably 40 to 80%.
  • a contact hole 7 for probing for transistor characteristic evaluation is formed in the etch stop layer 9.
  • the post-annealing described above is performed. As long as the post-annealing is after the formation of the etch stop layer 9, the post-annealing may be performed before the formation of the source / drain electrodes 5 described later or after the formation of the source / drain electrodes 5.
  • source / drain electrodes 5 are formed.
  • the type of the source / drain electrode 5 is not particularly limited, and a commonly used one can be used.
  • a metal or alloy such as Al, Mo, or Cu may be used as in the gate electrode.
  • the source / drain electrodes 5 for example, after forming a metal thin film by a magnetron sputtering method, patterning can be performed by photolithography, and wet etching can be performed to form an electrode.
  • heat treatment 200 ° C. to 300 ° C.
  • N 2 O plasma treatment may be performed as necessary to recover damage to the oxide surface.
  • the protective film 6 may be formed over the oxide semiconductor thin film 4 by a CVD method.
  • examples of the protective film 6 include SiNx films, SiOxNy films, SiOx films, Al 2 O 3 films, Ta 2 O 5 films, and any one of these films. Only one of these films may be used as a single layer, or any one of these films may be laminated and used, or two or more kinds of films may be laminated.
  • the transparent conductive film 8 is electrically connected to the source / drain electrode 5 through the contact hole 7.
  • the kind of the transparent conductive film 8 is not specifically limited, What is normally used can be used.
  • the first and second TFTs of the present invention thus obtained have a mobility of about 40 cm 2 / Vs or more when the mobility is measured by Hall measurement that derives the mobility from Id-Vg measurement. Very high mobility.
  • the present application includes Japanese Patent Application No. 2014-178857 filed on September 2, 2014, Japanese Patent Application No. 2014-245124 filed on December 3, 2014, and July 1, 2015. Claims the benefit of priority based on Japanese Patent Application No. 2015-132533 filed in. Japanese Patent Application No. 2014-178857 filed on September 2, 2014, Japanese Patent Application No. 2014-245124 filed on December 3, 2014, and Japanese Patent Application No. 2014-245124 filed on July 1, 2015 The entire contents of Japanese Patent Application No. 2015-132533 are incorporated herein by reference.
  • Example 1 In this example relating to the first TFT, the influence of the formation conditions of the oxide semiconductor thin film on the mobility of the TFT was examined. In Example 1, a film containing SiNx was used only for the protective film.
  • a Mo thin film of 100 nm as the gate electrode 2 and a SiO 2 (film thickness of 200 nm) as the gate insulating film 3 are sequentially formed.
  • the gate electrode 2 was formed by a DC sputtering method using a pure Mo sputtering target.
  • the sputtering conditions were film formation temperature: room temperature, film formation power density: 3.8 W / cm 2 , carrier gas: Ar, gas pressure during film formation: 2 mTorr, and Ar gas flow rate: 20 sccm.
  • the gate insulating film 3 uses a plasma CVD method, carrier gas: a mixed gas of SiH 4 and N 2 O, film formation power density: 0.96 W / cm 2 , film formation temperature: 320 ° C., gas during film formation The film was formed under a pressure of 133 Pa.
  • an oxide semiconductor thin film 4 (In—Ga—Sn—O film, film thickness: 40 nm) having the following composition was formed under various sputtering conditions shown in Table 1.
  • Ga: Sn 42.7: 26.7: 30.6 atomic%
  • a sputtering target having the same composition as that of the oxide semiconductor thin film 4 was used, and a film was formed by a sputtering method under the following conditions.
  • each content of the metal element of the oxide semiconductor thin film was analyzed by separately preparing a sample in which each oxide semiconductor thin film having a film thickness of 40 nm was formed on a glass substrate by the sputtering method in the same manner as described above.
  • the analysis was performed by ICP (Inductively Coupled Plasma) emission spectroscopy using CIROS Mark II (manufactured by Rigaku Corporation).
  • oxide semiconductor thin film 4 After forming the oxide semiconductor thin film 4 as described above, patterning was performed by photolithography and wet etching. As a wet etching solution, “ITO-07N” manufactured by Kanto Chemical Co., Inc. was used. In this example, it was confirmed that all oxide semiconductor thin films tested were free from residues due to wet etching and could be properly etched.
  • pre-annealing was performed to improve the film quality.
  • Pre-annealing was performed at 350 ° C. for 1 hour in an air atmosphere.
  • an SiOx film (film thickness: 100 nm) was formed on the oxide semiconductor thin film 4 as the etch stop layer 9.
  • the SiOx film was formed by a plasma CVD method using a mixed gas of N 2 O and SiH 4 .
  • the film formation conditions were film formation power density: 0.32 W / cm 2 , film formation temperature: 230 ° C., and gas pressure during film formation: 133 Pa.
  • the etch stop layer 9 was patterned by photolithography and dry etching.
  • a pure Mo film having a thickness of 200 nm was formed above the oxide semiconductor thin film 4 by sputtering.
  • the pure Mo film was formed under the following conditions: input power: DC 300 W (deposition power density: 3.8 W / cm 2 ), carrier gas: Ar, gas pressure: 2 mTorr, substrate temperature: room temperature.
  • a 100 nm thick SiOx film is formed by plasma CVD as a protective film 6 for protecting the oxide semiconductor thin film transistor, and a 150 nm thick SiNx film is further formed. It formed by plasma CVD method.
  • a mixed gas of SiH 4 , N 2 and N 2 O was used to form the SiOx film, and a mixed gas of SiH 4 , N 2 and NH 3 was used to form the SiNx film.
  • the film formation conditions were film formation power density: 0.32 W / cm 2 , film formation temperature: 150 ° C., and gas pressure during film formation: 133 Pa.
  • contact holes 7 for probing for transistor characteristic evaluation were formed in the protective film 6 by photolithography and dry etching. Then, as post-annealing, heat treatment was performed at 260 ° C. for 30 minutes in a nitrogen atmosphere.
  • an ITO film having a thickness of 80 nm was formed as the transparent conductive film 8 to produce the thin film transistor of FIG.
  • an ITO film is formed by DC sputtering using a carrier gas: a mixed gas of argon and oxygen gas, film formation power: 200 W (film formation power density: 2.5 W / cm 2 ), and gas pressure: 5 mTorr. A film was formed.
  • the fabricated thin film transistor had a channel length of 20 ⁇ m and a channel width of 200 ⁇ m.
  • Transistor characteristics (drain current-gate voltage characteristics, Id-Vg characteristics) were measured using a semiconductor parameter analyzer “HP4156C” manufactured by Agilent Technology. Detailed measurement conditions are as follows. No. in Table 1 The Id-Vg characteristic in 1-1 is shown in FIG. Source voltage: 0V Drain voltage: 10V Gate voltage: -30 to 30V (measurement interval: 0.25V) Substrate temperature: Room temperature
  • Threshold voltage The threshold voltage is roughly a value of a gate voltage when the transistor shifts from an off state (a state where the drain current is low) to an on state (a state where the drain current is high).
  • the voltage when the drain current is around 1 nA between the on-current and the off-current is defined as the threshold voltage, and the threshold voltage of each thin film transistor is measured.
  • Id drain current
  • L channel length
  • W channel width
  • Cox capacitance of gate insulating film
  • ⁇ FE field effect mobility
  • the field effect mobility ⁇ FE is derived from the slope of the drain current-gate voltage characteristic (Id-Vg characteristic) near the gate voltage that satisfies the linear region. The higher the field effect mobility, the better. In this example, 40 cm 2 / Vs was used as a reference, and more than that was accepted.
  • the S value is the minimum value of the gate voltage required to increase the drain current 10 times from the Id-Vg characteristic, and the lower the value, the better the characteristic. Specifically, in this case, the S value was 0.4 V / decade or less under favorable conditions.
  • Table 1 shows that when the oxygen partial pressure and the deposition power density are the same, the mobility increases as the gas pressure decreases (see Nos. 1-1, 4, 5, and 6 in Table 1). It was also found that, under the above experimental conditions, when the gas pressure and the deposition power density were the same, the smaller the oxygen partial pressure, the higher the mobility (see Nos. 1-1 to 3 in Table 1). In addition, regarding the film-forming power density, the influence which exerts on mobility was not seen so much.
  • FIG. 4 shows that the oxide semiconductor thin film of the present invention has a crystal structure.
  • the crystal structure of the oxide semiconductor thin film is confirmed immediately after the oxide semiconductor thin film 4 is formed on the gate insulating film 3, and it is demonstrated that the crystal structure is not greatly changed by the thin film transistor manufacturing process.
  • FIG. 5 shows a TEM observation of the cross section of the oxide semiconductor thin film at each timing of A: after formation of the oxide semiconductor thin film, B: after pre-annealing, C: after contact hole formation, and D: post-annealing. Results are shown.
  • FIGS. 5A to 5D An electron diffraction image of a circular region shining in the oxide semiconductor thin film 4 shown in FIGS. 5A to 5D is shown on the right side of FIGS. 5A to 5D. From the right diagrams shown in FIGS. 5A to 5D, it can be seen that there is a region in the ring shape that is slightly shining in any state, and the crystal structure is not greatly changed by the thin film transistor manufacturing process.
  • FIGS. 6 and 7 are different from the oxide semiconductor thin film 4 in the constituent elements, and after manufacturing the thin film transistor in which the oxide semiconductor thin film formed of the In—Ga—Zn—O film is formed, the oxide semiconductor thin film is formed.
  • the results of TEM observation of the oxide semiconductor thin film plane after pre-annealing are shown.
  • Substrate temperature room temperature gas pressure: 1 mTorr or 5 mTorr
  • Deposition power density: 2.55 W / cm 2 Sputtering target used: In: Ga: Zn 33.3: 33.3: 33.3 atomic%
  • FIG. 6 shows the result of forming an In—Ga—Zn—O film at a gas pressure of 1 mTorr
  • FIG. 6A shows the result after forming the In—Ga—Zn—O film
  • FIG. 6B shows the result after pre-annealing.
  • FIG. 7 shows the result of forming an In—Ga—Zn—O film at a gas pressure of 5 mTorr
  • FIG. 7A shows the result after forming the In—Ga—Zn—O film
  • FIG. 7B shows the result after pre-annealing. Yes.
  • FIG. 6 and FIG. 7 show electron beam diffraction images of a circular region shining in the oxide semiconductor thin film of FIGS.
  • spots diffraction points
  • FIGS. 6 and 7 do not include microcrystals. Therefore, it can be seen from the right diagrams of FIGS. 6 and 7 that there is no significant difference in light emission intensity in the ring shape, and it has an amorphous structure.
  • FIG. 8A shows the result of measuring the X-ray diffraction after forming the In—Ga—Sn—O film.
  • pre-annealing was performed to improve the film quality.
  • Pre-annealing was performed at 350 ° C. for 1 hour in an air atmosphere.
  • X-ray diffraction measurement is performed under the same conditions as above, and the measurement results are shown in FIG. 8B.
  • FIG. 8C the result of having measured the X-ray diffraction of the glass substrate as reference data is shown in FIG. 8C.
  • FIG. 8A measured after depositing the In—Ga—Sn—O film
  • FIG. 8B measured after pre-annealing, oxides near 31 ° and 55 ° other than the halo pattern derived from the glass substrate
  • no sharp peak based on crystals was observed.
  • the size of the formed crystal grains is considered to be less than 1 nm. That is, it is suggested that most of the film is amorphous, and the size of the formed crystal grains is less than 1 nm.
  • Example 2 In this example relating to the first TFT, TFTs having four types of shapes shown in the following patterns (i) to (iv) were produced, and the transistor characteristics after the formation of the protective film (insulating film) 6 were evaluated. In Example 2, a film containing SiNx was used only for the protective film.
  • FIGS. 9A to 9D are top views of the thin film transistor in order to clarify the shape of the TFT used in this example.
  • 10A to 10D are cross-sectional views taken along the line A-A 'of FIGS. 9A to 9D.
  • Cross-sectional views taken along the line B-B 'of FIGS. 9A to 9D are shown in FIGS. 11A to 11D.
  • ACT is a region corresponding to the oxide semiconductor thin film 4.
  • Pattern (i) See FIGS. 9A, 10A, and 11A
  • the pattern (i) corresponds to FIG. 1 described above.
  • the source / drain electrodes 5 are not in direct contact with both ends of the oxide semiconductor thin film 4 but are in direct contact with part of the upper surface of the oxide semiconductor thin film 4, and the etch stop layer 9 is formed of the oxide semiconductor thin film 4.
  • 4 is in contact with both ends of the oxide semiconductor thin film 4 and is in direct contact with part of the upper surface of the oxide semiconductor thin film 4.
  • the source / drain electrode 5 does not directly contact both ends of the oxide semiconductor thin film 4, but directly contacts a part of the upper surface of the oxide semiconductor thin film 4.
  • the etch stop layer 9 does not contact both end portions of the oxide semiconductor thin film 4 but directly contacts a part of the upper surface of the oxide semiconductor thin film 4.
  • the source / drain electrodes 5 are in direct contact with both ends of the oxide semiconductor thin film 4 in the channel length direction in the cross-sectional view of FIG.
  • the oxide semiconductor thin film 4 is not in direct contact but is in direct contact with a part of the upper surface of the oxide semiconductor thin film 4, and the etch stop layer 9 is not in contact with both ends of the oxide semiconductor thin film 4. It is in direct contact with a part of the top surface.
  • the pattern (iv) corresponds to FIG. 2 described above.
  • the source / drain electrodes 5 are in direct contact with both ends of the oxide semiconductor thin film 4 and in direct contact with part of the upper surface of the oxide semiconductor thin film 4, and the etch stop layer 9 is formed of the oxide semiconductor thin film 4.
  • the etch stop layer 9 is formed of the oxide semiconductor thin film 4.
  • the TFT with the above pattern (iv) was manufactured by designing a mask so as to obtain a desired shape.
  • a method for forming a TFT having a pattern (i) will be described. Since the shape of the pattern is the same as that of the first embodiment described above, the following description will focus on differences from the first embodiment.
  • Example 1 After the gate electrode 2 and the gate insulating film 3 were sequentially formed on the glass substrate 1 in the same manner as in Example 1 described above, an oxide semiconductor thin film (In—Ga—Sn—O, film thickness having the same composition as in Example 1 was formed. 40 nm).
  • the sputtering conditions are the same as in Example 1 except for the following points.
  • Gas pressure: 1mTorr Oxygen partial pressure: 100 ⁇ O 2 / (Ar + O 2 ) 4% by volume
  • an In—Ga—Zn—O film (with a thickness of 40 nm) described in Patent Document 1 or the like was formed as an oxide semiconductor thin film.
  • an ITO film (film thickness of 80 nm) was formed as the transparent conductive film 8 in the same manner as in Example 1 to produce a thin film transistor having a pattern (i).
  • No. Examples 2-1 to 15 are examples in which an In—Ga—Sn-based oxide having a composition defined in the present invention is used as the oxide semiconductor thin film 4.
  • No. of the example of this invention which has the shape of the pattern (i) which gave the manufacturing conditions prescribed
  • Both 2-5 and 12 have a very high mobility of 40 cm 2 / Vs or more.
  • No. No. 1 treated at 270 ° C. with a higher post-annealing temperature after forming the protective film. In 2-12, the mobility was remarkably high at about 67 cm 2 / Vs.
  • the comparative example No. having the shape of the pattern (iv) does not have the shape defined in the present invention. In 2-8, 11 and 15, the desired high mobility was not obtained.
  • the reason why a very high mobility can be obtained by the configuration of the present invention as in the above pattern (i) is unknown in detail, but it is assumed as follows, for example.
  • the upper surface of the oxide semiconductor thin film 4 is in contact with the source / drain electrode 5 through the contact hole 7 of the etch stop layer 9. That is, both end portions of the oxide semiconductor thin film 4 are not in direct contact with the source / drain electrodes 5.
  • An etch stop layer 9 is disposed on the oxide semiconductor thin film 4 except for the contact hole 7.
  • Mo or Al which is a constituent material of the source / drain electrode 5, is a material in which hydrogen does not easily permeate.
  • the protective film 6 is supplied from SiNx or directly from the etch stop layer 9.
  • the protective film 6 Since the amount of hydrogen in the etch stop layer 9 (SiOx) used in this example is about 5.0 atomic% and the amount of hydrogen in the protective film 6 (SiNx) is about 32 atomic%, the protective film 6 There is a very high possibility that the hydrogen contained therein diffuses into the oxide semiconductor thin film 4 and contributes to the expression of high mobility. Probably, hydrogen passivates the bottom level under the conductor, so that defects in the oxide semiconductor thin film 4 are reduced, leading to high mobility.
  • the portion other than the channel region of the oxide semiconductor thin film 4 is covered with the source / drain electrodes 5 as in the pattern (iv), the supply of hydrogen is limited, so that the mobility is not likely to increase.
  • the oxide semiconductor thin film 4 No. 1 using an In—Ga—Zn-based oxide having a conventional composition is used. In 2-16 to 31, no significantly improved mobility was measured, and the maximum was only 7.1 cm 2 / Vs. That is, no improvement in mobility due to post-annealing and no improvement in mobility due to TFT shape control as in the case of using an In—Ga—Sn-based oxide having the composition of the present invention was observed.
  • Example 3 In this example relating to the second TFT, except that the structure of the etch stop layer is different from that of Example 1, a TFT having the same shape as the pattern (i) was produced, and the transistor characteristics were evaluated.
  • the production method described below is represented as production method A. 3-1 to 8 are manufactured by manufacturing method A.
  • the protective film 6 for protecting the oxide semiconductor transistor is not provided in order to emphasize the usefulness when the layer containing SiNx is used as the etch stop layer 9, but the above-described embodiment 1 is not provided.
  • a protective film 6 may be provided.
  • a Mo thin film of 100 nm as the gate electrode 2 and a SiO 2 (film thickness of 200 nm) as the gate insulating film 3 are sequentially formed.
  • the gate electrode 2 was formed by a DC sputtering method using a pure Mo sputtering target.
  • the sputtering conditions were film formation temperature: room temperature, film formation power density: 3.8 W / cm 2 , carrier gas: Ar, gas pressure during film formation: 2 mTorr, and Ar gas flow rate: 20 sccm.
  • the gate insulating film 3 uses a plasma CVD method, carrier gas: a mixed gas of SiH 4 and N 2 O, film formation power density: 0.96 W / cm 2 , film formation temperature: 320 ° C., gas during film formation The film was formed under a pressure of 133 Pa.
  • an oxide semiconductor thin film 4 (In—Ga—Sn—O film, film thickness: 40 nm) having the following composition was formed under various sputtering conditions shown in Table 3.
  • Ga: Sn 42.7: 26.7: 30.6 atomic%
  • a sputtering target having the same composition as that of the oxide semiconductor thin film 4 was used, and a film was formed by a sputtering method under the following conditions.
  • each content of the metal element of the oxide semiconductor thin film was analyzed by separately preparing a sample in which each oxide semiconductor thin film having a film thickness of 40 nm was formed on a glass substrate by the sputtering method in the same manner as described above.
  • the analysis was performed by ICP (Inductively Coupled Plasma) emission spectroscopy using CIROS Mark II (manufactured by Rigaku Corporation).
  • oxide semiconductor thin film 4 After forming the oxide semiconductor thin film 4 as described above, patterning was performed by photolithography and wet etching. As a wet etching solution, “ITO-07N” manufactured by Kanto Chemical Co., Inc. was used. In this example, it was confirmed that all oxide semiconductor thin films tested were free from residues due to wet etching and could be properly etched.
  • pre-annealing was performed to improve the film quality.
  • Pre-annealing was performed at 350 ° C. for 1 hour in an air atmosphere.
  • an SiOx film 9-1 and a SiNx film 9-2 were formed on the oxide semiconductor thin film as an etch stop layer 9 (FIG. 13A).
  • the SiOx film 9-1 was formed by a plasma CVD method using a mixed gas of N 2 O and SiH 4 .
  • the film formation conditions were film formation power density: 0.32 W / cm 2 , film formation temperature: 230 ° C., and gas pressure during film formation: 133 Pa.
  • the SiNx film 9-2 was formed by a plasma CVD method using a mixed gas of SiH 4 , N 2 , and NH 3 .
  • the film formation conditions were film formation power density: 0.32 W / cm 2 , film formation temperature: 150 ° C., and gas pressure during film formation: 133 Pa.
  • the etch stop layer 9 was patterned by photolithography and dry etching (FIG. 13B). In Example 3-8, only the SiOx film was formed on the oxide semiconductor thin film for comparison.
  • a pure Mo film having a thickness of 200 nm was formed above the oxide semiconductor thin film 4 by sputtering.
  • the pure Mo film was formed under the following conditions: input power: DC 300 W (deposition power density: 3.8 W / cm 2 ), carrier gas: Ar, gas pressure: 2 mTorr, substrate temperature: room temperature.
  • the source / drain electrodes 5 were patterned by photolithography and wet etching to form contact holes 7 for probing for transistor characteristic evaluation (FIG. 13C).
  • FIG. 12 is a cross-sectional view of the manufactured transistor
  • FIG. 13 is a cross-sectional view of the transistor explaining the manufacturing process.
  • the manufactured thin film transistor has a channel length of 20 ⁇ m, a channel width of 200 ⁇ m (No. 3-2, 3, 7, 8), a channel length of 10 ⁇ m, a channel width of 200 ⁇ m (No. 3-4), a channel length of 10 ⁇ m, and a channel width of 100 ⁇ m (No. 3-5), channel length 10 ⁇ m, channel width 50 ⁇ m (No. 3-6).
  • the etch stop layer is formed only of the SiOx film, it is No. As in 3-8, the mobility was comparable to that of a general In—Ga—Zn—O (IGZO) film.
  • the etch stop layer is a laminated film of a SiOx film and a SiNx film, No. 1 is used. High mobility was obtained as in 3-2 to 7. That is, high mobility was obtained when a SiNx film was provided as an upper layer. Also, the mobility was higher when the ratio of the SiNx film thickness to the entire etch stop layer was higher. In addition, the longer the channel length, the higher the mobility, and the shorter the channel width, the higher the mobility.
  • the protective film 6 for protecting the oxide semiconductor transistor is not provided.
  • a protective film 6 may be provided as in Examples 1 and 2.
  • a Mo thin film of 100 nm as the gate electrode 2 and a SiO 2 (film thickness of 200 nm) as the gate insulating film 3 are sequentially formed.
  • the gate electrode 2 was formed by a DC sputtering method using a pure Mo sputtering target.
  • the sputtering conditions were film formation temperature: room temperature, film formation power density: 3.8 W / cm 2 , carrier gas: Ar, gas pressure during film formation: 2 mTorr, and Ar gas flow rate: 20 sccm.
  • the gate insulating film 3 uses a plasma CVD method, carrier gas: a mixed gas of SiH 4 and N 2 O, film formation power density: 0.96 W / cm 2 , film formation temperature: 320 ° C., gas during film formation The film was formed under a pressure of 133 Pa.
  • an oxide semiconductor thin film 4 (In—Ga—Sn—O film, film thickness 40 nm) having the following composition was formed under various sputtering conditions shown in Table 4.
  • Ga: Sn 42.7: 26.7: 30.6 atomic%
  • a sputtering target having the same composition as that of the oxide semiconductor thin film 4 was used, and a film was formed by a sputtering method under the following conditions.
  • each content of the metal element of the oxide semiconductor thin film was analyzed by separately preparing a sample in which each oxide semiconductor thin film having a film thickness of 40 nm was formed on a glass substrate by the sputtering method in the same manner as described above.
  • the analysis was performed by ICP (Inductively Coupled Plasma) emission spectroscopy using CIROS Mark II (manufactured by Rigaku Corporation).
  • oxide semiconductor thin film 4 After forming the oxide semiconductor thin film 4 as described above, patterning was performed by photolithography and wet etching. As a wet etching solution, “ITO-07N” manufactured by Kanto Chemical Co., Inc. was used. In this example, it was confirmed that all oxide semiconductor thin films tested were free from residues due to wet etching and could be properly etched.
  • pre-annealing was performed to improve the film quality.
  • Pre-annealing was performed at 350 ° C. for 1 hour in an air atmosphere.
  • an SiOx film 9-1 and a SiNx film 9-2 were formed on the oxide semiconductor thin film as an etch stop layer 9 as shown in Table 4, FIG. 12, and FIG. 13 (FIG. 13A).
  • the SiOx film 9-1 was formed by a plasma CVD method using a mixed gas of N 2 O and SiH 4 .
  • the film formation conditions were film formation power density: 0.32 W / cm 2 , film formation temperature: 230 ° C., and gas pressure during film formation: 133 Pa.
  • the SiNx film 9-2 was formed by a plasma CVD method using a mixed gas of SiH 4 , N 2 , and NH 3 .
  • the film formation conditions were film formation power density: 0.32 W / cm 2 , film formation temperature: 150 ° C., and gas pressure during film formation: 133 Pa. Then, as post-annealing, heat treatment was performed at 260 ° C. for 30 minutes in a nitrogen atmosphere. After the formation of the SiOx film 9-1 and the SiNx film 9-2, post-annealing was performed, and the etch stop layer 9 (9-1 and 9-2) was patterned by photolithography and dry etching (FIG. 13B). .
  • a pure Mo film having a thickness of 200 nm was formed above the oxide semiconductor thin film 4 by sputtering.
  • the pure Mo film was formed under the following conditions: input power: DC 300 W (deposition power density: 3.8 W / cm 2 ), carrier gas: Ar, gas pressure: 2 mTorr, substrate temperature: room temperature.
  • the source / drain electrodes 5 were patterned by photolithography and wet etching to form contact holes 7 for probing for transistor characteristic evaluation (FIG. 13C).
  • FIG. 12 is a cross-sectional view of the manufactured transistor
  • FIG. 13 is a cross-sectional view of the transistor explaining the manufacturing process.
  • the manufactured thin film transistor had a channel length of 20 ⁇ m, a channel width of 200 ⁇ m (No. 4-2), a channel length of 10 ⁇ m, and a channel width of 50 ⁇ m (No. 4-3).
  • Example 5 In Example 5, a transistor was produced in substantially the same manner as in Example 3 except that the shape TFT shown in the pattern (iv) was produced instead of the shape shown in the pattern (i) in Example 3, and transistor characteristics were obtained. Evaluated.
  • a Mo thin film of 100 nm as the gate electrode 2 and a SiO 2 (film thickness of 200 nm) as the gate insulating film 3 are sequentially formed.
  • the gate electrode 2 was formed by a DC sputtering method using a pure Mo sputtering target.
  • the sputtering conditions were film formation temperature: room temperature, film formation power density: 3.8 W / cm 2 , carrier gas: Ar, gas pressure during film formation: 2 mTorr, and Ar gas flow rate: 20 sccm.
  • the gate insulating film 3 uses a plasma CVD method, carrier gas: mixed gas of SiH 4 and N 2 O, deposition power density: 1.27 W / cm 2 , deposition temperature: 320 ° C., gas during deposition The film was formed under a pressure of 133 Pa.
  • an oxide semiconductor thin film 4 (In—Ga—Sn—O film, thickness 40 nm) having the following composition was formed under the sputtering conditions shown in Table 5.
  • Ga: Sn 42.7: 26.7: 30.6 atomic%
  • a sputtering target having the same composition as that of the oxide semiconductor thin film 4 was used, and a film was formed by a sputtering method under the following conditions.
  • each content of the metal element of the oxide semiconductor thin film was analyzed by separately preparing a sample in which each oxide semiconductor thin film having a film thickness of 40 nm was formed on a glass substrate by the sputtering method in the same manner as described above.
  • the analysis was performed by ICP (Inductively Coupled Plasma) emission spectroscopy using CIROS Mark II (manufactured by Rigaku Corporation).
  • oxide semiconductor thin film 4 After forming the oxide semiconductor thin film 4 as described above, patterning was performed by photolithography and wet etching. As a wet etching solution, “ITO-07N” manufactured by Kanto Chemical Co., Inc. was used. In this example, it was confirmed that all oxide semiconductor thin films tested were free from residues due to wet etching and could be properly etched.
  • pre-annealing was performed to improve the film quality.
  • Pre-annealing was performed at 350 ° C. for 1 hour in an air atmosphere.
  • an SiOx film 9-1 and a SiNx film 9-2 were formed on the oxide semiconductor thin film as an etch stop layer 9 as shown in Table 5, FIG. 14, and FIG. 15 (FIG. 15A).
  • the SiOx film 9-1 was formed by a plasma CVD method using a mixed gas of N 2 O and SiH 4 .
  • the film formation conditions were film formation power density: 0.32 W / cm 2 , film formation temperature: 230 ° C., and gas pressure during film formation: 133 Pa.
  • the SiNx film 9-2 was formed by a plasma CVD method using a mixed gas of SiH 4 , N 2 , and NH 3 .
  • the film formation conditions were film formation power density: 0.32 W / cm 2 , film formation temperature: 150 ° C., and gas pressure during film formation: 133 Pa.
  • the etch stop layer 9 was patterned by photolithography and dry etching (FIG. 15B).
  • a pure Mo film having a thickness of 200 nm was formed above the oxide semiconductor thin film 4 by sputtering.
  • the pure Mo film was formed under the following conditions: input power: DC 300 W (deposition power density: 3.8 W / cm 2 ), carrier gas: Ar, gas pressure: 2 mTorr, substrate temperature: room temperature.
  • the source / drain electrodes 5 were patterned by photolithography and wet etching to form contact holes 7 for probing for transistor characteristic evaluation (FIG. 15C).
  • FIG. 14 is a cross-sectional view of the manufactured transistor
  • FIG. 15 is a cross-sectional view of the transistor illustrating the manufacturing process.
  • the fabricated thin film transistors had a channel length of 10 ⁇ m, a channel width of 200 ⁇ m, 100 ⁇ m, and 25 ⁇ m (No. 5-1 to 3), a channel length of 25 ⁇ m, a channel width of 200 ⁇ m, 100 ⁇ m, and 25 ⁇ m (No. 5-4 to 6).
  • the mobility when the etch stop layer is only the SiOx film is low, but from Table 5, the etch stop layer is a laminated film of the SiOx film and the SiNx film, and the etch stop layer is the oxide semiconductor thin film. Even when arranged only in the channel portion, a high mobility of about 40 cm 2 / Vs or more was expressed. In addition, it was found that when the etch stop layer is a laminated film of a SiOx film and a SiNx film and the etch stop layer is disposed only in the channel portion of the oxide semiconductor thin film, the mobility is high regardless of the channel width.

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Abstract

L'invention concerne un transistor à couches minces comprenant une électrode de grille, un film d'isolation de grille, un film mince semi-conducteur à oxyde, une couche d'arrêt de gravure pour protéger le film mince semi-conducteur à oxyde, des électrodes de source et de drain et un film de protection, prévus dans cet ordre sur un substrat. Le film mince semi-conducteur à oxyde est fait d'un oxyde choisi dans le groupe comprenant In, Ga et Sn comme éléments métalliques, et O, et présente une structure amorphe, et la couche d'arrêt de gravure et/ou le film de protection comprend/comprennent du SiNx. Ce transistor à couches minces présente une mobilité extrêmement élevée supérieure ou égale à environ 40 cm2/Vs.
PCT/JP2015/072326 2014-09-02 2015-08-06 Transistor a couches minces WO2016035503A1 (fr)

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US15/327,296 US20170170029A1 (en) 2014-09-02 2015-08-06 Thin film transistor
KR1020177005510A KR101974754B1 (ko) 2014-09-02 2015-08-06 박막 트랜지스터
CN201580035556.7A CN106489209B (zh) 2014-09-02 2015-08-06 薄膜晶体管

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JP2014178587 2014-09-02
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