WO2010103587A1 - バリア層を構成層とする薄膜トランジスターおよびバリア層のスパッタ成膜に用いられるCu合金スパッタリングターゲット - Google Patents
バリア層を構成層とする薄膜トランジスターおよびバリア層のスパッタ成膜に用いられるCu合金スパッタリングターゲット Download PDFInfo
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- WO2010103587A1 WO2010103587A1 PCT/JP2009/005576 JP2009005576W WO2010103587A1 WO 2010103587 A1 WO2010103587 A1 WO 2010103587A1 JP 2009005576 W JP2009005576 W JP 2009005576W WO 2010103587 A1 WO2010103587 A1 WO 2010103587A1
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- 230000004888 barrier function Effects 0.000 title claims abstract description 65
- 239000010409 thin film Substances 0.000 title claims abstract description 38
- 229910000881 Cu alloy Inorganic materials 0.000 title claims abstract description 24
- 238000005477 sputtering target Methods 0.000 title claims abstract description 22
- 239000010408 film Substances 0.000 title abstract description 10
- 230000015572 biosynthetic process Effects 0.000 title abstract description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000011521 glass Substances 0.000 claims abstract description 13
- 239000012535 impurity Substances 0.000 claims abstract description 13
- 238000002161 passivation Methods 0.000 claims abstract description 7
- 238000004544 sputter deposition Methods 0.000 claims description 15
- 230000001590 oxidative effect Effects 0.000 claims description 11
- 239000000203 mixture Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims 1
- 230000008021 deposition Effects 0.000 claims 1
- 229910052802 copper Inorganic materials 0.000 abstract description 13
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 24
- 239000010949 copper Substances 0.000 description 18
- 239000001257 hydrogen Substances 0.000 description 15
- 229910052739 hydrogen Inorganic materials 0.000 description 15
- 238000009832 plasma treatment Methods 0.000 description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 10
- 239000001301 oxygen Substances 0.000 description 10
- 229910052760 oxygen Inorganic materials 0.000 description 10
- 238000012545 processing Methods 0.000 description 9
- 239000000470 constituent Substances 0.000 description 8
- 230000010354 integration Effects 0.000 description 7
- 230000000052 comparative effect Effects 0.000 description 6
- 238000000926 separation method Methods 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910000882 Ca alloy Inorganic materials 0.000 description 1
- 229910017767 Cu—Al Inorganic materials 0.000 description 1
- 206010021143 Hypoxia Diseases 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
-
- C—CHEMISTRY; METALLURGY
- C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
- C22C—ALLOYS
- C22C9/00—Alloys based on copper
- C22C9/01—Alloys based on copper with aluminium as the next major constituent
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/14—Metallic material, boron or silicon
- C23C14/16—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon
- C23C14/165—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon by cathodic sputtering
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/34—Sputtering
- C23C14/3407—Cathode assembly for sputtering apparatus, e.g. Target
- C23C14/3414—Metallurgical or chemical aspects of target preparation, e.g. casting, powder metallurgy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
Definitions
- the present invention relates to a thin film transistor used for various displays, and in particular, a barrier layer positioned between a pure copper wiring layer (drain electrode layer and source electrode layer) which is a constituent layer of the thin film transistor and an n-type Si semiconductor layer. And a Cu alloy sputtering target used for forming the barrier layer. More specifically, it has a high adhesion strength to the n-type Si semiconductor layer as well as the wiring layer, and a function of sufficiently preventing mutual diffusion of Si and Cu as constituent components of the upper and lower layers ( The following relates to a barrier layer having a barrier function) and a Cu alloy sputtering target used for forming the barrier layer.
- This application claims priority based on Japanese Patent Application No. 2009-057359 filed in Japan on March 11, 2009, the contents of which are incorporated herein by reference.
- Liquid crystal displays, plasma displays, organic EL displays, inorganic EL displays and the like are known as flat panel displays using thin film transistors driven by an active matrix method.
- a wiring made of a metal layer in a lattice form is formed in close contact with the surface of the glass substrate, and a thin film transistor is provided at an intersection of the lattice shaped wiring made of the metal layer. .
- the thin film transistor includes a pure copper gate electrode layer 3 bonded to the surface of the glass substrate 1 from the substrate side through a metal Mo adhesion layer 2 as illustrated in FIG.
- Silicon gate insulating layer 4 Si semiconductor layer 5, n-type Si semiconductor layer 6, a barrier layer formed by sputtering a Cu alloy target in an oxidizing atmosphere, and a pure copper drain electrode layer partitioned by separation grooves 8 It is also well known that it has a layer structure in which a wiring layer 9 composed of 9a and a source electrode layer 9b, and a passivation layer of silicon nitride and a transparent electrode layer are sequentially laminated, although not shown.
- a separation groove 8 is formed in the wiring layer 9 by wet etching to divide it into a drain electrode layer 9a and a source electrode layer 9b.
- the portion of the n-type Si semiconductor layer exposed on the bottom surface of the dispersion groove (separation groove 8) formed in the wiring layer 9 is removed by dry etching.
- hydrogen atoms are lost from the surface particularly in the dry etching process. Therefore, the surface becomes extremely unstable, that is, dangling bonds (dangling bonds) increase, which becomes a surface defect.
- the barrier layer which is a constituent layer of the thin film transistor is atomic% (hereinafter,% indicates atomic%), and contains one or more of Mg, Ti, Al, and Cr: 0.5 to 20% The remainder is formed by a method in which a Cu alloy sputtering target having a component composition consisting of Cu and inevitable impurities (however, 1% or less) is used, and after sputtering film formation, heat oxidation treatment is performed in an oxidizing atmosphere (air). It is also known that.
- An object of the present invention is to provide a thin film transistor including a barrier film having high adhesion strength between the barrier layer and the n-type Si semiconductor layer, and a Cu alloy sputtering target capable of forming the barrier layer.
- the present inventors have studied from the above viewpoint to ensure high adhesion strength between the barrier layer and the n-type Si semiconductor layer in the conventional thin film transistor. As a result, the following research results were obtained.
- gas 100% hydrogen gas
- hydrogen gas flow rate 10 to 1000 SCCM
- hydrogen gas pressure 10 to 500 Pa
- output 0.005 to 0.5 W / cm 2
- processing temperature 250 to 350 ° C.
- processing time 1
- hydrogen plasma treatment under high temperature and extended conditions, such as ⁇ 5 minutes.
- the oxygen component is activated, diffuses and moves to the wiring layer side and the n-type Si semiconductor layer side, and the oxygen content ratio of the barrier layer decreases (oxygen deficiency). There seems to be a cause.
- the present invention has been made based on the above research results and has the following requirements.
- the thin film transistor having a high adhesion strength between the barrier layer and the n-type Si semiconductor layer of the present invention includes a gate electrode layer, a gate insulating layer, a Si semiconductor layer, and an n-type Si bonded to the surface of the glass substrate via the adhesion layer.
- the barrier layer contains, in atomic%, Al: 1-10%, Ca: 0.1-2%, and a Cu alloy sputtering target having a composition containing Cu and 1% or less of inevitable impurities as the balance. Used and sputtered in an oxidizing atmosphere.
- the Cu alloy sputtering target used for sputter deposition of the barrier layer of the present invention is used for sputter deposition of the barrier layer constituting the thin film transistor in an oxidizing atmosphere, and is atomic%, Al: 1 to 10%, Ca : Containing 0.1 to 2%, with the balance being Cu alloy having a component composition containing Cu and 1% or less inevitable impurities.
- the barrier layer located between the upper pure copper wiring layer and the lower n-type Si semiconductor layer has Al: 1 to 10%, Ca: 0.1 to 2%.
- a Cu alloy sputtering target having a component composition containing Cu and 1% or less of inevitable impurities is used as the balance, and the film is formed by sputtering in an oxidizing atmosphere.
- the adhesion with the upper wiring layer the adhesion with the n-type Si semiconductor layer of the lower layer is excellent, and this excellent adhesion is applied during the manufacturing process of the thin film transistor. It is maintained even after hydrogen plasma treatment under high temperature and prolonged conditions. Furthermore, it also has an excellent barrier function.
- the thin film transistor of the present invention can sufficiently satisfy the large screen and high integration of the flat panel display.
- the Cu alloy sputtering target of the present invention can form a barrier film of the above-described thin film transistor.
- FIG. 1 is a schematic vertical sectional view of an essential part of a thin film transistor.
- Al ensures strong adhesion between the barrier layer and the upper wiring layer, and between the barrier layer and the lower n-type Si semiconductor layer, and has an excellent barrier function. It has the effect of providing the barrier layer to be formed. However, if the content is less than 1%, a desired improvement effect cannot be obtained in the above action. On the other hand, when the content ratio exceeds 10%, a decreasing tendency appears in conductivity. Therefore, the content ratio is set to 1 to 10%, desirably 2 to 8%.
- the Ca component stabilizes the barrier layer formed by sputtering film formation in an oxidizing atmosphere, and prevents adhesion deterioration even when the hydrogen plasma treatment conditions are increased in temperature and time. There is.
- oxygen as a constituent component diffuses and moves to the upper copper wiring layer and the lower n-type Si semiconductor layer, so that the oxygen content in the barrier layer is reduced. In some cases, oxygen itself was insufficient.
- the Ca component has an effect of preventing the barrier layer itself from being deficient in oxygen particularly by suppressing the above-described oxygen diffusion movement, and this is considered to suppress a decrease in adhesion.
- the content ratio is set to 0.1 to 2%.
- the content ratio of inevitable impurities in the sputtered barrier layer also exceeds 1%. In this case, a downward tendency appears in the adhesion. For this reason, the content of inevitable impurities must be 1% or less.
- FIG. 1 shows a longitudinal section of a main part of a thin film transistor of the present invention.
- the thin film transistor of the present invention comprises a gate electrode layer 3, a gate insulating layer 4, a Si semiconductor layer 5, an n-type Si semiconductor layer 6, a barrier layer 7, and a mutual separation bonded to the surface of the glass substrate 1 through an adhesion layer 2.
- the barrier layer 7 is formed by sputtering in an oxidizing atmosphere using the above-described Cu alloy sputtering target of the present invention.
- the adhesiveness between the barrier layer 7 and the wiring layer 9 and between the barrier layer 7 and the n-type Si semiconductor layer 6 is excellent. Furthermore, this excellent adhesion can be maintained even after hydrogen plasma treatment under high temperature and long time conditions. Also, an excellent barrier function can be obtained.
- the adhesion strength between the barrier layer and the n-type Si semiconductor layer of the thin film transistor of the present invention will be specifically described with reference to examples.
- bonding was performed from the surface side of a glass substrate having dimensions of length: 320 mm ⁇ width: 400 mm ⁇ thickness: 0.7 mm through a metal Mo adhesion layer having a thickness of 50 nm.
- a gate electrode layer made of pure copper having a thickness of 250 nm, a gate electrode layer made of silicon nitride having a thickness of 300 nm, a Si semiconductor layer having a thickness of 150 nm, and an n-type Si semiconductor layer having a thickness of 10 nm were sequentially stacked.
- a Cu alloy sputtering target of the present invention example of a Cu—Al—Ca alloy having the composition shown in Tables 1 and 2 (hereinafter referred to as a target of the present invention example) and a Cu example of a Cu—Al alloy comparative example
- An alloy sputtering target (hereinafter, referred to as a comparative target) was produced.
- the inevitable impurity content of the target was 1% or less.
- atmosphere pressure 0.4 Pa
- substrate heating Sputtering was performed at a temperature of 100 ° C. to form a barrier layer having a thickness of 50 nm. Further, a pure copper wiring layer was formed to a thickness of 250 nm.
- the obtained thin film transistor samples 1 to 20 of the present invention and the thin film transistor samples 1 to 10 of the comparative example were subjected to hydrogen plasma treatment under the following conditions.
- the above conditions are hydrogen plasma processing conditions corresponding to the increase in screen size and integration of flat panel displays, and the processing temperature is relatively higher than the conventional hydrogen plasma processing conditions. High and processing time is long.
- the cross-cut adhesion test is in accordance with JIS-K5400, using 11 cutters on the surface of the sample at intervals of 0.5 mm, 1 mm, 1.5 mm, and 2 mm, respectively, vertically and horizontally, n-type from the surface. Grooves (cuts) were made at a depth reaching the Si semiconductor layer and a groove width of 0.1 mm. As a result, 100 cells were formed at each interval. A 3M scotch tape was adhered and adhered over the entire mesh, and then peeled off at once. And the number (pieces / 100) of the squares which peeled among 100 squares of the sample surface was measured. The measurement results are shown in Tables 1 to 3.
- the thin film transistor of the present invention can sufficiently satisfy the large screen and high integration of the flat panel display.
- a thin film transistor including a barrier film having excellent barrier function and excellent adhesion between the barrier layer and the wiring layer and between the barrier layer and the n-type Si semiconductor layer.
- This excellent adhesion can be maintained even after hydrogen plasma treatment at high temperature for a long time. Therefore, it can be suitably applied as a thin film transistor that can satisfactorily cope with the large screen and high integration of flat panel displays.
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Abstract
Description
本願は、2009年3月11日に、日本に出願された特願2009-057359号に基づき優先権を主張し、その内容をここに援用する。
前記湿式エッチング処理およびドライエッチング処理後の分離溝8の底面に露出する部分のSi半導体層5においては、特に前記ドライエッチング処理で表面から水素原子が失われる。このため、その表面がきわめて不安定な状態となり、すなわち未結合手(ダングリングボンド)が増大し、これが表面欠陥となる。この表面欠陥が、薄膜トランジスターのオフ電流を増加させ、その結果、LCDのコントラストの低減や視野角を小さくするなどの問題点の発生が避けられない不安定な状態になる。このため、このSi半導体層5の露出表面に、ガス:100%水素ガス、水素ガス流量:10~1000SCCM、水素ガス圧:10~500Pa、処理温度:200~250℃、出力:0.005~0.5W/cm2、処理時間:0.5~1分の条件で水素プラズマ処理を施して、Si半導体層5の表面の未結合手(ダングリングボンド)を水素原子と結合させて安定化する処理が施されている。
上記の従来の薄膜トランジスターにおいては、ガラス基板1と純銅のゲート電極層3との間、前記ゲート電極層3と窒化珪素のゲート絶縁層4との間、前記ゲート絶縁層4とSi半導体層5との間、前記Si半導体層5とn型Si半導体層6との間、およびバリア層と純銅の配線層9との間、さらに純銅の配線層9と図示されていない窒化珪素のパッシベーション層、前記パッシベーション層と透明電極層との間には、上記の要求に十分満足に対応できる高い密着強度が確保されている。しかし、上記のバリア層とn型Si半導体層6との間の密着強度は、相対的に低く、上記の要求に満足に対応できる高い密着強度を具備していないのが現状である。
(a)薄膜トランジスターの構成層であるバリア層のn型Si半導体層に対する密着強度が、フラットパネルディスプレイの大画面化および高集積化に伴って低くなる原因としては、特に上記の水素プラズマ処理条件が、高温化および長時間化することが挙げられる。例えば、ガス:100%水素ガス、水素ガス流量:10~1000SCCM、水素ガス圧:10~500Pa、出力:0.005~0.5W/cm2、処理温度:250~350℃、処理時間:1~5分のように、高温化および長時間化した条件での水素プラズマ処理の必要性が生じる。この結果、バリア層の構成成分のうち、特に、酸素成分が活性化し、配線層側およびn型Si半導体層側に拡散移動し、前記バリア層の酸素含有割合が低下すること(酸素不足)に原因があると考えられる。
すなわち、Al:1~10%、Ca:0.1~2%を含有し、残部として、Cuと1%以下の不可避不純物を含む成分組成を有するCu合金スパッタリングターゲットを用いて、酸化雰囲気でスパッタ成膜することによりバリア層を形成し、特性を評価した。その結果、フラットパネルディスプレイの大画面化および高集積化に伴う高温で長時間の条件での水素プラズマ処理後でも、バリア層と配線層との間、およびバリア層とn型Si半導体層との間に高い密着強度が保持され、かつ優れたバリア機能も保持されたバリア層を形成できることが確認できた。
この理由は、合金成分であるCaの作用によって、配線層側およびn型Si半導体層側への酸素の拡散移動が著しく抑制されるようになるためであると考えられる。
本発明のバリア層とn型Si半導体層とが高い密着強度を有する薄膜トランジスターは、ガラス基板の表面に密着層を介して接合されたゲート電極層、ゲート絶縁層、Si半導体層、n型Si半導体層、バリア層、相互分離されたドレイン電極層とソース電極層からなる配線層、パッシベーション層、および透明電極層を有し、前記層は、この順に、前記ガラス基板側から順次積層形成され、上記バリア層は、原子%で、Al:1~10%、Ca:0.1~2%を含有し、残部として、Cuと1%以下の不可避不純物を含む成分組成を有するCu合金スパッタリングターゲットを用い、酸化雰囲気でスパッタ成膜されている。
本発明のバリア層のスパッタ成膜に用いられるCu合金スパッタリングターゲットは、薄膜トランジスターを構成するバリア層を酸化雰囲気でスパッタ成膜するために用いられ、原子%で、Al:1~10%、Ca:0.1~2%を含有し、残部として、Cuと1%以下の不可避不純物を含む成分組成を有するCu合金からなる。
前記上側層の配線層との密着性は勿論のこと、前記下側層のn型Si半導体層との密着性にも優れ、この優れた密着性は、薄膜トランジスターの製造工程中に施される高温化および長時間化した条件での水素プラズマ処理後でも保持される。更に、優れたバリア機能も具備する。以上により、本発明の薄膜トランジスターは、フラットパネルディスプレイの大画面化および高集積化に十分満足に対応できる。
この発明のCu合金スパッタリングターゲットは、上記した薄膜トランジスターのバリア膜を形成できる。
次に、この発明のCu合金スパッタリングターゲットの成分組成を上記の通りに限定した理由を説明する。
(a)Al
Al成分には、バリア層と上側層の配線層との間、およびバリア層と下側層のn型Si半導体層との間に、強固な密着性を確保すると共に、優れたバリア機能を、形成するバリア層に具備せしめる作用がある。しかし、その含有割合が1%未満では、前記作用に所望の向上効果が得られない。一方、その含有割合が10%を越えると、導電性に低下傾向が現れるようになる。このため、その含有割合を1~10%、望ましくは2~8%と定めた。
Ca成分には、上記の通り、酸化雰囲気でのスパッタ成膜で形成されたバリア層自体を安定化し、上記水素プラズマ処理条件が高温化および長時間化しても、密着性の低下を防止する作用がある。
水素プラズマ処理の際、構成成分である酸素が、上側層の純銅の配線層および下側層のn型Si半導体層に拡散移動して、前記バリア層における酸素の含有割合が低減し、すなわち層自体が酸素不足となる場合があった。Ca成分には、特に上記した酸素の拡散移動を抑制してバリア層自体が酸素不足となるのを防止する作用があり、これにより密着性の低下が抑制されると考えられる。
その含有割合が0.1%未満では、前記作用に所望の向上効果が得られない。一方、その含有割合が2%を越えても、より一層の向上効果が得られない。このため、その含有割合を0.1~2%と定めた。
ターゲットの不可避不純物が1%を越えると、スパッタ成膜されたバリア層における不可避不純物の含有割合も1%を越えて多くなってしまう。この場合、密着性に低下傾向が現れるようになる。このため、不可避不純物の含有割合は、1%以下にしなければならない。
図1は、本発明の薄膜トランジスターの要部縦断面を示す。
この発明の薄膜トランジスターは、ガラス基板1の表面に密着層2を介して接合されたゲート電極層3、ゲート絶縁層4、Si半導体層5、n型Si半導体層6、バリア層7、相互分離されたドレイン電極層9aとソース電極層9bからなる配線層9、パッシベーション層、および透明電極層を有する。これら層は、この順に、ガラス基板側から順次積層形成されている。
上記バリア層7は、前述した本発明のCu合金スパッタリングターゲットを用い、酸化雰囲気でスパッタ成膜されている。このため、前述したように、バリア層7と配線層9との間、およびバリア層7とn型Si半導体層6との間の密着性に優れる。さらに、この優れた密着性は、高温で長時間の条件での水素プラズマ処理後でも保持できる。また、優れたバリア機能も得られる。
従来の膜形成条件にしたがって、縦:320mm×横:400mm×厚さ:0.7mmの寸法をもったガラス基板の表面側から、膜厚:50nmの金属Moの密着層を介して接合された膜厚:250nmの純銅のゲート電極層、膜厚:300nmの窒化珪素のゲート電極層、膜厚:150nmのSi半導体層、および膜厚:10nmのn型Si半導体層を順次積層形成した。
さらに、純銅の配線層を250nmの膜厚で形成した。
以上により、本発明例の薄膜トランジスター試料1~20および比較例の薄膜トランジスター試料1~10をそれぞれ製造した。
ガス:100%水素ガス
水素ガス流量:500sccm
水素ガス圧:250Pa
処理温度:275℃
出力:0.1W/cm2
処理時間:3分
上記条件は、フラットパネルディスプレイの大画面化および高集積化に対応する水素プラズマ処理条件であり、従来行われている水素プラズマ処理条件に比して、相対的に処理温度が高く、かつ、処理時間が長い。
碁盤目付着試験は、JIS-K5400に準じ、上記試料の表面に、カッターを用いて、0.5mm、1mm、1.5mm、および2mmの間隔で、それぞれ縦横に11本ずつ、表面からn型Si半導体層に達する深さで、かつ0.1mmの溝幅で、溝(切り込み)を入れた。これにより、それぞれの間隔で100個の升目を形成した。この升目全体に亘って、3M社製スコッチテープを密着して貼り付け、次いで一気に引き剥がした。そして、試料表面の100個の升目のうち、剥離した升目の数(個/100)を測定した。この測定結果を表1~3に示した。
これに対して、従来Cu合金スパッタリングターゲットに相当する成分組成を有する比較例のターゲット1~10を用いて、同じスパッタ条件で形成されたバリア層を構成層とする比較例の薄膜トランジスター試料1~10においては、いずれも通常条件に比して高い処理温度および長い処理時間での水素プラズマ処理では、バリア層とn型Si半導体層との間の付着強度(密着性)は低いことがわかった。
上述のように、この発明の薄膜トランジスターは、フラットパネルディスプレイの大画面化および高集積化に十分満足に対応できる。
Claims (2)
- ガラス基板の表面に密着層を介して接合されたゲート電極層、ゲート絶縁層、Si半導体層、n型Si半導体層、バリア層、相互分離されたドレイン電極層とソース電極層からなる配線層、パッシベーション層、および透明電極層を有し、
前記層は、この順に、前記ガラス基板側から順次積層形成され、
上記バリア層は、原子%で、Al:1~10%、Ca:0.1~2%を含有し、残部として、Cuと1%以下の不可避不純物を含む成分組成を有するCu合金スパッタリングターゲットを用い、酸化雰囲気でスパッタ成膜されたことを特徴とする、バリア層とn型Si半導体層とが高い密着強度を有する薄膜トランジスター。 - 薄膜トランジスターを構成するバリア層を酸化雰囲気でスパッタ成膜するために用いられ、
原子%で、
Al:1~10%、
Ca:0.1~2%を含有し、
残部として、Cuと1%以下の不可避不純物を含む成分組成を有するCu合金からなることを特徴とするバリア層のスパッタ成膜に用いられるCu合金スパッタリングターゲット。
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KR1020117017282A KR101261786B1 (ko) | 2009-03-11 | 2009-10-22 | 배리어층을 구성층으로 하는 박막 트랜지스터 및 배리어층의 스퍼터 성막에 사용되는 Cu 합금 스퍼터링 타깃 |
CN200980157928.8A CN102349157B (zh) | 2009-03-11 | 2009-10-22 | 以阻挡层为构成层的薄膜晶体管以及用于阻挡层的溅射成膜的Cu合金溅射靶 |
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