CN109155243A - 层叠配线膜及薄膜晶体管元件 - Google Patents

层叠配线膜及薄膜晶体管元件 Download PDF

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Publication number
CN109155243A
CN109155243A CN201780029216.2A CN201780029216A CN109155243A CN 109155243 A CN109155243 A CN 109155243A CN 201780029216 A CN201780029216 A CN 201780029216A CN 109155243 A CN109155243 A CN 109155243A
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film
layer
wiring
alloy
stacking
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志田阳子
后藤裕史
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Kobe Steel Ltd
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Kobe Steel Ltd
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
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    • C03C17/00Surface treatment of glass, not in the form of fibres or filaments, by coating
    • C03C17/06Surface treatment of glass, not in the form of fibres or filaments, by coating with metals
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    • C03C17/00Surface treatment of glass, not in the form of fibres or filaments, by coating
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    • C03C17/34Surface treatment of glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions
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    • C03C17/00Surface treatment of glass, not in the form of fibres or filaments, by coating
    • C03C17/34Surface treatment of glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions
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Abstract

本发明涉及一种层叠配线膜,其具备包含电阻为10μΩcm以下的Cu或Cu合金的配线层、以及设于所述配线层的上层及下层中的至少一者的包含Cu与X元素的Cu‑X合金层,X元素为选自由Al、Mn、Zn以及Ni所组成的X群组中的至少一种,构成Cu‑X合金层的金属为特定的组成系。根据本发明的层叠配线膜,可提供一种电阻低、无利用CVD法的层间绝缘膜的SiOx成膜中的剥离、且即使进行400℃以上的高温热处理也无电阻上升的层叠配线膜。

Description

层叠配线膜及薄膜晶体管元件
技术领域
本发明涉及一种层叠配线膜及薄膜晶体管元件。
背景技术
作为用于液晶面板或有机电致发光(Electro Luminescence,EL)面板等平板显示器或触摸屏等显示装置的薄膜晶体管(以下,也称为TFT:Thin Film Transistor)的半导体材料,已知有氧化物半导体或低温多晶硅半导体(以下,也称为LTPS:Low TemperaturePoly-Silicon)。
氧化物半导体或LTPS半导体与现有所利用的非晶硅半导体材料相比,电子迁移率大而可使TFT元件高速化。
另一方面,正进行通过将配线材料低电阻化而加速TFT元件的驱动速度的研究。现有的平板显示器的电极配线中一直使用Al(铝)薄膜或氧化铟锡(Indium Tin Oxide,ITO)薄膜,但提出有电阻更低的Cu(铜)电极配线或Cu合金电极配线的应用。
然而,在使用Cu配线的情况下产生如下课题。例如,相较于现有的使用非晶硅的元件,使用氧化物半导体或LTPS半导体的TFT元件必须历经高温热处理工艺,必须耐受400℃~500℃左右的加热。另外,Cu配线与玻璃基板、Si(硅)膜等半导体膜、金属氧化物膜等的密接性差。
作为所述使用Cu的技术,在专利文献1中提出有一种具备与玻璃基板等透明基板的密接性优异的Cu合金膜的显示装置。在专利文献1的显示装置中,Cu合金膜的特征在于:具有包含第一层(Y)与第二层(X)的层叠结构,且第一层(Y)与透明基板接触,所述第一层(Y)包含含有合计为2原子%~20原子%的选自由Zn、Ni、Ti、Al、Mg、Ca、W、Nb以及Mn所组成的群组中至少一种元素的Cu合金,所述第二层(X)包含纯Cu、或者以Cu为主成分且电阻率低于所述第一层(Y)的Cu合金。通过所述构成,实现了透明基板与Cu合金膜中Cu的密接性及低电阻。
在专利文献2中提出有一种耐氧化性优异的触摸屏传感器用Cu合金配线膜,其特征在于,在透明导电膜以及与所述透明导电膜连接的触摸屏传感器用的配线膜中,所述配线膜具有包含Cu合金(第1层)与第2层的层叠结构,且所述第2层与所述透明导电膜连接,所述Cu合金(第1层)包含以合计量计为0.1原子%~40原子%的选自由Ni、Zn以及Mn所组成的群组中的合金元素的至少一种,所述第2层包含纯Cu、或者以Cu为主成分且电阻率低于所述第1层的Cu合金。
在TFT元件形成工艺中,作为层间绝缘膜的SiOx膜利用化学气相沉积法(ChemicalVapor Deposition,CVD)法进行成膜。SiOx膜在高温下进行成膜则可形成杂质少的膜。杂质对TFT元件的驱动带来不良影响,因此Cu配线需要能够耐受利用300℃以上的高温的CVD法的SiOx膜的成膜。然而,Cu为与氧亲和性高的材料。在利用CVD法形成SiOx膜时,导入N2O气体。N2O气体在等离子体中成为氧自由基,在以300℃以上的高温将SiOx膜形成于Cu单膜的情况下,如图3~图4那样氧自由基与Cu容易发生反应,形成氧化铜而剥离。如图3(a)以及图4(a)、(b)所示,在约200℃的温度下利用CVD法形成SiOx膜时未观察到膜剥离,如图3(b)所示,在约300℃的温度下成膜时产生了膜剥离。
现有技术文献
专利文献
专利文献1:日本专利特开2011-48323号公报
专利文献2:日本专利特开2013-120411号公报
发明内容
发明所要解决的问题
如上所述,使用氧化物半导体或LTPS半导体的TFT元件中,利用300℃以上的CVD法形成SiOx膜作为栅极绝缘膜(层间绝缘膜),因此,为了保护Cu配线免受SiOx成膜时的损伤,需要层叠盖层(cap layer)。通常已知盖层使用Cu-30at%Ni合金膜。通过层叠Cu-30at%Ni合金膜,如图5那样即使利用300℃以上的CVD法形成SiOx膜也可抑制膜的剥离,若进行400℃以上的热处理则层叠膜的电阻上升。
另外,期望将搭载有使用氧化物半导体或LTPS半导体的TFT元件的平板显示器用于高精细的面板。高精细面板中,为了提高开口率,而将源极漏极配线或栅极配线的配线宽度加工为10μm以下。关于配线形状,在盖层13如图6(a)那样较配线层12伸出而形成有延伸部13a的情况、及如图6(b)那样成为倒锥状的情况下,会导致层叠于其上层的层间绝缘膜或配线破裂。因此配线形状需要控制为正锥状(参照图6(c))。另外,在可获得正锥状的配线形状的情况下,当配线层12相对于基板11的锥角小时,端部的Cu配线部的露出宽度也变大。因此,也需要控制锥角。
专利文献1中,由于在盖层中添加有Ni等而包含在400℃以上的热处理时导致电阻上升的元素。另外,包含Zn等使锥角变小的元素,因此,存在Cu配线部的露出宽度变大的情况。专利文献2限定于触摸屏用途,必需与ITO薄膜的连接,且包含在500℃的加热时引起电阻上升的元素Ni。
本发明是着眼于所述实情而成者,其课题在于提供一种电阻低、无利用CVD法的层间绝缘膜的SiOx成膜中的剥离、且即使进行400℃以上的高温热处理也无电阻上升的层叠配线膜。另外,本发明课题还在于提供一种具备所述层叠配线膜的薄膜TFT元件。
解决问题的技术手段
本发明人等人反复进行了努力研究,结果发现,具备由特定的合金层所形成的盖层的Cu层叠配线膜可解决所述课题,从而完成了本发明。
即,本发明涉及下述[1]~[7]。
[1]一种层叠配线膜,其特征在于具备:包含电阻为10μΩcm以下的Cu或Cu合金的配线层、以及设于所述配线层的上层及下层中的至少一者的包含Cu与X元素的Cu-X合金层,所述X元素为选自由Al、Mn、Zn以及Ni所组成的X群组中的至少一种,构成所述Cu-X合金层的金属为下述(1)~(5)中的任一组成系,配线图案的宽度为10μm以下。
(1)只包含所述X群组中的一种元素,其含量为6at%以上且27at%以下。
(2)包含4at%以上且15at%以下的Al,进而包含5at%以上且10at%以下的Mn。
(3)包含5at%以上且10at%以下的Zn,进而包含5at%以上且26at%以下的Mn。
(4)包含4at%以上且14at%以下的Zn,进而包含5at%以上且15at%以下的Al。
(5)包含5at%以上且10at%以下的Al,进而包含2at%以上且10at%以下的Ni。
[2]根据所述[1]所记载的层叠配线膜,其中构成所述Cu-X合金层的金属为下述(1')~(5')中的任一组成系,配线图案的宽度为5μm以下。
(1')只包含所述X群组中的一种元素,其含量为6at%以上且14at%以下。
(2')包含4at%以上且9at%以下的Al,进而包含5at%以上且10at%以下的Mn。
(3')包含5at%以上且10at%以下的Zn,进而包含5at%以上且10at%以下的Mn。
(4')包含4at%以上且14at%以下的Zn,进而包含5at%以上且10at%以下的Al。
(5')包含5at%以上且10at%以下的Al,进而包含6at%以上且10at%以下的Ni。
[3]根据所述[1]或[2]所记载的层叠配线膜,其为层叠于基板的层叠配线膜,且在层叠于所述基板之侧的表面进而具有包含Ti的密接层。
[4]根据所述[1]或[2]所记载的层叠配线膜,其中所述配线层的膜厚为50nm以上且1000nm以下,所述Cu-X合金层的膜厚为5nm以上且200nm以下。
[5]根据所述[3]所记载的层叠配线膜,其中所述配线层的膜厚为50nm以上且1000nm以下,所述Cu-X合金层的膜厚为5nm以上且200nm以下。
[6]一种薄膜晶体管元件,其特征在于包含根据所述[1]所记载的层叠配线膜及氧化物半导体。
[7]一种薄膜晶体管元件,其特征在于包含根据所述[2]所记载的层叠配线膜及低温多晶硅半导体或氧化物半导体。
发明的效果
根据本发明,可提供一种电阻低、利用CVD法的层间绝缘膜的SiOx成膜中无剥离、且即使进行400℃以上的高温热处理也无电阻上升的Cu配线用的层叠配线膜及TFT元件。尤其,具备所述[1]的构成的层叠配线膜可适宜地用于使用氧化物半导体的TFT元件,具备所述[2]的构成的层叠配线膜可适宜地用于使用低温多晶硅半导体或氧化物半导体的TFT元件。
附图说明
[图1]图1是例示本发明的层叠配线膜的构成的概略剖面图。
[图2]图2是例示本发明的具备层叠配线膜的薄膜晶体管元件的构成的概略剖面图。
[图3]图3是在Cu单膜上利用CVD法形成SiOx膜时的外观照片图,(a)是在约200℃下成膜时的外观照片图,(b)是在约300℃下成膜时的外观照片图。
[图4]图4是在Cu单膜上利用CVD法,在约200℃的成膜温度下形成SiOx膜时的倍率为20万倍的剖面透射电子显微镜(Transmission Electron Microscope,TEM)观察照片,(a)是层叠膜的整体图,(b)是表面的放大图。
[图5]图5是在Cu-30at%Ni/Cu层叠膜上,利用成膜温度为200℃的CVD法形成SiOx膜时的外观照片图。
[图6]图6是利用湿式蚀刻法所获得的配线形状的概略图,(a)为盖层较配线层伸出而形成有延伸部的配线形状,(b)为倒锥状的配线形状,(c)为正锥状的配线形状。
[图7]图7是例示本发明的层叠配线膜的其他构成的概略剖面图。
具体实施方式
以下,关于本发明的层叠配线膜进行说明。
(层叠配线膜)
本发明的层叠配线膜具备:包含电阻为10μΩcm以下的Cu或Cu合金的配线层、以及设于所述配线层的上层及下层中的至少一者的包含Cu与X元素的Cu-X合金层,所述X元素为选自由Al、Mn、Zn以及Ni所组成的X群组中的至少一种。
图1是例示本发明的层叠配线膜的构成的概略剖面图。如图1所示,本实施方式中,在玻璃基板1上依序层叠有包含配线层2以及盖层(Cu-X合金层)3的层叠配线膜,进而在层叠配线膜上形成有绝缘膜(SiOx)4。作为绝缘膜(SiOx)4,可例示TFT中设于栅极电极(Cu配线)与氧化物半导体层之间的栅极绝缘膜等。
(配线层)
配线层为包含Cu或Cu合金的膜。以下,有时将这些膜称为“Cu系膜”。在将配线层形成为导电层时,所述配线层为Cu系膜,其电阻为10μΩcm以下。通过配线层的电阻为10μΩcm以下,可实现层叠配线膜的低电阻。为了进一步降低层叠配线膜的电阻、改善导电性,配线层的电阻优选为5μΩcm以下,更优选为4μΩcm以下。另外,Cu的电阻较Cu合金更低,因此配线层优选为由Cu形成。
作为形成配线层的Cu合金,可列举包含选自由Ti、Mn、Fe、Co、Ni、Ge以及Zn所组成的Z群组中的至少一种Z元素,且剩余部分包含Cu以及不可避免的杂质的合金。通过包含所述Z元素,而有改善各种耐蚀性或与基板的密接性等效果。这些Z元素可单独使用也可并用两种以上。例如可以合计超过0原子%且为2原子%以下的范围而含有Z元素。
考虑到面板所要求的性能而已确定电极电阻的规格,因此自在成膜时获得膜厚或成分均匀的膜的观点而言,配线膜的膜厚优选为50nm以上,更优选为70nm以上,进而优选为100nm以上。另一方面,自确保生产性与蚀刻加工性的观点而言,配线膜的膜厚优选为1000nm以下,更优选为700nm以下,进而优选为500nm以下。
(Cu-X合金层)
Cu-X合金层作为盖层而设于配线层的上层及下层中的至少一者。通过将盖层设于配线层的至少一个面,在400℃以上且500℃以下的高温热处理时也可抑制Cu系膜的电阻的上升,另外,可抑制SiOx成膜中的膜剥离。
Cu-X合金层由包含Cu与X元素的Cu合金形成。X元素为选自由Al、Mn、Zn以及Ni所组成的X群组中至少一种。X元素可单独使用一种也可并用两种以上。形成Cu-X合金层的Cu合金包含选自由Al、Mn、Zn以及Ni所组成的X群组中的至少一种X元素,且剩余部分包含Cu以及不可避免的杂质。
本发明中,构成Cu-X合金层的金属的X元素为下述(1)~(5)中的任一组成系。
(1)只包含所述X群组中的一种元素,其含量为6at%以上且27at%以下。
(2)包含4at%以上且15at%以下的Al,进而包含5at%以上且10at%以下的Mn。
(3)包含5at%以上且10at%以下的Zn,进而包含5at%以上且26at%以下的Mn。
(4)包含4at%以上且14at%以下的Zn,进而包含5at%以上且15at%以下的Al。
(5)包含5at%以上且10at%以下的Al,进而包含2at%以上且10at%以下的Ni。
若形成Cu-X合金层的Cu合金中的X元素的含量为所述(1)~(5),则可将400℃下的热处理后的电阻设为3μΩcm以下。若超出所述范围而含有X元素,则有时400℃热处理后的电极的电阻值超过3μΩcm。认为其原因在于:X元素通过热处理而在配线层中扩散。
具备具有所述组成系的Cu-X合金层的层叠配线膜可适宜地用作使用氧化物半导体的TFT元件用的Cu配线。
以热处理的温度超过400℃且为500℃以下进行热处理时,合成Cu-X合金层的金属优选为其X元素为下述(1')~(5')中的任一组成系。
(1')只包含所述X群组中的一种元素,其含量为6at%以上且14at%以下。
(2')包含4at%以上且9at%以下的Al,进而包含5at%以上且10at%以下的Mn。
(3')包含5at%以上且10at%以下的Zn,进而包含5at%以上且10at%以下的Mn。
(4')包含4at%以上且14at%以下的Zn,进而包含5at%以上且10at%以下的Al。
(5')包含5at%以上且10at%以下的Al,进而包含6at%以上且10at%以下的Ni。
若形成Cu-X合金层的Cu合金中的X元素的含量为所述(1')~(5'),则在500℃下也可将热处理后的电阻设为3μΩcm以下。
具备具有所述组成系的Cu-X合金层的层叠配线膜可适宜地用作使用氧化物半导体或LTPS半导体的TFT元件用的Cu配线。
若在氧化环境中对Cu-Mn膜进行加热、或在氧等离子体存在下对Cu-Mn膜进行处理,则Mn元素扩散至合金表面而形成浓化层。已浓化的Mn被氧化而不导态化。因此,除了在反应初期被氧化的Cu元素以外,均受已不导态化的Mn氧化物保护,而氧不会进一步扩散至Cu-Mn膜内部,从而有抑制氧化的进行的效果。此时,若Mn的含量低于规定范围,则有时无法以抑制氧化的程度来形成浓化层。另外,若Mn的含量超过规定范围,则在使用薄膜晶体管工序中所使用的过氧化氢水或混合酸系的蚀刻液的配线加工时,促进Cu-Mn膜的蚀刻,从而有时无法获得良好的配线形状。
X元素为Al、Zn的情况也与Mn同样地进行钝化,而有保护Cu的表面不被氧化的效果。然而,在使用过氧化氢水或混合酸系的蚀刻液时,这些X元素具有Al阻碍蚀刻而Zn促进蚀刻的效果。在添加这些元素时,若增加Al的添加量而为规定以上,则蚀刻速度较配线层更慢,Cu-X合金层较配线层伸出,延伸部残留,因此欠佳。另外,若增加Zn的添加量而为规定以上,则进一步促进Cu-X合金层的蚀刻速度,因此有时无法获得良好的蚀刻形状。
在X元素为Ni的情况下,若Ni的含量低于规定范围,则不被氧化的保护效果不充分,因此欠佳。另外,Ni为相对于Cu容易固溶的元素,通过加热而扩散至作为配线层而层叠的Cu或Cu合金内。若Ni的含量超过规定范围,则通过加热处理后的扩散而电阻增加,因此欠佳。
具备具有所述组成系的Cu-X合金层的层叠配线膜优选为在层叠于基板的情况下,在层叠于所述基板之侧的表面进而具有包含Ti的密接层。为了提升半导体基板(绝缘体)与配线层(Cu金属)的密接性,有时在半导体基板与配线层之间设置包含Ti的密接层(Ti单体、Ti合金、Ti氧化物、Ti氮化物等),但有因SiOx成膜时的高温热处理的影响,而Ti扩散至Cu中,配线电阻上升的担忧。另一方面,在设有由所述特定的合金层形成的盖层作为层叠配线膜时,可抑制Ti向Cu中的扩散,从而可抑制配线电阻的上升。
关于其理由虽不明确,但认为原因在于:Ti的扩散以氧为驱动源,因此,通过层叠本发明的盖层而阻碍氧进入配线层(Cu配线膜)中。
此外,在图7中示出例示使用包含Ti的密接层时的层叠配线膜的构成的概略剖面图。如图7所示,本实施方式中,在玻璃基板1上依序层叠有包含密接层14、配线层2以及盖层(Cu-X合金层)3的层叠配线膜,进而在层叠配线膜上形成有绝缘膜(SiOx)4。此外,对于本实施方式,也可为进而在密接层14与配线层2之间具有盖层3的形态。另外,也可为在玻璃基板1上依序层叠有密接层14、盖层3以及配线层2的形态。
密接层的膜厚优选为设为10nm以上,更优选为15nm以上,进而优选为20nm以上。另外,密接层的膜厚优选为设为50nm以下,更优选为40nm以下,进而优选为30nm以下。通过将密接层的膜厚设为所述范围,可在与基板之间形成均匀的密接层,从而可确保皮膜的密接性。
若Cu-X合金层的膜厚薄,则耐氧化性不充分,厚度与蚀刻加工性受损,而且,若Cu-X合金层的膜厚厚,则自Cu电极整体的电阻来看时电阻变大。因此,Cu-X合金层的膜厚优选为5nm以上且200nm以下。Cu-X合金层的膜厚更优选为10nm以上,进而优选为20nm以上,更优选为150nm以下,进而优选为100nm以下。
配线层与Cu-X合金层的合计膜厚、即层叠配线膜的膜厚优选为设为55nm以上,更优选为70nm以上,进而优选为100nm以上。另外,所述合计膜厚优选为设为1200nm以下,更优选为700nm以下,进而优选为500nm以下。若层叠配线膜的膜厚为所述范围,则能够廉价地成膜,且可获得良好的配线形状。
本发明的层叠配线膜优选为配线形状为如图6(c)所示那样的正锥形状。若Cu-X合金层为正锥形状而并非为较配线层伸出的形状,则可抑制被覆于Cu-X合金层上的层间绝缘膜或配线的破裂。
配线层的锥角优选为相对于基板为100°以下,更优选为相对于基板为30°~80°,进而优选为30°~60°,进而更优选为40°~60°。若配线层的锥角为所述范围,则可使配线层自层叠配线膜的锥端部露出的宽度变窄。锥角小、配线层的露出宽度大的情况意味着未受盖层保护的配线层的面积增加,而有在其后的处理中被氧化的担忧。通过氧化而锥端部氧化的情况意味着作为电阻低的配线而发挥功能的宽度变窄,而有配线电阻增加的担忧。
另外,配线层的锥角优选为相对于相同膜厚的Cu单层膜的锥角而为-25%~+50%的范围。通过相对于相同膜厚的Cu单层膜的锥角而言的配线层的锥角为所述范围,可进一步抑制被覆于Cu-X合金层上的层间绝缘膜或配线的破裂。
本发明中,配线层与Cu-X合金层优选为利用溅射法进行成膜。溅射法的生产性优异,且若使用溅射靶材,则可稳定地形成大致相同组成的合金膜。作为溅射法,例如可采用直流(Direct Current,DC)溅射法、射频(Radio-Frequency,RF)溅射法、磁控溅射法、反应性溅射法等任一溅射法,其形成条件只要适宜地设定即可。
在利用所述溅射法,形成例如Cu-X合金层时,若使用包含含有规定量的X元素的Cu合金、且与所期望的Cu-X合金层为相同组成的Cu合金溅射靶材作为所述靶材,则可形成所期望的成分/组成的Cu-X合金层而无组成偏差。或者,也可使用组成不同的两个以上的纯金属靶材或合金靶材,使这些同时放电来进行成膜。或者,也可通过将合金元素的金属晶载于纯Cu靶材而在调整成分的同时进行成膜。
在利用溅射法将Cu-X合金层成膜时,作为溅射条件的一例,可列举以下条件。
(溅射条件)
成膜装置:DC磁控溅射装置(爱发科(ULVAC)公司制造的“CS-200”)
基板:无碱玻璃(康宁(Corning)公司制造的“易格(eagle)2000”)
基板温度:室温
成膜气体:氩(Ar)气体
气压:2mTorr
溅射功率:300W
终极真空度:1×10-6Torr以下
本发明的Cu合金溅射靶材可列举其形状根据溅射装置的形状或结构而为任意形状,例如方型板状、圆形板状、环形板状等者。作为所述Cu合金溅射靶材的制造方法,可列举:利用熔融铸造法或粉末烧结法、喷射成形法来制造包含Cu合金的铸锭而获得Cu合金溅射靶材的方法;在制造包含Cu合金的预成形体、即获得最终的致密体之前的中间体后,利用致密化方法将所述预成形体致密化而获得Cu合金溅射靶材的方法。
配线图案可通过对本发明的层叠配线膜进行蚀刻等处理而形成。若使配线图案变细,则可提升像素元件的开口率。因此,可应对高精细的显示装置。使用氧化物半导体或低温多晶硅半导体的TFT元件搭载于高精细面板,谋求使配线宽度变细。自此种观点而言,具体的配线图案的宽度优选为10μm以下,更优选为5μm以下。
所述Cu-X合金层以外的各层的成膜方法可适宜地采用本发明的技术领域中通常所使用的方法。
本发明的层叠配线膜可适用于配线电极或输入装置。输入装置包含如触摸屏等那样显示装置中具备输入单元的输入装置、或如触控板(touch pad)那样不具有显示装置的输入装置。尤其,本发明的层叠配线膜优选为用于触摸屏传感器。
进而,关于本发明的薄膜晶体管元件进行说明。
(薄膜晶体管元件)
本发明的薄膜晶体管元件的特征在于使用层叠配线膜,所述层叠配线膜具备:包含电阻为10μΩcm以下的Cu或Cu合金的配线层、以及设于所述配线层的上层或下层中的至少一者的包含Cu与X元素的Cu-X合金层,所述X元素为选自由Al、Mn、Zn以及Ni所组成的X群组中至少一种。另外,作为FTF的活性层,可使用氧化物半导体或LTPS半导体。
图2是例示本发明的具备层叠配线膜的薄膜晶体管元件的构成的概略剖面图。如图2所示,本实施方式中,在玻璃基板1上依序层叠有:包含配线层2及盖层(Cu-X合金层)3的层叠配线膜;包含绝缘膜(SiOx)4、氧化物半导体5、配线层6及盖层(Cu-X合金层)7的层叠配线膜;绝缘膜(SiOx)8。作为盖层(Cu-X合金层)3以及盖层(Cu-X合金层)7,可适宜地使用所述特定的合金层。
实施例
以下,列举实施例及比较例进而更具体地说明本发明,但本发明并不限定于这些实施例,也可在适合其主旨的范围内加以变更来实施,这些均包含于本发明的技术的范围内。
<实施例1>
(1)层叠配线膜的制作
准备直径为4英寸、板厚为0.7mm的无碱玻璃板作为透明基板,利用中性洗剂清洗后,对准分子紫外线(Ultraviolet,UV)灯照射30分钟而去除表面的污染。在所述经表面处理的无碱玻璃板上,利用DC磁控溅射法而形成具备表1所示的配线层以及为Cu-X合金层的盖层的层叠配线膜。此外,试样No.1的配线膜是仅为配线层的单层膜。
成膜时,暂且将成膜前的腔室内的环境调整为3×10-6Torr,然后,利用下述溅射条件,在所述基板上以配线层、盖层的顺序进行溅射,形成层叠配线膜。作为溅射靶材,使用纯Cu溅射靶材、或者靶材的成分组成与各盖层相同的直径均为4英寸的圆盘型溅射靶材。使用所获的层叠配线膜进行下述评价。
(溅射条件)
成膜装置:DC磁控溅射装置(爱发科公司制造的“CS-200”)
基板:无碱玻璃板(康宁公司制造的“易格(eagle)2000”)
基板温度:室温
成膜气体:氩(Ar)气体
气压:2mTorr
溅射功率:300W
终极真空度:1×10-6Torr以下
(2)层叠配线膜的电阻率的测定
如下所述那样测定层叠配线膜的电阻率。即,利用4端子法,对在无碱玻璃板上,以所记载的膜厚在表1所记载的Cu系膜上形成有盖层的样品测定电阻。根据所测定的电阻、及Cu系膜与盖层的膜厚的合计值算出电阻率。继而,使用爱发科公司制造的红外线灯加热装置:RTP-6,在N2环境下分别在400℃与500℃下进行1小时的热处理后,同样地测定电阻,利用所述相同的方法算出电阻率。
将其结果示于表1中。本实施例中,400℃下电阻率为3μΩcm以下的试样就面向使用氧化物半导体的TFT元件的耐热性而言视为合格,500℃下电阻率为3μΩcm以下的试样面向使用氧化物半导体或LTPS的TFT元件而言视为合格。
(3)配线形状、锥角的评价
使用光抗蚀剂在层叠配线膜上形成包含线与空间的抗蚀剂图案。关于试样No.2~No.39中所记载的层叠配线膜,利用三菱气体化学股份有限公司制造的过氧化氢系蚀刻液进行蚀刻加工,其后,浸渍于丙酮中将抗蚀剂去除,从而连同透明基板一起开裂。其次,关于已进行所述蚀刻加工的试样,使用日立电力解决方案(Hitachi Power Solutions)股份有限公司制造的电子显微镜:S-4000来观察其剖面形状。将如图6(a)所示盖层13较配线层12伸出而形成有延伸部13(a)者评价为“有延伸部”,将如图6(b)所示那样成为倒锥状者评价为“倒锥形状”,将如图6(c)所示那样成为正锥状者评价为“正锥形状”。
继而,关于试样No.1~No.39中所记载的层叠配线膜,自剖面形状来测定相对于透明基板的锥角。另外,利用下述式(1)来计算以相同的方法而制作的试样No.1的配线层的锥角相对于Cu单膜的锥角的比率。此外,将相对于透明基板的锥角为30°~80°者判断为合格,尤其,将以试样No.1的配线层的锥角相对于Cu单膜的锥角的比率为-25%~+50%的范围内的角度加工而成者判断为更优异者。将其结果示于表1中。
相对于Cu单膜的锥角的比率(%)=[(Cu单膜的锥角)-(层叠配线膜的锥角)]/(Cu单膜的锥角)…(1)
(4)耐氧化的评价
在层叠配线膜的盖层上,使用萨姆肯(SAMCO)股份有限公司制造的等离子体CVD装置:PD-220ML来形成SiOx膜。成膜时使用SiH4与N2O气体,形成膜厚250nm的SiOx膜,通过目视来检查外观,并确认SiOx膜有无剥离。将其结果示于表1中。此外,在耐氧化不足的情况下,在SiOx膜的成膜时膜的表面进行氧化,而产生颜色不均或进而因界面的体积膨胀而产生SiOx膜的膜脱落,因此欠佳。
将所述(2)层叠配线膜的电阻率的测定、(3)配线形状、锥角的评价、以及(4)耐氧化的评价的结果示于表1中。
另外,根据所述(2)~(4)项的结果,400℃热处理下电阻率为3μΩcm以下、配线形状为正锥形状、且无利用CVD法进行SiOx成膜时的剥离者就适宜面向使用氧化物半导体的TFT元件而言视为合格『○』,将不满足所述条件的任一条件者视为不合格『×』。
而且,400℃及500℃热处理下电阻率为3μΩcm以下、配线形状为正锥形状、且相对于透明基板的锥角为30°~80°而且在利用CVD法进行SiOx成膜时无剥离者就适宜面向使用氧化物半导体及低温多晶硅半导体的TFT元件而言视为合格『○』,将不满足所述条件的任一条件者设为不合格『×』。
将结果汇总示于表1中。
[表1]
根据表1的结果,可知如下。首先,No.1为不具有盖层的Cu单膜的例子,在SiOx膜的成膜时观察到剥离。继而,No.2~No.13为作为盖层的Cu-X合金层包含Cu与一种元素的层叠配线膜。No.5、No.8~No.10、No.13为满足本发明规定的Cu-X合金层的X元素的组成系(1)的例子,配线形状为正锥状,在400℃的热处理后电阻也为3μΩcm以下的电阻,在SiOx膜的成膜时也未确认到剥离。相对于此,No.3、No.6无法稳定地获得高热处理时的低电阻,且No.3成为在Cu-X合金层形成有延伸部的配线形状。No.2、No.4、No.7、No.11以及No.12在SiOx膜的成膜时观察到剥离。
尤其,No.5与No.8为满足本发明所规定的Cu-X合金层的X元素的组成系(1')的例子,配线形状为正锥状,且锥角也为30°~80°,在400℃与500℃的热处理后的任一者中均为3μΩcm以下的电阻,在SiOx膜的成膜时也未确认到剥离。
另外,No.14~No.39为作为盖层的Cu-X合金层包含Cu与两种以上的元素的层叠配线膜。No.19~No.39为满足本发明所规定的Cu-X合金层的X元素的组成系(2)~组成系(5)的任一者的例子,配线形状为正锥状,在400℃的热处理后电阻也为3μΩcm以下的电阻,在SiOx膜的成膜时也未确认到剥离。相对于此,No.14~No.18无法稳定地获得高热处理时的低电阻。
尤其,No.19、No.27~No.30以及No.32~No.39为满足本发明所规定的Cu-X合金层的X元素的组成系(2')~组成系(5')的任一者的例子,配线形状为正锥状,且锥角也为30°~80°,在400℃与500℃的热处理后的任一者中均为3μΩcm以下的电阻,在SiOx膜的成膜时也未确认到剥离。
此外,若着眼于No.22~No.26的Cu-Zn-Mn合金层,则No.24~No.26的例子中,满足本发明所规定的Cu-X合金层的X元素的组成系(3'),且500℃的热处理后的电阻相较于No.22以及No.23成为低值(2.0μΩcm以下)。根据所述结果可知,使用Cu-Zn-Mn合金层时的Mn的含量优选为10at%以下。
另外,同样地,若着眼于No.35~No.39的Cu-Al-Ni合金层,则No.37及No.38的例子中,满足本发明所规定的Cu-X合金层的X元素的组成系(5'),且500℃的热处理后的电阻相较于No.35、No.36以及No.39成为低值(2.3μΩcm)。根据所述结果可知,使用Cu-Al-Ni合金层时的Ni的含量优选为6at%以上。
<实施例2>
通过下述顺序来制作使用包含Ti的密接层时的层叠配线膜。具体而言,与实施例1的情况同样地,在作为透明基板的无碱玻璃板上,利用DC磁控溅射法依序成膜具备表2所示的密接层、配线层以及作为Cu-X合金层的盖层的层叠配线膜。此外,试样No.40的配线膜为仅有密接层及配线层的层叠膜。密接层、配线层以及盖层的成膜条件与实施例1的情况相同。
关于以如上所述的方式而获得的层叠配线膜,在与实施例1的情况相同的条件下进行电阻率的测定以及耐氧化的评价。另外,根据所述结果,400℃热处理下电阻率为3μΩcm以下、无利用CVD法进行SiOx成膜时的剥离者就适宜面向使用氧化物半导体的TFT元件而言视为合格『○』,将不满足所述条件的任一条件者视为不合格『×』。
而且,400℃及500℃热处理下电阻率为3μΩcm以下、在利用CVD法进行SiOx成膜时无剥离者就适宜面向使用氧化物半导体及低温多晶硅半导体的TFT元件而言视为合格『○』,将不满足所述条件的任一条件者视为不合格『×』。
将层叠配线膜的电阻率的测定、耐氧化的评价、以及对使用氧化物半导体或低温多晶硅半导体的TFT元件的适合性的结果汇总示于表2中。
[表2]
根据表2的结果,可知如下。首先,No.40为仅有密接层及配线层的层叠膜的例子,在SiOx膜的成膜时观察到剥离。另外,不满足在500℃的热处理后电阻为3μΩcm以下。进而,No.41为不满足本发明所规定的Cu-X合金层的X元素的组成系(1)的例子,虽然在SiOx膜的成膜时未观察到剥离,但不满足在400℃及500℃的任一热处理后电阻也为3μΩcm以下。
相对于此,No.42~No.46为满足本发明所规定的Cu-X合金层的X元素的组成系(1)~(5)的任一者的例子,满足在400℃及500℃的任一热处理后电阻也为3μΩcm以下,在SiOx膜的成膜时未观察到剥离。
已参照特定的态样详细地说明了本发明,但对于本领域从业人员可明确的是:可不脱离本发明的精神与范围而进行各种变更及修正。此外,本申请基于2016年5月13日提出申请的日本专利申请(日本专利特愿2016-097321)以及2017年4月11日提出申请的日本专利申请(日本专利特愿2017-078505),通过引用而援用其整体。
符号的说明
1:玻璃基板
2:配线层
3:盖层(Cu-X合金层)
4:绝缘膜(SiOx)
5:氧化物半导体
6:配线层
7:盖层(Cu-X合金层)
8:绝缘膜(SiOx)
11:基板
12:配线层
13:盖层
13a:延伸部
14:密接层

Claims (7)

1.一种层叠配线膜,其特征在于,具备:包含电阻为10μΩcm以下的Cu或Cu合金的配线层、以及设于所述配线层的上层及下层中的至少一者的包含Cu与X元素的Cu-X合金层,
所述X元素为选自由Al、Mn、Zn以及Ni所组成的X群组中的至少一种,
构成所述Cu-X合金层的金属为下述(1)~(5)中的任一组成系,
配线图案的宽度为10μm以下:
(1)只包含所述X群组中的一种元素,其含量为6at%以上且27at%以下。
(2)包含4at%以上且15at%以下的Al,进而包含5at%以上且10at%以下的Mn。
(3)包含5at%以上且10at%以下的Zn,进而包含5at%以上且26at%以下的Mn。
(4)包含4at%以上且14at%以下的Zn,进而包含5at%以上且15at%以下的Al。
(5)包含5at%以上且10at%以下的Al,进而包含2at%以上且10at%以下的Ni。
2.根据权利要求1所述的层叠配线膜,其中构成所述Cu-X合金层的金属为下述(1')~(5')中的任一组成系,
配线图案的宽度为5μm以下:
(1')只包含所述X群组中的一种元素,其含量为6at%以上且14at%以下。
(2')包含4at%以上且9at%以下的Al,进而包含5at%以上且10at%以下的Mn。
(3')包含5at%以上且10at%以下的Zn,进而包含5at%以上且10at%以下的Mn。
(4')包含4at%以上且14at%以下的Zn,进而包含5at%以上且10at%以下的Al。
(5')包含5at%以上且10at%以下的Al,进而包含6at%以上且10at%以下的Ni。
3.根据权利要求1或2所述的层叠配线膜,其为层叠于基板的层叠配线膜,且在层叠于所述基板之侧的表面进而具有包含Ti的密接层。
4.根据权利要求1或2所述的层叠配线膜,其中所述配线层的膜厚为50nm以上且1000nm以下,所述Cu-X合金层的膜厚为5nm以上且200nm以下。
5.根据权利要求3所述的层叠配线膜,其中所述配线层的膜厚为50nm以上且1000nm以下,所述Cu-X合金层的膜厚为5nm以上且200nm以下。
6.一种薄膜晶体管元件,其特征在于,包含如权利要求1所述的层叠配线膜及氧化物半导体。
7.一种薄膜晶体管元件,其特征在于,包含如权利要求2所述的层叠配线膜及低温多晶硅半导体或氧化物半导体。
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