TWI652359B - 積層配線膜及薄膜電晶體元件 - Google Patents

積層配線膜及薄膜電晶體元件 Download PDF

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Publication number
TWI652359B
TWI652359B TW106115727A TW106115727A TWI652359B TW I652359 B TWI652359 B TW I652359B TW 106115727 A TW106115727 A TW 106115727A TW 106115727 A TW106115727 A TW 106115727A TW I652359 B TWI652359 B TW I652359B
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Taiwan
Prior art keywords
film
layer
wiring
less
alloy
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TW106115727A
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English (en)
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TW201812034A (zh
Inventor
Yoko Shida
志田陽子
Hiroshi Goto
後藤裕史
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Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.)
神戶製鋼所股份有限公司
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Publication of TW201812034A publication Critical patent/TW201812034A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C17/00—Surface treatment of glass, not in the form of fibres or filaments, by coating
    • C03C17/06—Surface treatment of glass, not in the form of fibres or filaments, by coating with metals
    • C03C17/09—Surface treatment of glass, not in the form of fibres or filaments, by coating with metals by deposition from the vapour phase
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C17/00—Surface treatment of glass, not in the form of fibres or filaments, by coating
    • C03C17/34—Surface treatment of glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions
    • C03C17/36—Surface treatment of glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions at least one coating being a metal
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C17/00—Surface treatment of glass, not in the form of fibres or filaments, by coating
    • C03C17/34—Surface treatment of glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions
    • C03C17/36—Surface treatment of glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions at least one coating being a metal
    • C03C17/3602—Surface treatment of glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions at least one coating being a metal the metal being present as a layer
    • C03C17/3649—Surface treatment of glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions at least one coating being a metal the metal being present as a layer made of metals other than silver
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C17/00—Surface treatment of glass, not in the form of fibres or filaments, by coating
    • C03C17/34—Surface treatment of glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions
    • C03C17/36—Surface treatment of glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions at least one coating being a metal
    • C03C17/3602—Surface treatment of glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions at least one coating being a metal the metal being present as a layer
    • C03C17/3655—Surface treatment of glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions at least one coating being a metal the metal being present as a layer the multilayer coating containing at least one conducting layer
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C17/00—Surface treatment of glass, not in the form of fibres or filaments, by coating
    • C03C17/34—Surface treatment of glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions
    • C03C17/36—Surface treatment of glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions at least one coating being a metal
    • C03C17/3602—Surface treatment of glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions at least one coating being a metal the metal being present as a layer
    • C03C17/3668—Surface treatment of glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions at least one coating being a metal the metal being present as a layer the multilayer coating having electrical properties
    • C03C17/3671—Surface treatment of glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions at least one coating being a metal the metal being present as a layer the multilayer coating having electrical properties specially adapted for use as electrodes
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C17/00—Surface treatment of glass, not in the form of fibres or filaments, by coating
    • C03C17/34—Surface treatment of glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions
    • C03C17/36—Surface treatment of glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions at least one coating being a metal
    • C03C17/40—Surface treatment of glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions at least one coating being a metal all coatings being metal coatings
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C23/00—Other surface treatment of glass not in the form of fibres or filaments
    • C03C23/0075—Cleaning of glass
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C9/00—Alloys based on copper
    • C22C9/01—Alloys based on copper with aluminium as the next major constituent
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C9/00—Alloys based on copper
    • C22C9/04—Alloys based on copper with zinc as the next major constituent
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C9/00—Alloys based on copper
    • C22C9/05—Alloys based on copper with manganese as the next major constituent
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C9/00—Alloys based on copper
    • C22C9/06—Alloys based on copper with nickel or cobalt as the next major constituent
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14—Metallic material, boron or silicon
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14—Metallic material, boron or silicon
    • C23C14/16—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon
    • C23C14/165—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon by cathodic sputtering
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    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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    • C23C14/34—Sputtering
    • C23C14/35—Sputtering by application of a magnetic field, e.g. magnetron sputtering
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02—Pretreatment of the material to be coated
    • C23C16/0272—Deposition of sub-layers, e.g. to promote the adhesion of the main coating
    • C23C16/0281—Deposition of sub-layers, e.g. to promote the adhesion of the main coating of metallic sub-layers
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34—Nitrides
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
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    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
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    • H01—ELECTRIC ELEMENTS
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
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    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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Abstract

本發明是有關於一種積層配線膜，其具備包含電阻為10 μΩcm以下的Cu或Cu合金的配線層、以及設於該配線層的上層及下層中的至少一者的包含Cu與X元素的Cu-X合金層，X元素為選自由Al、Mn、Zn以及Ni所組成的X群組中的至少一種，構成Cu-X合金層的金屬為特定的組成系。根據本發明的積層配線膜，可提供一種電阻低、無利用CVD法的層間絕緣膜的SiOx成膜中的剝離、且即使進行400℃以上的高溫熱處理亦無電阻上升的積層配線膜。

Description

積層配線膜及薄膜電晶體元件
本發明是有關於一種積層配線膜及薄膜電晶體元件。
作為用於液晶面板或有機電致發光（Electro Luminescence，EL）面板等平板顯示器或觸控面板等顯示裝置的薄膜電晶體（以下，亦稱為TFT：Thin Film Transistor）的半導體材料，已知有氧化物半導體或低溫多晶矽半導體（以下，亦稱為LTPS：Low Temperature Poly-Silicon）。
氧化物半導體或LTPS半導體與先前所利用的非晶矽半導體材料相比，電子遷移率大而可使TFT元件高速化。
另一方面，正進行藉由將配線材料低電阻化而加速TFT元件的驅動速度的研究。先前的平板顯示器的電極配線中一直使用Al（鋁）薄膜或氧化銦錫（Indium Tin Oxide，ITO）薄膜，但提出有電阻更低的Cu（銅）電極配線或Cu合金電極配線的應用。
然而，於使用Cu配線的情況下產生如下課題。例如，相較於先前的使用非晶矽的元件，使用氧化物半導體或LTPS半導體的TFT元件必須歷經高溫熱處理製程，必須耐受400℃～500℃左右的加熱。另外，Cu配線與玻璃基板、Si（矽）膜等半導體膜、金屬氧化物膜等的密接性差。
作為所述使用Cu的技術，於專利文獻1中提出有一種具備與玻璃基板等透明基板的密接性優異的Cu合金膜的顯示裝置。於專利文獻1的顯示裝置中，Cu合金膜的特徵在於：具有包含第一層（Y）與第二層（X）的積層結構，且第一層（Y）與透明基板接觸，所述第一層（Y）包含含有合計為2原子%～20原子%的選自由Zn、Ni、Ti、Al、Mg、Ca、W、Nb以及Mn所組成的群組中至少一種元素的Cu合金，所述第二層（X）包含純Cu、或者以Cu為主成分且電阻率低於所述第一層（Y）的Cu合金。藉由所述構成，實現了透明基板與Cu合金膜中Cu的密接性及低電阻。
於專利文獻2中提出有一種耐氧化性優異的觸控面板感測器用Cu合金配線膜，其特徵在於，於透明導電膜以及與所述透明導電膜連接的觸控面板感測器用的配線膜中，所述配線膜具有包含Cu合金（第1層）與第2層的積層結構，且所述第2層與所述透明導電膜連接，所述Cu合金（第1層）包含以合計量計為0.1原子%～40原子%的選自由Ni、Zn以及Mn所組成的群組中的合金元素的至少一種，所述第2層包含純Cu、或者以Cu為主成分且電阻率低於所述第1層的Cu合金。
於TFT元件形成製程中，作為層間絕緣膜的SiOx膜利用化學氣相沈積法（Chemical Vapor Deposition，CVD）法進行成膜。SiOx膜於高溫下進行成膜則可形成雜質少的膜。雜質對TFT元件的驅動帶來不良影響，因此Cu配線需要能夠耐受利用300℃以上的高溫的CVD法的SiOx膜的成膜。然而，Cu為與氧親和性高的材料。於利用CVD法形成SiOx膜時，導入N2 O氣體。N2 O氣體於電漿中成為氧自由基，於以300℃以上的高溫將SiOx膜形成於Cu單膜的情況下，如圖3中的（a）、圖3中的（b）～圖4中的（a）、圖4中的（b）般氧自由基與Cu容易發生反應，形成氧化銅而剝離。如圖3中的（a）以及圖4中的（a）、圖4中的（b）所示，於約200℃的溫度下利用CVD法形成SiOx膜時未觀察到膜剝離，如圖3中的（b）所示，於約300℃的溫度下成膜時產生了膜剝離。 [現有技術文獻] [專利文獻]
專利文獻1：日本專利特開2011-48323號公報 專利文獻2：日本專利特開2013-120411號公報
[發明所欲解決之課題] 如上所述，使用氧化物半導體或LTPS半導體的TFT元件中，利用300℃以上的CVD法形成SiOx膜作為閘極絕緣膜（層間絕緣膜），因此，為了保護Cu配線免受SiOx成膜時的損傷，需要積層蓋層（cap layer）。通常已知蓋層使用Cu-30 at%Ni合金膜。藉由積層Cu-30 at%Ni合金膜，如圖5般即使利用300℃以上的CVD法形成SiOx膜亦可抑制膜的剝離，若進行400℃以上的熱處理則積層膜的電阻上升。
另外，期望將搭載有使用氧化物半導體或LTPS半導體的TFT元件的平板顯示器用於高精細的面板。高精細面板中，為了提高開口率，而將源極汲極配線或閘極配線的配線寬度加工為10 μm以下。關於配線形狀，於蓋層13如圖6中的（a）般較配線層12伸出而形成有延伸部13a的情況、及如圖6中的（b）般成為倒錐狀的情況下，會導致積層於其上層的層間絕緣膜或配線破裂。因此配線形狀需要控制為正錐狀（參照圖6中的（c））。另外，於可獲得正錐狀的配線形狀的情況下，當配線層12相對於基板11的錐角小時，端部的Cu配線部的露出寬度亦變大。因此，亦需要控制錐角。
專利文獻1中，由於於蓋層中添加有Ni等而包含於400℃以上的熱處理時導致電阻上升的元素。另外，包含Zn等使錐角變小的元素，因此，存在Cu配線部的露出寬度變大的情況。專利文獻2限定於觸控面板用途，必需與ITO薄膜的連接，且包含於500℃的加熱時引起電阻上升的元素Ni。
本發明是著眼於所述實情而成者，其課題在於提供一種電阻低、無利用CVD法的層間絕緣膜的SiOx成膜中的剝離、且即使進行400℃以上的高溫熱處理亦無電阻上升的積層配線膜。另外，本發明課題還在於提供一種具備該積層配線膜的薄膜TFT元件。 [解決課題之手段]
本發明者等人反覆進行了努力研究，結果發現，具備由特定的合金層所形成的蓋層的Cu積層配線膜可解決所述課題，從而完成了本發明。
即，本發明是有關於下述[1]～[7]。 [1] 一種積層配線膜，其特徵在於具備：包含電阻為10 μΩcm以下的Cu或Cu合金的配線層、以及設於該配線層的上層及下層中的至少一者的包含Cu與X元素的Cu-X合金層，所述X元素為選自由Al、Mn、Zn以及Ni所組成的X群組中的至少一種，構成所述Cu-X合金層的金屬為下述（1）～（5）中的任一組成系，配線圖案的寬度為10 μm以下。 （1）只包含所述X群組中的一種元素，其含量為6 at%以上且27 at%以下。 （2）包含4 at%以上且15 at%以下的Al，進而包含5 at%以上且10 at%以下的Mn。 （3）包含5 at%以上且10 at%以下的Zn，進而包含5 at%以上且26 at%以下的Mn。 （4）包含4 at%以上且14 at%以下的Zn，進而包含5 at%以上且15 at%以下的Al。 （5）包含5 at%以上且10 at%以下的Al，進而包含2 at%以上且10 at%以下的Ni。 [2] 如所述[1]所記載的積層配線膜，其中構成所述Cu-X合金層的金屬為下述（1'）～（5'）中的任一組成系，配線圖案的寬度為5 μm以下。 （1'）只包含所述X群組中的一種元素，其含量為6 at%以上且14 at%以下。 （2'）包含4 at%以上且9 at%以下的Al，進而包含5 at%以上且10 at%以下的Mn。 （3'）包含5 at%以上且10 at%以下的Zn，進而包含5 at%以上且10 at%以下的Mn。 （4'）包含4 at%以上且14 at%以下的Zn，進而包含5 at%以上且10 at%以下的Al。 （5'）包含5 at%以上且10 at%以下的Al，進而包含6 at%以上且10 at%以下的Ni。 [3] 如所述[1]或[2]所記載的積層配線膜，其為積層於基板的積層配線膜，且於積層於所述基板之側的表面進而具有包含Ti的密接層。 [4] 如所述[1]或[2]所記載的積層配線膜，其中所述配線層的膜厚為50 nm以上且1000 nm以下，所述Cu-X合金層的膜厚為5 nm以上且200 nm以下。 [5] 如所述[3]所記載的積層配線膜，其中所述配線層的膜厚為50 nm以上且1000 nm以下，所述Cu-X合金層的膜厚為5 nm以上且200 nm以下。 [6] 一種薄膜電晶體元件，其特徵在於包含如所述[1]所記載的積層配線膜及氧化物半導體。 [7] 一種薄膜電晶體元件，其特徵在於包含如所述[2]所記載的積層配線膜及低溫多晶矽半導體或氧化物半導體。 [發明的效果]
根據本發明，可提供一種電阻低、利用CVD法的層間絕緣膜的SiOx成膜中無剝離、且即使進行400℃以上的高溫熱處理亦無電阻上升的Cu配線用的積層配線膜及TFT元件。尤其，具備所述[1]的構成的積層配線膜可適宜地用於使用氧化物半導體的TFT元件，具備所述[2]的構成的積層配線膜可適宜地用於使用低溫多晶矽半導體或氧化物半導體的TFT元件。
以下，關於本發明的積層配線膜進行說明。
（積層配線膜） 本發明的積層配線膜具備：包含電阻為10 μΩcm以下的Cu或Cu合金的配線層、以及設於該配線層的上層及下層中的至少一者的包含Cu與X元素的Cu-X合金層，所述X元素為選自由Al、Mn、Zn以及Ni所組成的X群組中的至少一種。
圖1是例示本發明的積層配線膜的構成的概略剖面圖。如圖1所示，本實施形態中，於玻璃基板1上依序積層有包含配線層2以及蓋層（Cu-X合金層）3的積層配線膜，進而於積層配線膜上形成有絕緣膜（SiOx）4。作為絕緣膜（SiOx）4，可例示TFT中設於閘極電極（Cu配線）與氧化物半導體層之間的閘極絕緣膜等。
（配線層） 配線層為包含Cu或Cu合金的膜。以下，有時將該些膜稱為「Cu系膜」。於將配線層形成為導電層時，該配線層為Cu系膜，其電阻為10 μΩcm以下。藉由配線層的電阻為10 μΩcm以下，可實現積層配線膜的低電阻。為了進一步降低積層配線膜的電阻、改善導電性，配線層的電阻較佳為5 μΩcm以下，更佳為4 μΩcm以下。另外，Cu的電阻較Cu合金更低，因此配線層較佳為由Cu形成。
作為形成配線層的Cu合金，可列舉包含選自由Ti、Mn、Fe、Co、Ni、Ge以及Zn所組成的Z群組中的至少一種Z元素，且剩餘部分包含Cu以及不可避免的雜質的合金。藉由包含所述Z元素，而有改善各種耐蝕性或與基板的密接性等效果。該些Z元素可單獨使用亦可倂用兩種以上。例如可以合計超過0原子%且為2原子%以下的範圍而含有Z元素。
考慮到面板所要求的性能而已確定電阻的規格，因此自於成膜時獲得膜厚或成分均勻的膜的觀點而言，配線膜的膜厚較佳為50 nm以上，更佳為70 nm以上，進而佳為100 nm以上。另一方面，自確保生產性與蝕刻加工性的觀點而言，配線膜的膜厚較佳為1000 nm以下，更佳為700 nm以下，進而佳為500 nm以下。
（Cu-X合金層） Cu-X合金層作為蓋層而設於配線層的上層及下層中的至少一者。藉由將蓋層設於配線層的至少一個面，於400℃以上且500℃以下的高溫熱處理時亦可抑制Cu系膜的電阻的上升，另外，可抑制SiOx成膜中的膜剝離。
Cu-X合金層由包含Cu與X元素的Cu合金形成。X元素為選自由Al、Mn、Zn以及Ni所組成的X群組中至少一種。X元素可單獨使用一種亦可倂用兩種以上。形成Cu-X合金層的Cu合金包含選自由Al、Mn、Zn以及Ni所組成的X群組中的至少一種X元素，且剩餘部分包含Cu以及不可避免的雜質。
本發明中，構成Cu-X合金層的金屬的X元素為下述（1）～（5）中的任一組成系。 （1）只包含所述X群組中的一種元素，其含量為6 at%以上且27 at%以下。 （2）包含4 at%以上且15 at%以下的Al，進而包含5 at%以上且10 at%以下的Mn。 （3）包含5 at%以上且10 at%以下的Zn，進而包含5 at%以上且26 at%以下的Mn。 （4）包含4 at%以上且14 at%以下的Zn，進而包含5 at%以上且15 at%以下的Al。 （5）包含5 at%以上且10 at%以下的Al，進而包含2 at%以上且10 at%以下的Ni。
若形成Cu-X合金層的Cu合金中的X元素的含量為所述（1）～（5），則可將400℃下的熱處理後的電阻設為3 μΩcm以下。若超出所述範圍而含有X元素，則有時400℃熱處理後的電極的電阻值超過3 μΩcm。認為其原因在於：X元素藉由熱處理而於配線層中擴散。
具備具有所述組成系的Cu-X合金層的積層配線膜可適宜地用作使用氧化物半導體的TFT元件用的Cu配線。
以熱處理的溫度超過400℃且為500℃以下進行熱處理時，合成Cu-X合金層的金屬較佳為其X元素為下述(1')~(5')中的任一組成系。
(1')只包含所述X群組中的一種元素，其含量為6at%以上且14at%以下。
(2')包含4at%以上且9at%以下的Al，進而包含5at%以上且10at%以下的Mn。
(3')包含5at%以上且10at%以下的Zn，進而包含5at%以上且10at%以下的Mn。
(4')包含4at%以上且14at%以下的Zn，進而包含5at%以上且10at%以下的Al。
(5')包含5at%以上且10at%以下的Al，進而包含6at%以上且10at%以下的Ni。
若形成Cu-X合金層的Cu合金中的X元素的含量為所述(1')~(5')，則於500℃下亦可將熱處理後的電阻設為3μΩcm以下。
具備具有所述組成系的Cu-X合金層的積層配線膜可適宜地用作使用氧化物半導體或LTPS半導體的TFT元件用的Cu配線。
若於氧化環境中對Cu-Mn膜進行加熱、或於氧電漿存在下對Cu-Mn膜進行處理，則Mn元素擴散至合金表面而形成濃化層。已濃化的Mn被氧化而鈍化。因此，除了於反應初期被氧 化的Cu元素以外，均受已鈍化的Mn氧化物保護，而氧不會進一步擴散至Cu-Mn膜內部，從而有抑制氧化的進行的效果。此時，若Mn的含量低於規定範圍，則有時無法以抑制氧化的程度來形成濃化層。另外，若Mn的含量超過規定範圍，則於使用薄膜電晶體步驟中所使用的過氧化氫水或混合酸系的蝕刻液的配線加工時，促進Cu-Mn膜的蝕刻，從而有時無法獲得良好的配線形狀。
X元素為Al、Zn的情況亦與Mn同樣地進行鈍化，而有保護Cu的表面不被氧化的效果。然而，於使用過氧化氫水或混合酸系的蝕刻液時，該些X元素具有Al阻礙蝕刻而Zn促進蝕刻的效果。於添加該些元素時，若增加Al的添加量而為規定以上，則蝕刻速度較配線層更慢，Cu-X合金層較配線層伸出，延伸部殘留，因此欠佳。另外，若增加Zn的添加量而為規定以上，則進一步促進Cu-X合金層的蝕刻速度，因此有時無法獲得良好的蝕刻形狀。
於X元素為Ni的情況下，若Ni的含量低於規定範圍，則不被氧化的保護效果不充分，因此欠佳。另外，Ni為相對於Cu容易固溶的元素，藉由加熱而擴散至作為配線層而積層的Cu或Cu合金內。若Ni的含量超過規定範圍，則藉由加熱處理後的擴散而電阻增加，因此欠佳。
具備具有所述組成系的Cu-X合金層的積層配線膜較佳為於積層於基板的情況下，於積層於所述基板之側的表面進而具有包含Ti的密接層。為了提升半導體基板(絕緣體)與配線層(Cu金屬）的密接性，有時於半導體基板與配線層之間設置包含Ti的密接層（Ti單體、Ti合金、Ti氧化物、Ti氮化物等），但有因SiOx成膜時的高溫熱處理的影響，而Ti擴散至Cu中，配線電阻上升的擔憂。另一方面，於設有由所述特定的合金層形成的蓋層作為積層配線膜時，可抑制Ti向Cu中的擴散，從而可抑制配線電阻的上升。
關於其理由雖不明確，但認為原因在於：Ti的擴散以氧為驅動源，因此，藉由積層本發明的蓋層而阻礙氧進入配線層（Cu配線膜）中。
此外，於圖7中示出例示使用包含Ti的密接層時的積層配線膜的構成的概略剖面圖。如圖7所示，本實施形態中，於玻璃基板1上依序積層有包含密接層14、配線層2以及蓋層（Cu-X合金層）3的積層配線膜，進而於積層配線膜上形成有絕緣膜（SiOx）4。此外，對於本實施形態，亦可為進而於密接層14與配線層2之間具有蓋層3的形態。另外，亦可為於玻璃基板1上依序積層有密接層14、蓋層3以及配線層2的形態。
密接層的膜厚較佳為設為10 nm以上，更佳為15 nm以上，進而佳為20 nm以上。另外，密接層的膜厚較佳為設為50 nm以下，更佳為40 nm以下，進而佳為30 nm以下。藉由將密接層的膜厚設為所述範圍，可於與基板之間形成均勻的密接層，從而可確保皮膜的密接性。
若Cu-X合金層的膜厚薄，則耐氧化性不充分，厚度與蝕刻加工性受損，而且，若Cu-X合金層的膜厚厚，則自Cu電極整體的電阻來看時電阻變大。因此，Cu-X合金層的膜厚較佳為5 nm以上且200 nm以下。Cu-X合金層的膜厚更佳為10 nm以上，進而佳為20 nm以上，更佳為150 nm以下，進而佳為100 nm以下。
配線層與Cu-X合金層的合計膜厚、即積層配線膜的膜厚較佳為設為55 nm以上，更佳為70 nm以上，進而佳為100 nm以上。另外，所述合計膜厚較佳為設為1200 nm以下，更佳為700 nm以下，進而佳為500 nm以下。若積層配線膜的膜厚為所述範圍，則能夠廉價地成膜，且可獲得良好的配線形狀。
本發明的積層配線膜較佳為配線形狀為如圖6中的（c）所示般的正錐形狀。若Cu-X合金層為正錐形狀而並非為較配線層伸出的形狀，則可抑制被覆於Cu-X合金層上的層間絕緣膜或配線的破裂。
配線層的錐角較佳為相對於基板為100°以下，更佳為相對於基板為30°～80°，進而佳為30°～60°，進而更佳為40°～60°。若配線層的錐角為所述範圍，則可使配線層自積層配線膜的錐端部露出的寬度變窄。錐角小、配線層的露出寬度大的情況意味著未受蓋層保護的配線層的面積增加，而有於其後的處理中被氧化的擔憂。藉由氧化而錐端部氧化的情況意味著作為電阻低的配線而發揮功能的寬度變窄，而有配線電阻增加的擔憂。
另外，配線層的錐角較佳為相對於相同膜厚的Cu單層膜的錐角而為-25%～+50%的範圍。藉由相對於相同膜厚的Cu單層膜的錐角而言的配線層的錐角為所述範圍，可進一步抑制被覆於Cu-X合金層上的層間絕緣膜或配線的破裂。
本發明中，配線層與Cu-X合金層較佳為利用濺鍍法進行成膜。濺鍍法的生產性優異，且若使用濺鍍靶材，則可穩定地形成大致相同組成的合金膜。作為濺鍍法，例如可採用直流（Direct Current，DC）濺鍍法、射頻（Radio-Frequency，RF）濺鍍法、磁控濺鍍法、反應性濺鍍法等任一濺鍍法，其形成條件只要適宜地設定即可。
於利用所述濺鍍法，形成例如Cu-X合金層時，若使用包含含有規定量的X元素的Cu合金、且與所期望的Cu-X合金層為相同組成的Cu合金濺鍍靶材作為所述靶材，則可形成所期望的成分/組成的Cu-X合金層而無組成偏差。或者，亦可使用組成不同的兩個以上的純金屬靶材或合金靶材，使該些同時放電來進行成膜。或者，亦可藉由將合金元素的金屬晶載於純Cu靶材而在調整成分的同時進行成膜。
於利用濺鍍法將Cu-X合金層成膜時，作為濺鍍條件的一例，可列舉以下條件。 （濺鍍條件） 成膜裝置：DC磁控濺鍍裝置（愛發科（ULVAC）公司製造的「CS-200」） 基板：無鹼玻璃（康寧（Corning）公司製造的「易格（eagle）2000」） 基板溫度：室溫 成膜氣體：氬（Ar）氣體 氣壓：2 mTorr 濺鍍功率：300 W 終極真空度：1×10-6 Torr以下
本發明的Cu合金濺鍍靶材可列舉其形狀根據濺鍍裝置的形狀或結構而為任意形狀，例如方型板狀、圓形板狀、環形板狀等者。作為所述Cu合金濺鍍靶材的製造方法，可列舉：利用熔融鑄造法或粉末燒結法、噴射成形法來製造包含Cu合金的鑄錠而獲得Cu合金濺鍍靶材的方法；於製造包含Cu合金的預成形體、即獲得最終的緻密體之前的中間體後，利用緻密化方法將該預成形體緻密化而獲得Cu合金濺鍍靶材的方法。
配線圖案可藉由對本發明的積層配線膜進行蝕刻等處理而形成。若使配線圖案變細，則可提升畫素元件的開口率。因此，可應對高精細的顯示裝置。使用氧化物半導體或低溫多晶矽半導體的TFT元件搭載於高精細面板，謀求使配線寬度變細。自此種觀點而言，具體的配線圖案的寬度較佳為10 μm以下，更佳為5 μm以下。
所述Cu-X合金層以外的各層的成膜方法可適宜地採用本發明的技術領域中通常所使用的方法。
本發明的積層配線膜可適用於配線電極或輸入裝置。輸入裝置包含如觸控面板等般顯示裝置中具備輸入單元的輸入裝置、或如觸控板（touch pad）般不具有顯示裝置的輸入裝置。尤其，本發明的積層配線膜較佳為用於觸控面板感測器。
進而，關於本發明的薄膜電晶體元件進行說明。
（薄膜電晶體元件） 本發明的薄膜電晶體元件的特徵在於使用積層配線膜，所述積層配線膜具備：包含電阻為10 μΩcm以下的Cu或Cu合金的配線層、以及設於該配線層的上層或下層中的至少一者的包含Cu與X元素的Cu-X合金層，所述X元素為選自由Al、Mn、Zn以及Ni所組成的X群組中至少一種。另外，作為FTF的活性層，可使用氧化物半導體或LTPS半導體。
圖2是例示本發明的具備積層配線膜的薄膜電晶體元件的構成的概略剖面圖。如圖2所示，本實施形態中，於玻璃基板1上依序積層有：包含配線層2及蓋層（Cu-X合金層）3的積層配線膜；包含絕緣膜（SiOx）4、氧化物半導體5、配線層6及蓋層（Cu-X合金層）7的積層配線膜；絕緣膜（SiOx）8。作為蓋層（Cu-X合金層）3以及蓋層（Cu-X合金層）7，可適宜地使用所述特定的合金層。 [實施例]
以下，列舉實施例及比較例進而更具體地說明本發明，但本發明並不限定於該些實施例，亦可於適合其主旨的範圍內加以變更來實施，該些均包含於本發明的技術的範圍內。
<實施例1>
(1)積層配線膜的製作
準備直徑為4吋、板厚為0.7mm的無鹼玻璃板作為透明基板，利用中性洗劑清洗後，利用準分子紫外線(Ultraviolet，UV)燈照射30分鐘而去除表面的污染。於該經表面處理的無鹼玻璃板上，藉由DC磁控濺鍍法而形成具備表1所示的配線層以及為Cu-X合金層的蓋層的積層配線膜。此外，試樣No.1的配線膜是僅為配線層的單層膜。
成膜時，暫且將成膜前的腔室內的環境調整為3×10-6Torr，然後，利用下述濺鍍條件，於所述基板上以配線層、蓋層的順序進行濺鍍，形成積層配線膜。作為濺鍍靶材，使用純Cu濺鍍靶材、或者靶材的成分組成與各蓋層相同的直徑均為4吋的圓盤型濺鍍靶材。使用所獲的積層配線膜進行下述評價。
(濺鍍條件)
成膜裝置：DC磁控濺鍍裝置(愛發科公司製造的「CS-200」)
基板：無鹼玻璃板(康寧公司製造的「易格(eagle)2000」)
基板溫度：室溫
成膜氣體：氬(Ar)氣體
氣壓：2mTorr
濺鍍功率：300W
終極真空度：1×10-6Torr以下
(2)積層配線膜的電阻率的測定
如下所述般測定積層配線膜的電阻率。即，利用4端子法，對在無鹼玻璃板上，以所記載的膜厚於表1所記載的Cu系膜上形成有蓋層的樣品測定電阻。根據所測定的電阻、及Cu系膜與蓋層的膜厚的合計值算出電阻率。繼而，使用愛發科公司製造的紅外線燈加熱裝置：RTP-6，在N2 環境下分別於400℃與500℃下進行1小時的熱處理後，同樣地測定電阻，利用所述相同的方法算出電阻率。
將其結果示於表1中。本實施例中，400℃下電阻率為3 μΩcm以下的試樣就面向使用氧化物半導體的TFT元件的耐熱性而言視為合格，500℃下電阻率為3 μΩcm以下的試樣面向使用氧化物半導體或LTPS的TFT元件而言視為合格。
（3）配線形狀、錐角的評價 使用光阻劑於積層配線膜上形成包含線與空間的抗蝕劑圖案。關於試樣No.2～No.39中所記載的積層配線膜，利用三菱氣體化學股份有限公司製造的過氧化氫系蝕刻液進行蝕刻加工，其後，浸漬於丙酮中將抗蝕劑去除，從而連同透明基板一起開裂。其次，關於已進行所述蝕刻加工的試樣，使用日立電力解決方案（Hitachi Power Solutions）股份有限公司製造的電子顯微鏡：S-4000來觀察其剖面形狀。將如圖6中的（a）所示蓋層13較配線層12伸出而形成有延伸部13（a）者評價為「有延伸部」，將如圖6中的（b）所示般成為倒錐狀者評價為「倒錐形狀」，將如圖6中的（c）所示般成為正錐狀者評價為「正錐形狀」。
繼而，關於試樣No.1～No.39中所記載的積層配線膜，自剖面形狀來測定相對於透明基板的錐角。另外，藉由下述式（1）來計算以相同的方法而製作的試樣No.1的配線層的錐角相對於Cu單膜的錐角的比率。此外，將相對於透明基板的錐角為30°～80°者判斷為合格，尤其，將以試樣No.1的配線層的錐角相對於Cu單膜的錐角的比率為-25%～+50%的範圍內的角度加工而成者判斷為更優異者。將其結果示於表1中｡ 相對於Cu單膜的錐角的比率（%）=[（Cu單膜的錐角）-（積層配線膜的錐角）]/（Cu單膜的錐角）…（1）
（4）耐氧化的評價 於積層配線膜的蓋層上，使用薩姆肯（SAMCO）股份有限公司製造的電漿CVD裝置：PD-220ML來形成SiOx膜。成膜時使用SiH4 與N2 O氣體，形成膜厚250 nm的SiOx膜，藉由目視來檢查外觀，並確認SiOx膜有無剝離。將其結果示於表1中。此外，於耐氧化不足的情況下，於SiOx膜的成膜時膜的表面進行氧化，而產生顏色不均或進而因界面的體積膨脹而產生SiOx膜的膜脫落，因此欠佳。
將所述（2）積層配線膜的電阻率的測定、（3）配線形狀、錐角的評價、以及（4）耐氧化的評價的結果示於表1中。
另外，根據所述（2）～（4）項的結果，400℃熱處理下電阻率為3 μΩcm以下、配線形狀為正錐形狀、且無利用CVD法進行SiOx成膜時的剝離者就適宜面向使用氧化物半導體的TFT元件而言視為合格『○』，將不滿足所述條件的任一條件者視為不合格『×』。
而且，400℃及500℃熱處理下電阻率為3 μΩcm以下、配線形狀為正錐形狀、且相對於透明基板的錐角為30°～80°而且於利用CVD法進行SiOx成膜時無剝離者就適宜面向使用氧化物半導體及低溫多晶矽半導體的TFT元件而言視為合格『○』，將不滿足所述條件的任一條件者設為不合格『×』。
將結果匯總示於表1中。
[表1]
根據表1的結果，可知如下。首先，No.1為不具有蓋層的Cu單膜的例子，於SiOx膜的成膜時觀察到剝離。繼而，No.2～No.13為作為蓋層的Cu-X合金層包含Cu與一種元素的積層配線膜。No.5、No.8～No.10、No.13為滿足本發明規定的Cu-X合金層的X元素的組成系（1）的例子，配線形狀為正錐狀，於400℃的熱處理後電阻亦為3 μΩcm以下的電阻，於SiOx膜的成膜時亦未確認到剝離。相對於此，No.3、No.6無法穩定地獲得高熱處理時的低電阻，且No.3成為於Cu-X合金層形成有延伸部的配線形狀。No.2、No.4、No.7、No.11以及No.12於SiOx膜的成膜時觀察到剝離。
尤其，No.5與No.8為滿足本發明所規定的Cu-X合金層的X元素的組成系（1'）的例子，配線形狀為正錐狀，且錐角亦為30°～80°，於400℃與500℃的熱處理後的任一者中均為3 μΩcm以下的電阻，於SiOx膜的成膜時亦未確認到剝離。
另外，No.14～No.39為作為蓋層的Cu-X合金層包含Cu與兩種以上的元素的積層配線膜。No.19～No.39為滿足本發明所規定的Cu-X合金層的X元素的組成系（2）～組成系（5）的任一者的例子，配線形狀為正錐狀，於400℃的熱處理後電阻亦為3 μΩcm以下的電阻，於SiOx膜的成膜時亦未確認到剝離。相對於此，No.14～No.18無法穩定地獲得高熱處理時的低電阻。
尤其，No.19、No.27～No.30以及No.32～No.39為滿足本發明所規定的Cu-X合金層的X元素的組成系（2'）～組成系（5'）的任一者的例子，配線形狀為正錐狀，且錐角亦為30°～80°，於400℃與500℃的熱處理後的任一者中均為3 μΩcm以下的電阻，於SiOx膜的成膜時亦未確認到剝離。
此外，若著眼於No.22～No.26的Cu-Zn-Mn合金層，則No.24～No.26的例子中，滿足本發明所規定的Cu-X合金層的X元素的組成系（3'），且500℃的熱處理後的電阻相較於No.22以及No.23成為低值（2.0 μΩcm以下）。根據該結果可知，使用Cu-Zn-Mn合金層時的Mn的含量較佳為10 at%以下。
另外，同樣地，若著眼於No.35～No.39的Cu-Al-Ni合金層，則No.37及No.38的例子中，滿足本發明所規定的Cu-X合金層的X元素的組成系（5'），且500℃的熱處理後的電阻相較於No.35、No.36以及No.39成為低值（2.3 μΩcm）。根據該結果可知，使用Cu-Al-Ni合金層時的Ni的含量較佳為6 at%以上。
＜實施例2＞ 藉由下述順序來製作使用包含Ti的密接層時的積層配線膜。具體而言，與實施例1的情況同樣地，於作為透明基板的無鹼玻璃板上，藉由DC磁控濺鍍法依序成膜具備表2所示的密接層、配線層以及作為Cu-X合金層的蓋層的積層配線膜。此外，試樣No.40的配線膜為僅有密接層及配線層的積層膜。密接層、配線層以及蓋層的成膜條件與實施例1的情況相同。
關於以如上所述的方式而獲得的積層配線膜，在與實施例1的情況相同的條件下進行電阻率的測定以及耐氧化的評價。另外，根據所述結果，400℃熱處理下電阻率為3 μΩcm以下、無利用CVD法進行SiOx成膜時的剝離者就適宜面向使用氧化物半導體的TFT元件而言視為合格『○』，將不滿足所述條件的任一條件者視為不合格『×』。
而且，400℃及500℃熱處理下電阻率為3 μΩcm以下、於利用CVD法進行SiOx成膜時無剝離者就適宜面向使用氧化物半導體及低溫多晶矽半導體的TFT元件而言視為合格『○』，將不滿足所述條件的任一條件者視為不合格『×』。
將積層配線膜的電阻率的測定、耐氧化的評價、以及對使用氧化物半導體或低溫多晶矽半導體的TFT元件的適合性的結果匯總示於表2中。
[表2]
根據表2的結果，可知如下。首先，No.40為僅有密接層及配線層的積層膜的例子，於SiOx膜的成膜時觀察到剝離。另外，不滿足於500℃的熱處理後電阻為3 μΩcm以下。進而，No.41為不滿足本發明所規定的Cu-X合金層的X元素的組成系（1）的例子，雖然於SiOx膜的成膜時未觀察到剝離，但不滿足於400℃及500℃的任一熱處理後電阻亦為3 μΩcm以下。
相對於此，No.42～No.46為滿足本發明所規定的Cu-X合金層的X元素的組成系（1）～（5）的任一者的例子，滿足於400℃及500℃的任一熱處理後電阻亦為3 μΩcm以下，於SiOx膜的成膜時未觀察到剝離。
已參照特定的態樣詳細地說明瞭本發明，但對於本領域從業人員可明確的是：可不脫離本發明的精神與範圍而進行各種變更及修正。此外，本申請案基於2016年5月13日提出申請的日本專利申請（日本專利特願2016-097321）以及2017年4月11日提出申請的日本專利申請（日本專利特願2017-078505），藉由引用而援用其整體。
1‧‧‧玻璃基板
2、6、12‧‧‧配線層
3、7‧‧‧蓋層（Cu-X合金層）
4、8‧‧‧絕緣膜（SiOx）
5‧‧‧氧化物半導體
11‧‧‧基板
13‧‧‧蓋層
13a‧‧‧延伸部
14‧‧‧密接層
圖1是例示本發明的積層配線膜的構成的概略剖面圖。 圖2是例示本發明的具備積層配線膜的薄膜電晶體元件的構成的概略剖面圖。 圖3是於Cu單膜上利用CVD法形成SiOx膜時的外觀照片，圖3中的（a）是於約200℃下成膜時的外觀照片，圖3中的（b）是於約300℃下成膜時的外觀照片。 圖4是於Cu單膜上利用CVD法，於約200℃的成膜溫度下形成SiOx膜時的、倍率為20萬倍的剖面穿透式電子顯微鏡（Transmission Electron Microscope，TEM）觀察照片，圖4中的（a）是積層膜的整體圖，圖4中的（b）是表面的放大圖。 圖5是於Cu-30 at%Ni/Cu積層膜上，利用成膜溫度為200℃的CVD法形成SiOx膜時的外觀照片。 圖6是利用濕式蝕刻法所獲得的配線形狀的概略圖，圖6中的（a）為蓋層較配線層伸出而形成有延伸部的配線形狀，圖6中的（b）為倒錐狀的配線形狀，圖6中的（c）為正錐狀的配線形狀。 圖7是例示本發明的積層配線膜的其他構成的概略剖面圖。

Claims (7)

  1. 一種積層配線膜，其特徵在於具備：包含電阻為10μΩcm以下的Cu或Cu合金的配線層、以及設於所述配線層的上層及下層中的至少一者的包含Cu與X元素的Cu-X合金層，所述X元素為選自由Al、Mn、Zn以及Ni所組成的X群組中的至少一種，構成所述Cu-X合金層的金屬為下述(1)~(4)中的任一組成系，配線圖案的寬度為10μm以下：(1)包含4at%以上且15at%以下的Al，進而包含5at%以上且10at%以下的Mn；(2)包含5at%以上且10at%以下的Zn，進而包含5at%以上且26at%以下的Mn；(3)包含4at%以上且14at%以下的Zn，進而包含5at%以上且15at%以下的Al；(4)包含5at%以上且10at%以下的Al，進而包含2at%以上且10at%以下的Ni。
  2. 如申請專利範圍第1項所述的積層配線膜，其中構成所述Cu-X合金層的金屬為下述(1')~(4')中的任一組成系，配線圖案的寬度為5μm以下：(1')包含4at%以上且9at%以下的Al，進而包含5at%以上且10at%以下的Mn；(2')包含5at%以上且10at%以下的Zn，進而包含5at%以上且10at%以下的Mn；(3')包含4at%以上且14at%以下的Zn，進而包含5at%以上且10at%以下的Al；(4')包含5at%以上且10at%以下的Al，進而包含6at%以上且10at%以下的Ni。
  3. 如申請專利範圍第1項或第2項所述的積層配線膜，其為積層於基板的積層配線膜，且於積層於所述基板之側的表面進而具有包含Ti的密接層。
  4. 如申請專利範圍第1項或第2項所述的積層配線膜，其中所述配線層的膜厚為50nm以上且1000nm以下，所述Cu-X合金層的膜厚為5nm以上且200nm以下。
  5. 如申請專利範圍第3項所述的積層配線膜，其中所述配線層的膜厚為50nm以上且1000nm以下，所述Cu-X合金層的膜厚為5nm以上且200nm以下。
  6. 一種薄膜電晶體元件，其特徵在於包含如申請專利範圍第1項所述的積層配線膜及氧化物半導體。
  7. 一種薄膜電晶體元件，其特徵在於包含如申請專利範圍第2項所述的積層配線膜及低溫多晶矽半導體或氧化物半導體。
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