WO2017145923A1 - 半導体素子搭載用基板、半導体装置及び光半導体装置、並びにそれらの製造方法 - Google Patents

半導体素子搭載用基板、半導体装置及び光半導体装置、並びにそれらの製造方法 Download PDF

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Publication number
WO2017145923A1
WO2017145923A1 PCT/JP2017/005832 JP2017005832W WO2017145923A1 WO 2017145923 A1 WO2017145923 A1 WO 2017145923A1 JP 2017005832 W JP2017005832 W JP 2017005832W WO 2017145923 A1 WO2017145923 A1 WO 2017145923A1
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Prior art keywords
semiconductor element
lead portion
lead
die pad
resist
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PCT/JP2017/005832
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English (en)
French (fr)
Japanese (ja)
Inventor
博幸 有馬
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Ｓｈマテリアル株式会社
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Application filed by Ｓｈマテリアル株式会社 filed Critical Ｓｈマテリアル株式会社
Priority to MYPI2018001471A priority Critical patent/MY188860A/en
Priority to CN201780012202.XA priority patent/CN108701658B/zh
Publication of WO2017145923A1 publication Critical patent/WO2017145923A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/85005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a semiconductor element mounting substrate, a semiconductor device, an optical semiconductor device, and a manufacturing method thereof.
  • a resist mask subjected to predetermined patterning is formed on one surface side of a conductive substrate. After plating metal on the conductive substrate exposed from the resist mask to form a die pad part for mounting a semiconductor element, and an internal terminal connected to the semiconductor element and a lead part functioning as an external terminal connected to an external device Then, by removing the resist mask, a semiconductor element mounting substrate is formed. The semiconductor element is mounted on the formed semiconductor element mounting substrate, and after wire bonding, resin sealing is performed, the conductive substrate is removed, the die pad portion and the lead portion are exposed, and the semiconductor device is completed (for example, (See Patent Documents 1 and 2).
  • Patent Document 1 discloses a semiconductor having a metal layer for mounting a semiconductor element and a protruding portion at the periphery of the upper end of an electrode layer for external connection by electrodepositing a conductive metal beyond the formed resist mask. A method for obtaining an element mounting substrate is described. As a result, the protruding portion of the metal layer and the electrode layer bites into the resin at the time of resin sealing, and can be reliably left on the resin side.
  • Patent Document 2 describes a method of forming a metal layer or an electrode layer in an inverted trapezoidal shape by forming a resist mask into a trapezoid using scattered ultraviolet light when forming a resist mask. Yes.
  • the cross-sectional shape of the electrode layer is inverted trapezoidal, when the semiconductor element is mounted and resin-sealed after wire bonding, the side surface of the electrode layer becomes an acute angle with respect to the conductive substrate, and the sealing resin Became difficult to wrap around. For this reason, unfilling of sealing resin such as voids may occur in some cases.
  • the sealing resin near the electrode layer base is naturally formed following this angle, so that the tip has an acute shape and is weak in strength, and the tip of the sealing resin portion is likely to be chipped or peeled off. There was a problem.
  • the resist layer is in a semi-exposure state and forms a tapered shape.
  • the dimensional accuracy of the bottom surface was prepared by exposing and developing the resist using parallel light.
  • the variation is larger than the dimensional accuracy and the dimensional accuracy is inferior.
  • the lead shape tends to become smaller due to the miniaturization and thinning of the semiconductor device, it is important to improve the dimensional accuracy of the bottom surface. With the configuration described in Patent Document 2, it is difficult to sufficiently meet this requirement. there were.
  • the present invention provides a semiconductor device completed by mounting a semiconductor element and then resin-sealing and removing the conductive substrate, and the degree of adhesion between the sealing resin and the lead portion is appropriate.
  • a semiconductor element mounting substrate includes a conductive substrate that can be removed after mounting a semiconductor element; A semiconductor element mounting region provided on the surface of the conductive substrate; A lead portion made of a plating layer provided in a predetermined region on the surface of the conductive substrate around the semiconductor element mounting region; The lead portion has a side surface substantially perpendicular to the surface of the conductive substrate, and a lower step portion extending upward in a column shape from the surface; And an upper step portion having a bottom surface on the upper surface of the lower step portion and a side surface extending upward and sideward in a tapered manner from the bottom surface.
  • a semiconductor device includes a semiconductor element, A lead portion made of a plating layer provided in a predetermined region around the semiconductor element and having an upper step portion and a lower step portion having different shapes; Connection means for electrically connecting the electrode of the semiconductor element and the upper surface of the upper portion of the lead portion; A resin that seals the semiconductor element, the lead portion, and the connecting means so that at least a bottom surface of the lower step portion of the lead portion is exposed;
  • the lower step portion of the lead portion has a columnar shape having a side surface extending vertically upward from the bottom surface,
  • the upper step portion of the lead portion has a bottom surface on the upper surface of the lower step portion, and has a tapered shape in which a side surface is tapered upward and laterally from the bottom surface.
  • An optical semiconductor device includes a die pad portion having a region for mounting an optical semiconductor element; A lead portion comprising a plating layer provided in a pair with the die pad portion and having an upper step portion and a lower step portion having different shapes; An optical semiconductor element mounted on the die pad portion; Connection means for electrically connecting the electrode of the optical semiconductor element and the upper surface of the upper portion of the lead portion; A transparent resin that seals a predetermined central region on the die pad portion and the lead portion including the optical semiconductor element and the connection means; A region between the die pad portion and the lead portion other than the bottom surface of the die pad portion and the lead portion, and predetermined areas of the die pad portion and the lead portion so that the bottom surfaces of the die pad portion and the lead portion are exposed.
  • the lower step portion of the lead portion has a columnar shape having a side surface extending vertically upward from the bottom surface, and the upper step portion of the lead portion has a bottom surface on the upper surface of the lower step portion. It has a tapered shape in which the side surface is widened upward and laterally.
  • a method for manufacturing a semiconductor element mounting substrate comprising: a first resist layer coated with a first resist having a first photosensitive wavelength on a surface of a conductive substrate; A step of sequentially forming a second resist layer coated with a second resist having a second photosensitive wavelength on the resist layer, and a third resist layer coated with the first resist on the second resist layer.
  • the first and third resist layers are cured, and development is performed in a state where the second resist layer is not cured, and the upper portion of the second resist layer is the first and third resist layers.
  • the present invention it is possible to prevent the lead portion from dropping and peeling when the conductive substrate is removed, and to improve the dimensional accuracy of the bottom surface of the lead portion.
  • FIG. 3A is a plan view showing an example of the lead portion.
  • FIG. 3B is an xx cross-sectional view of the lead portion shown in FIG. It is a figure for demonstrating the formation method of a lead part.
  • FIG. 4A shows an example of a resist mask for plating.
  • FIG. 4B is a diagram showing an example of plating using a plating resist mask. It is a figure for demonstrating the lead part which has a shape different from FIG. FIG.
  • FIG. 5A is a plan view showing an example of a lead portion having a shape different from that in FIG.
  • FIG. 5B is a cross-sectional view of the lead portion yy shown in FIG.
  • FIG. 5C is a zz cross-sectional view of the lead portion shown in FIG. It is the figure which showed a series of processes of an example of the manufacturing method of the board
  • FIG. 6A is a diagram illustrating an example of a substrate preparation process.
  • FIG. 6B is a diagram showing an example of a resist coating process.
  • FIG. 6C is a diagram showing an example of a resist mask forming process.
  • FIG. 6D is a diagram showing an example of the plating process.
  • FIG. 6A is a diagram illustrating an example of a substrate preparation process.
  • FIG. 6B is a diagram showing an example of a resist coating process.
  • FIG. 6C is a diagram showing an example of a resist mask forming
  • FIG. 6E is a diagram illustrating an example of a resist stripping process. It is the figure which showed a series of processes of an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention.
  • FIG. 7A is a diagram showing an example of a semiconductor element mounting process.
  • FIG. 7B is a diagram illustrating an example of a wire bonding process.
  • FIG. 7C is a diagram showing an example of the resin sealing process.
  • FIG. 7D is a diagram showing an example of the conductive substrate removing process.
  • FIG. 7E shows an example of the cutting process. It is sectional drawing which shows an example of the board
  • 10 is an enlarged view from the top surface of the lead portion of the semiconductor element mounting substrate according to the second embodiment, and is a partial enlarged view of a side surface of the lead portion. It is an enlarged view from the back surface of the lead part of the semiconductor element mounting substrate according to Example 2, and is an enlarged view of a part of the side surface on the back surface side of the lead part.
  • FIG. 1 is a cross-sectional view showing an example of a semiconductor element mounting substrate according to an embodiment of the present invention.
  • the semiconductor element mounting substrate 50 according to the present embodiment includes a conductive substrate 10, a semiconductor element mounting die pad portion 21 disposed on the surface 11, and a lead portion 22 for connecting to an external device. Has been.
  • the lead portion 22 is disposed around the die pad portion 21 that is a semiconductor element mounting region.
  • the die pad portion 21 is not manufactured after the semiconductor element mounting area is secured.
  • a semiconductor element is directly mounted on the conductive substrate 10 or a flip chip connection type in which an electrode of the semiconductor element is directly bonded to a lead portion. That is, in the present embodiment, it is not essential to provide the die pad portion 21, and it is only necessary to secure a semiconductor element mounting region in which a semiconductor element can be mounted.
  • the die pad portion 21 is provided as the semiconductor element mounting region will be described.
  • the die pad portion 21 and the lead portion 22 may be configured by the same plating layer 20.
  • symbol overlaps with the die pad part 21 and the lead part 22, and the plating layer 20, when it demonstrates from a viewpoint of the component of the board
  • the conductive substrate 10 is a substrate on which the plating layer 20 is formed on the surface 11, and is made of a conductive material so that the plating layer 20 can be formed by electroplating.
  • the material of the conductive substrate 10 to be used is not particularly limited as long as conductivity is obtained, but a metal material is generally used, for example, Cu or Cu alloy. When the conductive substrate is peeled off and removed, a SUS material may be used.
  • the die pad part 21 and the lead part 22 are constituted by a plating layer 20 formed on one surface (front surface 11) of the conductive substrate 10 by plating.
  • the semiconductor element mounting substrate 50 according to the embodiment of the present invention is characterized by the shape of the lead portion 22.
  • the lead portion 22 includes a columnar lower step portion 22b and a tapered upper step portion 22a.
  • the die pad portion 21 may have a columnar lower step portion 21b and a tapered upper step portion 21a. Details of the configurations of the die pad portion 21 and the lead portion 22 will be described later.
  • FIG. 2 is a cross-sectional view of an example of the semiconductor device 100 according to the embodiment of the present invention.
  • the semiconductor element 60 is mounted on the die pad portion 21, and the electrode 61 of the semiconductor element 60 and the lead portion 22 are connected via a bonding wire 70 or the like.
  • the whole including the connection means such as the semiconductor element 60 and the bonding wire 70 is sealed with the resin 80.
  • the die pad portion 21 and the lead portion 22 have the upper surface 23 and the side surface 24 covered with the resin 80, but the bottom surface 25 is exposed.
  • the conductive substrate 10 existing in FIG. 1 does not exist. The conductive substrate 10 is removed after sealing with the resin 80. That is, the semiconductor element 60 is mounted on the die pad portion 21 of the semiconductor element mounting substrate 50 shown in FIG.
  • the electrode 61 and the lead portion 22 of the semiconductor element 60 are connected via the bonding wire 70 by wire bonding. Thereafter, sealing is performed with a resin 80 on the semiconductor element mounting substrate 50. After the resin sealing, the conductive substrate 10 is removed, whereby the semiconductor device 100 as shown in FIG. 2 is manufactured. The bottom surface 25 of the lead portion 22 exposed by removing the conductive substrate 10 serves as an external terminal for soldering with an external device.
  • FIG. 3 is a view showing an example of the lead portion 22 of the semiconductor element mounting substrate 100 according to the embodiment of the present invention.
  • FIG. 3A is a plan view showing an example of the lead portion 22.
  • FIG. 3B is an xx cross-sectional view of the lead portion 22 shown in FIG.
  • the first feature of the semiconductor element mounting substrate 50 is the cross-sectional shape of the lead portion 22.
  • the lead portion 22 includes an upper step portion 22a and a lower step portion 22b having different shapes.
  • the cross section of the lower step portion 22b has a shape having a straight line portion in the vertical direction.
  • the cross section of the upper step portion 22a has a tapered shape in which the upper portion extends along the periphery of the lead portion.
  • the lower step portion 22b has a columnar shape extending upward from the surface 11 of the conductive substrate 10 perpendicularly to the surface 11.
  • the lower step portion 22b has a substantially rectangular planar shape or horizontal cross-sectional shape, and has a substantially quadrangular prism shape. Since the side surface 24b of the lower step portion 22b extends along the vertical direction, the planar shape and the horizontal cross-sectional shape of the lower step portion 22b are the same in all cases of cutting at the bottom surface, the upper surface, or between the bottom surface and the upper surface. is there.
  • the lower step portion 22b has a columnar shape with a constant planar shape and horizontal cross-sectional shape.
  • the upper step portion 22a is provided continuously and integrally with the lower step portion 22b on the upper surface of the lower step portion 22b. That is, the bottom surface (lower surface) of the upper step portion 22a is provided on the same horizontal plane as the upper surface of the lower step portion 22b.
  • the bottom surface of the upper step portion 22a is not necessarily congruent with the upper surface of the lower step portion 22b.
  • the bottom surface of the upper step portion 22a is formed wider than the lower step portion 22b, and the bottom surface of the upper step portion 22a is the lower step portion 22b. It may be formed so as to include the upper surface.
  • the bottom surface of the upper step portion 22a has substantially the same shape as the upper surface of the lower step portion 22b, and has a rectangular shape with rounded corners.
  • the side surface 24a of the upper step portion 22a has a shape that extends upward and laterally in a tapered shape from the bottom surface.
  • the upper surface of the upper step portion 22a has a shape similar to that of the lower step portion 22b, and is formed in a substantially rectangular shape.
  • the side surface 24a is generally tapered from the bottom surface of the upper step portion 22a and spreads at substantially the same ratio, and the planar shape of the upper surface of the upper step portion 22a is larger than the upper surface of the lower step portion 22b. Means.
  • the resin 80 can bite and get caught, and when the conductive substrate 10 is peeled off from the resin 80, the lead portion 22 can be separated from the resin 80. Dropping off can be prevented.
  • the die pad portion 21 may have an upper step portion 21 a and a lower step portion 21 b. Thereby, the die pad part 21 can also be prevented from falling off from the resin 80.
  • FIG. 4 is a view for explaining a method of forming the lead portion 22.
  • FIG. 4A shows an example of the resist mask 35 for plating.
  • FIG. 4B is a diagram showing an example of plating using the resist mask 35 for plating.
  • the lead portion 22 covers three resist layers 31, 32, 33 on the conductive substrate 10, and is exposed and developed to produce a resist mask 35 for plating. This is used for plating.
  • the resist layer in contact with the conductive substrate 10 is used as the first resist layer 31, and the uppermost resist is used as the third resist layer 33.
  • the intermediate resist layer becomes the second resist layer 32.
  • the pattern of the first resist layer 31 and the third resist layer 33 is a bottom shape pattern of the lead portion 22.
  • the first resist layer 31 and the third resist layer 33 are made of the same type of resist having the same photosensitive wavelength
  • the second resist layer 32 is made of the first and third resist layers 31. , 33 and resists having different wavelengths for exposure are used.
  • the resist layers 31 to 33 When the resist layers 31 to 33 are exposed, the first and third resist layers 31 and 33 are exposed to light, and the second resist layer 32 is exposed at a wavelength that is not exposed to light.
  • the resist layers 31 and 33 are cured, and the second resist layer 32 is brought into an unexposed state.
  • the first resist layer 31 and the third resist layer 33 are substantially the same as the bottom shape of the lead portion 22, and the vertical side (side surface 24b) of the vertical cross section becomes a straight line.
  • the second resist layer 32 Since the second resist layer 32 is developed in the direction of the first resist 31 from the opening 34 of the third resist layer 33, as shown in FIG.
  • the sides are tapered so that the upper surface side is narrower (the shape of the opening 34 is wider on the upper surface side).
  • the second resist layer 32 is in an unexposed state and is subjected to a curing process by exposure after development. In this manner, a plating resist mask 35 in which the second resist layer 32 has a tapered shape is produced.
  • the plating layer 20 is formed using the prepared resist mask 35 for plating.
  • the thickness of the plating layer 20 is set so that the upper surface of the plating layer 20 is between the second resist layers 32 before reaching the third resist layer 33.
  • the plating layer 20 is plated up to the third resist layer 33, the tapered shape of the third resist layer 33 becomes small even though the second resist layer 32 forms a tapered shape whose upper surface side is widened.
  • the plating thickness is set so that the upper surface of the plating layer 20 is between 1/2 and 4/5 of the second resist layer 32.
  • the taper shape of the second resist layer 32 can be adjusted by the thickness of the second resist layer 32, the developing time in the developing process, the discharge pressure of the developer, and the like.
  • the taper angle can be arbitrarily set on the basis of the horizontal direction. However, in consideration of the adhesiveness with the resin 80, it is preferably set to 30 ° to 80 °, and preferably set to 30 ° to 60 °. More preferred.
  • the lead portion 22 is formed by using the above-described three-layer resist mask 35 and plating the opening 34 of the resist mask 35 to form the plating layer 20. Since the plating layer 20 is formed following the shape of the resist mask 35, the side surface of the plating layer 20 is divided into an upper step portion 20a (second resist layer portion) and a lower step portion 20b (first resist layer portion). The side surface of the lower step portion 20 b has a linear portion in the vertical direction, and the side surface of the upper step portion 20 a has a tapered shape in which the upper portion extends along the periphery of the plating layer 20.
  • the thickness of the lower step portion 20 b of the plating layer 20 of the lead portion 22 is the thickness of the first resist layer 31.
  • the thickness of the lower step portion 20b of the plating layer 20 is not particularly limited, but is preferably 10 ⁇ m to 25 ⁇ m in consideration of the thickness of the first resist layer 31.
  • the thickness of the upper step portion 20a is not particularly limited, but as described above, the plating layer 20 preferably has a thickness of 2/5 to 4/5 of the second resist layer 32, or this taper. It is preferable to set the thickness to 20 ⁇ m to 50 ⁇ m because the portion improves the adhesion to the resin 80.
  • the cross-sectional shape of the lead portion 22 is divided into an upper step portion 22a (second resist layer portion) and a lower step portion 22b (first resist layer portion).
  • the side surface 24b of the lower step portion 22b has a straight portion in the vertical direction, and the side surface 24a of the upper step portion 22a can form a lead portion 22 having a tapered shape in which the upper portion extends along the periphery of the plating layer.
  • Patent Document 1 describes a shape having a protruding portion on the periphery of the upper end portion of the lead portion by electrodepositing a conductive metal beyond the formed resist mask. In this method, it is difficult to control the amount of overhang, and there is a problem that not all of the plating layers to be formed have the same overhang length or a problem that the overhang portion is connected to the adjacent plating layer.
  • the lead portion 22 is divided into an upper step portion 22a and a lower step portion 22b, and the upper step portion 22a is tapered. Since the taper shape of the upper step portion 22a is formed by the second resist layer 32, the shape can be controlled, and the thickness, length, and taper angle of the overhang portion can be arbitrarily set. In addition, the upper surface of the upper step portion 22a that functions as an internal terminal can obtain a substantially flat surface. Moreover, in the shape of patent document 1, when the overhang
  • Patent Document 2 describes that the cross-sectional shape of the lead portion is tapered.
  • the cross-sectional shape of the lead portion is an inverted trapezoid
  • the side surface portion of the electrode layer has an acute angle with respect to the conductive substrate when the semiconductor element is mounted and resin-sealed after wire bonding.
  • the sealing resin near the base of the lead portion is naturally formed following this angle, so that the tip has an acute shape and is weak in strength, and the tip of the sealing resin portion is likely to be chipped or peeled off. There was a problem.
  • the resist layer has a tapered shape, the dimensional accuracy of the bottom surface was inferior.
  • the lead portion 22 is divided into an upper step portion 22a and a lower step portion 22b, and the side surface of the lower step portion 22b has a straight portion in the vertical direction. Therefore, the bottom surface of the lead portion 22 does not become an acute angle with the conductive substrate 10. Thereby, generation
  • FIG. 5 is a view for explaining a lead portion 26 having a shape different from that in FIG.
  • FIG. 5A is a plan view showing an example of the lead portion 26.
  • FIG. 5B is a yy sectional view of the lead portion 26 shown in FIG.
  • FIG. 5C is a zz sectional view of the lead portion 26 shown in FIG.
  • the bottom shape of the lead portion is generally a substantially rectangular shape as shown in FIG.
  • an uneven shape may be added to each side constituting the side surface 27 of the lead portion 26.
  • the uneven shape includes, for example, a wavy shape, a zigzag shape in which a chevron shape is continuous, a saw shape, and the like.
  • Each vertex of the zigzag shape is a rounded curved shape.
  • the bottom surface 26d and the top surface 26c of the upper step portion 26a have a substantially rectangular bottom surface 26d, and the top surface 26c has an uneven shape.
  • the bottom surface 26d of the upper step portion 26a has a rectangular shape including the uneven shape of the upper surface of the lower step portion 26b.
  • the lead portion 26 is divided into an upper step portion 26a and a lower step portion 26b, and a side surface 27b of the lower step portion 26b is in a vertical direction.
  • the side surface 27a of the upper step portion 26a has a tapered shape having an upper portion extending along the periphery of the lead portion.
  • a part of the bottom surface 26d of the upper step portion 26a may have a horizontal portion 26e at the boundary between the upper step portion 26a and the lower step portion 26b.
  • a portion having a horizontal portion 26e at a part of the bottom surface 26d (the boundary between the upper step portion and the lower step portion) of the upper step portion 26a is formed in a recess portion 27c when an uneven shape is added to each side of the bottom shape of the lead portion 26 described above. can do.
  • the recess 27c By forming the recess 27c, the lower surface of the recess 27c can be filled with the resin 80, and the adhesion with the resin 80 can be further improved.
  • the concave amount of the concave portion of the concave / convex portion is about 1/2 times the thickness of the lower step portion 26b to three times the thickness of the lower step portion 26b. Is preferred. If the thickness of the lower step portion 26b is less than 1 ⁇ 2, the effect of adhesion is small, and if it exceeds three times, the possibility that a resist residue will occur when the first resist layer 31 is peeled off is increased. Preferably, it is about the thickness of the lower step part 26b. Since the horizontal portion 26e has a flat surface, it may be called the flat surface 26e.
  • the semiconductor device 100 has the resin pad 80, the die pad portion 21, the lead portions 22, 26, and the like by forming the die pad portion 21 and the lead portions 22, 26 as described above.
  • the resin pad 80 the die pad portion 21, the lead portions 22, 26, and the like by forming the die pad portion 21 and the lead portions 22, 26 as described above.
  • FIG. 6 is a diagram showing a series of steps of an example of a method for manufacturing a semiconductor element mounting substrate according to an embodiment of the present invention.
  • FIG. 6A is a diagram showing an example of the substrate preparation process.
  • the conductive substrate 10 is prepared.
  • the material of the conductive substrate 10 to be used is not particularly limited as long as conductivity can be obtained.
  • a metal material is used, and for example, a SUS material or Cu or Cu alloy is used.
  • FIG. 6B is a diagram showing an example of a resist coating process.
  • the entire front and back surfaces of the conductive substrate 10 are covered with a resist.
  • the surface side covers the three resist layers 31 to 33.
  • the back surface covers one resist layer 30.
  • the three resist layers 31 to 33 on the front side are a first resist layer 31, a second resist layer 32, and a third resist layer 33 from the conductive substrate 10 side.
  • the first resist layer 31 and the third resist layer 33 are the same kind of resist layers having substantially the same wavelength for exposure.
  • As the second resist layer 32 a resist layer having a different wavelength from that of the first and third resist layers 31 and 33 is used.
  • a resist to be used a conventionally known method such as laminating a dry film resist or coating a resist layer by applying and drying a liquid resist can be used.
  • FIG. 6C shows an example of a resist mask forming process.
  • the resist mask formation process includes an exposure process, a development process, and a curing process.
  • the exposure process the front and back surfaces of the conductive substrate 10 are coated with a resist in the previous resist coating process. Thereafter, the first resist layer 31 and the third resist layer 33 are exposed on the surface side, and the second resist layer 32 is exposed to light having a wavelength that is not exposed.
  • the back side is exposed with light having a wavelength to which the resist layer 30 on the back side is exposed.
  • the resist is covered with a mask (ultraviolet light shielding glass mask) on which the surface has a pattern in which a plurality of sets including a desired die pad portion 21 and lead portion 22 are arranged, and the back surface has a pattern covering the entire surface. And exposure.
  • a mask ultraviolet light shielding glass mask
  • the second resist layer 32 is in an unexposed state because the photosensitive wavelength is different from that of the first resist layer 31.
  • the resist layers 30 to 33 are developed by removing the mask. First, unexposed light is removed from the opening 34 of the third resist layer 33, and then developed with the second resist layer 32 and first with the resist layer 31. For this reason, since the second resist layer 32 is an unexposed portion, it is also removed in the horizontal direction from the third resist layer 33 side (upper side).
  • the shape of the opening 34 is a tapered shape in which the upper surface side is widened.
  • the taper angle is adjusted by controlling the development speed by the thickness of the second resist layer 32, the development time in the development process, the discharge pressure of the developer, and the like. Can do. Thereafter, the second resist layer is cured. The second resist layer 32 is in an unexposed state and is cured by exposure. In this manner, a resist mask for plating 35 having a taper shape on the second resist layer 32 is produced.
  • a mask ultraviolet light shielding glass
  • the development time is made longer than the tapered shape, so that the bottom surface of the upper step portion 26a that is the boundary between the upper step portion 26a and the lower step portion 26b corresponding to the recess portion 27c. It is possible to provide the horizontal part 26e in 26d. By adjusting the development time, the length of the horizontal portion 26e can be adjusted. Because it depends on the pattern shape, it is adjusted according to the situation.
  • FIG. 6D is a diagram showing an example of the plating process.
  • the plating step using the resist mask 35 formed in FIG. 6B, the exposed portion of the conductive substrate 10 in which the opening 34 is formed is plated to form the plated layer 20.
  • Plating is performed to a height of about 4/5 of the second resist layer 32.
  • the plating layer 20 is first formed along the shapes of the resist layer 31 and the second resist layer 32.
  • the side surface of the lead portion 22 is divided into an upper step portion 22a and a lower step portion 22b.
  • the side surface 24 b of the lower step portion 22 b has a straight line portion in the vertical direction, and the side surface 24 a of the upper step portion 22 a can be formed in a shape having a tapered shape in which the upper portion extends along the periphery of the lead portion 22.
  • plating there is no particular limitation on the type of plating.
  • the plating thickness of the die pad portion 21 and the lead portion 22 is also not particularly limited, but considering the adhesion with the sealing resin, Ni plating, which is relatively hard and inexpensive, extends from the lower side to the upper side. It is preferable to set the thickness.
  • a plating layer having a good bonding property is formed on the outermost surface as much as necessary.
  • FIG. 6E is a diagram showing an example of a resist stripping process.
  • the cured resist mask 35 and resist layer 30 are stripped. Thereby, the die pad part 21 and the lead part 22 made of the plating layer 20 are formed.
  • the semiconductor element mounting substrate 50 according to the embodiment of the present invention is obtained by cutting the conductive substrate 10 on which the die pad portion 21 and the lead portion 22 are formed into desired dimensions as necessary.
  • the semiconductor element mounting substrate 50 according to the embodiment of the present invention is manufactured by sequentially performing the above-described steps.
  • FIG. 7 is a diagram showing a series of steps in an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • FIG. 7A is a diagram showing an example of a semiconductor element mounting process.
  • the semiconductor element 60 is mounted on the die pad portion 21 of the semiconductor element mounting substrate 50.
  • the semiconductor element 60 may be bonded and fixed on the die pad portion 21 using, for example, a silver paste or an adhesive.
  • FIG. 7B is a diagram showing an example of the wire bonding process.
  • the wire 61 is formed by electrically connecting the electrode 61 of the semiconductor element 60 and the lead portion 22 using the bonding wire 70 by wire bonding.
  • FIG. 7C is a diagram showing an example of the resin sealing process.
  • the entire surface on which the semiconductor element 60 of the semiconductor element mounting substrate 50 is mounted is sealed with the resin 80.
  • FIG. 7D is a diagram showing an example of the conductive substrate removing process.
  • the conductive substrate removal step the conductive substrate 10 is removed from the resin-encapsulated portion.
  • the conductive substrate 10 is dissolved and removed using a solution.
  • FIG. 7E shows an example of the cutting process. Finally, the semiconductor device 100 is completed by cutting to a predetermined size of the semiconductor device 100.
  • optical semiconductor device mounting substrate and optical semiconductor device The present invention can be applied not only to a semiconductor device but also to an optical semiconductor device. Hereinafter, description will be made with reference to FIGS.
  • FIG. 8 is a cross-sectional view showing an example of an optical semiconductor element mounting substrate according to an embodiment of the present invention.
  • the configuration of the optical semiconductor element mounting substrate 51 is the same as that of the semiconductor element mounting substrate 50.
  • the die pad portion 21 and the lead portion 22 are formed in pairs, and a plurality of them are arranged as a set.
  • the conductive substrate 10 is a substrate on which the plating layer 20 is formed on the surface 11, and is made of a conductive material so that the plating layer 20 can be formed by electroplating.
  • the material of the conductive substrate 10 to be used is not particularly limited as long as conductivity is obtained, but a metal material is generally used, for example, Cu or Cu alloy.
  • the die pad portion 21 and the lead portion 22 are a plating layer 20 formed by plating on one side (surface 11) of the conductive substrate 10.
  • the features of the optical semiconductor element mounting substrate 51 according to the embodiment of the present invention of the die pad portion 21 and the lead portion 22 are the same as those of the semiconductor element mounting substrate 50.
  • FIG. 9 is a cross-sectional view of an example of the optical semiconductor device 101 according to the embodiment of the present invention.
  • an optical semiconductor element 62 is mounted on the die pad portion 21, and the electrode 63 and the lead portion 22 of the optical semiconductor element 62 are bonded to the bonding wire 70 and the like. Connected through.
  • an external resin 81 is formed on the die pad portion 21 and the lead portion 22 so as to surround a peripheral portion including connection portions such as the optical semiconductor element 62 and the bonding wire 70. Further, the external resin 81 is simultaneously filled in the space between the die pad portion 21 and the lead portion 22 facing each other.
  • the optical semiconductor element 62 surrounded by the external resin 81 and the periphery of the electrical connection portion are filled with a transparent resin 90.
  • the conductive substrate 10 existing in FIG. 8 does not exist.
  • the conductive substrate 10 is removed after sealing with the external resin 81 and the transparent resin 90. That is, in the optical semiconductor element mounting substrate 51 shown in FIG. 8, first, after sealing the external resin 81, the optical semiconductor element 62 is mounted on the die pad part 21, and the electrode 63 and the lead part 22 of the semiconductor element 62 are mounted. Are connected via a bonding wire 70 by wire bonding. Thereafter, the peripheral portion including the connecting portion such as the optical semiconductor element 62 and the bonding wire 70 opened in the external resin 81 is sealed with the transparent resin 90.
  • the conductive substrate 10 is removed, whereby an optical semiconductor device 101 as shown in FIG. 9 is manufactured.
  • the die pad portion 21 and the bottom surface 25 of the lead portion 22 exposed by removing the conductive substrate 10 serve as external terminals for soldering with external devices.
  • the die pad portion 21 and the lead portion 22 are arranged in pairs. Since the shape of the optical semiconductor device 101 is small, the adhesion between the external resin 81 and the die pad portion 21 and the lead portion 22 is important. Like the die pad portion 21 and the lead portion 22 of the optical semiconductor device 101 according to the embodiment of the present invention, the adhesiveness with the external resin 81 can be improved by having a tapered shape on the upper side.
  • the lead part 22 is replaced with the lead part 26, the unevenness is formed on each side of the outer shape of the die pad part 21 and the lead part 26, and the side surface of the lead part 26 is the upper stage part. 26a and the lower part 26b.
  • the side surface 27b of the lower step portion 26b has a linear portion in the vertical direction
  • the side surface 27a of the upper step portion 26a has a tapered shape in which the upper portion extends along the periphery of the lead portion.
  • a part of the side surface 27 may have a horizontal portion 26e at the boundary between the upper step portion 26a and the lower step portion 26b (the bottom surface 26d of the upper step portion 26a).
  • the portion having the horizontal portion 26e on a part of the bottom surface 26d of the upper step portion 26a can be formed in the concave portion 27c in which an uneven shape is added to each side of the bottom surface shape of the lower end portion 26b of the lead portion 26 described above.
  • the concave portion 27c By forming the concave portion 27c, the lower surface of the concave portion 27c can be filled with the external resin 81, and the adhesion with the external resin 81 can be further improved. Thereby, the optical semiconductor device 101 can be further reduced in size and thickness.
  • the manufacturing method of the optical semiconductor element mounting substrate 51 is the same as the manufacturing method of the semiconductor element mounting substrate 50.
  • a noble metal with high reflectivity is used to efficiently reflect light from the light emitting element (optical semiconductor element).
  • Plating is applied to the outermost layer.
  • the outermost plating layer is preferably Ag or Ag alloy plating from the viewpoint of light reflectance. For example, on the surface of the conductive substrate 10, five-layer plating in which an Au plating layer, a Pd plating layer, a Ni plating layer, an Au plating layer, and an Ag plating layer are sequentially stacked can be performed.
  • the above-described optical semiconductor element mounting substrate 51 is used and the external resin 81 is resin-sealed.
  • the external resin 81 is filled on the die pad portion 21 and the lead portion 22 so as to surround the peripheral portion including the connecting portion such as the optical semiconductor element 62 and the bonding wire 70. Further, the external resin 81 is simultaneously filled in the space portion between the die pad portion 21 and the lead portion 22 facing each other.
  • the optical semiconductor element 62 is mounted on the die pad portion 21, and the electrode 63 of the optical semiconductor element 62 and the lead portion 22 are connected via the bonding wire 70 by wire bonding.
  • a peripheral portion including a connection portion such as the optical semiconductor element 62 and the bonding wire 70 provided in a predetermined central region opened in the external resin 81 is sealed with a transparent resin 90.
  • the conductive substrate 10 is removed. Finally, cut to a predetermined size. Thereby, the optical semiconductor device 101 is manufactured.
  • Example 1 A SUS plate (SUS430) having a thickness of 0.2 mm is processed into a long plate shape having a width of 140 mm as the conductive base material 10, and then a 0.015 mm thick photosensitive dry film resist (Asahi Kasei Corporation) is formed on the surface of the conductive substrate 10. ADH manufactured by Materials Co., Ltd. was attached using a laminate roll.
  • a photosensitive dry film resist having a thickness of 0.05 mm (AQ manufactured by Asahi Kasei E-Materials Co., Ltd.) and a photosensitive dry film resist having a thickness of 0.025 mm (ADH manufactured by Asahi Kasei E-Materials Co., Ltd.) were sequentially pasted thereon.
  • a 0.040 mm thick photosensitive dry film resist (AQ manufactured by Asahi Kasei E-Materials Co., Ltd.) was attached to the back surface with a laminate roll.
  • a glass mask on which a pattern is formed is formed on the front surface side so as to form a desired pattern of the lead part 22 for connecting to the semiconductor device mounting die pad portion 21 and the outside, and a pattern covering the entire back surface on the back surface side. It was covered with a dry film resist and exposed to ultraviolet light. The exposure on the surface side was performed at a wavelength at which the first resist layer 31 and the third resist layer 33 were exposed and the second resist layer 32 was not exposed. For this reason, the dry film with a thickness of 0.05 mm, which is the second resist layer 32 on the surface side, was in an unexposed state. The back side exposure was performed at a wavelength at which the back side resist was exposed.
  • the bottom face shape of the lead part 22 and the die pad part 21 was rectangular, and the corner part was R-shaped (rounded shape).
  • the taper angle of the second resist layer 32 was set to about 45 ° by appropriately adjusting the development time, the discharge pressure of the developer, and the like. Thereafter, the second resist layer was cured by exposure.
  • electroplating was performed on the exposed portion surface of the conductive substrate 10 from which the resist layer was removed and the opening 34 was formed.
  • the die pad portion 21 and the lead portion 22 about 0.02 ⁇ m of Au plating, 0.02 ⁇ m of Pd plating, 40 ⁇ m of Ni plating, and 0.05 ⁇ m of Pd plating were sequentially performed.
  • the thickness of the plating layer was set with 2/3 of the second resist layer 32 as a guide.
  • the dry film resists 30 to 33 were peeled off with a sodium hydroxide solution to form the die pad portion 21 and the lead portion 22 on the conductive substrate 10.
  • the substrate 50 for mounting a semiconductor element according to Example 1 of the present invention was obtained by cutting into predetermined dimensions.
  • the semiconductor element 60 was mounted on the manufactured semiconductor element mounting substrate 50, the semiconductor element 60 and the lead portion 22 were connected by wire bonding 70, and the surface on which the semiconductor element 60 was mounted was sealed with a resin 80. Thereafter, the conductive substrate 10 was peeled off and removed from the resin-encapsulated portion. Finally, the semiconductor device 100 was cut to a predetermined size of the semiconductor device 100 to complete the semiconductor device 100 according to Example 1.
  • Example 2 In Example 2, the pattern was added with zigzag (or corrugated) uneven shapes on the rectangular sides of the lead part 26 and the die pad part 21 in Example 1. In addition, each vertex of the zigzag has an R shape. The length of the recess 27c was 0.03 mm. In the development process, a horizontal portion is provided at the boundary between the upper step portion 26a and the lower step portion 26b (the bottom surface of the upper step portion 26a) corresponding to the recess 27c by appropriately adjusting the developing time, the discharge pressure of the developer, and the like. . The development time was longer than that in Example 1. Other conditions are the same as in the first embodiment.
  • FIG. 10 is an enlarged view from the upper surface of the lead portion 26 of the semiconductor element mounting substrate 51 according to the second embodiment, and is an enlarged view of a part of the side surface of the lead portion.
  • an upper step portion 26a having a corrugated side surface is provided on the upper surface of a columnar lower step portion 26b having a corrugated side surface, and the side surface of the upper step portion 26a projects sideways and upward. It turns out that it forms in the taper shape. With this configuration, the upper portion 26a can be easily caught on the resin 80, the adhesion between the resin 80 and the lead portion 26 can be improved, and the lead portion 26 can be prevented from falling off and peeling off.
  • FIG. 11 is an enlarged view from the back surface of the lead portion 26 of the semiconductor element mounting substrate 51 according to the second embodiment, and is an enlarged view of a part of the side surface on the back surface side of the lead portion. That is, the lead part 26 is peeled from the conductive substrate 10 and only the lead part 26 is shown from the back side.
  • the bottom surface 26d of the upper step portion 26a provided on the upper surface of the columnar lower step portion 26b (downward in FIG. 11) includes the upper surface of the lower step portion 26b, and is flat in the corrugated recess.
  • a surface (horizontal plane) 26e is formed.
  • the resin 80 By providing the flat surface 26e on the bottom surface 26d of the upper end portion 26a, the resin 80 can be easily caught, and the adhesion between the resin 80 and the lead portion 26 is greatly improved. Further, the side surface 27a of the upper step portion 26a is also tapered, so that the adhesion between the resin 80 and the lead portion 26 can be improved.
  • Example 3 is an example in which an optical semiconductor element mounting substrate 51 was produced.
  • the pattern in Example 1 was set to a shape in which the die pad part 21 and the lead part 22 for the optical semiconductor device 101 were paired.
  • the plating layer 20 1 ⁇ m of Ag plating was added to the outermost layer of the plating layer of Example 1. Others are the same as the first embodiment.
  • the die pad is formed so as to surround the peripheral portion including the connection portion such as the optical semiconductor element 62 and the bonding wire 70 using the optical semiconductor element mounting substrate 51 manufactured above.
  • An external resin 81 was formed on the outer surfaces of the part 21 and the lead part 22.
  • an external resin 81 was also formed at the same time in the space where the die pad portion 21 and the lead portion 22 face each other. Then, the optical semiconductor element 62 was mounted on the die pad part 21, and the electrode 63 of the optical semiconductor element 62 and the lead part 22 were connected via the bonding wire 70 by wire bonding.
  • the peripheral portion (predetermined central region) including the connection portion such as the optical semiconductor element 62 and the bonding wire 70 opened in the external resin 81 was sealed with the transparent resin 90. After resin sealing, the conductive substrate 10 was removed. Finally, it was cut into predetermined dimensions. Thus, the optical semiconductor device 101 was completed.
  • Comparative Example 1 In Comparative Example 1, a 0.025 mm thick photosensitive dry film resist (AQ-4096 manufactured by Asahi Kasei E-Materials Co., Ltd.) was laminated on both sides of the conductive substrate in the resist coating step, and exposure development was performed. In the plating step, a plating layer was formed beyond the resist layer. Other conditions are the same as in the first embodiment.
  • Comparative Example 2 In Comparative Example 2, a photosensitive dry film resist (AQ-4096 manufactured by Asahi Kasei E-Materials Co., Ltd.) having a thickness of 0.05 mm was attached to the surface of the conductive substrate in the resist coating step. A 0.025 mm thick photosensitive dry film resist (AQ-4096 manufactured by Asahi Kasei E-Materials Co., Ltd.) was attached to the back surface with a laminate roll, and exposure was performed using scattered ultraviolet light in the exposure process. Thereafter, development was performed. By exposing with scattered ultraviolet light, the resist layer is in a semi-exposed state, and a tapered resist is formed. In the plating step, the opening portion of the formed tapered resist mask was plated to produce a reverse trapezoidal lead portion. Other conditions are the same as those in the first embodiment.
  • Example 1 Example 2, Example 3, Comparative Example 1, and Comparative Example 2 were evaluated by the following methods.
  • the shape of the bottom surface of the lead part was measured for 20 leads, and the variation was confirmed.
  • Example 1 In Example 1 and Comparative Example 1, the set value was within ⁇ 0.003 mm, and in Examples 2 and 3, the set value was ⁇ 0.004 mm, but in Comparative Example 2, the set value ⁇ 0.01 mm. And the variation was large.
  • Example 1 After mounting the semiconductor element using this semiconductor element mounting substrate and sealing with resin, the conductive substrate was peeled off, and it was observed whether there was a defect that the lead portion remained on the conductive substrate.
  • Example 2 Example 3, Comparative Example 1, and Comparative Example 2
  • Example 2 and Example 3 it was confirmed that sufficient adhesion with the sealing resin was secured.

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Led Device Packages (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
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PCT/JP2017/005832 2016-02-25 2017-02-17 半導体素子搭載用基板、半導体装置及び光半導体装置、並びにそれらの製造方法 WO2017145923A1 (ja)

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US10906304B2 (en) 2018-06-29 2021-02-02 Canon Kabushiki Kaisha Semiconductor element, recording element substrate, and liquid discharge head
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