WO2017145923A1 - Substrate for mounting semiconductor element, semiconductor device and optical semiconductor device, and method for manufacturing same - Google Patents

Substrate for mounting semiconductor element, semiconductor device and optical semiconductor device, and method for manufacturing same Download PDF

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Publication number
WO2017145923A1
WO2017145923A1 PCT/JP2017/005832 JP2017005832W WO2017145923A1 WO 2017145923 A1 WO2017145923 A1 WO 2017145923A1 JP 2017005832 W JP2017005832 W JP 2017005832W WO 2017145923 A1 WO2017145923 A1 WO 2017145923A1
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WIPO (PCT)
Prior art keywords
semiconductor element
lead portion
lead
die pad
resist
Prior art date
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PCT/JP2017/005832
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French (fr)
Japanese (ja)
Inventor
博幸 有馬
Original Assignee
Ｓｈマテリアル株式会社
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Publication date
Application filed by Ｓｈマテリアル株式会社 filed Critical Ｓｈマテリアル株式会社
Priority to CN201780012202.XA priority Critical patent/CN108701658B/en
Priority to MYPI2018001471A priority patent/MY188860A/en
Publication of WO2017145923A1 publication Critical patent/WO2017145923A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/85005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a semiconductor element mounting substrate, a semiconductor device, an optical semiconductor device, and a manufacturing method thereof.
  • a resist mask subjected to predetermined patterning is formed on one surface side of a conductive substrate. After plating metal on the conductive substrate exposed from the resist mask to form a die pad part for mounting a semiconductor element, and an internal terminal connected to the semiconductor element and a lead part functioning as an external terminal connected to an external device Then, by removing the resist mask, a semiconductor element mounting substrate is formed. The semiconductor element is mounted on the formed semiconductor element mounting substrate, and after wire bonding, resin sealing is performed, the conductive substrate is removed, the die pad portion and the lead portion are exposed, and the semiconductor device is completed (for example, (See Patent Documents 1 and 2).
  • Patent Document 1 discloses a semiconductor having a metal layer for mounting a semiconductor element and a protruding portion at the periphery of the upper end of an electrode layer for external connection by electrodepositing a conductive metal beyond the formed resist mask. A method for obtaining an element mounting substrate is described. As a result, the protruding portion of the metal layer and the electrode layer bites into the resin at the time of resin sealing, and can be reliably left on the resin side.
  • Patent Document 2 describes a method of forming a metal layer or an electrode layer in an inverted trapezoidal shape by forming a resist mask into a trapezoid using scattered ultraviolet light when forming a resist mask. Yes.
  • the cross-sectional shape of the electrode layer is inverted trapezoidal, when the semiconductor element is mounted and resin-sealed after wire bonding, the side surface of the electrode layer becomes an acute angle with respect to the conductive substrate, and the sealing resin Became difficult to wrap around. For this reason, unfilling of sealing resin such as voids may occur in some cases.
  • the sealing resin near the electrode layer base is naturally formed following this angle, so that the tip has an acute shape and is weak in strength, and the tip of the sealing resin portion is likely to be chipped or peeled off. There was a problem.
  • the resist layer is in a semi-exposure state and forms a tapered shape.
  • the dimensional accuracy of the bottom surface was prepared by exposing and developing the resist using parallel light.
  • the variation is larger than the dimensional accuracy and the dimensional accuracy is inferior.
  • the lead shape tends to become smaller due to the miniaturization and thinning of the semiconductor device, it is important to improve the dimensional accuracy of the bottom surface. With the configuration described in Patent Document 2, it is difficult to sufficiently meet this requirement. there were.
  • the present invention provides a semiconductor device completed by mounting a semiconductor element and then resin-sealing and removing the conductive substrate, and the degree of adhesion between the sealing resin and the lead portion is appropriate.
  • a semiconductor element mounting substrate includes a conductive substrate that can be removed after mounting a semiconductor element; A semiconductor element mounting region provided on the surface of the conductive substrate; A lead portion made of a plating layer provided in a predetermined region on the surface of the conductive substrate around the semiconductor element mounting region; The lead portion has a side surface substantially perpendicular to the surface of the conductive substrate, and a lower step portion extending upward in a column shape from the surface; And an upper step portion having a bottom surface on the upper surface of the lower step portion and a side surface extending upward and sideward in a tapered manner from the bottom surface.
  • a semiconductor device includes a semiconductor element, A lead portion made of a plating layer provided in a predetermined region around the semiconductor element and having an upper step portion and a lower step portion having different shapes; Connection means for electrically connecting the electrode of the semiconductor element and the upper surface of the upper portion of the lead portion; A resin that seals the semiconductor element, the lead portion, and the connecting means so that at least a bottom surface of the lower step portion of the lead portion is exposed;
  • the lower step portion of the lead portion has a columnar shape having a side surface extending vertically upward from the bottom surface,
  • the upper step portion of the lead portion has a bottom surface on the upper surface of the lower step portion, and has a tapered shape in which a side surface is tapered upward and laterally from the bottom surface.
  • An optical semiconductor device includes a die pad portion having a region for mounting an optical semiconductor element; A lead portion comprising a plating layer provided in a pair with the die pad portion and having an upper step portion and a lower step portion having different shapes; An optical semiconductor element mounted on the die pad portion; Connection means for electrically connecting the electrode of the optical semiconductor element and the upper surface of the upper portion of the lead portion; A transparent resin that seals a predetermined central region on the die pad portion and the lead portion including the optical semiconductor element and the connection means; A region between the die pad portion and the lead portion other than the bottom surface of the die pad portion and the lead portion, and predetermined areas of the die pad portion and the lead portion so that the bottom surfaces of the die pad portion and the lead portion are exposed.
  • the lower step portion of the lead portion has a columnar shape having a side surface extending vertically upward from the bottom surface, and the upper step portion of the lead portion has a bottom surface on the upper surface of the lower step portion. It has a tapered shape in which the side surface is widened upward and laterally.
  • a method for manufacturing a semiconductor element mounting substrate comprising: a first resist layer coated with a first resist having a first photosensitive wavelength on a surface of a conductive substrate; A step of sequentially forming a second resist layer coated with a second resist having a second photosensitive wavelength on the resist layer, and a third resist layer coated with the first resist on the second resist layer.
  • the first and third resist layers are cured, and development is performed in a state where the second resist layer is not cured, and the upper portion of the second resist layer is the first and third resist layers.
  • the present invention it is possible to prevent the lead portion from dropping and peeling when the conductive substrate is removed, and to improve the dimensional accuracy of the bottom surface of the lead portion.
  • FIG. 3A is a plan view showing an example of the lead portion.
  • FIG. 3B is an xx cross-sectional view of the lead portion shown in FIG. It is a figure for demonstrating the formation method of a lead part.
  • FIG. 4A shows an example of a resist mask for plating.
  • FIG. 4B is a diagram showing an example of plating using a plating resist mask. It is a figure for demonstrating the lead part which has a shape different from FIG. FIG.
  • FIG. 5A is a plan view showing an example of a lead portion having a shape different from that in FIG.
  • FIG. 5B is a cross-sectional view of the lead portion yy shown in FIG.
  • FIG. 5C is a zz cross-sectional view of the lead portion shown in FIG. It is the figure which showed a series of processes of an example of the manufacturing method of the board
  • FIG. 6A is a diagram illustrating an example of a substrate preparation process.
  • FIG. 6B is a diagram showing an example of a resist coating process.
  • FIG. 6C is a diagram showing an example of a resist mask forming process.
  • FIG. 6D is a diagram showing an example of the plating process.
  • FIG. 6A is a diagram illustrating an example of a substrate preparation process.
  • FIG. 6B is a diagram showing an example of a resist coating process.
  • FIG. 6C is a diagram showing an example of a resist mask forming
  • FIG. 6E is a diagram illustrating an example of a resist stripping process. It is the figure which showed a series of processes of an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention.
  • FIG. 7A is a diagram showing an example of a semiconductor element mounting process.
  • FIG. 7B is a diagram illustrating an example of a wire bonding process.
  • FIG. 7C is a diagram showing an example of the resin sealing process.
  • FIG. 7D is a diagram showing an example of the conductive substrate removing process.
  • FIG. 7E shows an example of the cutting process. It is sectional drawing which shows an example of the board
  • 10 is an enlarged view from the top surface of the lead portion of the semiconductor element mounting substrate according to the second embodiment, and is a partial enlarged view of a side surface of the lead portion. It is an enlarged view from the back surface of the lead part of the semiconductor element mounting substrate according to Example 2, and is an enlarged view of a part of the side surface on the back surface side of the lead part.
  • FIG. 1 is a cross-sectional view showing an example of a semiconductor element mounting substrate according to an embodiment of the present invention.
  • the semiconductor element mounting substrate 50 according to the present embodiment includes a conductive substrate 10, a semiconductor element mounting die pad portion 21 disposed on the surface 11, and a lead portion 22 for connecting to an external device. Has been.
  • the lead portion 22 is disposed around the die pad portion 21 that is a semiconductor element mounting region.
  • the die pad portion 21 is not manufactured after the semiconductor element mounting area is secured.
  • a semiconductor element is directly mounted on the conductive substrate 10 or a flip chip connection type in which an electrode of the semiconductor element is directly bonded to a lead portion. That is, in the present embodiment, it is not essential to provide the die pad portion 21, and it is only necessary to secure a semiconductor element mounting region in which a semiconductor element can be mounted.
  • the die pad portion 21 is provided as the semiconductor element mounting region will be described.
  • the die pad portion 21 and the lead portion 22 may be configured by the same plating layer 20.
  • symbol overlaps with the die pad part 21 and the lead part 22, and the plating layer 20, when it demonstrates from a viewpoint of the component of the board
  • the conductive substrate 10 is a substrate on which the plating layer 20 is formed on the surface 11, and is made of a conductive material so that the plating layer 20 can be formed by electroplating.
  • the material of the conductive substrate 10 to be used is not particularly limited as long as conductivity is obtained, but a metal material is generally used, for example, Cu or Cu alloy. When the conductive substrate is peeled off and removed, a SUS material may be used.
  • the die pad part 21 and the lead part 22 are constituted by a plating layer 20 formed on one surface (front surface 11) of the conductive substrate 10 by plating.
  • the semiconductor element mounting substrate 50 according to the embodiment of the present invention is characterized by the shape of the lead portion 22.
  • the lead portion 22 includes a columnar lower step portion 22b and a tapered upper step portion 22a.
  • the die pad portion 21 may have a columnar lower step portion 21b and a tapered upper step portion 21a. Details of the configurations of the die pad portion 21 and the lead portion 22 will be described later.
  • FIG. 2 is a cross-sectional view of an example of the semiconductor device 100 according to the embodiment of the present invention.
  • the semiconductor element 60 is mounted on the die pad portion 21, and the electrode 61 of the semiconductor element 60 and the lead portion 22 are connected via a bonding wire 70 or the like.
  • the whole including the connection means such as the semiconductor element 60 and the bonding wire 70 is sealed with the resin 80.
  • the die pad portion 21 and the lead portion 22 have the upper surface 23 and the side surface 24 covered with the resin 80, but the bottom surface 25 is exposed.
  • the conductive substrate 10 existing in FIG. 1 does not exist. The conductive substrate 10 is removed after sealing with the resin 80. That is, the semiconductor element 60 is mounted on the die pad portion 21 of the semiconductor element mounting substrate 50 shown in FIG.
  • the electrode 61 and the lead portion 22 of the semiconductor element 60 are connected via the bonding wire 70 by wire bonding. Thereafter, sealing is performed with a resin 80 on the semiconductor element mounting substrate 50. After the resin sealing, the conductive substrate 10 is removed, whereby the semiconductor device 100 as shown in FIG. 2 is manufactured. The bottom surface 25 of the lead portion 22 exposed by removing the conductive substrate 10 serves as an external terminal for soldering with an external device.
  • FIG. 3 is a view showing an example of the lead portion 22 of the semiconductor element mounting substrate 100 according to the embodiment of the present invention.
  • FIG. 3A is a plan view showing an example of the lead portion 22.
  • FIG. 3B is an xx cross-sectional view of the lead portion 22 shown in FIG.
  • the first feature of the semiconductor element mounting substrate 50 is the cross-sectional shape of the lead portion 22.
  • the lead portion 22 includes an upper step portion 22a and a lower step portion 22b having different shapes.
  • the cross section of the lower step portion 22b has a shape having a straight line portion in the vertical direction.
  • the cross section of the upper step portion 22a has a tapered shape in which the upper portion extends along the periphery of the lead portion.
  • the lower step portion 22b has a columnar shape extending upward from the surface 11 of the conductive substrate 10 perpendicularly to the surface 11.
  • the lower step portion 22b has a substantially rectangular planar shape or horizontal cross-sectional shape, and has a substantially quadrangular prism shape. Since the side surface 24b of the lower step portion 22b extends along the vertical direction, the planar shape and the horizontal cross-sectional shape of the lower step portion 22b are the same in all cases of cutting at the bottom surface, the upper surface, or between the bottom surface and the upper surface. is there.
  • the lower step portion 22b has a columnar shape with a constant planar shape and horizontal cross-sectional shape.
  • the upper step portion 22a is provided continuously and integrally with the lower step portion 22b on the upper surface of the lower step portion 22b. That is, the bottom surface (lower surface) of the upper step portion 22a is provided on the same horizontal plane as the upper surface of the lower step portion 22b.
  • the bottom surface of the upper step portion 22a is not necessarily congruent with the upper surface of the lower step portion 22b.
  • the bottom surface of the upper step portion 22a is formed wider than the lower step portion 22b, and the bottom surface of the upper step portion 22a is the lower step portion 22b. It may be formed so as to include the upper surface.
  • the bottom surface of the upper step portion 22a has substantially the same shape as the upper surface of the lower step portion 22b, and has a rectangular shape with rounded corners.
  • the side surface 24a of the upper step portion 22a has a shape that extends upward and laterally in a tapered shape from the bottom surface.
  • the upper surface of the upper step portion 22a has a shape similar to that of the lower step portion 22b, and is formed in a substantially rectangular shape.
  • the side surface 24a is generally tapered from the bottom surface of the upper step portion 22a and spreads at substantially the same ratio, and the planar shape of the upper surface of the upper step portion 22a is larger than the upper surface of the lower step portion 22b. Means.
  • the resin 80 can bite and get caught, and when the conductive substrate 10 is peeled off from the resin 80, the lead portion 22 can be separated from the resin 80. Dropping off can be prevented.
  • the die pad portion 21 may have an upper step portion 21 a and a lower step portion 21 b. Thereby, the die pad part 21 can also be prevented from falling off from the resin 80.
  • FIG. 4 is a view for explaining a method of forming the lead portion 22.
  • FIG. 4A shows an example of the resist mask 35 for plating.
  • FIG. 4B is a diagram showing an example of plating using the resist mask 35 for plating.
  • the lead portion 22 covers three resist layers 31, 32, 33 on the conductive substrate 10, and is exposed and developed to produce a resist mask 35 for plating. This is used for plating.
  • the resist layer in contact with the conductive substrate 10 is used as the first resist layer 31, and the uppermost resist is used as the third resist layer 33.
  • the intermediate resist layer becomes the second resist layer 32.
  • the pattern of the first resist layer 31 and the third resist layer 33 is a bottom shape pattern of the lead portion 22.
  • the first resist layer 31 and the third resist layer 33 are made of the same type of resist having the same photosensitive wavelength
  • the second resist layer 32 is made of the first and third resist layers 31. , 33 and resists having different wavelengths for exposure are used.
  • the resist layers 31 to 33 When the resist layers 31 to 33 are exposed, the first and third resist layers 31 and 33 are exposed to light, and the second resist layer 32 is exposed at a wavelength that is not exposed to light.
  • the resist layers 31 and 33 are cured, and the second resist layer 32 is brought into an unexposed state.
  • the first resist layer 31 and the third resist layer 33 are substantially the same as the bottom shape of the lead portion 22, and the vertical side (side surface 24b) of the vertical cross section becomes a straight line.
  • the second resist layer 32 Since the second resist layer 32 is developed in the direction of the first resist 31 from the opening 34 of the third resist layer 33, as shown in FIG.
  • the sides are tapered so that the upper surface side is narrower (the shape of the opening 34 is wider on the upper surface side).
  • the second resist layer 32 is in an unexposed state and is subjected to a curing process by exposure after development. In this manner, a plating resist mask 35 in which the second resist layer 32 has a tapered shape is produced.
  • the plating layer 20 is formed using the prepared resist mask 35 for plating.
  • the thickness of the plating layer 20 is set so that the upper surface of the plating layer 20 is between the second resist layers 32 before reaching the third resist layer 33.
  • the plating layer 20 is plated up to the third resist layer 33, the tapered shape of the third resist layer 33 becomes small even though the second resist layer 32 forms a tapered shape whose upper surface side is widened.
  • the plating thickness is set so that the upper surface of the plating layer 20 is between 1/2 and 4/5 of the second resist layer 32.
  • the taper shape of the second resist layer 32 can be adjusted by the thickness of the second resist layer 32, the developing time in the developing process, the discharge pressure of the developer, and the like.
  • the taper angle can be arbitrarily set on the basis of the horizontal direction. However, in consideration of the adhesiveness with the resin 80, it is preferably set to 30 ° to 80 °, and preferably set to 30 ° to 60 °. More preferred.
  • the lead portion 22 is formed by using the above-described three-layer resist mask 35 and plating the opening 34 of the resist mask 35 to form the plating layer 20. Since the plating layer 20 is formed following the shape of the resist mask 35, the side surface of the plating layer 20 is divided into an upper step portion 20a (second resist layer portion) and a lower step portion 20b (first resist layer portion). The side surface of the lower step portion 20 b has a linear portion in the vertical direction, and the side surface of the upper step portion 20 a has a tapered shape in which the upper portion extends along the periphery of the plating layer 20.
  • the thickness of the lower step portion 20 b of the plating layer 20 of the lead portion 22 is the thickness of the first resist layer 31.
  • the thickness of the lower step portion 20b of the plating layer 20 is not particularly limited, but is preferably 10 ⁇ m to 25 ⁇ m in consideration of the thickness of the first resist layer 31.
  • the thickness of the upper step portion 20a is not particularly limited, but as described above, the plating layer 20 preferably has a thickness of 2/5 to 4/5 of the second resist layer 32, or this taper. It is preferable to set the thickness to 20 ⁇ m to 50 ⁇ m because the portion improves the adhesion to the resin 80.
  • the cross-sectional shape of the lead portion 22 is divided into an upper step portion 22a (second resist layer portion) and a lower step portion 22b (first resist layer portion).
  • the side surface 24b of the lower step portion 22b has a straight portion in the vertical direction, and the side surface 24a of the upper step portion 22a can form a lead portion 22 having a tapered shape in which the upper portion extends along the periphery of the plating layer.
  • Patent Document 1 describes a shape having a protruding portion on the periphery of the upper end portion of the lead portion by electrodepositing a conductive metal beyond the formed resist mask. In this method, it is difficult to control the amount of overhang, and there is a problem that not all of the plating layers to be formed have the same overhang length or a problem that the overhang portion is connected to the adjacent plating layer.
  • the lead portion 22 is divided into an upper step portion 22a and a lower step portion 22b, and the upper step portion 22a is tapered. Since the taper shape of the upper step portion 22a is formed by the second resist layer 32, the shape can be controlled, and the thickness, length, and taper angle of the overhang portion can be arbitrarily set. In addition, the upper surface of the upper step portion 22a that functions as an internal terminal can obtain a substantially flat surface. Moreover, in the shape of patent document 1, when the overhang
  • Patent Document 2 describes that the cross-sectional shape of the lead portion is tapered.
  • the cross-sectional shape of the lead portion is an inverted trapezoid
  • the side surface portion of the electrode layer has an acute angle with respect to the conductive substrate when the semiconductor element is mounted and resin-sealed after wire bonding.
  • the sealing resin near the base of the lead portion is naturally formed following this angle, so that the tip has an acute shape and is weak in strength, and the tip of the sealing resin portion is likely to be chipped or peeled off. There was a problem.
  • the resist layer has a tapered shape, the dimensional accuracy of the bottom surface was inferior.
  • the lead portion 22 is divided into an upper step portion 22a and a lower step portion 22b, and the side surface of the lower step portion 22b has a straight portion in the vertical direction. Therefore, the bottom surface of the lead portion 22 does not become an acute angle with the conductive substrate 10. Thereby, generation
  • FIG. 5 is a view for explaining a lead portion 26 having a shape different from that in FIG.
  • FIG. 5A is a plan view showing an example of the lead portion 26.
  • FIG. 5B is a yy sectional view of the lead portion 26 shown in FIG.
  • FIG. 5C is a zz sectional view of the lead portion 26 shown in FIG.
  • the bottom shape of the lead portion is generally a substantially rectangular shape as shown in FIG.
  • an uneven shape may be added to each side constituting the side surface 27 of the lead portion 26.
  • the uneven shape includes, for example, a wavy shape, a zigzag shape in which a chevron shape is continuous, a saw shape, and the like.
  • Each vertex of the zigzag shape is a rounded curved shape.
  • the bottom surface 26d and the top surface 26c of the upper step portion 26a have a substantially rectangular bottom surface 26d, and the top surface 26c has an uneven shape.
  • the bottom surface 26d of the upper step portion 26a has a rectangular shape including the uneven shape of the upper surface of the lower step portion 26b.
  • the lead portion 26 is divided into an upper step portion 26a and a lower step portion 26b, and a side surface 27b of the lower step portion 26b is in a vertical direction.
  • the side surface 27a of the upper step portion 26a has a tapered shape having an upper portion extending along the periphery of the lead portion.
  • a part of the bottom surface 26d of the upper step portion 26a may have a horizontal portion 26e at the boundary between the upper step portion 26a and the lower step portion 26b.
  • a portion having a horizontal portion 26e at a part of the bottom surface 26d (the boundary between the upper step portion and the lower step portion) of the upper step portion 26a is formed in a recess portion 27c when an uneven shape is added to each side of the bottom shape of the lead portion 26 described above. can do.
  • the recess 27c By forming the recess 27c, the lower surface of the recess 27c can be filled with the resin 80, and the adhesion with the resin 80 can be further improved.
  • the concave amount of the concave portion of the concave / convex portion is about 1/2 times the thickness of the lower step portion 26b to three times the thickness of the lower step portion 26b. Is preferred. If the thickness of the lower step portion 26b is less than 1 ⁇ 2, the effect of adhesion is small, and if it exceeds three times, the possibility that a resist residue will occur when the first resist layer 31 is peeled off is increased. Preferably, it is about the thickness of the lower step part 26b. Since the horizontal portion 26e has a flat surface, it may be called the flat surface 26e.
  • the semiconductor device 100 has the resin pad 80, the die pad portion 21, the lead portions 22, 26, and the like by forming the die pad portion 21 and the lead portions 22, 26 as described above.
  • the resin pad 80 the die pad portion 21, the lead portions 22, 26, and the like by forming the die pad portion 21 and the lead portions 22, 26 as described above.
  • FIG. 6 is a diagram showing a series of steps of an example of a method for manufacturing a semiconductor element mounting substrate according to an embodiment of the present invention.
  • FIG. 6A is a diagram showing an example of the substrate preparation process.
  • the conductive substrate 10 is prepared.
  • the material of the conductive substrate 10 to be used is not particularly limited as long as conductivity can be obtained.
  • a metal material is used, and for example, a SUS material or Cu or Cu alloy is used.
  • FIG. 6B is a diagram showing an example of a resist coating process.
  • the entire front and back surfaces of the conductive substrate 10 are covered with a resist.
  • the surface side covers the three resist layers 31 to 33.
  • the back surface covers one resist layer 30.
  • the three resist layers 31 to 33 on the front side are a first resist layer 31, a second resist layer 32, and a third resist layer 33 from the conductive substrate 10 side.
  • the first resist layer 31 and the third resist layer 33 are the same kind of resist layers having substantially the same wavelength for exposure.
  • As the second resist layer 32 a resist layer having a different wavelength from that of the first and third resist layers 31 and 33 is used.
  • a resist to be used a conventionally known method such as laminating a dry film resist or coating a resist layer by applying and drying a liquid resist can be used.
  • FIG. 6C shows an example of a resist mask forming process.
  • the resist mask formation process includes an exposure process, a development process, and a curing process.
  • the exposure process the front and back surfaces of the conductive substrate 10 are coated with a resist in the previous resist coating process. Thereafter, the first resist layer 31 and the third resist layer 33 are exposed on the surface side, and the second resist layer 32 is exposed to light having a wavelength that is not exposed.
  • the back side is exposed with light having a wavelength to which the resist layer 30 on the back side is exposed.
  • the resist is covered with a mask (ultraviolet light shielding glass mask) on which the surface has a pattern in which a plurality of sets including a desired die pad portion 21 and lead portion 22 are arranged, and the back surface has a pattern covering the entire surface. And exposure.
  • a mask ultraviolet light shielding glass mask
  • the second resist layer 32 is in an unexposed state because the photosensitive wavelength is different from that of the first resist layer 31.
  • the resist layers 30 to 33 are developed by removing the mask. First, unexposed light is removed from the opening 34 of the third resist layer 33, and then developed with the second resist layer 32 and first with the resist layer 31. For this reason, since the second resist layer 32 is an unexposed portion, it is also removed in the horizontal direction from the third resist layer 33 side (upper side).
  • the shape of the opening 34 is a tapered shape in which the upper surface side is widened.
  • the taper angle is adjusted by controlling the development speed by the thickness of the second resist layer 32, the development time in the development process, the discharge pressure of the developer, and the like. Can do. Thereafter, the second resist layer is cured. The second resist layer 32 is in an unexposed state and is cured by exposure. In this manner, a resist mask for plating 35 having a taper shape on the second resist layer 32 is produced.
  • a mask ultraviolet light shielding glass
  • the development time is made longer than the tapered shape, so that the bottom surface of the upper step portion 26a that is the boundary between the upper step portion 26a and the lower step portion 26b corresponding to the recess portion 27c. It is possible to provide the horizontal part 26e in 26d. By adjusting the development time, the length of the horizontal portion 26e can be adjusted. Because it depends on the pattern shape, it is adjusted according to the situation.
  • FIG. 6D is a diagram showing an example of the plating process.
  • the plating step using the resist mask 35 formed in FIG. 6B, the exposed portion of the conductive substrate 10 in which the opening 34 is formed is plated to form the plated layer 20.
  • Plating is performed to a height of about 4/5 of the second resist layer 32.
  • the plating layer 20 is first formed along the shapes of the resist layer 31 and the second resist layer 32.
  • the side surface of the lead portion 22 is divided into an upper step portion 22a and a lower step portion 22b.
  • the side surface 24 b of the lower step portion 22 b has a straight line portion in the vertical direction, and the side surface 24 a of the upper step portion 22 a can be formed in a shape having a tapered shape in which the upper portion extends along the periphery of the lead portion 22.
  • plating there is no particular limitation on the type of plating.
  • the plating thickness of the die pad portion 21 and the lead portion 22 is also not particularly limited, but considering the adhesion with the sealing resin, Ni plating, which is relatively hard and inexpensive, extends from the lower side to the upper side. It is preferable to set the thickness.
  • a plating layer having a good bonding property is formed on the outermost surface as much as necessary.
  • FIG. 6E is a diagram showing an example of a resist stripping process.
  • the cured resist mask 35 and resist layer 30 are stripped. Thereby, the die pad part 21 and the lead part 22 made of the plating layer 20 are formed.
  • the semiconductor element mounting substrate 50 according to the embodiment of the present invention is obtained by cutting the conductive substrate 10 on which the die pad portion 21 and the lead portion 22 are formed into desired dimensions as necessary.
  • the semiconductor element mounting substrate 50 according to the embodiment of the present invention is manufactured by sequentially performing the above-described steps.
  • FIG. 7 is a diagram showing a series of steps in an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • FIG. 7A is a diagram showing an example of a semiconductor element mounting process.
  • the semiconductor element 60 is mounted on the die pad portion 21 of the semiconductor element mounting substrate 50.
  • the semiconductor element 60 may be bonded and fixed on the die pad portion 21 using, for example, a silver paste or an adhesive.
  • FIG. 7B is a diagram showing an example of the wire bonding process.
  • the wire 61 is formed by electrically connecting the electrode 61 of the semiconductor element 60 and the lead portion 22 using the bonding wire 70 by wire bonding.
  • FIG. 7C is a diagram showing an example of the resin sealing process.
  • the entire surface on which the semiconductor element 60 of the semiconductor element mounting substrate 50 is mounted is sealed with the resin 80.
  • FIG. 7D is a diagram showing an example of the conductive substrate removing process.
  • the conductive substrate removal step the conductive substrate 10 is removed from the resin-encapsulated portion.
  • the conductive substrate 10 is dissolved and removed using a solution.
  • FIG. 7E shows an example of the cutting process. Finally, the semiconductor device 100 is completed by cutting to a predetermined size of the semiconductor device 100.
  • optical semiconductor device mounting substrate and optical semiconductor device The present invention can be applied not only to a semiconductor device but also to an optical semiconductor device. Hereinafter, description will be made with reference to FIGS.
  • FIG. 8 is a cross-sectional view showing an example of an optical semiconductor element mounting substrate according to an embodiment of the present invention.
  • the configuration of the optical semiconductor element mounting substrate 51 is the same as that of the semiconductor element mounting substrate 50.
  • the die pad portion 21 and the lead portion 22 are formed in pairs, and a plurality of them are arranged as a set.
  • the conductive substrate 10 is a substrate on which the plating layer 20 is formed on the surface 11, and is made of a conductive material so that the plating layer 20 can be formed by electroplating.
  • the material of the conductive substrate 10 to be used is not particularly limited as long as conductivity is obtained, but a metal material is generally used, for example, Cu or Cu alloy.
  • the die pad portion 21 and the lead portion 22 are a plating layer 20 formed by plating on one side (surface 11) of the conductive substrate 10.
  • the features of the optical semiconductor element mounting substrate 51 according to the embodiment of the present invention of the die pad portion 21 and the lead portion 22 are the same as those of the semiconductor element mounting substrate 50.
  • FIG. 9 is a cross-sectional view of an example of the optical semiconductor device 101 according to the embodiment of the present invention.
  • an optical semiconductor element 62 is mounted on the die pad portion 21, and the electrode 63 and the lead portion 22 of the optical semiconductor element 62 are bonded to the bonding wire 70 and the like. Connected through.
  • an external resin 81 is formed on the die pad portion 21 and the lead portion 22 so as to surround a peripheral portion including connection portions such as the optical semiconductor element 62 and the bonding wire 70. Further, the external resin 81 is simultaneously filled in the space between the die pad portion 21 and the lead portion 22 facing each other.
  • the optical semiconductor element 62 surrounded by the external resin 81 and the periphery of the electrical connection portion are filled with a transparent resin 90.
  • the conductive substrate 10 existing in FIG. 8 does not exist.
  • the conductive substrate 10 is removed after sealing with the external resin 81 and the transparent resin 90. That is, in the optical semiconductor element mounting substrate 51 shown in FIG. 8, first, after sealing the external resin 81, the optical semiconductor element 62 is mounted on the die pad part 21, and the electrode 63 and the lead part 22 of the semiconductor element 62 are mounted. Are connected via a bonding wire 70 by wire bonding. Thereafter, the peripheral portion including the connecting portion such as the optical semiconductor element 62 and the bonding wire 70 opened in the external resin 81 is sealed with the transparent resin 90.
  • the conductive substrate 10 is removed, whereby an optical semiconductor device 101 as shown in FIG. 9 is manufactured.
  • the die pad portion 21 and the bottom surface 25 of the lead portion 22 exposed by removing the conductive substrate 10 serve as external terminals for soldering with external devices.
  • the die pad portion 21 and the lead portion 22 are arranged in pairs. Since the shape of the optical semiconductor device 101 is small, the adhesion between the external resin 81 and the die pad portion 21 and the lead portion 22 is important. Like the die pad portion 21 and the lead portion 22 of the optical semiconductor device 101 according to the embodiment of the present invention, the adhesiveness with the external resin 81 can be improved by having a tapered shape on the upper side.
  • the lead part 22 is replaced with the lead part 26, the unevenness is formed on each side of the outer shape of the die pad part 21 and the lead part 26, and the side surface of the lead part 26 is the upper stage part. 26a and the lower part 26b.
  • the side surface 27b of the lower step portion 26b has a linear portion in the vertical direction
  • the side surface 27a of the upper step portion 26a has a tapered shape in which the upper portion extends along the periphery of the lead portion.
  • a part of the side surface 27 may have a horizontal portion 26e at the boundary between the upper step portion 26a and the lower step portion 26b (the bottom surface 26d of the upper step portion 26a).
  • the portion having the horizontal portion 26e on a part of the bottom surface 26d of the upper step portion 26a can be formed in the concave portion 27c in which an uneven shape is added to each side of the bottom surface shape of the lower end portion 26b of the lead portion 26 described above.
  • the concave portion 27c By forming the concave portion 27c, the lower surface of the concave portion 27c can be filled with the external resin 81, and the adhesion with the external resin 81 can be further improved. Thereby, the optical semiconductor device 101 can be further reduced in size and thickness.
  • the manufacturing method of the optical semiconductor element mounting substrate 51 is the same as the manufacturing method of the semiconductor element mounting substrate 50.
  • a noble metal with high reflectivity is used to efficiently reflect light from the light emitting element (optical semiconductor element).
  • Plating is applied to the outermost layer.
  • the outermost plating layer is preferably Ag or Ag alloy plating from the viewpoint of light reflectance. For example, on the surface of the conductive substrate 10, five-layer plating in which an Au plating layer, a Pd plating layer, a Ni plating layer, an Au plating layer, and an Ag plating layer are sequentially stacked can be performed.
  • the above-described optical semiconductor element mounting substrate 51 is used and the external resin 81 is resin-sealed.
  • the external resin 81 is filled on the die pad portion 21 and the lead portion 22 so as to surround the peripheral portion including the connecting portion such as the optical semiconductor element 62 and the bonding wire 70. Further, the external resin 81 is simultaneously filled in the space portion between the die pad portion 21 and the lead portion 22 facing each other.
  • the optical semiconductor element 62 is mounted on the die pad portion 21, and the electrode 63 of the optical semiconductor element 62 and the lead portion 22 are connected via the bonding wire 70 by wire bonding.
  • a peripheral portion including a connection portion such as the optical semiconductor element 62 and the bonding wire 70 provided in a predetermined central region opened in the external resin 81 is sealed with a transparent resin 90.
  • the conductive substrate 10 is removed. Finally, cut to a predetermined size. Thereby, the optical semiconductor device 101 is manufactured.
  • Example 1 A SUS plate (SUS430) having a thickness of 0.2 mm is processed into a long plate shape having a width of 140 mm as the conductive base material 10, and then a 0.015 mm thick photosensitive dry film resist (Asahi Kasei Corporation) is formed on the surface of the conductive substrate 10. ADH manufactured by Materials Co., Ltd. was attached using a laminate roll.
  • a photosensitive dry film resist having a thickness of 0.05 mm (AQ manufactured by Asahi Kasei E-Materials Co., Ltd.) and a photosensitive dry film resist having a thickness of 0.025 mm (ADH manufactured by Asahi Kasei E-Materials Co., Ltd.) were sequentially pasted thereon.
  • a 0.040 mm thick photosensitive dry film resist (AQ manufactured by Asahi Kasei E-Materials Co., Ltd.) was attached to the back surface with a laminate roll.
  • a glass mask on which a pattern is formed is formed on the front surface side so as to form a desired pattern of the lead part 22 for connecting to the semiconductor device mounting die pad portion 21 and the outside, and a pattern covering the entire back surface on the back surface side. It was covered with a dry film resist and exposed to ultraviolet light. The exposure on the surface side was performed at a wavelength at which the first resist layer 31 and the third resist layer 33 were exposed and the second resist layer 32 was not exposed. For this reason, the dry film with a thickness of 0.05 mm, which is the second resist layer 32 on the surface side, was in an unexposed state. The back side exposure was performed at a wavelength at which the back side resist was exposed.
  • the bottom face shape of the lead part 22 and the die pad part 21 was rectangular, and the corner part was R-shaped (rounded shape).
  • the taper angle of the second resist layer 32 was set to about 45 ° by appropriately adjusting the development time, the discharge pressure of the developer, and the like. Thereafter, the second resist layer was cured by exposure.
  • electroplating was performed on the exposed portion surface of the conductive substrate 10 from which the resist layer was removed and the opening 34 was formed.
  • the die pad portion 21 and the lead portion 22 about 0.02 ⁇ m of Au plating, 0.02 ⁇ m of Pd plating, 40 ⁇ m of Ni plating, and 0.05 ⁇ m of Pd plating were sequentially performed.
  • the thickness of the plating layer was set with 2/3 of the second resist layer 32 as a guide.
  • the dry film resists 30 to 33 were peeled off with a sodium hydroxide solution to form the die pad portion 21 and the lead portion 22 on the conductive substrate 10.
  • the substrate 50 for mounting a semiconductor element according to Example 1 of the present invention was obtained by cutting into predetermined dimensions.
  • the semiconductor element 60 was mounted on the manufactured semiconductor element mounting substrate 50, the semiconductor element 60 and the lead portion 22 were connected by wire bonding 70, and the surface on which the semiconductor element 60 was mounted was sealed with a resin 80. Thereafter, the conductive substrate 10 was peeled off and removed from the resin-encapsulated portion. Finally, the semiconductor device 100 was cut to a predetermined size of the semiconductor device 100 to complete the semiconductor device 100 according to Example 1.
  • Example 2 In Example 2, the pattern was added with zigzag (or corrugated) uneven shapes on the rectangular sides of the lead part 26 and the die pad part 21 in Example 1. In addition, each vertex of the zigzag has an R shape. The length of the recess 27c was 0.03 mm. In the development process, a horizontal portion is provided at the boundary between the upper step portion 26a and the lower step portion 26b (the bottom surface of the upper step portion 26a) corresponding to the recess 27c by appropriately adjusting the developing time, the discharge pressure of the developer, and the like. . The development time was longer than that in Example 1. Other conditions are the same as in the first embodiment.
  • FIG. 10 is an enlarged view from the upper surface of the lead portion 26 of the semiconductor element mounting substrate 51 according to the second embodiment, and is an enlarged view of a part of the side surface of the lead portion.
  • an upper step portion 26a having a corrugated side surface is provided on the upper surface of a columnar lower step portion 26b having a corrugated side surface, and the side surface of the upper step portion 26a projects sideways and upward. It turns out that it forms in the taper shape. With this configuration, the upper portion 26a can be easily caught on the resin 80, the adhesion between the resin 80 and the lead portion 26 can be improved, and the lead portion 26 can be prevented from falling off and peeling off.
  • FIG. 11 is an enlarged view from the back surface of the lead portion 26 of the semiconductor element mounting substrate 51 according to the second embodiment, and is an enlarged view of a part of the side surface on the back surface side of the lead portion. That is, the lead part 26 is peeled from the conductive substrate 10 and only the lead part 26 is shown from the back side.
  • the bottom surface 26d of the upper step portion 26a provided on the upper surface of the columnar lower step portion 26b (downward in FIG. 11) includes the upper surface of the lower step portion 26b, and is flat in the corrugated recess.
  • a surface (horizontal plane) 26e is formed.
  • the resin 80 By providing the flat surface 26e on the bottom surface 26d of the upper end portion 26a, the resin 80 can be easily caught, and the adhesion between the resin 80 and the lead portion 26 is greatly improved. Further, the side surface 27a of the upper step portion 26a is also tapered, so that the adhesion between the resin 80 and the lead portion 26 can be improved.
  • Example 3 is an example in which an optical semiconductor element mounting substrate 51 was produced.
  • the pattern in Example 1 was set to a shape in which the die pad part 21 and the lead part 22 for the optical semiconductor device 101 were paired.
  • the plating layer 20 1 ⁇ m of Ag plating was added to the outermost layer of the plating layer of Example 1. Others are the same as the first embodiment.
  • the die pad is formed so as to surround the peripheral portion including the connection portion such as the optical semiconductor element 62 and the bonding wire 70 using the optical semiconductor element mounting substrate 51 manufactured above.
  • An external resin 81 was formed on the outer surfaces of the part 21 and the lead part 22.
  • an external resin 81 was also formed at the same time in the space where the die pad portion 21 and the lead portion 22 face each other. Then, the optical semiconductor element 62 was mounted on the die pad part 21, and the electrode 63 of the optical semiconductor element 62 and the lead part 22 were connected via the bonding wire 70 by wire bonding.
  • the peripheral portion (predetermined central region) including the connection portion such as the optical semiconductor element 62 and the bonding wire 70 opened in the external resin 81 was sealed with the transparent resin 90. After resin sealing, the conductive substrate 10 was removed. Finally, it was cut into predetermined dimensions. Thus, the optical semiconductor device 101 was completed.
  • Comparative Example 1 In Comparative Example 1, a 0.025 mm thick photosensitive dry film resist (AQ-4096 manufactured by Asahi Kasei E-Materials Co., Ltd.) was laminated on both sides of the conductive substrate in the resist coating step, and exposure development was performed. In the plating step, a plating layer was formed beyond the resist layer. Other conditions are the same as in the first embodiment.
  • Comparative Example 2 In Comparative Example 2, a photosensitive dry film resist (AQ-4096 manufactured by Asahi Kasei E-Materials Co., Ltd.) having a thickness of 0.05 mm was attached to the surface of the conductive substrate in the resist coating step. A 0.025 mm thick photosensitive dry film resist (AQ-4096 manufactured by Asahi Kasei E-Materials Co., Ltd.) was attached to the back surface with a laminate roll, and exposure was performed using scattered ultraviolet light in the exposure process. Thereafter, development was performed. By exposing with scattered ultraviolet light, the resist layer is in a semi-exposed state, and a tapered resist is formed. In the plating step, the opening portion of the formed tapered resist mask was plated to produce a reverse trapezoidal lead portion. Other conditions are the same as those in the first embodiment.
  • Example 1 Example 2, Example 3, Comparative Example 1, and Comparative Example 2 were evaluated by the following methods.
  • the shape of the bottom surface of the lead part was measured for 20 leads, and the variation was confirmed.
  • Example 1 In Example 1 and Comparative Example 1, the set value was within ⁇ 0.003 mm, and in Examples 2 and 3, the set value was ⁇ 0.004 mm, but in Comparative Example 2, the set value ⁇ 0.01 mm. And the variation was large.
  • Example 1 After mounting the semiconductor element using this semiconductor element mounting substrate and sealing with resin, the conductive substrate was peeled off, and it was observed whether there was a defect that the lead portion remained on the conductive substrate.
  • Example 2 Example 3, Comparative Example 1, and Comparative Example 2
  • Example 2 and Example 3 it was confirmed that sufficient adhesion with the sealing resin was secured.

Abstract

This invention has an electroconductive substrate that can be removed after a semiconductor element is mounted, a semiconductor element-mounting region provided on a surface of the electroconductive substrate, and a lead part comprising a plating layer provided on a predetermined region on the surface of the electroconductive substrate around the semiconductor element-mounting region. The lead part has: a lower level part, which has side surfaces substantially perpendicular to the surface of the electroconductive substrate and which extend upwards in a columnar shape from the surface; and an upper level part, which has a bottom surface on the upper surface of the lower level part and which has side surfaces extending upwards and sideways from the bottom surface in a tapered shape.

Description

半導体素子搭載用基板、半導体装置及び光半導体装置、並びにそれらの製造方法Semiconductor element mounting substrate, semiconductor device, optical semiconductor device, and manufacturing method thereof
　本発明は、半導体素子搭載用基板、半導体装置及び光半導体装置、並びにそれらの製造方法に関する。 The present invention relates to a semiconductor element mounting substrate, a semiconductor device, an optical semiconductor device, and a manufacturing method thereof.
　近年、携帯電話に代表されるように、電子機器の小型化・軽量化が急速に進み、それら電子機器に用いられる半導体装置にも小型化・軽量化・高機能化が要求されている。特に、半導体装置の厚みについて、薄型化が要求されている。かかる要求に応えるため、ＱＦＮ（Quad　Flat　No-Lead）等の金属材料を加工したリードフレームを用いた半導体装置から、導電性基板を最終的に除去する態様の半導体装置が開発されてきている。 In recent years, as represented by mobile phones, electronic devices are rapidly becoming smaller and lighter, and semiconductor devices used in these electronic devices are also required to be smaller, lighter, and more functional. In particular, the thickness of the semiconductor device is required to be reduced. In order to meet such a demand, a semiconductor device having an aspect in which a conductive substrate is finally removed from a semiconductor device using a lead frame obtained by processing a metal material such as QFN (Quad Flat No-Lead) has been developed.
　具体的には、導電性を有する基板の一面側に、所定のパターニングを施したレジストマスクを形成する。レジストマスクから露出した導電性基板に金属をめっきし、半導体素子搭載用のダイパッド部と、半導体素子と接続する内部端子及び外部機器と接続するための外部端子として機能するリード部とを形成した後、レジストマスクを除去することにより、半導体素子搭載用基板を形成する。形成した半導体素子搭載用基板に半導体素子を搭載し、ワイヤーボンディングした後に樹脂封止を行い、導電性基板を除去してダイパッド部やリード部を露出させ、半導体装置を完成させている（例えば、特許文献１、２参照）。 Specifically, a resist mask subjected to predetermined patterning is formed on one surface side of a conductive substrate. After plating metal on the conductive substrate exposed from the resist mask to form a die pad part for mounting a semiconductor element, and an internal terminal connected to the semiconductor element and a lead part functioning as an external terminal connected to an external device Then, by removing the resist mask, a semiconductor element mounting substrate is formed. The semiconductor element is mounted on the formed semiconductor element mounting substrate, and after wire bonding, resin sealing is performed, the conductive substrate is removed, the die pad portion and the lead portion are exposed, and the semiconductor device is completed (for example, (See Patent Documents 1 and 2).
特開２００２－９１９６号公報JP 2002-9196 A 特開２００７－１０３４５０号公報JP 2007-103450 A
　しかしながら、これらの半導体装置は、封止樹脂との密着度が低いため、封止樹脂から端子部が脱落したり、脱落しないものの剥離し、半導体装置の信頼性が低下したりするという問題があり、種々の改善がなされてきた。 However, since these semiconductor devices have a low degree of adhesion to the sealing resin, there is a problem that the terminal part is dropped from the sealing resin, or the terminal part is not dropped but is peeled off and the reliability of the semiconductor device is lowered. Various improvements have been made.
　例えば、特許文献１には、形成したレジストマスクを超えて導電性金属を電着させることで、半導体素子搭載用の金属層と、外部接続用の電極層の上端部周縁に張り出し部を有する半導体素子搭載用基板を得る方法が記載されている。これにより、樹脂封止の際に金属層と電極層の張り出し部が樹脂に食い込む形となり、確実に樹脂側に残るようにすることができる。 For example, Patent Document 1 discloses a semiconductor having a metal layer for mounting a semiconductor element and a protruding portion at the periphery of the upper end of an electrode layer for external connection by electrodepositing a conductive metal beyond the formed resist mask. A method for obtaining an element mounting substrate is described. As a result, the protruding portion of the metal layer and the electrode layer bites into the resin at the time of resin sealing, and can be reliably left on the resin side.
　特許文献１に記載されたレジストマスクを超えて導電性金属を電着させる方法においては、レジストマスクをオーバーハングさせてめっき層を形成するが、オーバーハング量をコントロールすることは難しい。よって、形成するめっき層の全てが同じ張り出し長さにならない問題や、張り出し部が大きくなると隣のめっき層と繋がってしまう問題が発生している。また、めっき層が薄くなると、張り出し部の幅も厚みも小さくなることから、封止樹脂との密着性が低下する問題も抱えている。さらに、オーバーハングさせためっき層の上面は、めっきの縦方向と横方向の成長比率の関係で球状となるため、ボンディングの信頼性を低下させる要因ともなる。 In the method of electrodepositing a conductive metal beyond the resist mask described in Patent Document 1, a plating layer is formed by overhanging the resist mask, but it is difficult to control the overhang amount. Therefore, the problem that all the plating layers to be formed do not have the same overhang length or the problem that the overhang portion is connected to the adjacent plating layer occurs. Further, when the plating layer is thinned, the width and thickness of the overhanging portion are reduced, so that the adhesion with the sealing resin is also lowered. Furthermore, since the upper surface of the overhanged plating layer is spherical due to the growth ratio in the vertical and horizontal directions of plating, it also causes a decrease in bonding reliability.
　また、特許文献２には、レジストマスクを形成する際に、散乱紫外光を用いてレジストマスクを台形に形成することで、金属層あるいは電極層を逆台形の形状に形成する方法が記載されている。 Patent Document 2 describes a method of forming a metal layer or an electrode layer in an inverted trapezoidal shape by forming a resist mask into a trapezoid using scattered ultraviolet light when forming a resist mask. Yes.
　特許文献２に記載された、散乱紫外光を用いてレジスト層の開口部の断面形状を台形に形成する方法は、電極層の断面形状が逆台形に形成されている。このため、封止樹脂との密着度は向上し、封止樹脂から金属層や電極層の脱落や剥離の発生はなく、効果はあった。 In the method described in Patent Document 2 in which the cross-sectional shape of the opening of the resist layer is formed into a trapezoid using scattered ultraviolet light, the cross-sectional shape of the electrode layer is formed in an inverted trapezoid. For this reason, the degree of adhesion with the sealing resin is improved, and the metal layer and the electrode layer are not dropped or peeled off from the sealing resin, which is effective.
　しかしながら、電極層の断面形状を逆台形にしたことで、半導体素子を搭載し、ワイヤーボンディングした後に樹脂封止する際、電極層の側面部が導電性基板に対して鋭角になり、封止樹脂が回り込みづらくなった。このため、場合によっては、ボイド等封止樹脂の未充填が発生する場合があった。また、電極層基部付近の封止樹脂は、当然、この角度に倣い形成されるため、先端が鋭角な形状となり強度的にも弱く、封止樹脂部の先端の欠けや剥がれが発生し易いという問題があった。 However, since the cross-sectional shape of the electrode layer is inverted trapezoidal, when the semiconductor element is mounted and resin-sealed after wire bonding, the side surface of the electrode layer becomes an acute angle with respect to the conductive substrate, and the sealing resin Became difficult to wrap around. For this reason, unfilling of sealing resin such as voids may occur in some cases. In addition, the sealing resin near the electrode layer base is naturally formed following this angle, so that the tip has an acute shape and is weak in strength, and the tip of the sealing resin portion is likely to be chipped or peeled off. There was a problem.
　また、散乱光を使用するため、レジスト層は半露光状態になりテーパー形状を形成するが、半露光状態のため、底面の寸法精度は、平行光を用いてレジストを露光・現像して作製した寸法精度よりもばらつきが大きく、寸法精度が劣るという問題もあった。特に、半導体装置の小型化、薄型化により、リード形状が小さくなる傾向ある中では、底面寸法精度の向上は重要であり、特許文献２に記載の構成では、この要請に十分応えることが困難であった。 In addition, since the scattered light is used, the resist layer is in a semi-exposure state and forms a tapered shape. However, since the resist layer is in a semi-exposure state, the dimensional accuracy of the bottom surface was prepared by exposing and developing the resist using parallel light. There is also a problem that the variation is larger than the dimensional accuracy and the dimensional accuracy is inferior. In particular, when the lead shape tends to become smaller due to the miniaturization and thinning of the semiconductor device, it is important to improve the dimensional accuracy of the bottom surface. With the configuration described in Patent Document 2, it is difficult to sufficiently meet this requirement. there were.
　そこで、本発明は、半導体素子を搭載後、樹脂封止し導電性基板を除去して完成する半導体装置において、封止樹脂とリード部等の密着度が適切であり、樹脂封止後、導電性基板の除去時等に封止樹脂からリード部等が脱落したり剥離したりする不具合がなく、かつ、リード底面の寸法精度が良好な半導体素子搭載用基板、半導体装置及び光半導体装置、並びにそれらの製造方法を提供することを目的とする。 Therefore, the present invention provides a semiconductor device completed by mounting a semiconductor element and then resin-sealing and removing the conductive substrate, and the degree of adhesion between the sealing resin and the lead portion is appropriate. A semiconductor element mounting substrate, a semiconductor device and an optical semiconductor device, in which there is no inconvenience that the lead portion or the like is dropped or peeled off from the sealing resin when the conductive substrate is removed, and the lead bottom surface has good dimensional accuracy, and It aims at providing those manufacturing methods.
　上記目的を達成するため、本発明の一態様に係る半導体素子搭載用基板は、半導体素子搭載後に除去可能な導電性基板と、
　該導電性基板の表面上に設けられた半導体素子搭載領域と、
　該半導体素子搭載領域の周囲の前記導電性基板の前記表面上の所定領域に設けられためっき層からなるリード部と、を有し、
　該リード部は、前記導電性基板の前記表面と略垂直な側面を有して前記表面から柱状に上方に延びる下段部と、
　該下段部の上面上に底面を有し、該底面からテーパー状に上方及び側方に広がる側面を有する上段部と、を有する。 In order to achieve the above object, a semiconductor element mounting substrate according to one embodiment of the present invention includes a conductive substrate that can be removed after mounting a semiconductor element;
A semiconductor element mounting region provided on the surface of the conductive substrate;
A lead portion made of a plating layer provided in a predetermined region on the surface of the conductive substrate around the semiconductor element mounting region;
The lead portion has a side surface substantially perpendicular to the surface of the conductive substrate, and a lower step portion extending upward in a column shape from the surface;
And an upper step portion having a bottom surface on the upper surface of the lower step portion and a side surface extending upward and sideward in a tapered manner from the bottom surface.
　本発明の他の態様に係る半導体装置は、半導体素子と、
　該半導体素子の周囲の所定領域に設けられ、形状の異なる上段部と下段部とを有するめっき層からなるリード部と、
　前記半導体素子の電極と前記リード部の前記上段部の上面とを電気的に接続する接続手段と、
　少なくとも前記リード部の前記下段部の底面が露出するように前記半導体素子、前記リード部及び前記接続手段を封止する樹脂と、を有し、
　前記リード部の前記下段部は、前記底面から上方に垂直に延びる側面を有する柱状形状を有し、
　前記リード部の前記上段部は、前記下段部の上面上に底面を有し、該底面からテーパー状に上方及び側方に側面が広がるテーパー形状を有する。 A semiconductor device according to another aspect of the present invention includes a semiconductor element,
A lead portion made of a plating layer provided in a predetermined region around the semiconductor element and having an upper step portion and a lower step portion having different shapes;
Connection means for electrically connecting the electrode of the semiconductor element and the upper surface of the upper portion of the lead portion;
A resin that seals the semiconductor element, the lead portion, and the connecting means so that at least a bottom surface of the lower step portion of the lead portion is exposed;
The lower step portion of the lead portion has a columnar shape having a side surface extending vertically upward from the bottom surface,
The upper step portion of the lead portion has a bottom surface on the upper surface of the lower step portion, and has a tapered shape in which a side surface is tapered upward and laterally from the bottom surface.
　本発明の他の態様に係る光半導体装置は、光半導体素子を搭載する領域を有するダイパッド部と、
　前記ダイパッド部と対に設けられ、形状の異なる上段部と下段部とを有するめっき層からなるリード部と、
　前記ダイパッド部に搭載された光半導体素子と、
　該光半導体素子の電極と前記リード部の前記上段部の上面とを電気的に接続する接続手段と、
　前記光半導体素子及び前記接続手段を含む前記ダイパッド部上及び前記リード部上の所定の中央領域を封止する透明樹脂と、
　前記ダイパッド部及び前記リード部の底面が露出するように、前記ダイパッド部及び前記リード部の底面以外の前記ダイパッド部と前記リード部との間の領域と、前記ダイパッド部及び前記リード部の所定の外側領域とを封止する外部樹脂と、を有し、
　前記リード部の前記下段部は、前記底面から上方に垂直に延びる側面を有する柱状形状を有し、前記リード部の前記上段部は、前記下段部の上面上に底面を有し、該底面からテーパー状に上方及び側方に側面が広がるテーパー形状を有する。 An optical semiconductor device according to another aspect of the present invention includes a die pad portion having a region for mounting an optical semiconductor element;
A lead portion comprising a plating layer provided in a pair with the die pad portion and having an upper step portion and a lower step portion having different shapes;
An optical semiconductor element mounted on the die pad portion;
Connection means for electrically connecting the electrode of the optical semiconductor element and the upper surface of the upper portion of the lead portion;
A transparent resin that seals a predetermined central region on the die pad portion and the lead portion including the optical semiconductor element and the connection means;
A region between the die pad portion and the lead portion other than the bottom surface of the die pad portion and the lead portion, and predetermined areas of the die pad portion and the lead portion so that the bottom surfaces of the die pad portion and the lead portion are exposed. An external resin that seals the outer region;
The lower step portion of the lead portion has a columnar shape having a side surface extending vertically upward from the bottom surface, and the upper step portion of the lead portion has a bottom surface on the upper surface of the lower step portion. It has a tapered shape in which the side surface is widened upward and laterally.
　本発明の他の態様に係る半導体素子搭載用基板の製造方法は、導電性基板の表面上に、第１の感光波長を有する第１のレジストで被覆した第１のレジスト層、該第１のレジスト層上に第２の感光波長を有する第２のレジストで被覆した第２のレジスト層、該第２のレジスト層上に前記第１のレジストで被覆した第３のレジスト層を順次形成する工程と、
　第１の露光により、前記第１及び第３のレジスト層を硬化させるとともに、前記第２のレジスト層を硬化させていない状態で現像を行い、前記第２のレジスト層の上部が前記第１及び第３のレジスト層よりも内側に削れ、テーパー状の形状を有するパターンを形成する工程と、
　第２の露光により、第２のレジスト層を硬化させる工程と、
　前記第１乃至第３のレジスト層からなるパターンをめっきマスクとしてめっきを行い、前記第１のレジスト層により形成された部分が柱状形状を有し、前記第２のレジスト層により形成された部分がテーパー形状を有するめっき層を形成する工程と、
　前記めっきマスクを除去する工程と、を有する。 According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor element mounting substrate, comprising: a first resist layer coated with a first resist having a first photosensitive wavelength on a surface of a conductive substrate; A step of sequentially forming a second resist layer coated with a second resist having a second photosensitive wavelength on the resist layer, and a third resist layer coated with the first resist on the second resist layer. When,
In the first exposure, the first and third resist layers are cured, and development is performed in a state where the second resist layer is not cured, and the upper portion of the second resist layer is the first and third resist layers. A step of forming a pattern having a tapered shape that is scraped inward from the third resist layer;
A step of curing the second resist layer by the second exposure;
Plating is performed using the pattern composed of the first to third resist layers as a plating mask, the portion formed by the first resist layer has a columnar shape, and the portion formed by the second resist layer is Forming a plating layer having a tapered shape;
Removing the plating mask.
　本発明によれば、導電性基板の除去時におけるリード部の脱落及び剥離を防止できるとともに、リード部底面の寸法精度を向上させることができる。 According to the present invention, it is possible to prevent the lead portion from dropping and peeling when the conductive substrate is removed, and to improve the dimensional accuracy of the bottom surface of the lead portion.
本発明の実施形態に係る半導体素子搭載用基板の一例を示す断面図である。It is sectional drawing which shows an example of the board | substrate for semiconductor element mounting which concerns on embodiment of this invention. 本発明の実施形態に係る半導体装置の一例の断面図である。It is sectional drawing of an example of the semiconductor device which concerns on embodiment of this invention. 本発明の実施形態に係る半導体素子搭載用基板のリード部の一例を示した図である。図３（ａ）は、リード部の一例を示した平面図である。図３（ｂ）は、図３（ａ）に示したリード部のｘ－ｘ断面図である。It is the figure which showed an example of the lead part of the board | substrate for semiconductor element mounting which concerns on embodiment of this invention. FIG. 3A is a plan view showing an example of the lead portion. FIG. 3B is an xx cross-sectional view of the lead portion shown in FIG. リード部の形成方法を説明するための図である。図４（ａ）は、めっき用レジストマスクの一例を示した図である。図４（ｂ）は、めっき用レジストマスクを用いためっき加工の一例を示した図である。It is a figure for demonstrating the formation method of a lead part. FIG. 4A shows an example of a resist mask for plating. FIG. 4B is a diagram showing an example of plating using a plating resist mask. 図３と異なる形状を有するリード部を説明するための図である。図５（ａ）は、図３と異なる形状を有するリード部の一例を示した平面図である。図５（ｂ）は、図５（ａ）に示したリード部ｙ－ｙ断面図である。図５（ｃ）は、図５（ａ）に示したリード部のｚ－ｚ断面図である。It is a figure for demonstrating the lead part which has a shape different from FIG. FIG. 5A is a plan view showing an example of a lead portion having a shape different from that in FIG. FIG. 5B is a cross-sectional view of the lead portion yy shown in FIG. FIG. 5C is a zz cross-sectional view of the lead portion shown in FIG. 本発明の実施形態に係る半導体素子搭載用基板の製造方法の一例の一連の工程を示した図である。図６（ａ）は、基板用意工程の一例を示した図である。図６（ｂ）は、レジスト被覆工程の一例を示した図である。図６（ｃ）は、レジストマスク形成工程の一例を示した図である。図６（ｄ）は、めっき工程の一例を示した図である。図６（ｅ）は、レジスト剥離工程の一例を示した図である。It is the figure which showed a series of processes of an example of the manufacturing method of the board | substrate for semiconductor element mounting which concerns on embodiment of this invention. FIG. 6A is a diagram illustrating an example of a substrate preparation process. FIG. 6B is a diagram showing an example of a resist coating process. FIG. 6C is a diagram showing an example of a resist mask forming process. FIG. 6D is a diagram showing an example of the plating process. FIG. 6E is a diagram illustrating an example of a resist stripping process. 本発明の実施形態に係る半導体装置の製造方法の一例の一連の工程を示した図である。図７（ａ）は、半導体素子搭載工程の一例を示した図である。図７（ｂ）は、ワイヤーボンディング工程の一例を示した図である。図７（ｃ）は、樹脂封止工程の一例を示した図である。図７（ｄ）は、導電性基板除去工程の一例を示した図である。図７（ｅ）は、切断工程の一例を示した図である。It is the figure which showed a series of processes of an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. FIG. 7A is a diagram showing an example of a semiconductor element mounting process. FIG. 7B is a diagram illustrating an example of a wire bonding process. FIG. 7C is a diagram showing an example of the resin sealing process. FIG. 7D is a diagram showing an example of the conductive substrate removing process. FIG. 7E shows an example of the cutting process. 本発明の実施形態に係る光半導体素子搭載用基板の一例を示す断面図である。It is sectional drawing which shows an example of the board | substrate for optical semiconductor element mounting which concerns on embodiment of this invention. 本発明の実施形態に係る光半導体装置の一例の断面図である。It is sectional drawing of an example of the optical semiconductor device which concerns on embodiment of this invention. 実施例２に係る半導体素子搭載用基板のリード部の上面からの拡大図で、リード部の側面の一部の拡大図である。FIG. 10 is an enlarged view from the top surface of the lead portion of the semiconductor element mounting substrate according to the second embodiment, and is a partial enlarged view of a side surface of the lead portion. 実施例２に係る半導体素子搭載用基板のリード部の裏面からの拡大図で、リード部の裏面側における側面の一部の拡大図である。It is an enlarged view from the back surface of the lead part of the semiconductor element mounting substrate according to Example 2, and is an enlarged view of a part of the side surface on the back surface side of the lead part.
　以下、図面を参照して、本発明を実施するための形態の説明を行う。 Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.
　［半導体素子搭載用基板及び半導体装置］
　図１は、本発明の実施形態に係る半導体素子搭載用基板の一例を示す断面図である。本実施形態に係る半導体素子搭載用基板５０は、導電性基板１０と、その表面１１上に配置された半導体素子搭載用のダイパッド部２１と、外部機器と接続するためのリード部２２とで構成されている。リード部２２は、半導体素子搭載領域であるダイパッド部２１の周囲に配置される。 [Semiconductor element mounting substrate and semiconductor device]
FIG. 1 is a cross-sectional view showing an example of a semiconductor element mounting substrate according to an embodiment of the present invention. The semiconductor element mounting substrate 50 according to the present embodiment includes a conductive substrate 10, a semiconductor element mounting die pad portion 21 disposed on the surface 11, and a lead portion 22 for connecting to an external device. Has been. The lead portion 22 is disposed around the die pad portion 21 that is a semiconductor element mounting region.
　また、パターンによっては、半導体素子搭載領域を確保した上で、ダイパッド部２１を作製しないパターンもある。例えば、導電性基板１０に半導体素子を直接搭載するもの、あるいは、半導体素子の電極をリード部に直接接合するフリップチップ接続タイプ等がある。つまり、本実施形態において、ダイパッド部２１を設けることは必須ではなく、半導体素子を搭載可能な半導体素子搭載領域が確保されていればよい。但し、以下の説明においては、半導体素子搭載領域として、ダイパッド部２１が設けられている例について説明する。なお、ダイパッド部２１が設けられる場合、ダイパッド部２１とリード部２２は、同一のめっき層２０で構成されてもよい。なお、ダイパッド部２１及びリード部２２とめっき層２０とは、符号が重複するが、半導体素子搭載用基板５０の構成要素の観点から説明する場合にはダイパッド部２１、リード部２２と呼び、製造上の観点及び構成材料の観点から説明する場合には、めっき層２０と呼んでもよいこととする。 Further, depending on the pattern, there is a pattern in which the die pad portion 21 is not manufactured after the semiconductor element mounting area is secured. For example, there is a type in which a semiconductor element is directly mounted on the conductive substrate 10 or a flip chip connection type in which an electrode of the semiconductor element is directly bonded to a lead portion. That is, in the present embodiment, it is not essential to provide the die pad portion 21, and it is only necessary to secure a semiconductor element mounting region in which a semiconductor element can be mounted. However, in the following description, an example in which the die pad portion 21 is provided as the semiconductor element mounting region will be described. When the die pad portion 21 is provided, the die pad portion 21 and the lead portion 22 may be configured by the same plating layer 20. In addition, although the code | symbol overlaps with the die pad part 21 and the lead part 22, and the plating layer 20, when it demonstrates from a viewpoint of the component of the board | substrate 50 for semiconductor element mounting, it is called the die pad part 21 and the lead part 22, and is manufactured. In the case of explaining from the viewpoints of the above and the constituent materials, it may be called the plating layer 20.
　導電性基板１０は、表面１１上にめっき層２０が形成される基板であり、電気めっきによりめっき層２０を形成することが可能なように、導電性を有する材料から構成される。使用する導電性基板１０の材質は、導電性が得られれば特に限定はないが、一般的には金属材料が用いられ、例えば、ＣｕまたはＣｕ合金等が使用される。導電性基板を引き剥がし除去する場合は、ＳＵＳ材が使用されることもある。 The conductive substrate 10 is a substrate on which the plating layer 20 is formed on the surface 11, and is made of a conductive material so that the plating layer 20 can be formed by electroplating. The material of the conductive substrate 10 to be used is not particularly limited as long as conductivity is obtained, but a metal material is generally used, for example, Cu or Cu alloy. When the conductive substrate is peeled off and removed, a SUS material may be used.
　ダイパッド部２１やリード部２２は、導電性基板１０の片面（表面１１）にめっき加工により形成されためっき層２０から構成される。本発明の実施形態に係る半導体素子搭載用基板５０は、リード部２２の形状に特徴がある。具体的には、リード部２２は、柱状の下段部２２ｂと、テーパー状の上段部２２ａとを有する。また、同様に、ダイパッド部２１も、柱状の下段部２１ｂと、テーパー状の上段部２１ａとを有してもよい。なお、ダイパッド部２１及びリード部２２の構成の詳細については、後述する。 The die pad part 21 and the lead part 22 are constituted by a plating layer 20 formed on one surface (front surface 11) of the conductive substrate 10 by plating. The semiconductor element mounting substrate 50 according to the embodiment of the present invention is characterized by the shape of the lead portion 22. Specifically, the lead portion 22 includes a columnar lower step portion 22b and a tapered upper step portion 22a. Similarly, the die pad portion 21 may have a columnar lower step portion 21b and a tapered upper step portion 21a. Details of the configurations of the die pad portion 21 and the lead portion 22 will be described later.
　次に、図２を用いて、本発明の実施形態に係る半導体素子搭載用基板５０を用いた半導体装置１００の一例について説明する。図２は、本発明の実施形態に係る半導体装置１００の一例の断面図である。 Next, an example of the semiconductor device 100 using the semiconductor element mounting substrate 50 according to the embodiment of the present invention will be described with reference to FIG. FIG. 2 is a cross-sectional view of an example of the semiconductor device 100 according to the embodiment of the present invention.
　図２に示すように、本発明の実施形態に係る半導体装置１００は、ダイパッド部２１に半導体素子６０が搭載され、半導体素子６０の電極６１とリード部２２とがボンディングワイヤー７０等を介して接続されている。また、半導体素子６０及びボンディングワイヤー７０等の接続手段を含めて全体が樹脂８０により封止されている。ダイパッド部２１及びリード部２２は、上面２３及び側面２４は樹脂８０により覆われているが、底面２５は露出している。また、図１で存在していた導電性基板１０は存在しない。導電性基板１０は、樹脂８０により封止が行われた後、除去されている。つまり、図１で示した半導体素子搭載用基板５０のダイパッド部２１上に半導体素子６０が搭載され、半導体素子６０の電極６１とリード部２２とがワイヤーボンディングによりボンディングワイヤー７０を介して接続された後、半導体素子搭載用基板５０上で樹脂８０により封止が行われる。樹脂封止の後、導電性基板１０が除去されることにより、図２に示すような半導体装置１００が作製される。導電性基板１０の除去により露出したリード部２２の底面２５は、外部機器とのはんだ接合するための外部端子となる。 As shown in FIG. 2, in the semiconductor device 100 according to the embodiment of the present invention, the semiconductor element 60 is mounted on the die pad portion 21, and the electrode 61 of the semiconductor element 60 and the lead portion 22 are connected via a bonding wire 70 or the like. Has been. Further, the whole including the connection means such as the semiconductor element 60 and the bonding wire 70 is sealed with the resin 80. The die pad portion 21 and the lead portion 22 have the upper surface 23 and the side surface 24 covered with the resin 80, but the bottom surface 25 is exposed. Further, the conductive substrate 10 existing in FIG. 1 does not exist. The conductive substrate 10 is removed after sealing with the resin 80. That is, the semiconductor element 60 is mounted on the die pad portion 21 of the semiconductor element mounting substrate 50 shown in FIG. 1, and the electrode 61 and the lead portion 22 of the semiconductor element 60 are connected via the bonding wire 70 by wire bonding. Thereafter, sealing is performed with a resin 80 on the semiconductor element mounting substrate 50. After the resin sealing, the conductive substrate 10 is removed, whereby the semiconductor device 100 as shown in FIG. 2 is manufactured. The bottom surface 25 of the lead portion 22 exposed by removing the conductive substrate 10 serves as an external terminal for soldering with an external device.
　次に、図３を用いて、本発明の実施形態に係る半導体素子搭載用基板５０及び半導体装置１００の特徴であるリード部２２の形状について説明する。 Next, the shape of the lead portion 22 which is a feature of the semiconductor element mounting substrate 50 and the semiconductor device 100 according to the embodiment of the present invention will be described with reference to FIG.
　図３は、本発明の実施形態に係る半導体素子搭載用基板１００のリード部２２の一例を示した図である。図３（ａ）は、リード部２２の一例を示した平面図である。図３（ｂ）は、図３（ａ）に示したリード部２２のｘ－ｘ断面図である。 FIG. 3 is a view showing an example of the lead portion 22 of the semiconductor element mounting substrate 100 according to the embodiment of the present invention. FIG. 3A is a plan view showing an example of the lead portion 22. FIG. 3B is an xx cross-sectional view of the lead portion 22 shown in FIG.
　図３に示されるように、本発明の実施形態に係る半導体素子搭載用基板５０の第１の特徴は、リード部２２の断面形状である。図３（ａ）、（ｂ）で示すように、リード部２２は、形状の異なる上段部２２ａと下段部２２ｂとを有する。下段部２２ｂの断面は、垂直方向に直線部を有する形状となっている。上段部２２ａの断面は、リード部周縁に沿い上部が広がるテーパー形状を有する。 As shown in FIG. 3, the first feature of the semiconductor element mounting substrate 50 according to the embodiment of the present invention is the cross-sectional shape of the lead portion 22. As shown in FIGS. 3A and 3B, the lead portion 22 includes an upper step portion 22a and a lower step portion 22b having different shapes. The cross section of the lower step portion 22b has a shape having a straight line portion in the vertical direction. The cross section of the upper step portion 22a has a tapered shape in which the upper portion extends along the periphery of the lead portion.
　より詳細に説明すると、下段部２２ｂは、導電性基板１０の表面１１から、表面１１に垂直に上方に延びる柱状の形状を有する。図３（ａ）、（ｂ）に示されるように、下段部２２ｂは、略長方形の平面形状又は水平断面形状を有し、略四角柱の形状を有する。下段部２２ｂの側面２４ｂは、鉛直方向に沿って延びているので、下段部２２ｂにおける平面形状及び水平断面形状は、底面、上面、底面と上面の中間で切ったいずれの場合も総て同じである。このように、下段部２２ｂは、平面形状及び水平断面形状が一定な柱状の形状を有する。 More specifically, the lower step portion 22b has a columnar shape extending upward from the surface 11 of the conductive substrate 10 perpendicularly to the surface 11. As shown in FIGS. 3A and 3B, the lower step portion 22b has a substantially rectangular planar shape or horizontal cross-sectional shape, and has a substantially quadrangular prism shape. Since the side surface 24b of the lower step portion 22b extends along the vertical direction, the planar shape and the horizontal cross-sectional shape of the lower step portion 22b are the same in all cases of cutting at the bottom surface, the upper surface, or between the bottom surface and the upper surface. is there. Thus, the lower step portion 22b has a columnar shape with a constant planar shape and horizontal cross-sectional shape.
　上段部２２ａは、下段部２２ｂの上面上に、下段部２２ｂと連続的かつ一体的に設けられる。即ち、上段部２２ａの底面（下面）は、下段部２２ｂの上面と同一水平面上に設けられる。しかしながら、上段部２２ａの底面は、下段部２２ｂの上面と必ずしも合同である必要は無く、例えば、上段部２２ａの底面が、下段部２２ｂよりも広く形成され、上段部２２ａの底面が下段部２２ｂの上面を包含するように形成されてもよい。但し、図３（ａ）、（ｂ）の例においては、上段部２２ａの底面は、下段部２２ｂの上面と略同一の形状を有し、角が丸い長方形の形状となっている。 The upper step portion 22a is provided continuously and integrally with the lower step portion 22b on the upper surface of the lower step portion 22b. That is, the bottom surface (lower surface) of the upper step portion 22a is provided on the same horizontal plane as the upper surface of the lower step portion 22b. However, the bottom surface of the upper step portion 22a is not necessarily congruent with the upper surface of the lower step portion 22b. For example, the bottom surface of the upper step portion 22a is formed wider than the lower step portion 22b, and the bottom surface of the upper step portion 22a is the lower step portion 22b. It may be formed so as to include the upper surface. However, in the example shown in FIGS. 3A and 3B, the bottom surface of the upper step portion 22a has substantially the same shape as the upper surface of the lower step portion 22b, and has a rectangular shape with rounded corners.
　上段部２２ａの側面２４ａは、その底面からテーパー状に上方及び側方に広がるような形状を有する。図３（ａ）に示されるように、上段部２２ａの上面は、下段部２２ｂと類似した形状を有し、略長方形に構成されている。これは、図３の構成においては、上段部２２ａの底面から側面２４ａが全体にテーパー状に略同じ割合で広がり、上段部２２ａの上面の平面形状は下段部２２ｂの上面よりも大きくなったことを意味する。上段部２２ａの側面２４ａがこのようなテーパー形状を有することにより、樹脂８０への食い付き、引っ掛かりができ、導電性基板１０を樹脂８０から剥離する際等に、リード部２２の樹脂８０からの脱落等を防止することができる。 The side surface 24a of the upper step portion 22a has a shape that extends upward and laterally in a tapered shape from the bottom surface. As shown in FIG. 3A, the upper surface of the upper step portion 22a has a shape similar to that of the lower step portion 22b, and is formed in a substantially rectangular shape. In the configuration of FIG. 3, the side surface 24a is generally tapered from the bottom surface of the upper step portion 22a and spreads at substantially the same ratio, and the planar shape of the upper surface of the upper step portion 22a is larger than the upper surface of the lower step portion 22b. Means. Since the side surface 24a of the upper step portion 22a has such a tapered shape, the resin 80 can bite and get caught, and when the conductive substrate 10 is peeled off from the resin 80, the lead portion 22 can be separated from the resin 80. Dropping off can be prevented.
　なお、図１、２に示すように、リード部２２のみならず、ダイパッド部２１も上段部２１ａ及び下段部２１ｂを有する構成としてもよい。これにより、ダイパッド部２１についても、樹脂８０からの脱落等を防止することができる。 As shown in FIGS. 1 and 2, not only the lead portion 22 but also the die pad portion 21 may have an upper step portion 21 a and a lower step portion 21 b. Thereby, the die pad part 21 can also be prevented from falling off from the resin 80.
　次に、図４を用いて、リード部２２の形成方法について説明する。図４は、リード部２２の形成方法を説明するための図である。図４（ａ）は、めっき用レジストマスク３５の一例を示した図である。図４（ｂ）は、めっき用レジストマスク３５を用いためっき加工の一例を示した図である。 Next, a method for forming the lead portion 22 will be described with reference to FIG. FIG. 4 is a view for explaining a method of forming the lead portion 22. FIG. 4A shows an example of the resist mask 35 for plating. FIG. 4B is a diagram showing an example of plating using the resist mask 35 for plating.
　リード部２２は、図４（ａ）に示すように、導電性基板１０の上に３枚のレジスト層３１、３２、３３を被覆し、露光、現像してめっき用レジストマスク３５を作製し、これを用いてめっき加工を行い形成している。導電性基板１０に接触するレジスト層から第１のレジスト層３１とし、最上位のレジストを第３のレジスト層３３とする。中間のレジスト層は第２のレジスト層３２となる。第１のレジスト層３１と第３のレジスト層３３のパターンは、リード部２２の底面形状のパターンとする。また、第１のレジスト層３１と第３のレジスト層３３には、感光する波長が略同一な同種のレジストを使用し、第２のレジスト層３２には、第１及び第３のレジスト層３１、３３と感光する波長が異なる種類のレジストを使用する。これらのレジスト層３１～３３を露光する際、第１及び第３のレジスト層３１、３３は感光し、第２のレジスト層３２は感光しない波長にて露光することにより、第１と第３のレジスト層３１、３３を硬化させ、第２のレジスト層３２を未露光状態にする。これを現像することにより、第１のレジスト層３１と第３のレジスト層３３は、リード部２２の底面形状と略同一で、垂直方向断面の垂直方向の辺（側面２４ｂ）は直線となる。第２のレジスト層３２は、第３のレジスト層３３の開口部３４から第１のレジスト３１の方向に現像されるため、図４（ａ）に示されるように、垂直方向断面の垂直方向の辺は上面側が狭くなる様な（開口部３４の形状は上面側が広がる）テーパー形状になる。第２のレジスト層３２は、未露光状態であり、現像後、露光により硬化処理を行う。このようにして、第２のレジスト層３２がテーパー形状を有するめっき用レジストマスク３５を作製する。 As shown in FIG. 4A, the lead portion 22 covers three resist layers 31, 32, 33 on the conductive substrate 10, and is exposed and developed to produce a resist mask 35 for plating. This is used for plating. The resist layer in contact with the conductive substrate 10 is used as the first resist layer 31, and the uppermost resist is used as the third resist layer 33. The intermediate resist layer becomes the second resist layer 32. The pattern of the first resist layer 31 and the third resist layer 33 is a bottom shape pattern of the lead portion 22. The first resist layer 31 and the third resist layer 33 are made of the same type of resist having the same photosensitive wavelength, and the second resist layer 32 is made of the first and third resist layers 31. , 33 and resists having different wavelengths for exposure are used. When the resist layers 31 to 33 are exposed, the first and third resist layers 31 and 33 are exposed to light, and the second resist layer 32 is exposed at a wavelength that is not exposed to light. The resist layers 31 and 33 are cured, and the second resist layer 32 is brought into an unexposed state. By developing this, the first resist layer 31 and the third resist layer 33 are substantially the same as the bottom shape of the lead portion 22, and the vertical side (side surface 24b) of the vertical cross section becomes a straight line. Since the second resist layer 32 is developed in the direction of the first resist 31 from the opening 34 of the third resist layer 33, as shown in FIG. The sides are tapered so that the upper surface side is narrower (the shape of the opening 34 is wider on the upper surface side). The second resist layer 32 is in an unexposed state and is subjected to a curing process by exposure after development. In this manner, a plating resist mask 35 in which the second resist layer 32 has a tapered shape is produced.
　次に、図４（ｂ）に示されるように、作製されためっき用レジストマスク３５を用いてめっき層２０を形成する。めっき層２０の厚さは、めっき層２０の上面が第３のレジスト層３３に至る前であって、第２のレジスト層３２の間になるように設定する。めっき層２０が第３レジスト層３３までめっきされると、第２のレジスト層３２で上面側が広がるテーパー形状を形成したのに、第３のレジスト層３３でテーパー形状が小さくなってしまう。逆に、第１のレジスト層３１までのめっき層２０では、張り出し形状が形成されず、樹脂８０との密着性を向上させることができない。好ましくは、第２のレジスト層３２の１／２から４／５までにめっき層２０の上面が来るようにめっき厚さを設定する。 Next, as shown in FIG. 4B, the plating layer 20 is formed using the prepared resist mask 35 for plating. The thickness of the plating layer 20 is set so that the upper surface of the plating layer 20 is between the second resist layers 32 before reaching the third resist layer 33. When the plating layer 20 is plated up to the third resist layer 33, the tapered shape of the third resist layer 33 becomes small even though the second resist layer 32 forms a tapered shape whose upper surface side is widened. On the contrary, in the plating layer 20 up to the first resist layer 31, an overhanging shape is not formed, and the adhesion with the resin 80 cannot be improved. Preferably, the plating thickness is set so that the upper surface of the plating layer 20 is between 1/2 and 4/5 of the second resist layer 32.
　第２のレジスト層３２のテーパー形状は、第２のレジスト層３２の厚みや現像工程での現像時間、現像液の吐出圧力等によりテーパーの角度を調整することができる。テーパー角度は、水平方向を基準に任意に設定することができるが、樹脂８０との密着性を考慮すると、３０°～８０°に設定することが好ましく、３０°～６０°に設定することがより好ましい。 The taper shape of the second resist layer 32 can be adjusted by the thickness of the second resist layer 32, the developing time in the developing process, the discharge pressure of the developer, and the like. The taper angle can be arbitrarily set on the basis of the horizontal direction. However, in consideration of the adhesiveness with the resin 80, it is preferably set to 30 ° to 80 °, and preferably set to 30 ° to 60 °. More preferred.
　リード部２２は、上述の３層のレジストマスク３５を使用し、レジストマスク３５の開口部３４にめっきを行い、めっき層２０を形成することにより形成される。めっき層２０は、レジストマスク３５の形状に倣い形成されるので、めっき層２０の側面は、上段部２０ａ（第２レジスト層部）と下段部２０ｂ（第１レジスト層部）に分かれる。下段部２０ｂの側面は垂直方向に直線部を有し、上段部２０ａの側面は、めっき層２０の周縁に沿い上部が広がるテーパー形状となる。 The lead portion 22 is formed by using the above-described three-layer resist mask 35 and plating the opening 34 of the resist mask 35 to form the plating layer 20. Since the plating layer 20 is formed following the shape of the resist mask 35, the side surface of the plating layer 20 is divided into an upper step portion 20a (second resist layer portion) and a lower step portion 20b (first resist layer portion). The side surface of the lower step portion 20 b has a linear portion in the vertical direction, and the side surface of the upper step portion 20 a has a tapered shape in which the upper portion extends along the periphery of the plating layer 20.
　リード部２２のめっき層２０の下段部２０ｂの厚みは、第１のレジスト層３１の厚みとなる。めっき層２０の下段部２０ｂの厚みは特に限定はないが、第１のレジスト層３１の厚みを考慮すると、１０μｍ～２５μｍが好ましい。上段部２０ａの厚みは、特に限定はないが、上述のように、めっき層２０は、第２のレジスト層３２の２／５から４／５までの厚さとすることが好ましいことや、このテーパー部が樹脂８０との密着性を向上させることから、２０μｍ～５０μｍに設定することが好ましい。 The thickness of the lower step portion 20 b of the plating layer 20 of the lead portion 22 is the thickness of the first resist layer 31. The thickness of the lower step portion 20b of the plating layer 20 is not particularly limited, but is preferably 10 μm to 25 μm in consideration of the thickness of the first resist layer 31. The thickness of the upper step portion 20a is not particularly limited, but as described above, the plating layer 20 preferably has a thickness of 2/5 to 4/5 of the second resist layer 32, or this taper. It is preferable to set the thickness to 20 μm to 50 μm because the portion improves the adhesion to the resin 80.
　これにより、リード部２２の断面形状が上段部２２ａ（第２レジスト層部）と下段部２２ｂ（第１レジスト層部）に分かれる。そして、下段部２２ｂの側面２４ｂは垂直方向に直線部を有し、上段部２２ａの側面２４ａは、めっき層周縁に沿い上部が広がるテーパー形状となるリード部２２を形成できる。 Thereby, the cross-sectional shape of the lead portion 22 is divided into an upper step portion 22a (second resist layer portion) and a lower step portion 22b (first resist layer portion). The side surface 24b of the lower step portion 22b has a straight portion in the vertical direction, and the side surface 24a of the upper step portion 22a can form a lead portion 22 having a tapered shape in which the upper portion extends along the periphery of the plating layer.
　本発明の実施形態に係る半導体素子搭載用基板５０及び半導体装置１００のリード部２０の形状は、例えば、特許文献１に記載された発明と比較して以下の利点がある。特許文献１では、形成したレジストマスクを超えて導電性金属を電着させることで、リード部の上端部周縁に張り出し部を有する形状が記載されている。この方法では、オーバーハング量をコントロールすることは難しく、形成するめっき層の全てが同じ張り出し長さにならない問題や、張り出し部が大きくなると隣のめっき層と繋がってしまう問題が発生している。 The shape of the semiconductor element mounting substrate 50 and the lead portion 20 of the semiconductor device 100 according to the embodiment of the present invention has the following advantages as compared with the invention described in Patent Document 1, for example. Patent Document 1 describes a shape having a protruding portion on the periphery of the upper end portion of the lead portion by electrodepositing a conductive metal beyond the formed resist mask. In this method, it is difficult to control the amount of overhang, and there is a problem that not all of the plating layers to be formed have the same overhang length or a problem that the overhang portion is connected to the adjacent plating layer.
　本発明の実施形態に係る半導体素子搭載用基板５０及び半導体装置１００では、リード部２２が上段部２２ａと下段部２２ｂに分かれ、上段部２２ａはテーパー形状になっている。上段部２２ａのテーパー形状は、第２のレジスト層３２で形成されるので、形状を制御することが可能であり、張り出し部の厚さ、長さ、テーパー角度を任意に設定できる。また、内部端子として機能する上段部２２ａの上面は、ほぼフラットな面を得ることができる。また、特許文献１の形状においては、張り出し部が大きくなると、めっき後にレジスト層を除去する際、張り出し部の根元部にレジストが残りやすい。しかしながら、本発明の実施形態に係る半導体素子搭載用基板５０及び半導体装置１００のリード部２０の形状であれば、張り出し部は上側部が上方及び側方に広がる様なテーパー形状であり、レジストマスク３５は除去されやすい。 In the semiconductor element mounting substrate 50 and the semiconductor device 100 according to the embodiment of the present invention, the lead portion 22 is divided into an upper step portion 22a and a lower step portion 22b, and the upper step portion 22a is tapered. Since the taper shape of the upper step portion 22a is formed by the second resist layer 32, the shape can be controlled, and the thickness, length, and taper angle of the overhang portion can be arbitrarily set. In addition, the upper surface of the upper step portion 22a that functions as an internal terminal can obtain a substantially flat surface. Moreover, in the shape of patent document 1, when the overhang | projection part becomes large, when removing a resist layer after plating, a resist will remain easily in the root part of an overhang | projection part. However, if the shape of the semiconductor element mounting substrate 50 and the lead portion 20 of the semiconductor device 100 according to the embodiment of the present invention is used, the overhanging portion has a tapered shape such that the upper portion spreads upward and laterally. 35 is easy to remove.
　特許文献２では、リード部の断面形状をテーパー形状にする記載がある。この場合、リード部の断面形状を逆台形にしたことで、半導体素子を搭載し、ワイヤーボンディングした後に樹脂封止する際、電極層の側面部は導電性基板に対して鋭角になった。これにより、封止樹脂が回り込みづらくなり、場合によっては、ボイド等未充填が発生する場合があった。また、リード部基部付近の封止樹脂は、当然、この角度に倣い形成されるため、先端が鋭角な形状となり強度的にも弱く、この封止樹脂部の先端の欠けや剥がれが発生し易いという問題があった。また、レジスト層はテーパー形状を形成するため、底面の寸法精度は劣っていた。 Patent Document 2 describes that the cross-sectional shape of the lead portion is tapered. In this case, since the cross-sectional shape of the lead portion is an inverted trapezoid, the side surface portion of the electrode layer has an acute angle with respect to the conductive substrate when the semiconductor element is mounted and resin-sealed after wire bonding. Thereby, it becomes difficult for the sealing resin to wrap around, and in some cases, an unfilled void or the like may occur. In addition, the sealing resin near the base of the lead portion is naturally formed following this angle, so that the tip has an acute shape and is weak in strength, and the tip of the sealing resin portion is likely to be chipped or peeled off. There was a problem. Further, since the resist layer has a tapered shape, the dimensional accuracy of the bottom surface was inferior.
　本発明の実施形態に係る半導体素子搭載用基板５０及び半導体装置１００では、リード部２２が上段部２２ａと下段部２２ｂとに分かれ、下段部２２ｂの側面は、垂直方向に直線部を有しており、リード部２２の底面において導電性基板１０と鋭角になることはない。これにより、樹脂８０の回り込み不具合等の発生を防止できる。また、下段部２２ｂの底面の寸法精度は、第１のレジスト層で露光、現像するため上記テーパー形状に比べて向上する。 In the semiconductor element mounting substrate 50 and the semiconductor device 100 according to the embodiment of the present invention, the lead portion 22 is divided into an upper step portion 22a and a lower step portion 22b, and the side surface of the lower step portion 22b has a straight portion in the vertical direction. Therefore, the bottom surface of the lead portion 22 does not become an acute angle with the conductive substrate 10. Thereby, generation | occurrence | production of the wraparound defect etc. of the resin 80 can be prevented. Further, the dimensional accuracy of the bottom surface of the lower step portion 22b is improved as compared with the tapered shape because the first resist layer is exposed and developed.
　図５は、図３と異なる形状を有するリード部２６を説明するための図である。図５（ａ）は、リード部２６の一例を示した平面図である。図５（ｂ）は、図５（ａ）に示したリード部２６のｙ－ｙ断面図である。図５（ｃ）は、図５（ａ）に示したリード部２６のｚ－ｚ断面図である。 FIG. 5 is a view for explaining a lead portion 26 having a shape different from that in FIG. FIG. 5A is a plan view showing an example of the lead portion 26. FIG. 5B is a yy sectional view of the lead portion 26 shown in FIG. FIG. 5C is a zz sectional view of the lead portion 26 shown in FIG.
　リード部の底面形状は、一般的には、図３（ａ）に示すように略矩形である。しかしながら、図５（ａ）、（ｃ）に示すように、リード部２６の側面２７を構成する各辺に凹凸形状を付加してもよい。凹凸形状を付加することで、樹脂８０との密着性をより向上させることができる。凹凸形状は、例えば、波型、山形形状を連続させたジグザク形状、のこぎり形状等を含む。なお、ジグザク形状の各頂点は丸みを帯びた曲線形状とする。 The bottom shape of the lead portion is generally a substantially rectangular shape as shown in FIG. However, as shown in FIGS. 5A and 5C, an uneven shape may be added to each side constituting the side surface 27 of the lead portion 26. By adding the concavo-convex shape, the adhesion with the resin 80 can be further improved. The uneven shape includes, for example, a wavy shape, a zigzag shape in which a chevron shape is continuous, a saw shape, and the like. Each vertex of the zigzag shape is a rounded curved shape.
　また、図５（ａ）に示すように、上段部２６ａの底面２６ｄ及び上面２６ｃの形状は、底面２６ｄが略長方形の形状であり、上面２６ｃは凹凸形状を有している。上段部２６ａの底面２６ｄは、下段部２６ｂの上面の凹凸形状を包含する長方形状となっている。 Further, as shown in FIG. 5A, the bottom surface 26d and the top surface 26c of the upper step portion 26a have a substantially rectangular bottom surface 26d, and the top surface 26c has an uneven shape. The bottom surface 26d of the upper step portion 26a has a rectangular shape including the uneven shape of the upper surface of the lower step portion 26b.
　また、リード部２６の断面形状は、図５（ａ）、（ｂ）で示したように、リード部２６は、上段部２６ａと下段部２６ｂに分かれ、下段部２６ｂの側面２７ｂは垂直方向に直線部を有し、上段部２６ａの側面２７ａは、リード部周縁に沿い上部が広がるテーパー形状を有する。これと同時に、図５（ａ）、（ｃ）に示すように、上段部２６ａの底面２６ｄの一部には、上段部２６ａと下段部２６ｂの境界に水平部２６ｅを有してもよい。上段部２６ａの底面２６ｄ（上段部と下段部の境界）の一部に水平部２６ｅを有する箇所は、前述のリード部２６の底面形状の各辺に凹凸形状を付加した場合の凹部２７ｃに形成することができる。この凹部２７ｃを形成することで、凹部２７ｃの下面にも樹脂８０を充填することができ、より樹脂８０との密着性を向上させることができる。この凹凸部の凹部の凹み量、つまり凹凸の波の上端と下端の間の振幅の大きさ（長さ）は、下段部２６ｂの厚さ１／２～下段部２６ｂの厚さの３倍程度が好ましい。下段部２６ｂの厚さ１／２未満だと密着性の効果が小さく、３倍を超えると、第１のレジスト層３１を剥離する時、レジスト残りが発生する可能性が高くなる。好ましくは、下段部２６ｂの厚さ程度である。なお、水平部２６ｅは、平坦面を有するので、平坦面２６ｅと呼んでもよいこととする。 5A and 5B, the lead portion 26 is divided into an upper step portion 26a and a lower step portion 26b, and a side surface 27b of the lower step portion 26b is in a vertical direction. The side surface 27a of the upper step portion 26a has a tapered shape having an upper portion extending along the periphery of the lead portion. At the same time, as shown in FIGS. 5A and 5C, a part of the bottom surface 26d of the upper step portion 26a may have a horizontal portion 26e at the boundary between the upper step portion 26a and the lower step portion 26b. A portion having a horizontal portion 26e at a part of the bottom surface 26d (the boundary between the upper step portion and the lower step portion) of the upper step portion 26a is formed in a recess portion 27c when an uneven shape is added to each side of the bottom shape of the lead portion 26 described above. can do. By forming the recess 27c, the lower surface of the recess 27c can be filled with the resin 80, and the adhesion with the resin 80 can be further improved. The concave amount of the concave portion of the concave / convex portion, that is, the amplitude (length) between the upper and lower ends of the concave / convex wave is about 1/2 times the thickness of the lower step portion 26b to three times the thickness of the lower step portion 26b. Is preferred. If the thickness of the lower step portion 26b is less than ½, the effect of adhesion is small, and if it exceeds three times, the possibility that a resist residue will occur when the first resist layer 31 is peeled off is increased. Preferably, it is about the thickness of the lower step part 26b. Since the horizontal portion 26e has a flat surface, it may be called the flat surface 26e.
　本発明の実施形態に係る半導体装置１００は、上で説明したように、ダイパッド部２１及びリード部２２、２６を上述の形状にすることで、樹脂８０とダイパッド部２１及びリード部２２、２６との密着性を向上することが可能であり、従来の半導体装置に比べ、より小型化、薄型化を図ることが可能となる。 As described above, the semiconductor device 100 according to the embodiment of the present invention has the resin pad 80, the die pad portion 21, the lead portions 22, 26, and the like by forming the die pad portion 21 and the lead portions 22, 26 as described above. Thus, it is possible to further reduce the size and thickness as compared with the conventional semiconductor device.
　［半導体素子搭載用基板の製造方法］
　次に、図６を参照して本発明の実施形態に係る半導体素子搭載用基板の製造方法について説明する。図６は、本発明の実施形態に係る半導体素子搭載用基板の製造方法の一例の一連の工程を示した図である。 [Manufacturing method of semiconductor element mounting substrate]
Next, a method for manufacturing a semiconductor element mounting substrate according to an embodiment of the present invention will be described with reference to FIG. FIG. 6 is a diagram showing a series of steps of an example of a method for manufacturing a semiconductor element mounting substrate according to an embodiment of the present invention.
　図６（ａ）は、基板用意工程の一例を示した図である。図６（ａ）に示されるように、本発明の実施形態に係る半導体素子搭載用基板５０を製造するに当たり、まずは導電性基板１０を用意する。使用する導電性基板１０の材質は、導電性が得られるものであれば特に限定はないが、一般的には金属材料が用いられ、例えば、ＳＵＳ材またはＣｕあるいはＣｕ合金等が使用される。 FIG. 6A is a diagram showing an example of the substrate preparation process. As shown in FIG. 6A, in manufacturing the semiconductor element mounting substrate 50 according to the embodiment of the present invention, first, the conductive substrate 10 is prepared. The material of the conductive substrate 10 to be used is not particularly limited as long as conductivity can be obtained. Generally, a metal material is used, and for example, a SUS material or Cu or Cu alloy is used.
　図６（ｂ）は、レジスト被覆工程の一例を示した図である。レジスト被覆工程では、導電性基板１０の表・裏面全体を、レジストで被う。なお、表面側は、３枚のレジスト層３１～３３を被覆する。裏面は１枚のレジスト層３０を被覆する。表面側は３枚のレジスト層３１～３３は、導電性基板１０側より、第１のレジスト層３１、第２のレジスト層３２、第３のレジスト層３３とする。第１のレジスト層３１、第３のレジスト層３３は、感光する波長が略同一の同種のレジスト層とする。第２のレジスト層３２は感光する波長が第１及び第３のレジスト層３１、３３と異なる種類のレジスト層を使用する。使用するレジストとしては、ドライフィルムレジストのラミネート、又は液状レジストの塗布及び乾燥によるレジスト層の被覆等、従来からの公知の方法を用いて行うことができる。 FIG. 6B is a diagram showing an example of a resist coating process. In the resist coating step, the entire front and back surfaces of the conductive substrate 10 are covered with a resist. Note that the surface side covers the three resist layers 31 to 33. The back surface covers one resist layer 30. The three resist layers 31 to 33 on the front side are a first resist layer 31, a second resist layer 32, and a third resist layer 33 from the conductive substrate 10 side. The first resist layer 31 and the third resist layer 33 are the same kind of resist layers having substantially the same wavelength for exposure. As the second resist layer 32, a resist layer having a different wavelength from that of the first and third resist layers 31 and 33 is used. As a resist to be used, a conventionally known method such as laminating a dry film resist or coating a resist layer by applying and drying a liquid resist can be used.
　図６（ｃ）は、レジストマスク形成工程の一例を示した図である。詳細には、レジストマスク形成工程は、露光工程、現像工程及び硬化処理工程を有する。露光工程では、前のレジスト被覆工程で導電性基板１０の表・裏面にレジストを被覆する。その後、表面側は第１のレジスト層３１、第３のレジスト層３３が感光し、第２のレジスト層３２が感光しない波長の光で露光する。裏面側は、裏面のレジスト層３０が感光する波長の光で露光する。この時、そのレジスト上に表面は所望のダイパッド部２１やリード部２２を組とした複数の組を配置したパターン、裏面は全面を覆うパターンが形成されたマスク（紫外光遮蔽ガラスマスク）を被せ、露光を行う。 FIG. 6C shows an example of a resist mask forming process. Specifically, the resist mask formation process includes an exposure process, a development process, and a curing process. In the exposure process, the front and back surfaces of the conductive substrate 10 are coated with a resist in the previous resist coating process. Thereafter, the first resist layer 31 and the third resist layer 33 are exposed on the surface side, and the second resist layer 32 is exposed to light having a wavelength that is not exposed. The back side is exposed with light having a wavelength to which the resist layer 30 on the back side is exposed. At this time, the resist is covered with a mask (ultraviolet light shielding glass mask) on which the surface has a pattern in which a plurality of sets including a desired die pad portion 21 and lead portion 22 are arranged, and the back surface has a pattern covering the entire surface. And exposure.
　なお、第２のレジスト層３２は、第１のレジスト層３１と感光の波長が違うため未露光状態となる。現像工程では、マスクを除去してレジスト層３０～３３を現像する。まず第３レジスト層３３の開口部３４より未露光が除去され、次に第２のレジスト層３２、第１にレジスト層３１と現像される。このため、第２のレジスト層３２は、未露光部であるため第３レジスト層３３側（上部側）から水平方向にも除去されていく。開口部３４の形状は、上面側が広がるテーパー形状になる。第２のレジスト層３２のテーパー形状については、第２のレジスト層３２の厚みや現像工程での現像時間、現像液の吐出圧力等により、現像速度を制御することによりテーパーの角度を調整することができる。その後、第２レジスト層の硬化処理を行う。第２のレジスト層３２の未露光状態であり、露光により硬化させる。このようにして、第２のレジスト層３２にテーパー形状を有するめっき用レジストマスク３５を作製する。 It should be noted that the second resist layer 32 is in an unexposed state because the photosensitive wavelength is different from that of the first resist layer 31. In the development step, the resist layers 30 to 33 are developed by removing the mask. First, unexposed light is removed from the opening 34 of the third resist layer 33, and then developed with the second resist layer 32 and first with the resist layer 31. For this reason, since the second resist layer 32 is an unexposed portion, it is also removed in the horizontal direction from the third resist layer 33 side (upper side). The shape of the opening 34 is a tapered shape in which the upper surface side is widened. Regarding the taper shape of the second resist layer 32, the taper angle is adjusted by controlling the development speed by the thickness of the second resist layer 32, the development time in the development process, the discharge pressure of the developer, and the like. Can do. Thereafter, the second resist layer is cured. The second resist layer 32 is in an unexposed state and is cured by exposure. In this manner, a resist mask for plating 35 having a taper shape on the second resist layer 32 is produced.
　なお、図５で説明したように、リード部２６の底面形状の各辺を凹凸形状にする場合には、露光工程で、リード形状がその旨のパターンになるようにマスクを（紫外光遮蔽ガラスマスク）を被せ、露光を行う。また、各辺の凹凸部の凹部２７ｃの箇所の上段部２６ａの底面２６ｄに水平部２６ｅを有してもよい。この場合は、現像工程において、第２レジスト層３２を現像する際、テーパー形状より現像時間を長くすることで、凹部２７ｃに該当する上段部２６ａと下段部２６ｂの境界である上段部２６ａの底面２６ｄに水平部２６ｅを設けることが可能である。現像時間を調整することで、水平部２６ｅの長さを調整することができる。パターン形状にもよるので状況により都度調整する。 As described with reference to FIG. 5, when each side of the bottom surface shape of the lead portion 26 is formed into an uneven shape, a mask (ultraviolet light shielding glass) is used so that the lead shape becomes a pattern to that effect in the exposure process. A mask is applied and exposure is performed. Moreover, you may have the horizontal part 26e in the bottom face 26d of the upper step part 26a of the recessed part 27c of the uneven | corrugated | grooved part of each side. In this case, when developing the second resist layer 32 in the development step, the development time is made longer than the tapered shape, so that the bottom surface of the upper step portion 26a that is the boundary between the upper step portion 26a and the lower step portion 26b corresponding to the recess portion 27c. It is possible to provide the horizontal part 26e in 26d. By adjusting the development time, the length of the horizontal portion 26e can be adjusted. Because it depends on the pattern shape, it is adjusted according to the situation.
　図６（ｄ）は、めっき工程の一例を示した図である。めっき工程では、図６（ｂ）で形成したレジストマスク３５を用い、開口部３４が形成された導電性基板１０の露出部分にめっきを施して、めっき層２０を形成する。めっきは、第２のレジスト層３２の４／５程度の高さまで行う。これにより、めっき層２０は、第１にレジスト層３１と第２のレジスト層３２の形状に沿って形成されることになる。リード部２２の側面は、上段部２２ａと下段部２２ｂに分かれる。下段部２２ｂの側面２４ｂは垂直方向に直線部を有し、上段部２２ａの側面２４ａは、リード部２２の周縁に沿い上部が広がるテーパー形状を有する形状に形成することができる。 FIG. 6D is a diagram showing an example of the plating process. In the plating step, using the resist mask 35 formed in FIG. 6B, the exposed portion of the conductive substrate 10 in which the opening 34 is formed is plated to form the plated layer 20. Plating is performed to a height of about 4/5 of the second resist layer 32. Thus, the plating layer 20 is first formed along the shapes of the resist layer 31 and the second resist layer 32. The side surface of the lead portion 22 is divided into an upper step portion 22a and a lower step portion 22b. The side surface 24 b of the lower step portion 22 b has a straight line portion in the vertical direction, and the side surface 24 a of the upper step portion 22 a can be formed in a shape having a tapered shape in which the upper portion extends along the periphery of the lead portion 22.
　めっきの種類は、特に限定は無い。例えば、導電性基板１０の表面上に、Ａｕめっき層、第２のＰｄめっき層、Ｎｉめっき層、Ｐｄめっきを順に層状に積み重ねる４層めっき、あるいは、更にＡｕめっきを行う５層めっき等を行う。ダイパッド部２１やリード部２２のめっき厚さも、特に限定は無いが、封止樹脂との密着性を考慮すれば、比較的硬度があり安価であるＮｉめっきを下段側から上段側をまたぐように厚さを設定することが好ましい。また、最表面には、ボンディング性の良いめっき層を必要最低限形成する。 There is no particular limitation on the type of plating. For example, an Au plating layer, a second Pd plating layer, a Ni plating layer, four-layer plating in which Pd plating is stacked in order on the surface of the conductive substrate 10, or five-layer plating for further Au plating is performed. . The plating thickness of the die pad portion 21 and the lead portion 22 is also not particularly limited, but considering the adhesion with the sealing resin, Ni plating, which is relatively hard and inexpensive, extends from the lower side to the upper side. It is preferable to set the thickness. In addition, a plating layer having a good bonding property is formed on the outermost surface as much as necessary.
　図６（ｅ）は、レジスト剥離工程の一例を示した図である。レジスト剥離工程では、硬化しているレジストマスク３５及びレジスト層３０を剥離する。これにより、めっき層２０からなるダイパッド部２１、リード部２２が形成される。 FIG. 6E is a diagram showing an example of a resist stripping process. In the resist stripping step, the cured resist mask 35 and resist layer 30 are stripped. Thereby, the die pad part 21 and the lead part 22 made of the plating layer 20 are formed.
　ダイパッド部２１、リード部２２が形成された導電性基板１０を、必要に応じて所望の寸法に切断することにより、本発明の実施形態に係る半導体素子搭載用基板５０が得られる。 The semiconductor element mounting substrate 50 according to the embodiment of the present invention is obtained by cutting the conductive substrate 10 on which the die pad portion 21 and the lead portion 22 are formed into desired dimensions as necessary.
　このように、上述の各工程を順に経ることにより、本発明の実施形態に係る半導体素子搭載用基板５０が作製される。 Thus, the semiconductor element mounting substrate 50 according to the embodiment of the present invention is manufactured by sequentially performing the above-described steps.
　［半導体装置の製造方法］
　次に、図７を用いて、上述の製造方法によって作製された半導体素子搭載用基板５０を用いて半導体装置１００を製造する半導体装置１００の製造方法の一例について説明する。図７は、本発明の実施形態に係る半導体装置の製造方法の一例の一連の工程を示した図である。 [Method for Manufacturing Semiconductor Device]
Next, an example of a manufacturing method of the semiconductor device 100 for manufacturing the semiconductor device 100 using the semiconductor element mounting substrate 50 manufactured by the above-described manufacturing method will be described with reference to FIG. FIG. 7 is a diagram showing a series of steps in an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
　図７（ａ）は、半導体素子搭載工程の一例を示した図である。半導体素子搭載工程においては、半導体素子搭載用基板５０のダイパッド部２１上に半導体素子６０を搭載する。その際、半導体素子６０は、ダイパッド部２１上に、例えば、銀ペーストや接着剤等を用いて接着固定されてもよい。 FIG. 7A is a diagram showing an example of a semiconductor element mounting process. In the semiconductor element mounting step, the semiconductor element 60 is mounted on the die pad portion 21 of the semiconductor element mounting substrate 50. At that time, the semiconductor element 60 may be bonded and fixed on the die pad portion 21 using, for example, a silver paste or an adhesive.
　図７（ｂ）は、ワイヤーボンディング工程の一例を示した図である。ワイヤーボンディング工程では、ワイヤーボンディングにより、ボンディングワイヤー７０を用いて半導体素子６０の電極６１とリード部２２とを電気的に接続して配線を形成する。 FIG. 7B is a diagram showing an example of the wire bonding process. In the wire bonding step, the wire 61 is formed by electrically connecting the electrode 61 of the semiconductor element 60 and the lead portion 22 using the bonding wire 70 by wire bonding.
　図７（ｃ）は、樹脂封止工程の一例を示した図である。樹脂封止工程では、半導体素子搭載用基板５０の半導体素子６０を搭載した面全体を樹脂８０により封止する。 FIG. 7C is a diagram showing an example of the resin sealing process. In the resin sealing step, the entire surface on which the semiconductor element 60 of the semiconductor element mounting substrate 50 is mounted is sealed with the resin 80.
　図７（ｄ）は、導電性基板除去工程の一例を示した図である。導電性基板除去工程では、樹脂封止部分から、導電性基板１０を除去する。導電性基板１０の除去方法は、溶解液を用いて、導電性基板１０を溶解除去する。あるいは、引き剥がし除去する方法もある。 FIG. 7D is a diagram showing an example of the conductive substrate removing process. In the conductive substrate removal step, the conductive substrate 10 is removed from the resin-encapsulated portion. As a method for removing the conductive substrate 10, the conductive substrate 10 is dissolved and removed using a solution. Alternatively, there is a method of peeling and removing.
　図７（ｅ）は、切断工程の一例を示した図である。最後に、所定の半導体装置１００の寸法になるように切断し、半導体装置１００を完成させる。 FIG. 7E shows an example of the cutting process. Finally, the semiconductor device 100 is completed by cutting to a predetermined size of the semiconductor device 100.
　［光半導体素子搭載用基板および光半導体装置］
　本発明は、半導体装置に限らず、光半導体装置にも適用することができる。以下、図８、図９も用いて説明する。 [Optical semiconductor device mounting substrate and optical semiconductor device]
The present invention can be applied not only to a semiconductor device but also to an optical semiconductor device. Hereinafter, description will be made with reference to FIGS.
　図８は、本発明の実施形態に係る光半導体素子搭載用基板の一例を示す断面図である。光半導体素子搭載用基板５１は、半導体素子搭載用基板５０と構成は変わらない。図８に示されるように、導電性基板１０と、その表面１１上に配置された光半導体素子搭載用のダイパッド部２１と光半導体素子とワイヤボンディン等により接続するためのリード部２２とで構成されている。ダイパッド部２１とリード部２２は、対をなして形成され、それを一組として複数配置される。導電性基板１０は、表面１１上にめっき層２０が形成される基板であり、電気めっきによりめっき層２０を形成することが可能なように、導電性を有する材料から構成される。使用する導電性基板１０の材質は、導電性が得られれば特に限定はないが、一般的には金属材料が用いられ、例えば、ＣｕまたはＣｕ合金等が使用される。ダイパッド部２１やリード部２２は、導電性基板１０の片面（表面１１）にめっき加工により形成されためっき層２０である。ダイパッド部２１及びリード部２２の本発明の実施形態に係る光半導体素子搭載用基板５１の特徴については、半導体素子搭載用基板５０と同一である。 FIG. 8 is a cross-sectional view showing an example of an optical semiconductor element mounting substrate according to an embodiment of the present invention. The configuration of the optical semiconductor element mounting substrate 51 is the same as that of the semiconductor element mounting substrate 50. As shown in FIG. 8, the conductive substrate 10, the die pad portion 21 for mounting the optical semiconductor element disposed on the surface 11, and the lead portion 22 for connecting the optical semiconductor element to the optical semiconductor element by wire bonding or the like. It is configured. The die pad portion 21 and the lead portion 22 are formed in pairs, and a plurality of them are arranged as a set. The conductive substrate 10 is a substrate on which the plating layer 20 is formed on the surface 11, and is made of a conductive material so that the plating layer 20 can be formed by electroplating. The material of the conductive substrate 10 to be used is not particularly limited as long as conductivity is obtained, but a metal material is generally used, for example, Cu or Cu alloy. The die pad portion 21 and the lead portion 22 are a plating layer 20 formed by plating on one side (surface 11) of the conductive substrate 10. The features of the optical semiconductor element mounting substrate 51 according to the embodiment of the present invention of the die pad portion 21 and the lead portion 22 are the same as those of the semiconductor element mounting substrate 50.
　次に、図９を用いて、光半導体装置について説明する。図９は、本発明の実施形態に係る光半導体装置１０１の一例の断面図である。 Next, the optical semiconductor device will be described with reference to FIG. FIG. 9 is a cross-sectional view of an example of the optical semiconductor device 101 according to the embodiment of the present invention.
　図９に示すように、本発明の実施形態に係る光半導体装置１０１は、ダイパッド部２１に光半導体素子６２が搭載され、光半導体素子６２の電極６３とリード部２２とをボンディングワイヤー７０等を介して接続されている。また、光半導体素子６２及びボンディングワイヤー７０等の接続部を含む周辺部を取り囲む形で、ダイパッド部２１とリード部２２の上に外部樹脂８１が形成されている。また、ダイパッド部２１とリード部２２が対向する間の空間部分にも同時に外部樹脂８１が充填される。外部樹脂８１が取り囲んだ光半導体素子６２と電気的接続部周辺は、透明樹脂９０で充填されている。ダイパッド部２１及びリード部２２は、上面２３及び側面２４は外部樹脂８１及び透明樹脂９０により覆われているが、底面２５は露出している。また、図８で存在していた導電性基板１０は存在しない。導電性基板１０は、外部樹脂８１及び透明樹脂９０により封止が行われた後、除去されている。つまり、図８で示した光半導体素子搭載用基板５１は、まず、外部樹脂８１を封止後、ダイパッド部２１上に光半導体素子６２が搭載され、半導体素子６２の電極６３とリード部２２とがワイヤーボンディングによりボンディングワイヤー７０を介して接続される。その後、外部樹脂８１に開口された光半導体素子６２及びボンディングワイヤー７０等の接続部を含む周辺部を透明樹脂９０により封止が行われる。樹脂封止の後、導電性基板１０が除去されることにより、図９に示すような光半導体装置１０１が作製される。導電性基板１０の除去により露出したダイパッド部２１やリード部２２の底面２５は、外部機器とのはんだ接合するための外部端子となる。 As shown in FIG. 9, in the optical semiconductor device 101 according to the embodiment of the present invention, an optical semiconductor element 62 is mounted on the die pad portion 21, and the electrode 63 and the lead portion 22 of the optical semiconductor element 62 are bonded to the bonding wire 70 and the like. Connected through. In addition, an external resin 81 is formed on the die pad portion 21 and the lead portion 22 so as to surround a peripheral portion including connection portions such as the optical semiconductor element 62 and the bonding wire 70. Further, the external resin 81 is simultaneously filled in the space between the die pad portion 21 and the lead portion 22 facing each other. The optical semiconductor element 62 surrounded by the external resin 81 and the periphery of the electrical connection portion are filled with a transparent resin 90. In the die pad portion 21 and the lead portion 22, the upper surface 23 and the side surface 24 are covered with the external resin 81 and the transparent resin 90, but the bottom surface 25 is exposed. Further, the conductive substrate 10 existing in FIG. 8 does not exist. The conductive substrate 10 is removed after sealing with the external resin 81 and the transparent resin 90. That is, in the optical semiconductor element mounting substrate 51 shown in FIG. 8, first, after sealing the external resin 81, the optical semiconductor element 62 is mounted on the die pad part 21, and the electrode 63 and the lead part 22 of the semiconductor element 62 are mounted. Are connected via a bonding wire 70 by wire bonding. Thereafter, the peripheral portion including the connecting portion such as the optical semiconductor element 62 and the bonding wire 70 opened in the external resin 81 is sealed with the transparent resin 90. After the resin sealing, the conductive substrate 10 is removed, whereby an optical semiconductor device 101 as shown in FIG. 9 is manufactured. The die pad portion 21 and the bottom surface 25 of the lead portion 22 exposed by removing the conductive substrate 10 serve as external terminals for soldering with external devices.
　光半導体装置１０１は、ダイパッド部２１とリード部２２が対に配置されている。光半導体装置１０１の形状は小さいため、外部樹脂８１とダイパッド部２１及びリード部２２との密着性は重要である。本発明の実施形態に係る光半導体装置１０１のダイパッド部２１及びリード部２２のように、上側にテーパー形状を有することで外部樹脂８１との密着性を向上させることが可能である。 In the optical semiconductor device 101, the die pad portion 21 and the lead portion 22 are arranged in pairs. Since the shape of the optical semiconductor device 101 is small, the adhesion between the external resin 81 and the die pad portion 21 and the lead portion 22 is important. Like the die pad portion 21 and the lead portion 22 of the optical semiconductor device 101 according to the embodiment of the present invention, the adhesiveness with the external resin 81 can be improved by having a tapered shape on the upper side.
　更に、図５で説明したように、リード部２２をリード部２６に置き換え、ダイパッド部２１とリード部２６の外形形状の各辺に凹凸を形成し、かつ、リード部２６の側面は、上段部２６ａと下段部２６ｂに分かれる。下段部２６ｂの側面２７ｂは垂直方向に直線部を有し、上段部２６ａの側面２７ａは、リード部周縁に沿い上部が広がるテーパー形状を有する。それとともに、その側面２７の一部には、上段部２６ａと下段部２６ｂの境界（上段部２６ａの底面２６ｄ）に水平部２６ｅを有してもよい。この上段部２６ａの底面２６ｄの一部に水平部２６ｅを有する箇所は、前述のリード部２６の下端部２６ｂの底面形状の各辺に凹凸形状を付加した凹部２７ｃに形成することができる。この凹部２７ｃを形成することで、凹部２７ｃの下面にも外部樹脂８１を充填することができ、より外部樹脂８１との密着性を向上させることができる。これにより、光半導体装置１０１は、より小型化、薄型化を図ることが可能となる。 Furthermore, as explained in FIG. 5, the lead part 22 is replaced with the lead part 26, the unevenness is formed on each side of the outer shape of the die pad part 21 and the lead part 26, and the side surface of the lead part 26 is the upper stage part. 26a and the lower part 26b. The side surface 27b of the lower step portion 26b has a linear portion in the vertical direction, and the side surface 27a of the upper step portion 26a has a tapered shape in which the upper portion extends along the periphery of the lead portion. In addition, a part of the side surface 27 may have a horizontal portion 26e at the boundary between the upper step portion 26a and the lower step portion 26b (the bottom surface 26d of the upper step portion 26a). The portion having the horizontal portion 26e on a part of the bottom surface 26d of the upper step portion 26a can be formed in the concave portion 27c in which an uneven shape is added to each side of the bottom surface shape of the lower end portion 26b of the lead portion 26 described above. By forming the concave portion 27c, the lower surface of the concave portion 27c can be filled with the external resin 81, and the adhesion with the external resin 81 can be further improved. Thereby, the optical semiconductor device 101 can be further reduced in size and thickness.
　［光半導体素子搭載用基板の製造方法および光半導体装置の製造方法］
　次に、光半導体素子搭載用基板５１の製造方法および光半導体装置１０１の製造方法について説明する。光半導体素子搭載用基板５１の製造方法は、半導体素子搭載用基板５０の製造方法と同一である。なお、ダイパッド部２１及びリード部２２のめっき層２０のめっきの種類については、光半導体装置１０１の場合、発光素子（光半導体素子）からの光を効率的に反射させるため、反射率の高い貴金属めっきが最外層に施される。最外層のめっき層は、ＡｇまたはＡｇ合金めっきが光反射率の点から好適である。例えば、導電性基板１０の表面上に、Ａｕめっき層、Ｐｄめっき層、Ｎｉめっき層、Ａｕめっき層、Ａｇめっき層を順に層状に積み重ねる５層めっき等を行うことができる。 [Manufacturing method of substrate for mounting optical semiconductor element and manufacturing method of optical semiconductor device]
Next, a method for manufacturing the optical semiconductor element mounting substrate 51 and a method for manufacturing the optical semiconductor device 101 will be described. The manufacturing method of the optical semiconductor element mounting substrate 51 is the same as the manufacturing method of the semiconductor element mounting substrate 50. In addition, regarding the type of plating of the plating layer 20 of the die pad portion 21 and the lead portion 22, in the case of the optical semiconductor device 101, a noble metal with high reflectivity is used to efficiently reflect light from the light emitting element (optical semiconductor element). Plating is applied to the outermost layer. The outermost plating layer is preferably Ag or Ag alloy plating from the viewpoint of light reflectance. For example, on the surface of the conductive substrate 10, five-layer plating in which an Au plating layer, a Pd plating layer, a Ni plating layer, an Au plating layer, and an Ag plating layer are sequentially stacked can be performed.
　光半導体装置１０１の製造方法については、上述した光半導体素子搭載用基板５１を使用し、外部樹脂８１を樹脂封止する。外部樹脂８１は、光半導体素子６２及びボンディングワイヤー７０等の接続部を含む周辺部を取り囲む形で、ダイパッド部２１とリード部２２の上に充填されている。また、ダイパッド部２１とリード部２２が対向する両者の間の空間部分にも同時に外部樹脂８１が充填される。その後、ダイパッド部２１上に光半導体素子６２が搭載され、光半導体素子６２の電極６３とリード部２２とがワイヤーボンディングによりボンディングワイヤー７０を介して接続される。次に、外部樹脂８１に開口された所定の中央領域に設けられた、光半導体素子６２及びボンディングワイヤー７０等の接続部を含む周辺部を、透明樹脂９０により封止する。樹脂封止の後、導電性基板１０が除去される。最後に所定の寸法になるように切断する。これにより光半導体装置１０１が作製される。 For the method of manufacturing the optical semiconductor device 101, the above-described optical semiconductor element mounting substrate 51 is used and the external resin 81 is resin-sealed. The external resin 81 is filled on the die pad portion 21 and the lead portion 22 so as to surround the peripheral portion including the connecting portion such as the optical semiconductor element 62 and the bonding wire 70. Further, the external resin 81 is simultaneously filled in the space portion between the die pad portion 21 and the lead portion 22 facing each other. Thereafter, the optical semiconductor element 62 is mounted on the die pad portion 21, and the electrode 63 of the optical semiconductor element 62 and the lead portion 22 are connected via the bonding wire 70 by wire bonding. Next, a peripheral portion including a connection portion such as the optical semiconductor element 62 and the bonding wire 70 provided in a predetermined central region opened in the external resin 81 is sealed with a transparent resin 90. After the resin sealing, the conductive substrate 10 is removed. Finally, cut to a predetermined size. Thereby, the optical semiconductor device 101 is manufactured.
　以下、本発明の実施形態に係る半導体素子搭載用基板５０、５１及び半導体装置１００、１０１を作製して実施した実施例について説明する。なお、理解の容易のため、上述の実施形態の構成要素に対応する構成要素については、実施形態と同一の参照符号を付すこととする。 Hereinafter, examples in which the semiconductor element mounting substrates 50 and 51 and the semiconductor devices 100 and 101 according to the embodiment of the present invention are manufactured and implemented will be described. For easy understanding, components corresponding to the components of the above-described embodiment are denoted by the same reference numerals as those of the embodiment.
　［実施例１］
　導電性基材１０として板厚０．２ｍｍのＳＵＳ板（ＳＵＳ４３０）を幅１４０ｍｍの長尺板状に加工し、次に導電性基板１０の表面に厚み０．０１５ｍｍ感光性ドライフィルムレジスト（旭化成イーマテリアルズ社製ＡＤＨ）を、ラミネートロールを用いて貼り付けた。引き続き、その上に、厚み０．０５ｍｍの感光性ドライフィルムレジスト（旭化成イーマテリアルズ社製ＡＱ）、厚み０．０２５ｍｍ感光性ドライフィルムレジスト（旭化成イーマテリアルズ社製ＡＤＨ）を順に貼り付けた。裏面には、厚み０．０４０ｍｍ感光性ドライフィルムレジスト（旭化成イーマテリアルズ社製ＡＱ）をラミネートロールで貼り付けた。 [Example 1]
A SUS plate (SUS430) having a thickness of 0.2 mm is processed into a long plate shape having a width of 140 mm as the conductive base material 10, and then a 0.015 mm thick photosensitive dry film resist (Asahi Kasei Corporation) is formed on the surface of the conductive substrate 10. ADH manufactured by Materials Co., Ltd. was attached using a laminate roll. Subsequently, a photosensitive dry film resist having a thickness of 0.05 mm (AQ manufactured by Asahi Kasei E-Materials Co., Ltd.) and a photosensitive dry film resist having a thickness of 0.025 mm (ADH manufactured by Asahi Kasei E-Materials Co., Ltd.) were sequentially pasted thereon. A 0.040 mm thick photosensitive dry film resist (AQ manufactured by Asahi Kasei E-Materials Co., Ltd.) was attached to the back surface with a laminate roll.
　次に、表面側に半導体素子搭載用のダイパッド部２１と外部と接続するためのリード部２２の所望のパターン、裏面側には裏面全面を覆うパターンを形成すべく、パターンを形成したガラスマスクをドライフィルムレジストの上に被せ、紫外光で露光した。表面側の露光は、第１のレジスト層３１、第３のレジスト層３３が感光し、第２のレジスト層３２が感光しない波長で行った。このため、表面側の第２のレジスト層３２である厚み０．０５ｍｍのドライフィルムは未露光状態になった。裏面側の露光は裏面のレジストが感光する波長で行った。 Next, a glass mask on which a pattern is formed is formed on the front surface side so as to form a desired pattern of the lead part 22 for connecting to the semiconductor device mounting die pad portion 21 and the outside, and a pattern covering the entire back surface on the back surface side. It was covered with a dry film resist and exposed to ultraviolet light. The exposure on the surface side was performed at a wavelength at which the first resist layer 31 and the third resist layer 33 were exposed and the second resist layer 32 was not exposed. For this reason, the dry film with a thickness of 0.05 mm, which is the second resist layer 32 on the surface side, was in an unexposed state. The back side exposure was performed at a wavelength at which the back side resist was exposed.
　なお、リード部２２及びダイパッド部２１の底面形状は矩形で、角部はＲ形状（丸め形状）とした。 In addition, the bottom face shape of the lead part 22 and the die pad part 21 was rectangular, and the corner part was R-shaped (rounded shape).
　その後、炭酸ナトリウム溶液を用いて、紫外光の照射が遮られて感光しなかった未硬化のドライフィルムレジストを溶かす現像処理を行った。現像時間、現像液の吐出圧力等適宜調整することで、第２のレジスト層３２のテーパーの角度が約４５°になるように設定した。その後、露光により第２のレジスト層を硬化処理した。 Thereafter, using a sodium carbonate solution, development processing was performed to dissolve uncured dry film resist that was not exposed to ultraviolet light irradiation. The taper angle of the second resist layer 32 was set to about 45 ° by appropriately adjusting the development time, the discharge pressure of the developer, and the like. Thereafter, the second resist layer was cured by exposure.
　次に、レジスト層が除去されて開口部３４が形成された導電性基材１０の露出部表面に、電気めっきを行った。ダイパッド部２１及びリード部２２を形成するため、Ａｕめっきを約０．０２μｍ、第Ｐｄめっきを０．０２μｍ、Ｎｉめっきを４０μｍ、Ｐｄめっきを０．０５μｍ順次施した。めっき層の厚さは、第２のレジスト層３２の２／３を目安に設定した。 Next, electroplating was performed on the exposed portion surface of the conductive substrate 10 from which the resist layer was removed and the opening 34 was formed. In order to form the die pad portion 21 and the lead portion 22, about 0.02 μm of Au plating, 0.02 μm of Pd plating, 40 μm of Ni plating, and 0.05 μm of Pd plating were sequentially performed. The thickness of the plating layer was set with 2/3 of the second resist layer 32 as a guide.
　最後に、水酸化ナトリウム溶液でドライフィルムレジスト３０～３３を剥離して、導電性基板上１０にダイパッド部２１及びリード部２２を形成した。 Finally, the dry film resists 30 to 33 were peeled off with a sodium hydroxide solution to form the die pad portion 21 and the lead portion 22 on the conductive substrate 10.
　その後、所定寸法に切断することにより、本発明の実施例１に係る半導体素子搭載用基板５０を得た。 Thereafter, the substrate 50 for mounting a semiconductor element according to Example 1 of the present invention was obtained by cutting into predetermined dimensions.
　次いで、作製した半導体素子搭載用基板５０に半導体素子６０を搭載し、半導体素子６０とリード部２２をワイヤーボンディング７０で接続し、半導体素子６０が搭載されている面を樹脂８０で封止した。その後、樹脂封止部分から導電性基材１０を引き剥がし除去した。最後に、所定の半導体装置１００の寸法になるように切断し、実施例１に係る半導体装置１００を完成させた。 Next, the semiconductor element 60 was mounted on the manufactured semiconductor element mounting substrate 50, the semiconductor element 60 and the lead portion 22 were connected by wire bonding 70, and the surface on which the semiconductor element 60 was mounted was sealed with a resin 80. Thereafter, the conductive substrate 10 was peeled off and removed from the resin-encapsulated portion. Finally, the semiconductor device 100 was cut to a predetermined size of the semiconductor device 100 to complete the semiconductor device 100 according to Example 1.
　［実施例２］
　実施例２は、実施例１においてパターンをリード部２６及びダイパッド部２１の矩形の各辺にジグザグ（又は波型）の凹凸形状を付加した。また、ジグザグの各頂点はＲ形状とした。凹部２７ｃの長さは、０．０３ｍｍとした。また、現像工程では、現像時間、現像液の吐出圧力等適宜調整することで、凹部２７ｃに該当する上段部２６ａと下段部２６ｂの境界（上段部２６ａの底面）に水平部を設けるようにした。なお、現像時間は、実施例１より長くした。その他の条件は、実施例１と同様である。 [Example 2]
In Example 2, the pattern was added with zigzag (or corrugated) uneven shapes on the rectangular sides of the lead part 26 and the die pad part 21 in Example 1. In addition, each vertex of the zigzag has an R shape. The length of the recess 27c was 0.03 mm. In the development process, a horizontal portion is provided at the boundary between the upper step portion 26a and the lower step portion 26b (the bottom surface of the upper step portion 26a) corresponding to the recess 27c by appropriately adjusting the developing time, the discharge pressure of the developer, and the like. . The development time was longer than that in Example 1. Other conditions are the same as in the first embodiment.
　図１０は、実施例２に係る半導体素子搭載用基板５１のリード部２６の上面からの拡大図で、リード部の側面の一部の拡大図である。図１０に示されるように、波型の側面を有する柱状の下段部２６ｂの上面上にやはり波型の側面を有する上段部２６ａが設けられ、上段部２６ａの側面が側方及び上方に張り出してテーパー状に形成されていることが分かる。かかる構成により、上段部２６ａの樹脂８０への引っ掛かりが良好となり、樹脂８０とリード部２６との密着性を向上させ、リード部２６の脱落及び剥離を防止することができる。 FIG. 10 is an enlarged view from the upper surface of the lead portion 26 of the semiconductor element mounting substrate 51 according to the second embodiment, and is an enlarged view of a part of the side surface of the lead portion. As shown in FIG. 10, an upper step portion 26a having a corrugated side surface is provided on the upper surface of a columnar lower step portion 26b having a corrugated side surface, and the side surface of the upper step portion 26a projects sideways and upward. It turns out that it forms in the taper shape. With this configuration, the upper portion 26a can be easily caught on the resin 80, the adhesion between the resin 80 and the lead portion 26 can be improved, and the lead portion 26 can be prevented from falling off and peeling off.
　図１１は、実施例２に係る半導体素子搭載用基板５１のリード部２６の裏面からの拡大図で、リード部の裏面側における側面の一部の拡大図である。即ち、リード部２６を導電性基板１０から剥離し、リード部２６のみを裏面から示した図である。図１１に示されるように、柱状の下段部２６ｂの上面上（図１１では下方）に設けられた上段部２６ａの底面２６ｄが下段部２６ｂの上面を包含しており、波型の凹部において平坦面（水平面）２６ｅが形成されている。かかる平坦面２６ｅを上端部２６ａの底面２６ｄに設けることにより、樹脂８０の引っ掛かりが良好になり、樹脂８０とリード部２６との密着性が大幅に向上する。また、上段部２６ａの側面２７ａもテーパー状となっており、樹脂８０とリード部２６との密着性を向上させることができる。 FIG. 11 is an enlarged view from the back surface of the lead portion 26 of the semiconductor element mounting substrate 51 according to the second embodiment, and is an enlarged view of a part of the side surface on the back surface side of the lead portion. That is, the lead part 26 is peeled from the conductive substrate 10 and only the lead part 26 is shown from the back side. As shown in FIG. 11, the bottom surface 26d of the upper step portion 26a provided on the upper surface of the columnar lower step portion 26b (downward in FIG. 11) includes the upper surface of the lower step portion 26b, and is flat in the corrugated recess. A surface (horizontal plane) 26e is formed. By providing the flat surface 26e on the bottom surface 26d of the upper end portion 26a, the resin 80 can be easily caught, and the adhesion between the resin 80 and the lead portion 26 is greatly improved. Further, the side surface 27a of the upper step portion 26a is also tapered, so that the adhesion between the resin 80 and the lead portion 26 can be improved.
　［実施例３］
　実施例３は、光半導体素子搭載用基板５１を作製した例である。実施例３では、実施例１におけるパターンを光半導体装置１０１用のダイパッド部２１とリード部２２が対になった形状に設定した。めっき層２０は、実施例１のめっき層の最表層にＡｇめっき１μｍを追加した。その他は、実施例１と同じである。 [Example 3]
Example 3 is an example in which an optical semiconductor element mounting substrate 51 was produced. In Example 3, the pattern in Example 1 was set to a shape in which the die pad part 21 and the lead part 22 for the optical semiconductor device 101 were paired. For the plating layer 20, 1 μm of Ag plating was added to the outermost layer of the plating layer of Example 1. Others are the same as the first embodiment.
　実施例３の光半導体装置１０１を作製すべく、上で作製した光半導体素子搭載用基板５１を用いて、光半導体素子６２及びボンディングワイヤー７０等の接続部を含む周辺部を取り囲む形で、ダイパッド部２１とリード部２２の外側の表面上に外部樹脂８１を形成した。また、ダイパッド部２１とリード部２２とが対向する間隔をなす空間部分にも同時に外部樹脂８１を形成した。その後、ダイパッド部２１上に光半導体素子６２を搭載し、光半導体素子６２の電極６３とリード部２２とをワイヤーボンディングによりボンディングワイヤー７０を介して接続した。次に、外部樹脂８１に開口された光半導体素子６２及びボンディングワイヤー７０等の接続部を含む周辺部（所定の中央領域）を、透明樹脂９０により封止した。樹脂封止の後、導電性基板１０を除去した。最後に所定の寸法に切断した。これにより光半導体装置１０１を完成させた。 In order to fabricate the optical semiconductor device 101 of the third embodiment, the die pad is formed so as to surround the peripheral portion including the connection portion such as the optical semiconductor element 62 and the bonding wire 70 using the optical semiconductor element mounting substrate 51 manufactured above. An external resin 81 was formed on the outer surfaces of the part 21 and the lead part 22. In addition, an external resin 81 was also formed at the same time in the space where the die pad portion 21 and the lead portion 22 face each other. Then, the optical semiconductor element 62 was mounted on the die pad part 21, and the electrode 63 of the optical semiconductor element 62 and the lead part 22 were connected via the bonding wire 70 by wire bonding. Next, the peripheral portion (predetermined central region) including the connection portion such as the optical semiconductor element 62 and the bonding wire 70 opened in the external resin 81 was sealed with the transparent resin 90. After resin sealing, the conductive substrate 10 was removed. Finally, it was cut into predetermined dimensions. Thus, the optical semiconductor device 101 was completed.
　［比較例１］
　比較例１では、レジスト被覆工程で、導電性基板の両面に厚み０．０２５ｍｍ感光性ドライフィルムレジスト（旭化成イーマテリアルズ社製ＡＱ－４０９６）をラミネートロール貼り付け、露光現像をおこなった。めっき工程では、レジスト層を超えてめっき層を形成した。その他条件は、実施例１と同様である。 [Comparative Example 1]
In Comparative Example 1, a 0.025 mm thick photosensitive dry film resist (AQ-4096 manufactured by Asahi Kasei E-Materials Co., Ltd.) was laminated on both sides of the conductive substrate in the resist coating step, and exposure development was performed. In the plating step, a plating layer was formed beyond the resist layer. Other conditions are the same as in the first embodiment.
　［比較例２］
比較例２では、レジスト被覆工程で導電性基板の表面に厚み０．０５ｍｍの感光性ドライフィルムレジスト（旭化成イーマテリアルズ社製ＡＱ－４０９６）を貼り付けた。裏面には、厚み０．０２５ｍｍ感光性ドライフィルムレジスト（旭化成イーマテリアルズ社製ＡＱ－４０９６）をラミネートロールで貼り付け、露光工程では散乱紫外光用いて露光を行った。その後、現像を行った。散乱紫外光で露光することで、レジスト層は半露光状態となり、テーパー形状のレジストが形成される。めっき工程では、形成されたテーパー形状のレジストマスクの開口部にめっきを行い、逆台形形状のリード部を作製した。その他の条件は実施例１と同じである。 [Comparative Example 2]
In Comparative Example 2, a photosensitive dry film resist (AQ-4096 manufactured by Asahi Kasei E-Materials Co., Ltd.) having a thickness of 0.05 mm was attached to the surface of the conductive substrate in the resist coating step. A 0.025 mm thick photosensitive dry film resist (AQ-4096 manufactured by Asahi Kasei E-Materials Co., Ltd.) was attached to the back surface with a laminate roll, and exposure was performed using scattered ultraviolet light in the exposure process. Thereafter, development was performed. By exposing with scattered ultraviolet light, the resist layer is in a semi-exposed state, and a tapered resist is formed. In the plating step, the opening portion of the formed tapered resist mask was plated to produce a reverse trapezoidal lead portion. Other conditions are the same as those in the first embodiment.
　［評価］
　実施例１、実施例２、実施例３及び比較例１、比較例２については、以下の方法で評価を行った。 [Evaluation]
Example 1, Example 2, Example 3, Comparative Example 1, and Comparative Example 2 were evaluated by the following methods.
　半導体素子搭載用基板において、リード部の底面形状寸法を各２０リード測定し、そのばらつきを確認した。 In the semiconductor element mounting substrate, the shape of the bottom surface of the lead part was measured for 20 leads, and the variation was confirmed.
　実施例１、比較例１においては、設定値±０．００３ｍｍ以内、実施例２及び実施例３は設定値±０．００４ｍｍと良好であったが、比較例２では、設定値±０．０１ｍｍとばらつきが大きかった。 In Example 1 and Comparative Example 1, the set value was within ± 0.003 mm, and in Examples 2 and 3, the set value was ± 0.004 mm, but in Comparative Example 2, the set value ± 0.01 mm. And the variation was large.
　また、半導体素子搭載用基板の製作工程のレジスト剥離工程で、レジスト残り不具合があるか顕微鏡で１００枚観察した。その結果、実施例１及び実施例２、実施例３、比較例２に関してはレジスト残りの発生が無かったが、比較例１では、一部リード部に発生が見られた。 In addition, in the resist stripping process of the manufacturing process of the substrate for mounting semiconductor elements, 100 pieces were observed with a microscope to see if there was a resist residue defect. As a result, no residual resist was generated in Example 1, Example 2, Example 3, and Comparative Example 2, but in Comparative Example 1, generation was partially observed in the lead portion.
　また、この半導体素子搭載用基板を使用して半導体素子を搭載し樹脂封止後、導電性基板を引き剥がし除去工程で、リード部が導電性基板に残る不具合があるか観察を行った。この結果、実施例１、実施例２、実施例３、比較例１、比較例２では封止樹脂と導電性基板との間でリード部が導電性基板に残る不具合はなく良好であった。実施例１、実施例２及び実施例３においても十分封止樹脂と密着性を確保していることが確認できた。 In addition, after mounting the semiconductor element using this semiconductor element mounting substrate and sealing with resin, the conductive substrate was peeled off, and it was observed whether there was a defect that the lead portion remained on the conductive substrate. As a result, in Example 1, Example 2, Example 3, Comparative Example 1, and Comparative Example 2, there was no problem that the lead portion remained on the conductive substrate between the sealing resin and the conductive substrate, which was good. Also in Example 1, Example 2 and Example 3, it was confirmed that sufficient adhesion with the sealing resin was secured.
　以上、本発明の好ましい実施形態及び実施例について詳説したが、本発明は、上述した実施形態及び実施例に制限されることはなく、本発明の範囲を逸脱することなく、上述した実施形態及び実施例に種々の変形及び置換を加えることができる。 The preferred embodiments and examples of the present invention have been described in detail above. However, the present invention is not limited to the above-described embodiments and examples, and the above-described embodiments and examples can be performed without departing from the scope of the present invention. Various modifications and substitutions can be made to the embodiments.
　本願は、日本特許庁に２０１６年２月２５日に出願された基礎出願２０１６－３４９１３号の優先権を主張するものであり、その全内容を参照によりここに援用する。 This application claims priority of the basic application 2016-34913 filed with the Japan Patent Office on February 25, 2016, the entire contents of which are incorporated herein by reference.
　１０　　導電性基板
　２０　　めっき層
　２１　　ダイパッド部
　２２、２６　　リード部
　２２ａ、２６ａ　　上段部
　２２ｂ、２６ｂ　　下段部
　２３　　上面
　２４、２４ａ、２４ｂ、２７、２７ａ、２７ｂ　　側面
　２５　　裏面
　２６ｃ　　上段部の上面
　２６ｄ　　上段部の底面
　２６ｅ　　水平部
　２７ｃ　　凹部
　３１　　第１のレジスト層
　３２　　第２のレジスト層
　３３　　第３のレジスト層
　３４　　開口部
　３５　　めっき用レジストマスク
　５０　　半導体素子搭載用基板
　５１　　光半導体素子搭載用基板
　６０　　半導体素子
　６１、６３　　電極
　６２　　光半導体素子
　７０　　ボンディングワイヤー
　８０　　樹脂
　８１　　外部樹脂
　９０　　透明樹脂
　１００　　半導体装置
　１０１　　光半導体装置 DESCRIPTION OF SYMBOLS 10 Conductive substrate 20 Plating layer 21 Die pad part 22, 26 Lead part 22a, 26a Upper part 22b, 26b Lower part 23 Upper surface 24, 24a, 24b, 27, 27a, 27b Side surface 25 Back surface 26c Upper surface 26d Upper part part 26d Bottom surface 26e Horizontal portion 27c Recessed portion 31 First resist layer 32 Second resist layer 33 Third resist layer 34 Opening portion 35 Plating resist mask 50 Semiconductor device mounting substrate 51 Optical semiconductor device mounting substrate 60 Semiconductor device 61, 63 Electrode 62 Optical Semiconductor Element 70 Bonding Wire 80 Resin 81 External Resin 90 Transparent Resin 100 Semiconductor Device 101 Optical Semiconductor Device

Claims (18)

  1. 　半導体素子搭載後に除去可能な導電性基板と、
    　該導電性基板の表面上に設けられた半導体素子搭載領域と、
    　該半導体素子搭載領域の周囲の前記導電性基板の前記表面上の所定領域に設けられためっき層からなるリード部と、を有し、
    　該リード部は、前記導電性基板の前記表面と略垂直な側面を有して前記表面から柱状に上方に延びる下段部と、
    　該下段部の上面上に底面を有し、該底面からテーパー状に上方及び側方に広がる側面を有する上段部と、を有する半導体素子搭載用基板。     A conductive substrate that can be removed after mounting the semiconductor element;
    A semiconductor element mounting region provided on the surface of the conductive substrate;
    A lead portion made of a plating layer provided in a predetermined region on the surface of the conductive substrate around the semiconductor element mounting region;
    The lead portion has a side surface substantially perpendicular to the surface of the conductive substrate, and a lower step portion extending upward in a column shape from the surface;
    A semiconductor element mounting substrate having a bottom surface on an upper surface of the lower step portion, and an upper step portion having a side surface extending upward and sideward in a tapered shape from the bottom surface.
  2. 　前記リード部の前記上段部の前記側面のテーパー角度は、３０°～８５°の範囲である請求項１に記載の半導体素子搭載用基板。 2. The semiconductor element mounting substrate according to claim 1, wherein a taper angle of the side surface of the upper portion of the lead portion is in a range of 30 ° to 85 °.
  3. 　前記リード部の前記下段部の前記側面は凹凸を有する平面形状を有し、
    　前記リード部の前記上段部の前記底面は、前記下段部の上面を包含する平面形状を有し、前記凹凸の凹部を覆う領域が露出した平坦面を有する請求項１に記載の半導体素子搭載用基板。     The side surface of the lower step portion of the lead portion has a planar shape having irregularities,
    2. The semiconductor element mounting device according to claim 1, wherein the bottom surface of the upper step portion of the lead portion has a planar shape including an upper surface of the lower step portion, and has a flat surface in which a region covering the concave portion of the unevenness is exposed. substrate.
  4. 　前記リード部の前記上段部の上面及び水平断面は、前記下段部の平面形状と類似した平面形状を有する請求項１に記載の半導体素子搭載用基板。 2. The semiconductor element mounting substrate according to claim 1, wherein an upper surface and a horizontal cross section of the upper portion of the lead portion have a planar shape similar to the planar shape of the lower portion.
  5. 　前記半導体素子搭載領域には、前記リード部と同様の形状を有するめっき層からなるダイパッド部が設けられている請求項１に記載の半導体素子搭載用基板。 The semiconductor element mounting substrate according to claim 1, wherein a die pad portion made of a plating layer having a shape similar to that of the lead portion is provided in the semiconductor element mounting region.
  6. 　前記リード部は、前記半導体素子搭載領域の周囲に複数個設けられている請求項１に記載の半導体素子搭載用基板。 The semiconductor element mounting substrate according to claim 1, wherein a plurality of the lead portions are provided around the semiconductor element mounting region.
  7. 　前記リード部は、前記半導体素子搭載領域に対応して１個だけ対になるように設けられている請求項１に記載の半導体素子搭載用基板。 2. The semiconductor element mounting substrate according to claim 1, wherein only one lead portion is provided corresponding to the semiconductor element mounting region.
  8. 　半導体素子と、
    　該半導体素子の周囲の所定領域に設けられ、形状の異なる上段部と下段部とを有するめっき層からなるリード部と、
    　前記半導体素子の電極と前記リード部の前記上段部の上面とを電気的に接続する接続手段と、
    　少なくとも前記リード部の前記下段部の底面が露出するように前記半導体素子、前記リード部及び前記接続手段を封止する樹脂と、を有し、
    　前記リード部の前記下段部は、前記底面から上方に垂直に延びる側面を有する柱状形状を有し、
    　前記リード部の前記上段部は、前記下段部の上面上に底面を有し、該底面からテーパー状に上方及び側方に側面が広がるテーパー形状を有する半導体装置。     A semiconductor element;
    A lead portion made of a plating layer provided in a predetermined region around the semiconductor element and having an upper step portion and a lower step portion having different shapes;
    Connection means for electrically connecting the electrode of the semiconductor element and the upper surface of the upper portion of the lead portion;
    A resin that seals the semiconductor element, the lead portion, and the connecting means so that at least a bottom surface of the lower step portion of the lead portion is exposed;
    The lower step portion of the lead portion has a columnar shape having a side surface extending vertically upward from the bottom surface,
    The semiconductor device having a taper shape in which the upper step portion of the lead portion has a bottom surface on an upper surface of the lower step portion, and a side surface is tapered upward and laterally from the bottom surface.
  9. 　前記リード部の前記上段部の前記テーパー形状のテーパー角度は、３０°～８５°の範囲である請求項８に記載の半導体装置。 9. The semiconductor device according to claim 8, wherein a taper angle of the taper shape of the upper portion of the lead portion is in a range of 30 ° to 85 °.
  10. 　前記リード部の前記下段部の前記側面は波型の凹凸を有する平面形状を有し、
    　前記リード部の前記上段部の前記底面は、前記下段部の上面を包含する平面形状を有し、前記波型の凹部を覆う領域が露出した平坦面を有する請求項８に記載の半導体装置。     The side surface of the lower step portion of the lead portion has a planar shape having corrugated irregularities,
    The semiconductor device according to claim 8, wherein the bottom surface of the upper step portion of the lead portion has a planar shape including an upper surface of the lower step portion, and has a flat surface in which a region covering the corrugated recess is exposed.
  11. 　前記半導体素子は、めっき層からなるダイパッド部上に搭載されて設けられ、
    　該ダイパッド部は、前記リード部と同様の形状を有している請求項８に記載の半導体装置。     The semiconductor element is provided mounted on a die pad portion made of a plating layer,
    The semiconductor device according to claim 8, wherein the die pad portion has a shape similar to that of the lead portion.
  12. 　光半導体素子を搭載する領域を有するダイパッド部と、
    　前記ダイパッド部と対に設けられ、形状の異なる上段部と下段部とを有するめっき層からなるリード部と、
    　前記ダイパッド部に搭載された光半導体素子と、
    　該光半導体素子の電極と前記リード部の前記上段部の上面とを電気的に接続する接続手段と、
    　前記光半導体素子及び前記接続手段を含む前記ダイパッド部上及び前記リード部上の所定の中央領域を封止する透明樹脂と、
    　前記ダイパッド部及び前記リード部の底面が露出するように、前記ダイパッド部及び前記リード部の底面以外の前記ダイパッド部と前記リード部との間の領域と、前記ダイパッド部及び前記リード部の所定の外側領域とを封止する外部樹脂と、を有し、
    　前記リード部の前記下段部は、前記底面から上方に垂直に延びる側面を有する柱状形状を有し、
    　前記リード部の前記上段部は、前記下段部の上面上に底面を有し、該底面からテーパー状に上方及び側方に側面が広がるテーパー形状を有する光半導体装置。     A die pad portion having a region for mounting an optical semiconductor element;
    A lead portion comprising a plating layer provided in a pair with the die pad portion and having an upper step portion and a lower step portion having different shapes;
    An optical semiconductor element mounted on the die pad portion;
    Connection means for electrically connecting the electrode of the optical semiconductor element and the upper surface of the upper portion of the lead portion;
    A transparent resin that seals a predetermined central region on the die pad portion and the lead portion including the optical semiconductor element and the connection means;
    A region between the die pad portion and the lead portion other than the bottom surface of the die pad portion and the lead portion, and predetermined areas of the die pad portion and the lead portion so that the bottom surfaces of the die pad portion and the lead portion are exposed. An external resin that seals the outer region;
    The lower step portion of the lead portion has a columnar shape having a side surface extending vertically upward from the bottom surface,
    The optical semiconductor device, wherein the upper portion of the lead portion has a tapered shape having a bottom surface on the upper surface of the lower step portion, and a side surface extending upward and laterally from the bottom surface.
  13. 　前記リード部の前記上段部の前記テーパー形状のテーパー角度は、３０°～８５°の範囲である請求項１２に記載の光半導体装置。 13. The optical semiconductor device according to claim 12, wherein a taper angle of the tapered shape of the upper portion of the lead portion is in a range of 30 ° to 85 °.
  14. 　前記リード部の前記下段部の前記側面は凹凸を有する平面形状を有し、
    　前記リード部の前記上段部の前記底面は、前記下段部の上面を包含する平面形状を有し、前記凹凸の凹部を覆う領域が露出した平坦面を有する請求項１２に記載の光半導体装置。     The side surface of the lower step portion of the lead portion has a planar shape having irregularities,
    The optical semiconductor device according to claim 12, wherein the bottom surface of the upper step portion of the lead portion has a planar shape including an upper surface of the lower step portion, and has a flat surface in which a region covering the concave portion of the unevenness is exposed.
  15. 　導電性基板の表面上に、第１の感光波長を有する第１のレジストで被覆した第１のレジスト層、該第１のレジスト層上に第２の感光波長を有する第２のレジストで被覆した第２のレジスト層、該第２のレジスト層上に前記第１のレジストで被覆した第３のレジスト層を順次形成する工程と、
    　第１の露光により、前記第１及び第３のレジスト層を硬化させるとともに、前記第２のレジスト層を硬化させていない状態で現像を行い、前記第２のレジスト層の上部が前記第１及び第３のレジスト層よりも内側に削れ、テーパー状の形状を有するパターンを形成する工程と、
    　第２の露光により、第２のレジスト層を硬化させる工程と、
    　前記第１乃至第３のレジスト層からなるパターンをめっきマスクとしてめっきを行い、前記第１のレジスト層により形成された部分が柱状形状を有し、前記第２のレジスト層により形成された部分がテーパー形状を有するめっき層を形成する工程と、
    　前記めっきマスクを除去する工程と、を有する半導体素子搭載用基板の製造方法。     A first resist layer coated with a first resist having a first photosensitive wavelength is coated on the surface of the conductive substrate, and a second resist having a second photosensitive wavelength is coated on the first resist layer. Sequentially forming a second resist layer, and a third resist layer coated with the first resist on the second resist layer;
    In the first exposure, the first and third resist layers are cured, and development is performed in a state where the second resist layer is not cured, and the upper portion of the second resist layer is the first and third resist layers. A step of forming a pattern having a tapered shape that is scraped inward from the third resist layer;
    A step of curing the second resist layer by the second exposure;
    Plating is performed using the pattern composed of the first to third resist layers as a plating mask, the portion formed by the first resist layer has a columnar shape, and the portion formed by the second resist layer is Forming a plating layer having a tapered shape;
    And a step of removing the plating mask.
  16. 　請求項１５に記載の半導体素子搭載用基板の製造方法により製造された半導体素子搭載用基板の所定の半導体素子搭載領域に、半導体素子を搭載する工程と、
    　該半導体素子の電極と前記めっき層の上面とを接続手段により電気的に接続する工程と、
    　前記めっき層の底面及び前記半導体素子の前記電極が設けられていない面のみが露出するように、前記半導体素子、前記めっき層及び前記接続手段を樹脂で封止する工程と、を有する半導体装置の製造方法。     Mounting a semiconductor element on a predetermined semiconductor element mounting region of a semiconductor element mounting substrate manufactured by the method for manufacturing a semiconductor element mounting substrate according to claim 15;
    Electrically connecting the electrode of the semiconductor element and the upper surface of the plating layer by connecting means;
    Sealing the semiconductor element, the plating layer, and the connecting means with a resin so that only the bottom surface of the plating layer and the surface of the semiconductor element on which the electrode is not provided are exposed. Production method.
  17. 　請求項１５に記載の半導体素子搭載用基板の製造方法により製造された半導体素子搭載用基板の前記めっき層は、ダイパッド部とリード部であり、
    　ダイパッド部に、半導体素子を搭載する工程と、
    　該半導体素子の電極と前記リード部の上面とを接続手段により電気的に接続する工程と、
    　前記リード部及び前記ダイパッド部の底面のみが露出するように、前記半導体素子、前記リード部及び前記接続手段を樹脂で封止する工程と、を有する半導体装置の製造方法。     The plating layer of the semiconductor element mounting substrate manufactured by the method for manufacturing a semiconductor element mounting substrate according to claim 15 is a die pad portion and a lead portion.
    Mounting a semiconductor element on the die pad portion;
    Electrically connecting the electrode of the semiconductor element and the upper surface of the lead portion by connecting means;
    Sealing the semiconductor element, the lead portion, and the connecting means with a resin so that only the bottom surfaces of the lead portion and the die pad portion are exposed.
  18. 　請求項１５に記載の半導体素子搭載用基板の製造方法により製造された半導体素子搭載用基板の前記めっき層は、ダイパッド部とリード部であり、
    　ダイパッド部に、光半導体素子を搭載する工程と、
    　該光半導体素子の電極と前記リード部の上面とを接続手段により電気的に接続する工程と、
    　前記リード部及び前記ダイパッド部の底面のみが露出するように、前記光半導体素子及び前記接続手段が設けられた所定の中央領域よりも外側の領域及び前記リード部と前記ダイパッド部との間の領域を外部樹脂で封止する工程と、
    　前記所定の中央領域を透明樹脂で封止する工程と、を有する光半導体装置の製造方法。     The plating layer of the semiconductor element mounting substrate manufactured by the method for manufacturing a semiconductor element mounting substrate according to claim 15 is a die pad portion and a lead portion.
    Mounting an optical semiconductor element on the die pad portion;
    Electrically connecting the electrode of the optical semiconductor element and the upper surface of the lead portion by connecting means;
    A region outside the predetermined central region where the optical semiconductor element and the connection means are provided, and a region between the lead portion and the die pad portion so that only the bottom surfaces of the lead portion and the die pad portion are exposed. Sealing with external resin,
    Sealing the predetermined central region with a transparent resin.
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