CN102324412B - 无基岛预填塑封料先镀后刻引线框结构及其生产方法 - Google Patents

无基岛预填塑封料先镀后刻引线框结构及其生产方法 Download PDF

Info

Publication number
CN102324412B
CN102324412B CN2011102683574A CN201110268357A CN102324412B CN 102324412 B CN102324412 B CN 102324412B CN 2011102683574 A CN2011102683574 A CN 2011102683574A CN 201110268357 A CN201110268357 A CN 201110268357A CN 102324412 B CN102324412 B CN 102324412B
Authority
CN
China
Prior art keywords
metal substrate
back side
photoresist film
lead frame
pin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN2011102683574A
Other languages
English (en)
Other versions
CN102324412A (zh
Inventor
梁志忠
谢洁人
吴昊
耿丛正
夏文斌
郁科峰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JCET Group Co Ltd
Original Assignee
Jiangsu Changjiang Electronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Changjiang Electronics Technology Co Ltd filed Critical Jiangsu Changjiang Electronics Technology Co Ltd
Priority to CN2011102683574A priority Critical patent/CN102324412B/zh
Publication of CN102324412A publication Critical patent/CN102324412A/zh
Priority to PCT/CN2012/001160 priority patent/WO2013037186A1/en
Application granted granted Critical
Publication of CN102324412B publication Critical patent/CN102324412B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828Etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861Lead-frames fixed on or encapsulated in insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49579Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582Metallic layers on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本发明涉及一种无基岛预填塑封料先镀后刻引线框结构及其生产方法,所述结构包括引脚(2),所述引脚(2)正面镀有第一金属层(5),引脚(2)背面镀有第二金属层(6),所述引脚(2)与引脚(2)之间的蚀刻区域填充有塑封料(4),所述塑封料(4)与第一金属层(5)和第二金属层(6)齐平。本发明的有益效果是:引线框底部不需要再贴附一层昂贵的抗高温软性有机物胶膜,也没有背景中所述的装片、打线、包封会产生的各种问题,成品良率得到大大提升,而且引线框采用正背面同时蚀刻,在工序上可减少50%的复杂度,降低了成本,又可以减少因为二次对位造成的错位风险。

Description

无基岛预填塑封料先镀后刻引线框结构及其生产方法
技术领域
本发明涉及一种引线框结构及其生产方法,属于半导体封装技术领域。
背景技术
传统的引线框结构主要有两种:
一种是四面扁平无引脚封装(QFN)引线框,这种结构的引线框为了防止引线框正面包封作业时,引线框的背面会产生塑封料的溢料,故在引线框背面贴附有一层昂贵的高温胶膜(如图14所示),这种引线框结构存在以下缺点:
1、金属引线框的底部贴附了一层抗高温胶膜,增加了至少50%的引线框成本;
2、金属引线框底部贴附的胶膜是软性有机物质,所以在后续的封装过程的装片与金属丝键合作业中,会因为高温烘烤产生了有机物的挥发性污染,会直接污染到芯片正面与引线框正面与金属丝键合的结合性,甚至会影响到芯片正面与引线框正面后续封装过程中导致与塑封料的结合能力失败(俗称分层);
3、因为引线框底部贴附了软性有机胶膜,所以在后续的封装过程中的金属丝键合作业中,其部分键合的力量被软性的有机胶膜给吸收,增加了金属丝键合的难度,造成金属丝键合良率的不稳定,可能产生可靠性问题;
4、因为引线框底部贴附了软性有机胶膜,致使键合作业时金属丝材料也被受限在较为软性且昂贵的金丝,而不能使用硬质且成本低廉的铜质、铝质或其他低成本的金属丝或金属带;
5、因为引线框底部贴附了软性有机胶膜,所以在后续的包封作业时,会因为胶膜与金属引线框发生分离而造成在高压塑封过程中,塑封料渗入管脚或基岛与软性有机胶膜的中间(如图15、图16所示)。
6、通常情况下QFN产品必须存在金属基岛才可以装片,有时候会给线路板设计带来一些麻烦,因为必须要防止线路与金属基岛短路。
另一种双面蚀刻预包封引线框(如图17所示)的设计与制造是采用金属基板先进行背面蚀刻后,再进行背面塑封料的预包封,然后再进行引线框正面引脚的蚀刻与表面电镀。这种引线框结构存在以下缺点:
1、引线框的制作程序太过复杂,造成引线框成本增加;
2、引线框的蚀刻分成上下面各蚀刻一次,容易因为上下蚀刻位置的重复定位误差,造成错位。
发明内容
本发明的目的在于克服上述不足,提供一种无基岛预填塑封料先镀后刻引线框结构及其生产方法,它省去了背面的耐高温胶膜,当然地解决了因软性胶膜所带来的缺点,并同时的降低了封装材料、制程与生产效率等的成本,相对的提高了封装过程的可靠性,而且生产工艺步骤简单、成本低,并且可以再无金属基岛时装片,给线路板设计带来方便。
本发明的目的是这样实现的:一种无基岛预填塑封料先镀后刻引线框结构,它包括引脚,所述引脚正面镀有第一金属层,引脚背面镀有第二金属层,所述引脚与引脚之间的蚀刻区域填充有塑封料,所述塑封料与第一金属层和第二金属层齐平。
本发明无基岛预填塑封料先镀后刻引线框的生产方法,所述方法包括以下工艺步骤:
步骤一、取金属基板
步骤二、贴膜作业
利用贴膜设备在金属基板的正面及背面分别贴上可进行曝光显影的光刻胶膜,
步骤三、金属基板正面及背面去除部分光刻胶膜
利用曝光显影设备将步骤二完成贴膜作业的金属基板正面及背面进行曝光、显影与去除部分光刻胶膜,以露出金属基板上后续需要进行电镀的区域,
步骤四、镀金属层
在步骤三中金属基板正面去除部分光刻胶膜的区域镀上第一金属层,在步骤三中金属基板背面去除部分光刻胶膜的区域镀上第二金属层,
步骤五、金属基板正面及背面揭膜作业
将金属基板正面及背面余下的光刻胶膜揭除,
步骤六、贴膜作业
利用贴膜设备在步骤五揭除光刻胶膜后的金属基板正面及背面再次分别贴上可进行曝光显影的光刻胶膜,
步骤七、金属基板正面及背面去除部分光刻胶膜
利用曝光显影设备将步骤六完成贴膜作业的金属基板正面及背面进行曝光、显影与去除部分光刻胶膜,以露出金属基板上后续需要进行蚀刻的区域,
步骤八、金属基板正面及背面进行全蚀刻或半蚀刻
对步骤七中金属基板正面及背面去除部分光刻胶膜的区域同时进行全蚀刻或半蚀刻,在金属基板正面及背面形成凹陷的蚀刻区域,同时相对形引脚,
步骤九、金属基板正面及背面揭膜作业
将金属基板正面及背面余下的光刻胶膜揭除,
步骤十、金属基板蚀刻区域预填充塑封料
在步骤八形成的金属基板的蚀刻区域内,利用包封模具填充塑封料,完成引线框的预填充,
所述包封模具包括上模具和下模具,所述下模具或上模具上开设有注料孔,包封时将步骤就揭除光刻胶膜后的金属基板放置于上模具与下模具之间,待上模具和下模具合模后通过下模具上向上的注料孔或上模具上向下的注料孔往引脚与引脚之间的蚀刻区域内填充塑封料,完成引线框的预填充。
与现有技术相比,本发明的有益效果是:
本发明涉及一种无基岛预填塑封料先镀后刻引线框结构,其引脚与引脚之间的蚀刻区域内填充有塑封料,且塑封料与第一金属层和第二金属层齐平,它具有以下优点:
1、引线框底部不需要再贴附一层昂贵的抗高温软性有机物胶膜。因此也没有前面背景中所述的装片、打线、包封会产生的各种问题,材料成本、制程成本与质量成本等都得到大大降低,并且可以再无金属基岛时装片,给线路板设计带来方便。
2、引线框采用正背面同时蚀刻,对比双面蚀刻预包封引线框,在工序上可减少50%的复杂度,降低成本;又可以减少因为二次对位造成的错位风险。
附图说明
图1~图12为本发明无基岛预填塑封料先镀后刻引线框的生产方法各工序示意图。
图13为本发明无基岛预填塑封料先镀后刻引线框结构示意图。
图14为以往四面无引脚引线框背面贴上耐高温胶膜的示意图。
图15为以往背面贴上耐高温胶膜的四面无引脚引线框封装时溢料的示意图。
图16为封装时产生溢料的四面无引脚引线框封装揭下耐高温胶膜后的示意图。
图17为以往预包封双面蚀刻引线框的结构示意图。
其中:
基岛1
引脚2
耐高温胶膜3
塑封料4
第一金属层5
第二金属层6
上模具7
下模具8
金属基板9
光刻胶膜10和11
蚀刻区域12。
具体实施方式
本发明涉及一种无基岛预填塑封料先镀后刻引线框生产方法如下:
步骤一、取金属基板
参见图1,取一片厚度合适的金属基板9,金属基板9的材质可以依据芯片的功能与特性进行变换,例如:铜、铝、铁、铜合金、不锈钢或镍铁合金等。
步骤二、贴膜作业
参见图2,利用贴膜设备在镀完金属层的金属基板9正面及背面分别贴上可进行曝光显影的光刻胶膜10和11,所述光刻胶膜10和11可以是干膜,也可以是湿膜。
步骤三、金属基板正面及背面去除部分光刻胶膜
参见图3,利用曝光显影设备将步骤二完成贴膜作业的金属基板9正面及背面进行曝光、显影与去除部分光刻胶膜,以露出金属基板9上后续需要进行电镀的区域。
步骤四、镀金属层
参见图4,在步骤三中金属基板9正面去除部分光刻胶膜的区域镀上第一金属层5,在步骤三中金属基板9背面去除部分光刻胶膜的区域镀上第二金属层6,电镀的材料可以为金、镍金、镍钯金或银。
步骤五、金属基板正面及背面揭膜作业
参见图5,将金属基板9正面及背面余下的光刻胶膜揭除。
步骤六、贴膜作业
参见图6,利用贴膜设备在步骤五揭除光刻胶膜后的金属基板9正面及背面再次分别贴上可进行曝光显影的光刻胶膜10和11,以保护后续的蚀刻工艺作业,所述光刻胶膜10和11可以是干膜,也可以是湿膜。
步骤七、金属基板正面及背面去除部分光刻胶膜
参见图7,利用曝光显影设备将步骤六完成贴膜作业的金属基板9正面及背面进行曝光、显影与去除部分光刻胶膜,以露出金属基板9上后续需要进行蚀刻的区域。
步骤八、金属基板正面及背面进行全蚀刻或半蚀刻
参见图5,对步骤七中金属基板9正面及背面去除部分光刻胶膜的区域同时进行全蚀刻或半蚀刻,在金属基板9正面及背面形成凹陷的蚀刻区域12,同时相对形成引脚2。
步骤九、金属基板正面及背面揭膜作业
参见图9,将金属基板正面及背面余下的光刻胶膜揭除。
步骤十、金属基板蚀刻区域预填充塑封料
参见图10~图12,在步骤八形成的金属基板的蚀刻区域内,利用包封模具填充塑封料,完成引线框的预填充。
所述包封模具包括上模具7和下模具8,所述上模具7或下模具8上开设有注料孔,包封时将步骤九揭除光刻胶膜后的金属基板放置于上模具7与下模具8之间,待上模具7和下模具8合模后通过下模具8向上的注料孔或上模具7向下的注料孔往引脚2与引脚2之间的蚀刻区域12内填充塑封料,完成引线框的预填充。
最后成品参见图13,本发明无基岛预填塑封料先镀后刻引线框结构,它包括引脚2,所述引脚2的正面镀有第一金属层5,引脚2的背面镀有第二金属层6,所述引脚2与引脚2之间的蚀刻区域填充有塑封料4,所述塑封料4与第一金属层5和第二金属层6齐平。

Claims (2)

1.一种无基岛预填塑封料先镀后刻引线框结构,它包括引脚(2),所述引脚(2)正面镀有第一金属层(5),引脚(2)背面镀有第二金属层(6),其特征在于:所述引脚(2)与引脚(2)之间的蚀刻区域填充有塑封料(4),所述塑封料(4)与第一金属层(5)的正面和第二金属层(6)的背面齐平。
2.一种如权利要求1所述的无基岛预填塑封料先镀后刻引线框结构的生产方法,其特征在于所述方法包括以下工艺步骤:
步骤一、取金属基板,
步骤二、贴膜作业,
利用贴膜设备在金属基板的正面及背面分别贴上可进行曝光显影的光刻胶膜,
步骤三、金属基板正面及背面去除部分光刻胶膜,
利用曝光显影设备将步骤二完成贴膜作业的金属基板正面及背面进行曝光、显影与去除部分光刻胶膜,以露出金属基板上后续需要进行电镀的区域,
步骤四、镀金属层,
在步骤三中金属基板正面去除部分光刻胶膜的区域镀上第一金属层,在步骤三中金属基板背面去除部分光刻胶膜的区域镀上第二金属层,
步骤五、金属基板正面及背面揭膜作业,
将金属基板正面及背面余下的光刻胶膜揭除,
步骤六、贴膜作业,
利用贴膜设备在步骤五揭除光刻胶膜后的金属基板正面及背面再次分别贴上可进行曝光显影的光刻胶膜,
步骤七、金属基板正面及背面去除部分光刻胶膜,
利用曝光显影设备将步骤六完成贴膜作业的金属基板正面及背面进行曝光、显影与去除部分光刻胶膜,以露出金属基板上后续需要进行蚀刻的区域,
步骤八、金属基板正面及背面进行全蚀刻或半蚀刻,
对步骤七中金属基板正面及背面去除部分光刻胶膜的区域同时进行全蚀刻或半蚀刻,在金属基板正面及背面形成凹陷的蚀刻区域,同时相对形成引脚,
步骤九、金属基板正面及背面揭膜作业,
将金属基板正面及背面余下的光刻胶膜揭除,
步骤十、金属基板蚀刻区域预填充塑封料,
在步骤八形成的金属基板的蚀刻区域内,利用包封模具填充塑封料,完成引线框的预填充,
所述包封模具包括上模具和下模具,所述下模具或上模具上开设有注料孔,包封时将步骤九揭除光刻胶膜后的金属基板放置于上模具与下模具之间,待上模具和下模具合模后通过下模具上向上的注料孔或上模具上向下的注料孔往引脚与引脚之间的蚀刻区域内填充塑封料,完成引线框的预填充。
CN2011102683574A 2011-09-13 2011-09-13 无基岛预填塑封料先镀后刻引线框结构及其生产方法 Active CN102324412B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN2011102683574A CN102324412B (zh) 2011-09-13 2011-09-13 无基岛预填塑封料先镀后刻引线框结构及其生产方法
PCT/CN2012/001160 WO2013037186A1 (en) 2011-09-13 2012-08-28 Islandless pre-encapsulated plating-then-etching lead frame structures and manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2011102683574A CN102324412B (zh) 2011-09-13 2011-09-13 无基岛预填塑封料先镀后刻引线框结构及其生产方法

Publications (2)

Publication Number Publication Date
CN102324412A CN102324412A (zh) 2012-01-18
CN102324412B true CN102324412B (zh) 2013-03-06

Family

ID=45452123

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011102683574A Active CN102324412B (zh) 2011-09-13 2011-09-13 无基岛预填塑封料先镀后刻引线框结构及其生产方法

Country Status (2)

Country Link
CN (1) CN102324412B (zh)
WO (1) WO2013037186A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107393896A (zh) * 2017-08-09 2017-11-24 林英洪 引线框制作方法

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102324412B (zh) * 2011-09-13 2013-03-06 江苏长电科技股份有限公司 无基岛预填塑封料先镀后刻引线框结构及其生产方法
CN103745939B (zh) * 2013-12-05 2017-02-15 通富微电子股份有限公司 封装结构的形成方法
JP6524533B2 (ja) * 2016-02-25 2019-06-05 大口マテリアル株式会社 半導体素子搭載用基板、半導体装置及び光半導体装置、並びにそれらの製造方法
CN109065459A (zh) * 2018-07-27 2018-12-21 大连德豪光电科技有限公司 焊盘的制作方法
CN113534612B (zh) * 2020-04-17 2023-02-17 中铝洛阳铜加工有限公司 一种检测蚀刻用高精度引线框架材料平整度的快速方法
CN113161241B (zh) * 2021-02-05 2022-02-11 东莞市春瑞电子科技有限公司 一种分立式半导体封装支架制备方法
CN113395836A (zh) * 2021-05-19 2021-09-14 惠州市金百泽电路科技有限公司 小间距高厚度纯铜电路板制作方法
CN113241338B (zh) * 2021-07-09 2021-10-19 东莞市春瑞电子科技有限公司 一种无引线预塑封半导体封装支架制备方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4027147B2 (ja) * 2002-04-19 2007-12-26 大日本印刷株式会社 パッケージ基板の製造方法
US7144517B1 (en) * 2003-11-07 2006-12-05 Amkor Technology, Inc. Manufacturing method for leadframe and for semiconductor package using the leadframe
CN100555592C (zh) * 2007-02-08 2009-10-28 百慕达南茂科技股份有限公司 芯片封装结构及其制作方法
CN100539054C (zh) * 2007-03-13 2009-09-09 百慕达南茂科技股份有限公司 芯片封装结构及其制作方法
CN101814481B (zh) * 2010-04-30 2012-01-25 江苏长电科技股份有限公司 无基岛引线框结构及其生产方法
CN101958257B (zh) * 2010-09-04 2012-07-04 江苏长电科技股份有限公司 双面图形芯片直接置放先镀后刻模组封装方法
CN102324412B (zh) * 2011-09-13 2013-03-06 江苏长电科技股份有限公司 无基岛预填塑封料先镀后刻引线框结构及其生产方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107393896A (zh) * 2017-08-09 2017-11-24 林英洪 引线框制作方法
CN107393896B (zh) * 2017-08-09 2019-08-23 林英洪 引线框制作方法

Also Published As

Publication number Publication date
CN102324412A (zh) 2012-01-18
WO2013037186A1 (en) 2013-03-21

Similar Documents

Publication Publication Date Title
CN102324412B (zh) 无基岛预填塑封料先镀后刻引线框结构及其生产方法
CN102324413B (zh) 有基岛预填塑封料先刻后镀引线框结构及其生产方法
CN102324415B (zh) 无基岛预填塑封料先刻后镀引线框结构及其生产方法
CN101814482B (zh) 有基岛引线框结构及其生产方法
CN101840901B (zh) 无基岛静电释放圈引线框结构及其生产方法
CN102324414B (zh) 有基岛预填塑封料先镀后刻引线框结构及其生产方法
CN101814481A (zh) 无基岛引线框结构及其生产方法
US9659842B2 (en) Methods of fabricating QFN semiconductor package and metal plate
TW201320276A (zh) 封裝基板及其製法
KR101674537B1 (ko) 리드프레임 제조방법과 그에 따른 리드프레임 및 반도체 패키지 제조방법과 그에 따른 반도체 패키지
CN108198790A (zh) 具有引脚侧壁爬锡功能的堆叠封装结构及其制造工艺
CN102263077A (zh) 一种双扁平无载体无引脚的ic芯片封装件
CN105932006A (zh) 预包封侧边可浸润引线框架结构及其制造方法
CN102420206B (zh) 先镀后刻四面无引脚封装结构及其制造方法
CN201838581U (zh) 四面无引脚封装结构
CN202259267U (zh) 无基岛预填塑封料先刻后镀引线框结构
CN108198804A (zh) 具有引脚侧壁爬锡功能的堆叠封装结构及其制造工艺
JP4418764B2 (ja) 樹脂封止型半導体パッケージの製造方法
CN202259268U (zh) 有基岛预填塑封料先刻后镀引线框结构
JP2014017390A (ja) リードフレーム、プリモールドリードフレーム、半導体装置、プリモールドリードフレームの製造方法、および、半導体装置の製造方法
JP2010010634A (ja) リードフレーム及び半導体装置の製造方法
CN111668183A (zh) 一种用于芯片封装的引线框架及制备方法
JP2011040625A (ja) 半導体装置の製造方法
CN202259203U (zh) 用于引线框填缝作业的的新型模具结构
US9293395B2 (en) Lead frame with mold lock structure

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20170204

Address after: Tianjin free trade zone (Dongjiang Bonded Port) No. 6865 North Road, 1-1-1802-7 financial and trade center of Asia

Patentee after: Xin Xin finance leasing (Tianjin) Co., Ltd.

Address before: 214434 Binjiang Middle Road, Jiangyin Development Zone, Jiangsu, China, No. 275, No.

Patentee before: Jiangsu Changjiang Electronics Technology Co., Ltd.

EE01 Entry into force of recordation of patent licensing contract

Application publication date: 20120118

Assignee: Jiangsu Changjiang Electronics Technology Co., Ltd.

Assignor: Xin Xin finance leasing (Tianjin) Co., Ltd.

Contract record no.: 2017320000152

Denomination of invention: Island-free lead frame structure prefilled with plastic encapsulating material, plated firstly and etched later and production method thereof

Granted publication date: 20130306

License type: Exclusive License

Record date: 20170614

EE01 Entry into force of recordation of patent licensing contract
EC01 Cancellation of recordation of patent licensing contract

Assignee: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY Co.,Ltd.

Assignor: Xin Xin finance leasing (Tianjin) Co., Ltd.

Contract record no.: 2017320000152

Date of cancellation: 20200416

EC01 Cancellation of recordation of patent licensing contract
TR01 Transfer of patent right

Effective date of registration: 20200424

Address after: 78 Changshan Road, Chengjiang Town, Jiangyin City, Wuxi City, Jiangsu Province

Patentee after: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY Co.,Ltd.

Address before: 1-1-1802-7, North Zone, financial and Trade Center, No. 6865, Asia Road, Tianjin pilot free trade zone (Dongjiang Free Trade Port)

Patentee before: Xin Xin finance leasing (Tianjin) Co., Ltd.

TR01 Transfer of patent right