CN102324412A - 无基岛预填塑封料先镀后刻引线框结构及其生产方法 - Google Patents
无基岛预填塑封料先镀后刻引线框结构及其生产方法 Download PDFInfo
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- CN102324412A CN102324412A CN201110268357A CN201110268357A CN102324412A CN 102324412 A CN102324412 A CN 102324412A CN 201110268357 A CN201110268357 A CN 201110268357A CN 201110268357 A CN201110268357 A CN 201110268357A CN 102324412 A CN102324412 A CN 102324412A
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- metal substrate
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- photoresist film
- lead frame
- pin
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- 239000000463 material Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 103
- 239000002184 metal Substances 0.000 claims abstract description 103
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims description 71
- 229920002120 photoresistant polymer Polymers 0.000 claims description 42
- 239000005022 packaging material Substances 0.000 claims description 33
- 238000005530 etching Methods 0.000 claims description 23
- 238000003384 imaging method Methods 0.000 claims description 12
- 238000007789 sealing Methods 0.000 claims description 6
- 238000007747 plating Methods 0.000 claims description 5
- 238000005253 cladding Methods 0.000 claims description 3
- -1 Step 4 Substances 0.000 claims 1
- 238000005538 encapsulation Methods 0.000 abstract description 6
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 2
- 239000012528 membrane Substances 0.000 description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000011112 process operation Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
Images
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
Claims (2)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2011102683574A CN102324412B (zh) | 2011-09-13 | 2011-09-13 | 无基岛预填塑封料先镀后刻引线框结构及其生产方法 |
PCT/CN2012/001160 WO2013037186A1 (en) | 2011-09-13 | 2012-08-28 | Islandless pre-encapsulated plating-then-etching lead frame structures and manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2011102683574A CN102324412B (zh) | 2011-09-13 | 2011-09-13 | 无基岛预填塑封料先镀后刻引线框结构及其生产方法 |
Publications (2)
Publication Number | Publication Date |
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CN102324412A true CN102324412A (zh) | 2012-01-18 |
CN102324412B CN102324412B (zh) | 2013-03-06 |
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CN2011102683574A Active CN102324412B (zh) | 2011-09-13 | 2011-09-13 | 无基岛预填塑封料先镀后刻引线框结构及其生产方法 |
Country Status (2)
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CN (1) | CN102324412B (zh) |
WO (1) | WO2013037186A1 (zh) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2013037186A1 (en) * | 2011-09-13 | 2013-03-21 | Jiangsu Changjiang Electronics Technology Co. Ltd | Islandless pre-encapsulated plating-then-etching lead frame structures and manufacturing method |
CN103745939A (zh) * | 2013-12-05 | 2014-04-23 | 南通富士通微电子股份有限公司 | 封装结构的形成方法 |
CN107393896A (zh) * | 2017-08-09 | 2017-11-24 | 林英洪 | 引线框制作方法 |
CN108701658A (zh) * | 2016-02-25 | 2018-10-23 | 大口电材株式会社 | 半导体元件承载用基板、半导体装置及光半导体装置及其制造方法 |
CN109065459A (zh) * | 2018-07-27 | 2018-12-21 | 大连德豪光电科技有限公司 | 焊盘的制作方法 |
CN113161241A (zh) * | 2021-02-05 | 2021-07-23 | 东莞市春瑞电子科技有限公司 | 一种分立式半导体封装支架制备方法 |
CN113241338A (zh) * | 2021-07-09 | 2021-08-10 | 东莞市春瑞电子科技有限公司 | 一种无引线预塑封半导体封装支架及其制备方法 |
CN113395836A (zh) * | 2021-05-19 | 2021-09-14 | 惠州市金百泽电路科技有限公司 | 小间距高厚度纯铜电路板制作方法 |
CN113534612A (zh) * | 2020-04-17 | 2021-10-22 | 中铝洛阳铜加工有限公司 | 一种检测蚀刻用高精度引线框架材料平整度的快速方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003318329A (ja) * | 2002-04-19 | 2003-11-07 | Dainippon Printing Co Ltd | パッケージ基板の製造方法及びそれにより製造されたパッケージ基板並びにそれを用いた半導体パッケージ |
CN101814481A (zh) * | 2010-04-30 | 2010-08-25 | 江苏长电科技股份有限公司 | 无基岛引线框结构及其生产方法 |
CN101958257A (zh) * | 2010-09-04 | 2011-01-26 | 江苏长电科技股份有限公司 | 双面图形芯片直接置放先镀后刻模组封装方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7144517B1 (en) * | 2003-11-07 | 2006-12-05 | Amkor Technology, Inc. | Manufacturing method for leadframe and for semiconductor package using the leadframe |
CN100555592C (zh) * | 2007-02-08 | 2009-10-28 | 百慕达南茂科技股份有限公司 | 芯片封装结构及其制作方法 |
CN100539054C (zh) * | 2007-03-13 | 2009-09-09 | 百慕达南茂科技股份有限公司 | 芯片封装结构及其制作方法 |
CN102324412B (zh) * | 2011-09-13 | 2013-03-06 | 江苏长电科技股份有限公司 | 无基岛预填塑封料先镀后刻引线框结构及其生产方法 |
-
2011
- 2011-09-13 CN CN2011102683574A patent/CN102324412B/zh active Active
-
2012
- 2012-08-28 WO PCT/CN2012/001160 patent/WO2013037186A1/en active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003318329A (ja) * | 2002-04-19 | 2003-11-07 | Dainippon Printing Co Ltd | パッケージ基板の製造方法及びそれにより製造されたパッケージ基板並びにそれを用いた半導体パッケージ |
CN101814481A (zh) * | 2010-04-30 | 2010-08-25 | 江苏长电科技股份有限公司 | 无基岛引线框结构及其生产方法 |
CN101958257A (zh) * | 2010-09-04 | 2011-01-26 | 江苏长电科技股份有限公司 | 双面图形芯片直接置放先镀后刻模组封装方法 |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2013037186A1 (en) * | 2011-09-13 | 2013-03-21 | Jiangsu Changjiang Electronics Technology Co. Ltd | Islandless pre-encapsulated plating-then-etching lead frame structures and manufacturing method |
CN103745939A (zh) * | 2013-12-05 | 2014-04-23 | 南通富士通微电子股份有限公司 | 封装结构的形成方法 |
CN108701658A (zh) * | 2016-02-25 | 2018-10-23 | 大口电材株式会社 | 半导体元件承载用基板、半导体装置及光半导体装置及其制造方法 |
CN108701658B (zh) * | 2016-02-25 | 2021-07-27 | 大口电材株式会社 | 半导体元件承载用基板、半导体装置及光半导体装置及其制造方法 |
CN107393896A (zh) * | 2017-08-09 | 2017-11-24 | 林英洪 | 引线框制作方法 |
CN107393896B (zh) * | 2017-08-09 | 2019-08-23 | 林英洪 | 引线框制作方法 |
CN109065459A (zh) * | 2018-07-27 | 2018-12-21 | 大连德豪光电科技有限公司 | 焊盘的制作方法 |
CN113534612A (zh) * | 2020-04-17 | 2021-10-22 | 中铝洛阳铜加工有限公司 | 一种检测蚀刻用高精度引线框架材料平整度的快速方法 |
CN113534612B (zh) * | 2020-04-17 | 2023-02-17 | 中铝洛阳铜加工有限公司 | 一种检测蚀刻用高精度引线框架材料平整度的快速方法 |
CN113161241A (zh) * | 2021-02-05 | 2021-07-23 | 东莞市春瑞电子科技有限公司 | 一种分立式半导体封装支架制备方法 |
CN113395836A (zh) * | 2021-05-19 | 2021-09-14 | 惠州市金百泽电路科技有限公司 | 小间距高厚度纯铜电路板制作方法 |
CN113241338A (zh) * | 2021-07-09 | 2021-08-10 | 东莞市春瑞电子科技有限公司 | 一种无引线预塑封半导体封装支架及其制备方法 |
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Publication number | Publication date |
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WO2013037186A1 (en) | 2013-03-21 |
CN102324412B (zh) | 2013-03-06 |
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