WO2017020362A1 - Tft基板的制作方法及tft基板 - Google Patents

Tft基板的制作方法及tft基板 Download PDF

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Publication number
WO2017020362A1
WO2017020362A1 PCT/CN2015/087912 CN2015087912W WO2017020362A1 WO 2017020362 A1 WO2017020362 A1 WO 2017020362A1 CN 2015087912 W CN2015087912 W CN 2015087912W WO 2017020362 A1 WO2017020362 A1 WO 2017020362A1
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Prior art keywords
contact region
layer
drain
source
region
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English (en)
French (fr)
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卢马才
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/778,090 priority Critical patent/US9570618B1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a TFT substrate and a TFT substrate.
  • TFT Thin Film Transistor
  • LCD Liquid Crystal Display
  • AMOLED Active Matrix/Organic Light-Emitting Diode
  • the main drive components are directly related to the development direction of high-performance flat panel display devices.
  • the thin film transistor has various structures, and the material of the thin film transistor for preparing the corresponding structure is also various.
  • Low temperature poly-silicon (LTPS) material is one of the more preferable ones, due to the atomic regular arrangement of the low temperature polysilicon, The mobility of the carrier is high.
  • the polysilicon thin film transistor can realize the deflection driving of the liquid crystal molecules by using a thin film transistor due to its high mobility.
  • the volume occupied by the thin film transistor is reduced, the light transmission area is increased, and higher brightness and resolution are obtained.
  • the low temperature polysilicon thin film transistor can be better. Meet the drive current requirements.
  • the hot carrier effect is an important failure mechanism of metal oxide semiconductor (MOS) devices. As the size of MOS devices shrinks, the hot carrier injection effect of devices becomes more and more serious.
  • PMOS P-type metal oxide semiconductor
  • holes in the channel are accelerated by a high transverse electric field between the drain and source to form high-energy carriers, and high-energy carriers collide with the silicon lattice.
  • Producing ionized electron-hole pairs electrons are collected by the substrate to form a substrate current, and most of the collision-generated holes flow to the drain, but some holes are injected into the gate under the action of the longitudinal electric field.
  • the gate current is formed. This phenomenon is called hot carrier injection.
  • Hot carriers cause cleavage of the energy bond at the interface between the silicon substrate and the silicon dioxide gate, creating an interface state at the interface between the silicon substrate and the silicon dioxide gate oxide, resulting in device performance such as threshold voltage, transconductance, and linearity.
  • the degradation of the current in the region/saturation region eventually causes the MOS device to fail.
  • MOS device failure usually occurs first at the drain end. This is because the carrier accelerates through the electric field of the entire channel. After reaching the drain terminal, the energy of the carrier reaches a maximum, so the hot carrier injection phenomenon at the drain is serious. . Therefore, how to reduce the hot carrier injection damage of a semiconductor device has become a worker in the field. Research hotspots.
  • LTPS TFTs low temperature polysilicon thin film transistors
  • a-Si TFTs amorphous silicon polysilicon thin film transistors
  • the carrier moves under the high electric field (>4E10 ⁇ 4V/cm)
  • the energy obtained from the electric field is greater than the energy lost by the lattice action
  • the carrier velocity is getting larger and larger, and the hot carrier effect occurs
  • the current method is generally to form a shallow doped transition region by ion implantation, such as Lightly Doped Drain (LDD), gate overlap lightly doped drain region (Gate Overlapped) Lightly Doped Drain, GOLDD), etc., and these methods are complicated and prone to doping bias and fail.
  • LDD Lightly Doped Drain
  • GOLDD Gate Overlapped Lightly Doped Drain
  • An object of the present invention is to provide a method for fabricating a TFT substrate by etching a source and a drain contact region of an active layer to a height lower than a height of the intermediate channel region, and contacting the source and drain electrodes
  • the region is designed to be stepped. Due to the existence of the step of the drain contact region, the peak electric field (Vds electric field) peak intensity near the channel drain is lowered and the drain vertical electric field (Vgs electric field) intensity is lowered, and the pinch-off point moves to the drain end.
  • the threshold voltage Vth drift or the like is reduced to improve the reliability of the TFT device.
  • Another object of the present invention is to provide a TFT substrate which can reduce the hot carrier effect, reduce the threshold voltage Vth drift, and improve the reliability of the thin film transistor.
  • the present invention first provides a method for fabricating a TFT substrate, comprising the following steps:
  • Step 1 Providing a substrate, sequentially depositing a buffer layer and an amorphous silicon layer on the substrate;
  • Step 2 performing an excimer laser annealing or solid phase crystallization treatment on the amorphous silicon layer to convert the amorphous silicon layer into a low temperature polysilicon layer, and patterning the low temperature polysilicon layer by using a photolithography process Obtaining a first active layer and a second active layer disposed at intervals;
  • Step 3 coating a photoresist layer on the first active layer, the second active layer, and the substrate, and exposing and developing the photoresist layer to expose two of the first active layers An end region, wherein the photoresist layer is used as a shielding layer, and N-type or P-type ion implantation is performed on both ends of the first active layer to obtain first source contacts respectively located at opposite ends of the first active layer a region and a first drain contact region; defining a region between the first source contact region and the first drain contact region as a first channel region;
  • Step 4 performing ashing treatment on the photoresist layer, and partially etching the first source contact region and the first drain contact region of the first active layer to make the first source contact region
  • the height of the contact area with the first drain is lower than the height of the first channel region
  • Step 5 peeling off the photoresist layer, depositing on the first active layer, the second active layer, and the substrate a gate insulating layer, a first metal layer is deposited on the gate insulating layer, and the first metal layer is patterned by a photolithography process to obtain a first active layer and a second active layer respectively a first gate and a second gate above;
  • Step 6 Apply a photoresist layer over the first gate and the second gate, and expose and develop the photoresist layer to expose the second gate and the gate insulating layer corresponding to the first a region above the two active layers; using the second gate as a shielding layer, performing P-type or N-type ion implantation on both ends of the second active layer to obtain respectively located at two ends of the second active layer a second source contact region, a second drain contact region, defining a region between the second source contact region and the second drain contact region as a second channel region;
  • Step 7 Stripping the photoresist layer, depositing an interlayer dielectric layer on the first gate electrode, the second gate electrode, and the gate insulating layer, and using a photolithography process to the interlayer dielectric layer and the gate electrode
  • the insulating layer is patterned, and a first via hole is formed on the interlayer dielectric layer and the gate insulating layer corresponding to the first source contact region and the first drain contact region, corresponding to the Forming a second through hole above the second source contact region and the second drain contact region;
  • Step 8 Depositing a second metal layer on the interlayer dielectric layer, and patterning the second metal layer by using a photolithography process to obtain a first source, a first drain, a second source, a second drain, the first source and the first drain are respectively in contact with the first source contact region and the first drain contact region via a first via, the second source and the second The drain is in contact with the second source contact region and the second drain contact region via the second via hole respectively;
  • Step 9 Apply a planarization layer on the first source, the first drain, the second source, the second drain, and the interlayer dielectric layer, and deposit a passivation layer on the planar layer. a planarization process is performed on the planarization layer and the passivation layer, and a third via hole is formed on the planarization layer and the passivation layer corresponding to the second drain;
  • Step 10 depositing a transparent conductive oxide layer on the passivation layer, patterning the transparent conductive oxide layer by a photolithography process to obtain a pixel electrode, and the pixel electrode is connected to the The second drains are in contact to complete the fabrication of the TFT substrate.
  • the upper surface of the first source contact region and the first drain contact region is a plane or a slope lower than the upper surface of the first channel region, that is, the first The source contact region and the upper surface of the first drain contact region form a step with respect to the upper surface of the first channel region;
  • the upper surface of the first source contact region and the first drain contact region includes a plurality of steps sequentially decreasing from the first channel region to the outer side, and the step faces of the plurality of steps are plane or Beveled.
  • the photoresist layer is ashed by using oxygen, and a polysilicon etch gas is added to the oxygen to engrave the first source contact region and the first drain contact region. eclipse;
  • the photoresist layer is first ashed with oxygen, and then the first source contact region and the first drain contact region are etched by a photolithography process.
  • the step 6 performs P-type ions on the second source contact region and the second drain contact region. injection;
  • the step 6 performs N-type ions on the second source contact region and the second drain contact region. injection.
  • the N-type ions are phosphorus ions, and the P-type ions are boron ions.
  • the present invention also provides a TFT substrate, comprising: a substrate, a buffer layer disposed on the substrate, a first active layer and a second active layer disposed on the buffer layer, disposed on the first a gate insulating layer on the active layer and the second active layer, a first gate disposed on the gate insulating layer and corresponding to the first active layer and the second active layer, respectively a second gate, an interlayer dielectric layer disposed on the first gate and the second gate, a first source, a first drain, and a second source disposed on the interlayer dielectric layer a second drain, a flat layer disposed on the first source, the first drain, the second source, and the second drain, a passivation layer disposed on the planar layer, and a passivation layer a pixel electrode on the passivation layer;
  • the first active layer and the second active layer are both low temperature polysilicon layers
  • the first active layer includes a first channel region in the middle, a first source contact region, a first drain contact region on both sides of the first channel region, and the first source region
  • the height of the contact region and the first drain contact region are both lower than the height of the first channel region
  • the second active layer includes a second channel region located in the middle and completely corresponding to the second gate, and second source contact regions and second drains on opposite sides of the second channel region Contact area.
  • the upper surface of the first source contact region and the first drain contact region is a plane or a slope lower than an upper surface of the first channel region, that is, the first source contact region and the first drain contact
  • the upper surface of the region forms a step with respect to the upper surface of the first channel region
  • the upper surface of the first source contact region and the first drain contact region includes a plurality of steps sequentially decreasing from the first channel region to the outer side, and the step faces of the plurality of steps are plane or Beveled.
  • the first source contact region and the first drain contact region are both N-type heavily doped regions, and the second source contact region and the second drain contact region are both P-type heavily doped regions;
  • the first source contact region and the first drain contact region are both P-type heavily doped regions, and the second source contact region and the second drain contact region are both N-type heavily doped regions.
  • the impurity incorporated in the N-type heavily doped region is phosphorus ion, and the impurity incorporated in the P-type heavily doped region is boron ion.
  • the interlayer dielectric layer and the gate insulating layer are respectively provided with first via holes corresponding to the first source contact region and the first drain contact region, and corresponding to the second source respectively. a second via hole above the contact region and the second drain contact region; the first source and the first drain are respectively connected to the first source contact region and the first drain contact region via the first via hole Contacting, the second source and the second drain are respectively in contact with the second source contact region and the second drain contact region via the second via hole;
  • a third via hole is disposed on the flat layer and the passivation layer corresponding to the second drain, and the pixel electrode is in contact with the second drain via the third via.
  • the present invention also provides a TFT substrate, comprising: a substrate, a buffer layer disposed on the substrate, a first active layer and a second active layer disposed on the buffer layer, disposed on the first a gate insulating layer on the active layer and the second active layer, a first gate disposed on the gate insulating layer and corresponding to the first active layer and the second active layer, respectively a second gate, an interlayer dielectric layer disposed on the first gate and the second gate, a first source, a first drain, and a second source disposed on the interlayer dielectric layer a second drain, a flat layer disposed on the first source, the first drain, the second source, and the second drain, a passivation layer disposed on the planar layer, and a passivation layer a pixel electrode on the passivation layer;
  • the first active layer and the second active layer are both low temperature polysilicon layers
  • the first active layer includes a first channel region in the middle, a first source contact region, a first drain contact region on both sides of the first channel region, and the first source region
  • the height of the contact region and the first drain contact region are both lower than the height of the first channel region
  • the second active layer includes a second channel region located in the middle and completely corresponding to the second gate, and second source contact regions and second drains on opposite sides of the second channel region Contact area
  • the upper surface of the first source contact region and the first drain contact region is a plane or a slope lower than an upper surface of the first channel region, that is, the first source contact region and the first drain.
  • the upper surface of the pole contact region forms a step with respect to the upper surface of the first channel region;
  • the upper surface of the first source contact region and the first drain contact region includes a plurality of steps sequentially decreasing from the first channel region to the outer side, and the step faces of the plurality of steps are plane or Bevel
  • the first source contact region and the first drain contact region are both N-type heavily doped regions, and the second source contact region and the second drain contact region are both P-type heavily doped regions;
  • first source contact region and the first drain contact region are both P-type heavily doped regions, and the second source contact region and the second drain contact region are both N-type heavily doped regions;
  • the interlayer dielectric layer and the gate insulating layer are respectively provided with first through holes corresponding to the first source contact regions and the first drain contact regions, and respectively corresponding to the second holes.
  • a third via hole is disposed on the flat layer and the passivation layer corresponding to the second drain, and the pixel electrode is in contact with the second drain via the third via.
  • the TFT substrate of the present invention is formed by etching a source and a drain contact region of an active layer to a height lower than a height of the intermediate channel region, and the source and the drain are
  • the contact region is designed to be stepped such that the carrier is subjected to an electric field (Vds electric field) deviating from the interface direction of the polysilicon/gate insulating layer in the vicinity of the drain contact region, and the migration path is pulled away from the interface of the polysilicon/gate insulating layer to reduce high energy.
  • Vds electric field an electric field
  • the carrier is implanted into the gate insulating layer, and due to the existence of the step of the drain contact region, the peak electric field (Vds electric field) peak intensity near the drain contact region and the vertical electric field (Vgs electric field) intensity of the drain contact region are both lowered.
  • the break point moves toward the edge of the drain contact region, reduces the threshold voltage drift, and the like, and improves the reliability of the TFT.
  • the TFT substrate of the present invention is designed to have a lower height of the source and drain contact regions of the active layer than the middle trench.
  • the height of the track region, and the source and drain contact regions are designed to be stepped such that the peak electric field (Vds electric field) peak intensity near the drain contact region and the vertical electric field (Vgs electric field) intensity of the drain contact region Drop, pinch-off point moves to the edge of the drain contact region, the threshold voltage drift is reduced, improving the reliability of TFT.
  • Vds electric field peak electric field
  • Vgs electric field vertical electric field
  • step 1 is a schematic view of step 1 of a method of fabricating a TFT substrate of the present invention
  • step 2 is a schematic view of step 2 of a method for fabricating a TFT substrate of the present invention
  • FIG. 3 is a schematic view showing a step 3 of a method for fabricating a TFT substrate of the present invention
  • FIG. 4 is a schematic view showing a step 4 of a method of fabricating a TFT substrate of the present invention
  • step 5 is a schematic view of step 5 of a method for fabricating a TFT substrate of the present invention.
  • FIG. 6 is a schematic view showing a step 6 of a method of fabricating a TFT substrate of the present invention
  • FIG. 7 is a schematic view showing a step 7 of a method of fabricating a TFT substrate of the present invention.
  • FIG. 8 is a schematic view showing a step 8 of a method of fabricating a TFT substrate of the present invention.
  • FIG. 9 is a schematic view showing a step 9 of a method of fabricating a TFT substrate of the present invention.
  • FIG. 10 is a schematic view showing the step 10 of the method for fabricating the TFT substrate of the present invention and a schematic structural view of the TFT substrate of the present invention.
  • the present invention first provides a method for fabricating a TFT substrate, including the following steps:
  • Step 1 As shown in FIG. 1, a substrate 1 is provided, and a buffer layer 2 and an amorphous silicon layer 21 are sequentially deposited on the substrate 1.
  • the buffer layer 2 may be a silicon oxide (SiO x ) layer, a silicon nitride (SiN x ) layer, or a stacked combination of a silicon oxide layer and a silicon nitride layer.
  • Step 2 As shown in FIG. 2, the amorphous silicon layer 21 is subjected to Excimer Laser Annealing (ELA) or Solid Phase Crystallization (SPC) treatment to form the amorphous silicon layer.
  • ELA Excimer Laser Annealing
  • SPC Solid Phase Crystallization
  • the low temperature polysilicon layer is converted into a low temperature polysilicon layer, and the low temperature polysilicon layer is patterned by a photolithography process to obtain a first active layer 31 and a second active layer 32 which are spaced apart.
  • Step 3 as shown in FIG. 3, the photoresist layer 30 is coated on the first active layer 31, the second active layer 32, and the substrate 1, and the photoresist layer 30 is exposed and developed. Exposing the two end regions of the first active layer 31, using the photoresist layer 30 as a shielding layer, and performing N-type or P-type ion implantation on both ends of the first active layer 31 to obtain respectively a first source contact region 311 and a first drain contact region 312 at both ends of the first active layer 31; a region defined between the first source contact region 311 and the first drain contact region 312 is A channel region 313.
  • the N-type ion may be a pentavalent ion such as a phosphorus ion
  • the P-type ion may be a trivalent ion such as a boron ion.
  • Step 4 as shown in FIG. 4, the photoresist layer 30 is subjected to ashing treatment, and the first source contact region 311 and the first drain contact region 312 of the first active layer 31 are partially etched.
  • the heights of the first source contact region 311 and the first drain contact region 312 are both lower than the height of the first channel region 313.
  • the upper surface of the first source contact region 311 and the first drain contact region 312 is lower than the upper surface of the first channel region 313 (eg, The upper surface of the first source contact region 311 and the first drain contact region 312 forms a step with respect to the upper surface of the first channel region 313, and the step surface is The height difference of the upper surface of the first channel region 313 is
  • the upper surface of the first source contact region 311 and the first drain contact region 312 includes a plurality of steps sequentially decreasing from the first channel region 313 to the outer height, and the stepped surfaces of the plurality of steps It is a plane or a slope, and the height difference between two adjacent step faces is
  • the ashing process of the photoresist layer 30 and the etching process of the first source contact region 311 and the first drain contact region 312 may be performed simultaneously, for example, ashing the photoresist layer 55 with oxygen.
  • the first source contact region 311 and the first drain contact region 312 are etched by adding a polysilicon etch gas to the oxygen.
  • the ashing process of the photoresist layer 55 and the etching process of the first source contact region 311 and the first drain contact region 312 may also be performed in two steps, for example, first using oxygen to the photoresist
  • the layer 30 is subjected to ashing treatment, and then the first source contact region 311 and the first drain contact region 312 are etched by other methods such as photolithography.
  • Step 5 stripping the photoresist layer 30, depositing a gate insulating layer 4 on the first active layer 31, the second active layer 32, and the substrate 1, at the gate insulating layer Depositing a first metal layer on the fourth metal layer, and patterning the first metal layer by a photolithography process to obtain a first gate electrode 51 corresponding to the first active layer 31 and the second active layer 32, respectively.
  • Two gates 52 are two gates 52.
  • the gate insulating layer 4 may be a silicon oxide layer, a silicon nitride layer, or a stacked combination of a silicon oxide layer and a silicon nitride layer.
  • the first metal layer may be a composite layer structure (Mo/Al/Mo) in which an aluminum layer is interposed between two molybdenum layers, or a composite layer structure in which an aluminum layer is interposed between two titanium layers ( Ti/Al/Ti).
  • Step 6 as shown in FIG. 6 , a photoresist layer 50 is coated on the first gate 51 and the second gate 52 , and the photoresist layer 50 is exposed and developed to expose the second gate 52 . And a region on the gate insulating layer 4 corresponding to the upper portion of the second active layer 32; and the second gate 52 is used as a shielding layer, and P-type or N is performed on both ends of the second active layer 32.
  • Type ion implantation to obtain a second source contact region 321 and a second drain contact region 322 respectively located at the two ends of the second active layer 32; defining the second source contact region 321 and the second drain contact region The area between 322 is the second channel region 323.
  • the N-type ion may be a pentavalent ion such as a phosphorus ion
  • the P-type ion may be a trivalent ion such as a boron ion.
  • the step 4 when the step 4 is performing N-type ion implantation on the first source contact region 311 and the first drain contact region 312, the step 6 is performed on the second source contact region 321 and the second The drain contact region 322 performs P-type ion implantation;
  • the step 4 When the step 4 performs P-type ion implantation on the first source contact region 311 and the first drain contact region 312, the step 6 contacts the second source contact region 321 and the second drain. Zone 322 performs N-type ion implantation.
  • Step 7 stripping the photoresist layer 50, depositing an interlayer dielectric layer 6 on the first gate 51, the second gate 52, and the gate insulating layer 4, using a photolithography process Patterning the interlayer dielectric layer 6 and the gate insulating layer 4 on the interlayer dielectric layer 6 and the gate insulating layer 4 corresponding to the first source contact region 311, first A first via hole 61 is formed above the drain contact region 312, and a second via hole 62 is formed above the second source contact region 321 and the second drain contact region 322.
  • Step 8 depositing a second metal layer on the interlayer dielectric layer 6, and patterning the second metal layer by a photolithography process to obtain a first source 71, first
  • the drain electrode 72, the second source 73, and the second drain 74, the first source 71 and the first drain 72 are respectively connected to the first source contact region 311 and the first drain via the first via 61.
  • the contact regions 312 are in contact with each other, and the second source 73 and the second drain 74 are in contact with the second source contact region 321 and the second drain contact region 322 via the second via 62, respectively.
  • the second metal layer may be a composite layer structure (Mo/Al/Mo) in which an aluminum layer is interposed between two molybdenum layers, or a composite layer structure in which an aluminum layer is interposed between two titanium layers ( Ti/Al/Ti).
  • Step 9 as shown in FIG. 9, coating the flat layer 8 on the first source 71, the first drain 72, the second source 73, the second drain 74, and the interlayer dielectric layer 6, Depositing a passivation layer 9 on the planar layer 8, and patterning the planar layer 8 and the passivation layer 9 by a photolithography process, corresponding to the flat layer 8 and the passivation layer 9 A third through hole 91 is formed above the second drain 74.
  • Step 10 depositing a transparent conductive oxide layer on the passivation layer 9, and patterning the transparent conductive oxide layer by a photolithography process to obtain a pixel electrode 10, the pixel electrode 10 is in contact with the second drain 74 via the third via hole 91, thereby completing fabrication of the TFT substrate.
  • the material of the transparent conductive oxide layer is ITO (indium tin oxide).
  • the present invention further provides a TFT substrate, comprising: a substrate 1 , a buffer layer 2 disposed on the substrate 1 , and a buffer layer 2 disposed on the buffer layer 2
  • An active layer 31, a second active layer 32, and a gate insulating layer 4 disposed on the first active layer 31 and the second active layer 32 are disposed on the gate insulating layer 4 and respectively a first gate 51 and a second gate 52 disposed corresponding to the first active layer 31 and the second active layer 32 are disposed between the layers on the first gate 51 and the second gate 52 a first source 71, a first drain 72, a second source 73, and a second drain 74 disposed on the interlayer dielectric layer 6 are disposed on the first source 71.
  • the first active layer 31 and the second active layer 32 are both low temperature polysilicon layers.
  • the first active layer 31 includes a first channel region 313 located in the middle, and is located at a first source contact region 311 and a first drain contact region 312 on both sides of the first channel region 313, and the heights of the first source contact region 311 and the first drain contact region 312 are both lower than a height of the first channel region 313;
  • the upper surface of the first source contact region 311 and the first drain contact region 312 is a plane (as shown in FIG. 10) or a slope lower than the upper surface of the first channel region 313, that is,
  • the upper surface of the first source contact region 311 and the first drain contact region 312 form a step with respect to the upper surface of the first channel region 313, the step surface and the upper surface of the first channel region 313 Height difference is
  • the upper surface of the first source contact region 311 and the first drain contact region 312 includes a plurality of steps sequentially decreasing from the first channel region 313 to the outer height, and the stepped surfaces of the plurality of steps It is a plane or a slope, and the height difference between two adjacent step faces is
  • the second active layer 32 includes a second channel region 323 located in the middle and completely corresponding to the second gate 52, and a second source located at two sides of the second channel region 323.
  • first source contact region 311 and the first drain contact region 312 are both N-type heavily doped regions, and the second source contact region 321 and the second drain contact region 322 are both P-type.
  • first source contact region 311 and the first drain contact region 312 are both P-type heavily doped regions, and the second source contact region 321 and the second drain contact region 322 are both N-type heavily.
  • the impurity incorporated in the N-type heavily doped region is a pentavalent ion such as a phosphorus ion
  • the impurity incorporated in the P-type heavily doped region is a trivalent ion such as a boron ion.
  • the interlayer dielectric layer 6 and the gate insulating layer 4 are respectively provided with first through holes 61 corresponding to the first source contact regions 311 and the first drain contact regions 312, and respectively Corresponding to the second source contact region 321 and the second via hole 62 above the second drain contact region 322; the first source electrode 71 and the first drain electrode 72 are respectively connected to the first via hole 61
  • the first source contact region 311 and the first drain contact region 312 are in contact with each other, and the second source 73 and the second drain 74 are respectively connected to the second source contact region 321 via the second via 62
  • the two drain contact regions 322 are in contact.
  • a third through hole 91 is disposed on the flat layer 8 and the passivation layer 9 corresponding to the second drain 74, and the pixel electrode 10 passes through the third through hole 91 and the second drain The poles 74 are in contact.
  • the buffer layer 2 may be a silicon oxide (SiO x ) layer, a silicon nitride (SiN x ) layer, or a stacked combination of a silicon oxide layer and a silicon nitride layer.
  • the first gate 51, the second gate 52, the first source 71, the first drain 72, the second source 73, and the second drain 74 may have an aluminum layer interposed between the molybdenum layers.
  • Composite layer structure Mo/Al/Mo
  • Ti/Al/Ti composite layer structure in which an aluminum layer is interposed between the two titanium layers.
  • the material of the pixel electrode 10 is ITO (Indium Tin Oxide).
  • the TFT substrate of the present invention is formed by etching the source and drain contact regions of the active layer to a height lower than the height of the intermediate channel region, and contacting the source and drain electrodes.
  • the region is designed to be stepped such that the carrier is subjected to an electric field (Vds electric field) deviating from the interface direction of the polysilicon/gate insulating layer in the vicinity of the drain contact region, and the migration path is pulled away from the interface of the polysilicon/gate insulating layer to reduce high energy load.
  • Vds electric field an electric field
  • the peak electric field (Vds electric field) peak intensity near the drain contact region and the vertical contact electric field (Vgs electric field) intensity of the drain contact region are both lowered, pinched off Pointing to the edge of the drain contact region, reducing threshold voltage drift, etc., improving TFT reliability;
  • the TFT substrate of the present invention by designing the height of the source and drain contact regions of the active layer to be lower than the intermediate channel The height of the region, and the source and drain contact regions are designed to be stepped such that the peak electric field (Vds electric field) peak intensity near the drain contact region and the vertical contact electric field (Vgs electric field) intensity of the drain contact region are both decreased. Break contact region moves toward the edge of the drain, the threshold voltage drift is reduced, improving the reliability of TFT.

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Abstract

一种TFT基板的制作方法及TFT基板，制作方法是通过对多晶硅有源层(31、32)的源、漏极接触区(311、312)进行蚀刻，使其高度低于中间沟道区(313)的高度，并且将所述源、漏极接触区设计为台阶状，使得载流子在漏极接触区附近受到偏离多晶硅/栅极绝缘层(4)界面方向电场的作用(Vds电场)，迁移路径被拉离多晶硅/栅极绝缘层界面，减少高能载子注入栅极绝缘层内，并且由于漏极接触区的台阶的存在，使得漏极接触区附近横向电场(Vds电场)峰值强度以及漏极接触区纵向电场(Vgs电场)强度均下降，夹断点往漏极接触区边缘移动，减小阈值电压漂移，提高TFT可靠性。

Description

TFT基板的制作方法及TFT基板 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT基板的制作方法及TFT基板。
背景技术
薄膜晶体管(Thin Film Transistor，简称TFT)是目前液晶显示装置(Liquid Crystal Display，简称LCD)和有源矩阵驱动式有机电致发光显示装置(Active Matrix/Organic Light-Emitting Diode，简称AMOLED)中的主要驱动元件，直接关系到高性能平板显示装置的发展方向。薄膜晶体管具有多种结构，制备相应结构的薄膜晶体管的材料也具有多种，低温多晶硅(Low Temperature Poly-silicon，简称LTPS)材料是其中较为优选的一种，由于低温多晶硅的原子规则排列，载流子迁移率高，对电压驱动式的液晶显示装置而言，多晶硅薄膜晶体管由于其具有较高的迁移率，可以使用体积较小的薄膜晶体管实现对液晶分子的偏转驱动，在很大程度上缩小了薄膜晶体管所占的体积，增加透光面积，得到更高的亮度和解析度；对于电流驱动式的有源矩阵驱动式有机电致发光显示装置而言，低温多晶硅薄膜晶体管可以更好的满足驱动电流要求。
热载流子效应是金属氧化物半导体(MOS)器件的一个重要的失效机理，随着MOS器件尺寸的日益缩小，器件的热载流子注入效应越来越严重。以P型金属氧化物半导体(PMOS)器件为例，沟道中的空穴，在漏源之间高横向电场的作用下被加速，形成高能载流子，高能载流子与硅晶格碰撞，产生电离的电子空穴对，电子由衬底收集，形成衬底电流，大部分碰撞产生的空穴，流向漏极，但还有部分空穴，在纵向电场的作用下，注入到栅极中形成栅极电流，这种现象称为热载流子注入(Hot Carrier Injection)。
热载流子会造成硅衬底与二氧化硅栅氧界面处能键的断裂，在硅衬底与二氧化硅栅氧界面处产生界面态，导致器件性能，如阈值电压、跨导以及线性区/饱和区电流的退化，最终造成MOS器件失效。MOS器件失效通常首先发生在漏端，这是由于载流子通过整个沟道的电场加速，在到达漏端后，载流子的能量达到最大值，因此漏端的热载流子注入现象比较严重。因此，如何减小半导体器件热载流子注入损伤成为本领域工作人员的 研究热点。
对于低温多晶硅薄膜晶体管(LTPS TFT)来说，相较于非晶硅多晶硅薄膜晶体管(a-Si TFT)拥有较高的约20-100倍的载流子迁移率，同样容易出现热载流子效应，载流子在高电场(>4E10^4V/cm)下运动，从电场中获得能量大于与晶格作用损失的能量，载流子速率越来越大，出现热载流子效应；为减小热载流子注入损伤，目前一般采取方法是通过用离子注入形成浅掺杂过渡区，如轻掺杂漏区(Lightly Doped Drain，LDD)、栅极重叠轻掺杂漏区(Gate Overlapped Lightly Doped Drain，GOLDD)等，而这些方法较为复杂且容易出现掺杂偏差而失效。
发明内容
本发明的目的在于提供一种TFT基板的制作方法，通过对有源层的源、漏极接触区进行蚀刻，使其高度低于中间沟道区的高度，并且将所述源、漏极接触区设计为台阶状，由于漏极接触区的台阶的存在，降低沟道漏极附近横向电场(Vds电场)峰值强度以及降低漏极纵向电场(Vgs电场)强度，夹断点往漏极端移动，减小阈值电压Vth漂移等，提高TFT器件的可靠性。
本发明的目的还在于提供一种TFT基板，可以减少热载子效应，减少阈值电压Vth漂移，提高薄膜晶体管的可靠性。
为实现上述目的，本发明首先提供一种TFT基板的制作方法，包括如下步骤：
步骤1、提供一基板，在基板上依次沉积缓冲层与非晶硅层；
步骤2、对所述非晶硅层进行准分子激光退火或固相晶化处理，使所述非晶硅层转化为低温多晶硅层，采用一道光刻制程对所述低温多晶硅层进行图案化处理，得到间隔设置的第一有源层、第二有源层；
步骤3、在所述第一有源层、第二有源层、及基板上涂布光阻层，通过对所述光阻层进行曝光、显影，暴露出所述第一有源层的两端区域，以所述光阻层为遮蔽层，对所述第一有源层的两端进行N型或P型离子注入，得到分别位于所述第一有源层两端的第一源极接触区与第一漏极接触区；定义所述第一源极接触区与第一漏极接触区之间的区域为第一沟道区；
步骤4、对所述光阻层进行灰化处理，对所述第一有源层的第一源极接触区与第一漏极接触区进行部分刻蚀，使所述第一源极接触区与第一漏极接触区的高度均低于所述第一沟道区的高度；
步骤5、剥离光阻层，在所述第一有源层、第二有源层、及基板上沉积 栅极绝缘层，在所述栅极绝缘层上沉积第一金属层，采用一道光刻制程对该第一金属层进行图案化处理，得到分别对应于第一有源层、第二有源层上方的第一栅极、第二栅极；
步骤6、在所述第一栅极、第二栅极上方涂布光阻层，对所述光阻层进行曝光、显影，暴露出第二栅极以及栅极绝缘层上对应于所述第二有源层上方的区域；以所述第二栅极为遮蔽层，对所述第二有源层的两端进行P型或N型离子注入，得到分别位于所述第二有源层两端的第二源极接触区、第二漏极接触区，定义所述第二源极接触区与第二漏极接触区之间的区域为第二沟道区；
步骤7、剥离光阻层，在所述第一栅极、第二栅极、及栅极绝缘层上沉积层间介电层，采用一道光刻制程对所述层间介电层及栅极绝缘层进行图案化处理，在所述层间介电层及栅极绝缘层上对应于所述第一源极接触区、第一漏极接触区的上方形成第一通孔，对应于所述第二源极接触区、第二漏极接触区的上方形成第二通孔；
步骤8、在所述层间介电层上沉积第二金属层，采用一道光刻制程对该第二金属层进行图案化处理，得到第一源极、第一漏极、第二源极、第二漏极，所述第一源极、第一漏极分别经由第一通孔与所述第一源极接触区、第一漏极接触区相接触，所述第二源极、第二漏极分别经由第二通孔与所述第二源极接触区、第二漏极接触区相接触；
步骤9、在所述第一源极、第一漏极、第二源极、第二漏极、及层间介电层上涂布平坦层，在所述平坦层上沉积钝化层，采用一道光刻制程对所述平坦层及钝化层进行图案化处理，在所述平坦层及钝化层上对应于所述第二漏极的上方形成第三通孔；
步骤10、在所述钝化层沉积透明导电氧化物层，采用一道光刻制程对所述透明导电氧化物层进行图案化处理，得到像素电极，所述像素电极经由第三通孔与所述第二漏极相接触，从而完成TFT基板的制作。
经过所述步骤4的刻蚀后，所述第一源极接触区、第一漏极接触区的上表面为低于所述第一沟道区上表面的平面或斜面，即所述第一源极接触区、第一漏极接触区的上表面相对于所述第一沟道区上表面形成一个台阶；
或者，所述第一源极接触区、第一漏极接触区的上表面包括从所述第一沟道区向外侧高度依次递减的数个台阶，所述数个台阶的台阶面为平面或斜面。
所述步骤4中，采用氧气对所述光阻层进行灰化处理，同时在氧气中加入多晶硅刻蚀性气体对所述第一源极接触区与第一漏极接触区进行刻 蚀；
或者，首先采用氧气对所述光阻层进行灰化处理，然后采用光刻制程对所述第一源极接触区与第一漏极接触区进行刻蚀。
当所述步骤4对第一源极接触区与第一漏极接触区进行N型离子注入时，所述步骤6对所述第二源极接触区与第二漏极接触区进行P型离子注入；
当所述步骤4对所述第一源极接触区与第一漏极接触区进行P型离子注入时，所述步骤6对第二源极接触区与第二漏极接触区进行N型离子注入。
所述N型离子为磷离子，所述P型离子为硼离子。
本发明还提供一种TFT基板，包括：一基板，设于所述基板上的缓冲层，设于所述缓冲层上的第一有源层、第二有源层，设于所述第一有源层、第二有源层上的栅极绝缘层，设于所述栅极绝缘层上且分别与所述第一有源层、第二有源层对应设置的第一栅极、第二栅极，设于所述第一栅极、第二栅极上的层间介电层，设于所述层间介电层上的第一源极、第一漏极、第二源极、第二漏极，设于所述第一源极、第一漏极、第二源极、第二漏极上的平坦层，设于所述平坦层上的钝化层，以及设于所述钝化层上的像素电极；
其中，所述第一有源层、第二有源层均为低温多晶硅层；
所述第一有源层包括位于中间的第一沟道区、及位于所述第一沟道区两侧的第一源极接触区、第一漏极接触区，且所述第一源极接触区与第一漏极接触区的高度均低于所述第一沟道区的高度；
所述第二有源层包括位于中间且与所述第二栅极完全对应的第二沟道区、及位于所述第二沟道区两侧的第二源极接触区、第二漏极接触区。
所述第一源极接触区、第一漏极接触区的上表面为低于所述第一沟道区上表面的平面或斜面，即所述第一源极接触区、第一漏极接触区的上表面相对于所述第一沟道区上表面形成一个台阶；
或者，所述第一源极接触区、第一漏极接触区的上表面包括从所述第一沟道区向外侧高度依次递减的数个台阶，所述数个台阶的台阶面为平面或斜面。
所述第一源极接触区与第一漏极接触区均为N型重掺杂区，所述第二源极接触区与第二漏极接触区均为P型重掺杂区；
或者，所述第一源极接触区与第一漏极接触区均为P型重掺杂区，所述第二源极接触区与第二漏极接触区均为N型重掺杂区。
所述N型重掺杂区中掺入的杂质为磷离子，所述P型重掺杂区中掺入的杂质为硼离子。
所述层间介电层及栅极绝缘层上设有分别对应于所述第一源极接触区、第一漏极接触区上方的第一通孔，以及分别对应于所述第二源极接触区、第二漏极接触区上方的第二通孔；所述第一源极、第一漏极分别经由第一通孔与所述第一源极接触区、第一漏极接触区相接触，所述第二源极、第二漏极分别经由第二通孔与所述第二源极接触区、第二漏极接触区相接触；
所述平坦层及钝化层上对应于所述第二漏极的上方设有第三通孔，所述像素电极经由第三通孔与所述第二漏极相接触。
本发明还提供一种TFT基板，包括：一基板，设于所述基板上的缓冲层，设于所述缓冲层上的第一有源层、第二有源层，设于所述第一有源层、第二有源层上的栅极绝缘层，设于所述栅极绝缘层上且分别与所述第一有源层、第二有源层对应设置的第一栅极、第二栅极，设于所述第一栅极、第二栅极上的层间介电层，设于所述层间介电层上的第一源极、第一漏极、第二源极、第二漏极，设于所述第一源极、第一漏极、第二源极、第二漏极上的平坦层，设于所述平坦层上的钝化层，以及设于所述钝化层上的像素电极；
其中，所述第一有源层、第二有源层均为低温多晶硅层；
所述第一有源层包括位于中间的第一沟道区、及位于所述第一沟道区两侧的第一源极接触区、第一漏极接触区，且所述第一源极接触区与第一漏极接触区的高度均低于所述第一沟道区的高度；
所述第二有源层包括位于中间且与所述第二栅极完全对应的第二沟道区、及位于所述第二沟道区两侧的第二源极接触区、第二漏极接触区；
其中，所述第一源极接触区、第一漏极接触区的上表面为低于所述第一沟道区上表面的平面或斜面，即所述第一源极接触区、第一漏极接触区的上表面相对于所述第一沟道区上表面形成一个台阶；
或者，所述第一源极接触区、第一漏极接触区的上表面包括从所述第一沟道区向外侧高度依次递减的数个台阶，所述数个台阶的台阶面为平面或斜面；
其中，所述第一源极接触区与第一漏极接触区均为N型重掺杂区，所述第二源极接触区与第二漏极接触区均为P型重掺杂区；
或者，所述第一源极接触区与第一漏极接触区均为P型重掺杂区，所述第二源极接触区与第二漏极接触区均为N型重掺杂区；
其中，所述层间介电层及栅极绝缘层上设有分别对应于所述第一源极接触区、第一漏极接触区上方的第一通孔，以及分别对应于所述第二源极接触区、第二漏极接触区上方的第二通孔；所述第一源极、第一漏极分别经由第一通孔与所述第一源极接触区、第一漏极接触区相接触，所述第二源极、第二漏极分别经由第二通孔与所述第二源极接触区、第二漏极接触区相接触；
所述平坦层及钝化层上对应于所述第二漏极的上方设有第三通孔，所述像素电极经由第三通孔与所述第二漏极相接触。
本发明的有益效果：本发明的TFT基板的制作方法，通过对有源层的源、漏极接触区进行蚀刻，使其高度低于中间沟道区的高度，并且将所述源、漏极接触区设计为台阶状，使得载流子在漏极接触区附近受到偏离多晶硅/栅极绝缘层界面方向电场的作用(Vds电场)，迁移路径被拉离多晶硅/栅极绝缘层界面，减少高能载子注入栅极绝缘层内，并且由于漏极接触区的台阶的存在，使得漏极接触区附近横向电场(Vds电场)峰值强度以及漏极接触区纵向电场(Vgs电场)强度均下降，夹断点往漏极接触区边缘移动，减小阈值电压漂移等，提高TFT可靠性；本发明的TFT基板，通过将所述有源层的源、漏极接触区的高度设计为低于中间沟道区的高度，并且将所述源、漏极接触区设计为台阶状，使得漏极接触区附近横向电场(Vds电场)峰值强度以及漏极接触区纵向电场(Vgs电场)强度均下降，夹断点往漏极接触区边缘移动，减小阈值电压漂移等，提高TFT可靠性。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明TFT基板的制作方法的步骤1的示意图；
图2为本发明TFT基板的制作方法的步骤2的示意图；
图3为本发明TFT基板的制作方法的步骤3的示意图；
图4为本发明TFT基板的制作方法的步骤4的示意图；
图5为本发明TFT基板的制作方法的步骤5的示意图；
图6为本发明TFT基板的制作方法的步骤6的示意图；
图7为本发明TFT基板的制作方法的步骤7的示意图；
图8为本发明TFT基板的制作方法的步骤8的示意图；
图9为本发明TFT基板的制作方法的步骤9的示意图；
图10为本发明TFT基板的制作方法的步骤10的示意图兼本发明TFT基板的结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1-10，本发明首先提供一种TFT基板的制作方法，包括如下步骤：
步骤1、如图1所示，提供一基板1，在基板1上依次沉积缓冲层2与非晶硅层21。
具体的，所述缓冲层2可以为氧化硅(SiOx)层、氮化硅(SiNx)层、或氧化硅层与氮化硅层的堆叠组合。
步骤2、如图2所示，对所述非晶硅层21进行准分子激光退火(Excimer Laser Annealing，ELA)或固相晶化(Solid Phase Crystallization，SPC)处理，使所述非晶硅层转化为低温多晶硅层，采用一道光刻制程对所述低温多晶硅层进行图案化处理，得到间隔设置的第一有源层31、第二有源层32。
步骤3、如图3所示，在所述第一有源层31、第二有源层32、及基板1上涂布光阻层30，通过对所述光阻层30进行曝光、显影，暴露出所述第一有源层31的两端区域，以所述光阻层30为遮蔽层，对所述第一有源层31的两端进行N型或P型离子注入，得到分别位于所述第一有源层31两端的第一源极接触区311与第一漏极接触区312；定义所述第一源极接触区311与第一漏极接触区312之间的区域为第一沟道区313。
具体的，所述N型离子可以为磷离子等五价离子，所述P型离子可以为硼离子等三价离子。
步骤4、如图4所示，对所述光阻层30进行灰化处理，对所述第一有源层31的第一源极接触区311与第一漏极接触区312进行部分刻蚀，使所述第一源极接触区311与第一漏极接触区312的高度均低于所述第一沟道区313的高度。
具体的，通过所述步骤4的刻蚀后，所述第一源极接触区311、第一漏极接触区312的上表面为低于所述第一沟道区313上表面的平面(如图4所示)或斜面，即所述第一源极接触区311、第一漏极接触区312的上表面相对于所述第一沟道区313上表面形成一个台阶，该台阶面与所述第一沟道区313上表面的高度差为
Figure PCTCN2015087912-appb-000001
或者，所述第一源极接触区311、第一漏极接触区312的上表面包括从所述第一沟道区313向外侧高度依次递减的数个台阶，所述数个台阶的台阶面为平面或斜面，相邻两台阶面的高度差为
Figure PCTCN2015087912-appb-000002
具体的，所述光阻层30的灰化处理和第一源极接触区311、第一漏极接触区312的刻蚀过程可以同时进行，比如：采用氧气对所述光阻层55进行灰化处理，同时在氧气中加入多晶硅刻蚀性气体对所述第一源极接触区311与第一漏极接触区312进行刻蚀。
具体的，所述光阻层55的灰化处理和第一源极接触区311、第一漏极接触区312的刻蚀过程也可以分两步进行，比如：首先采用氧气对所述光阻层30进行灰化处理，然后采用其它方法如光刻制程对所述第一源极接触区311与第一漏极接触区312进行刻蚀。
步骤5、如图5所示，剥离光阻层30，在所述第一有源层31、第二有源层32、及基板1上沉积栅极绝缘层4，在所述栅极绝缘层4上沉积第一金属层，采用一道光刻制程对该第一金属层进行图案化处理，得到分别对应于第一有源层31、第二有源层32上方的第一栅极51、第二栅极52。
具体的，所述栅极绝缘层4可以为氧化硅层、氮化硅层、或氧化硅层与氮化硅层的堆叠组合。
具体的，所述第一金属层可以为两钼层之间夹设一铝层的复合层结构(Mo/Al/Mo)、或者为两钛层之间夹设一铝层的复合层结构(Ti/Al/Ti)。
步骤6、如图6所示，在所述第一栅极51、第二栅极52上方涂布光阻层50，对所述光阻层50进行曝光、显影，暴露出第二栅极52以及栅极绝缘层4上对应于所述第二有源层32上方的区域；以所述第二栅极52为遮蔽层，对所述第二有源层32的两端进行P型或N型离子注入，得到分别位于所述第二有源层32两端的第二源极接触区321、第二漏极接触区322；定义所述第二源极接触区321与第二漏极接触区322之间的区域为第二沟道区323。
具体的，所述N型离子可以为磷离子等五价离子，所述P型离子可以为硼离子等三价离子。
具体的，当所述步骤4对所述第一源极接触区311与第一漏极接触区312进行N型离子注入时，所述步骤6对所述第二源极接触区321与第二漏极接触区322进行P型离子注入；
当所述步骤4对所述第一源极接触区311与第一漏极接触区312进行P型离子注入时，所述步骤6对所述第二源极接触区321与第二漏极接触区322进行N型离子注入。
步骤7、如图7所示，剥离光阻层50，在所述第一栅极51、第二栅极52、及栅极绝缘层4上沉积层间介电层6，采用一道光刻制程对所述层间介电层6及栅极绝缘层4进行图案化处理，在所述层间介电层6及栅极绝缘层4上对应于所述第一源极接触区311、第一漏极接触区312的上方形成第一通孔61，对应于所述第二源极接触区321、第二漏极接触区322的上方形成第二通孔62。
步骤8、如图8所示，在所述层间介电层6上沉积第二金属层，采用一道光刻制程对该第二金属层进行图案化处理，得到第一源极71、第一漏极72、第二源极73、第二漏极74，所述第一源极71、第一漏极72分别经由第一通孔61与所述第一源极接触区311、第一漏极接触区312相接触，所述第二源极73、第二漏极74分别经由第二通孔62与所述第二源极接触区321、第二漏极接触区322相接触。
具体的，所述第二金属层可以为两钼层之间夹设一铝层的复合层结构(Mo/Al/Mo)、或者为两钛层之间夹设一铝层的复合层结构(Ti/Al/Ti)。
步骤9、如图9所示，在所述第一源极71、第一漏极72、第二源极73、第二漏极74、及层间介电层6上涂布平坦层8，在所述平坦层8上沉积钝化层9，采用一道光刻制程对所述平坦层8及钝化层9进行图案化处理，在所述平坦层8及钝化层9上对应于所述第二漏极74的上方形成第三通孔91。
步骤10、如图10所示，在所述钝化层9沉积透明导电氧化物层，采用一道光刻制程对所述透明导电氧化物层进行图案化处理，得到像素电极10，所述像素电极10经由第三通孔91与所述第二漏极74相接触，从而完成TFT基板的制作。
具体的，所述透明导电氧化物层的材料为ITO(氧化铟锡)。
请参阅图10，基于上述TFT基板的制作方法，本发明还提供一种TFT基板，包括：一基板1，设于所述基板1上的缓冲层2，设于所述缓冲层2上的第一有源层31、第二有源层32，设于所述第一有源层31、第二有源层32上的栅极绝缘层4，设于所述栅极绝缘层4上且分别与所述第一有源层31、第二有源层32对应设置的第一栅极51、第二栅极52，设于所述第一栅极51、第二栅极52上的层间介电层6，设于所述层间介电层6上的第一源极71、第一漏极72、第二源极73、第二漏极74，设于所述第一源极71、第一漏极72、第二源极73、第二漏极74上的平坦层8，设于所述平坦层8上的钝化层9，以及设于所述钝化层9上的像素电极10。
具体的，所述第一有源层31、第二有源层32均为低温多晶硅层。
具体的，所述第一有源层31包括位于中间的第一沟道区313、及位于 所述第一沟道区313两侧的第一源极接触区311、第一漏极接触区312，且所述第一源极接触区311与第一漏极接触区312的高度均低于所述第一沟道区313的高度；
具体的，所述第一源极接触区311、第一漏极接触区312的上表面为低于所述第一沟道区313上表面的平面(如图10所示)或斜面，即所述第一源极接触区311、第一漏极接触区312的上表面相对于所述第一沟道区313上表面形成一个台阶，该台阶面与所述第一沟道区313上表面的高度差为
Figure PCTCN2015087912-appb-000003
或者，所述第一源极接触区311、第一漏极接触区312的上表面包括从所述第一沟道区313向外侧高度依次递减的数个台阶，所述数个台阶的台阶面为平面或斜面，相邻两台阶面的高度差为
Figure PCTCN2015087912-appb-000004
具体的，所述第二有源层32包括位于中间且与所述第二栅极52完全对应的第二沟道区323、及位于所述第二沟道区323两侧的第二源极接触区321、第二漏极接触区322。
具体的，所述第一源极接触区311与第一漏极接触区312均为N型重掺杂区，所述第二源极接触区321与第二漏极接触区322均为P型重掺杂区；
或者，所述第一源极接触区311与第一漏极接触区312均为P型重掺杂区，所述第二源极接触区321与第二漏极接触区322均为N型重掺杂区；
所述N型重掺杂区中掺入的杂质为磷离子等五价离子，所述P型重掺杂区中掺入的杂质为硼离子等三价离子。
具体的，所述层间介电层6及栅极绝缘层4上设有分别对应于所述第一源极接触区311、第一漏极接触区312上方的第一通孔61，以及分别对应于所述第二源极接触区321、第二漏极接触区322上方的第二通孔62；所述第一源极71、第一漏极72分别经由第一通孔61与所述第一源极接触区311、第一漏极接触区312相接触，所述第二源极73、第二漏极74分别经由第二通孔62与所述第二源极接触区321、第二漏极接触区322相接触。
具体的，所述平坦层8及钝化层9上对应于所述第二漏极74的上方设有第三通孔91，所述像素电极10经由第三通孔91与所述第二漏极74相接触。
具体的，所述缓冲层2可以为氧化硅(SiOx)层、氮化硅(SiNx)层、或氧化硅层与氮化硅层的堆叠组合。
所述第一栅极51、第二栅极52、第一源极71、第一漏极72、第二源极73、第二漏极74可以为两钼层之间夹设一铝层的复合层结构 (Mo/Al/Mo)、或者为两钛层之间夹设一铝层的复合层结构(Ti/Al/Ti)。
具体的，所述像素电极10的材料为ITO(氧化铟锡)。
综上所述，本发明的TFT基板的制作方法，通过对有源层的源、漏极接触区进行蚀刻，使其高度低于中间沟道区的高度，并且将所述源、漏极接触区设计为台阶状，使得载流子在漏极接触区附近受到偏离多晶硅/栅极绝缘层界面方向电场的作用(Vds电场)，迁移路径被拉离多晶硅/栅极绝缘层界面，减少高能载子注入栅极绝缘层内，并且由于漏极接触区的台阶的存在，使得漏极接触区附近横向电场(Vds电场)峰值强度以及漏极接触区纵向电场(Vgs电场)强度均下降，夹断点往漏极接触区边缘移动，减小阈值电压漂移等，提高TFT可靠性；本发明的TFT基板，通过将所述有源层的源、漏极接触区的高度设计为低于中间沟道区的高度，并且将所述源、漏极接触区设计为台阶状，使得漏极接触区附近横向电场(Vds电场)峰值强度以及漏极接触区纵向电场(Vgs电场)强度均下降，夹断点往漏极接触区边缘移动，减小阈值电压漂移等，提高TFT可靠性。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (12)

  1. 一种TFT基板的制作方法，包括如下步骤：
    步骤1、提供一基板，在基板上依次沉积缓冲层与非晶硅层；
    步骤2、对所述非晶硅层进行准分子激光退火或固相晶化处理，使所述非晶硅层转化为低温多晶硅层，采用一道光刻制程对所述低温多晶硅层进行图案化处理，得到间隔设置的第一有源层、第二有源层；
    步骤3、在所述第一有源层、第二有源层、及基板上涂布光阻层，通过对所述光阻层进行曝光、显影，暴露出所述第一有源层的两端区域，以所述光阻层为遮蔽层，对所述第一有源层的两端进行N型或P型离子注入，得到分别位于所述第一有源层两端的第一源极接触区与第一漏极接触区；定义所述第一源极接触区与第一漏极接触区之间的区域为第一沟道区；
    步骤4、对所述光阻层进行灰化处理，对所述第一有源层的第一源极接触区与第一漏极接触区进行部分刻蚀，使所述第一源极接触区与第一漏极接触区的高度均低于所述第一沟道区的高度；
    步骤5、剥离光阻层，在所述第一有源层、第二有源层、及基板上沉积栅极绝缘层，在所述栅极绝缘层上沉积第一金属层，采用一道光刻制程对该第一金属层进行图案化处理，得到分别对应于第一有源层、第二有源层上方的第一栅极、第二栅极；
    步骤6、在所述第一栅极、第二栅极上方涂布光阻层，对所述光阻层进行曝光、显影，暴露出第二栅极以及栅极绝缘层上对应于所述第二有源层上方的区域；以所述第二栅极为遮蔽层，对所述第二有源层的两端进行P型或N型离子注入，得到分别位于所述第二有源层两端的第二源极接触区、第二漏极接触区，定义所述第二源极接触区与第二漏极接触区之间的区域为第二沟道区；
    步骤7、剥离光阻层，在所述第一栅极、第二栅极、及栅极绝缘层上沉积层间介电层，采用一道光刻制程对所述层间介电层及栅极绝缘层进行图案化处理，在所述层间介电层及栅极绝缘层上对应于所述第一源极接触区、第一漏极接触区的上方形成第一通孔，对应于所述第二源极接触区、第二漏极接触区的上方形成第二通孔；
    步骤8、在所述层间介电层上沉积第二金属层，采用一道光刻制程对该第二金属层进行图案化处理，得到第一源极、第一漏极、第二源极、第二漏极，所述第一源极、第一漏极分别经由第一通孔与所述第一源极接触区、 第一漏极接触区相接触，所述第二源极、第二漏极分别经由第二通孔与所述第二源极接触区、第二漏极接触区相接触；
    步骤9、在所述第一源极、第一漏极、第二源极、第二漏极、及层间介电层上涂布平坦层，在所述平坦层上沉积钝化层，采用一道光刻制程对所述平坦层及钝化层进行图案化处理，在所述平坦层及钝化层上对应于所述第二漏极的上方形成第三通孔；
    步骤10、在所述钝化层沉积透明导电氧化物层，采用一道光刻制程对所述透明导电氧化物层进行图案化处理，得到像素电极，所述像素电极经由第三通孔与所述第二漏极相接触，从而完成TFT基板的制作。
  2. 如权利要求1所述的TFT基板的制作方法，其中，经过所述步骤4的刻蚀后，所述第一源极接触区、第一漏极接触区的上表面为低于所述第一沟道区上表面的平面或斜面，即所述第一源极接触区、第一漏极接触区的上表面相对于所述第一沟道区上表面形成一个台阶；
    或者，所述第一源极接触区、第一漏极接触区的上表面包括从所述第一沟道区向外侧高度依次递减的数个台阶，所述数个台阶的台阶面为平面或斜面。
  3. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤4中，采用氧气对所述光阻层进行灰化处理，同时在氧气中加入多晶硅刻蚀性气体对所述第一源极接触区与第一漏极接触区进行刻蚀；
    或者，首先采用氧气对所述光阻层进行灰化处理，然后采用光刻制程对所述第一源极接触区与第一漏极接触区进行刻蚀。
  4. 如权利要求1所述的TFT基板的制作方法，其中，当所述步骤4对第一源极接触区与第一漏极接触区进行N型离子注入时，所述步骤6对所述第二源极接触区与第二漏极接触区进行P型离子注入；
    当所述步骤4对所述第一源极接触区与第一漏极接触区进行P型离子注入时，所述步骤6对第二源极接触区与第二漏极接触区进行N型离子注入。
  5. 如权利要求1所述的TFT基板的制作方法，其中，所述N型离子为磷离子，所述P型离子为硼离子。
  6. 一种TFT基板，包括：一基板，设于所述基板上的缓冲层，设于所述缓冲层上的第一有源层、第二有源层，设于所述第一有源层、第二有源层上的栅极绝缘层，设于所述栅极绝缘层上且分别与所述第一有源层、第二有源层对应设置的第一栅极、第二栅极，设于所述第一栅极、第二栅极上的层间介电层，设于所述层间介电层上的第一源极、第一漏极、第二源 极、第二漏极，设于所述第一源极、第一漏极、第二源极、第二漏极上的平坦层，设于所述平坦层上的钝化层，以及设于所述钝化层上的像素电极；
    其中，所述第一有源层、第二有源层均为低温多晶硅层；
    所述第一有源层包括位于中间的第一沟道区、及位于所述第一沟道区两侧的第一源极接触区、第一漏极接触区，且所述第一源极接触区与第一漏极接触区的高度均低于所述第一沟道区的高度；
    所述第二有源层包括位于中间且与所述第二栅极完全对应的第二沟道区、及位于所述第二沟道区两侧的第二源极接触区、第二漏极接触区。
  7. 如权利要求6所述的TFT基板，其中，所述第一源极接触区、第一漏极接触区的上表面为低于所述第一沟道区上表面的平面或斜面，即所述第一源极接触区、第一漏极接触区的上表面相对于所述第一沟道区上表面形成一个台阶；
    或者，所述第一源极接触区、第一漏极接触区的上表面包括从所述第一沟道区向外侧高度依次递减的数个台阶，所述数个台阶的台阶面为平面或斜面。
  8. 如权利要求6所述的TFT基板，其中，所述第一源极接触区与第一漏极接触区均为N型重掺杂区，所述第二源极接触区与第二漏极接触区均为P型重掺杂区；
    或者，所述第一源极接触区与第一漏极接触区均为P型重掺杂区，所述第二源极接触区与第二漏极接触区均为N型重掺杂区。
  9. 如权利要求8所述的TFT基板，其中，所述N型重掺杂区中掺入的杂质为磷离子，所述P型重掺杂区中掺入的杂质为硼离子。
  10. 如权利要求6所述的TFT基板，其中，所述层间介电层及栅极绝缘层上设有分别对应于所述第一源极接触区、第一漏极接触区上方的第一通孔，以及分别对应于所述第二源极接触区、第二漏极接触区上方的第二通孔；所述第一源极、第一漏极分别经由第一通孔与所述第一源极接触区、第一漏极接触区相接触，所述第二源极、第二漏极分别经由第二通孔与所述第二源极接触区、第二漏极接触区相接触；
    所述平坦层及钝化层上对应于所述第二漏极的上方设有第三通孔，所述像素电极经由第三通孔与所述第二漏极相接触。
  11. 一种TFT基板，包括：一基板，设于所述基板上的缓冲层，设于所述缓冲层上的第一有源层、第二有源层，设于所述第一有源层、第二有源层上的栅极绝缘层，设于所述栅极绝缘层上且分别与所述第一有源层、第二有源层对应设置的第一栅极、第二栅极，设于所述第一栅极、第二栅 极上的层间介电层，设于所述层间介电层上的第一源极、第一漏极、第二源极、第二漏极，设于所述第一源极、第一漏极、第二源极、第二漏极上的平坦层，设于所述平坦层上的钝化层，以及设于所述钝化层上的像素电极；
    其中，所述第一有源层、第二有源层均为低温多晶硅层；
    所述第一有源层包括位于中间的第一沟道区、及位于所述第一沟道区两侧的第一源极接触区、第一漏极接触区，且所述第一源极接触区与第一漏极接触区的高度均低于所述第一沟道区的高度；
    所述第二有源层包括位于中间且与所述第二栅极完全对应的第二沟道区、及位于所述第二沟道区两侧的第二源极接触区、第二漏极接触区；
    其中，所述第一源极接触区、第一漏极接触区的上表面为低于所述第一沟道区上表面的平面或斜面，即所述第一源极接触区、第一漏极接触区的上表面相对于所述第一沟道区上表面形成一个台阶；
    或者，所述第一源极接触区、第一漏极接触区的上表面包括从所述第一沟道区向外侧高度依次递减的数个台阶，所述数个台阶的台阶面为平面或斜面；
    其中，所述第一源极接触区与第一漏极接触区均为N型重掺杂区，所述第二源极接触区与第二漏极接触区均为P型重掺杂区；
    或者，所述第一源极接触区与第一漏极接触区均为P型重掺杂区，所述第二源极接触区与第二漏极接触区均为N型重掺杂区；
    其中，所述层间介电层及栅极绝缘层上设有分别对应于所述第一源极接触区、第一漏极接触区上方的第一通孔，以及分别对应于所述第二源极接触区、第二漏极接触区上方的第二通孔；所述第一源极、第一漏极分别经由第一通孔与所述第一源极接触区、第一漏极接触区相接触，所述第二源极、第二漏极分别经由第二通孔与所述第二源极接触区、第二漏极接触区相接触；
    所述平坦层及钝化层上对应于所述第二漏极的上方设有第三通孔，所述像素电极经由第三通孔与所述第二漏极相接触。
  12. 如权利要求11所述的TFT基板，其中，所述N型重掺杂区中掺入的杂质为磷离子，所述P型重掺杂区中掺入的杂质为硼离子。
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