US20170040462A1 - Tft substrate manufacturing method and tft substrate - Google Patents
Tft substrate manufacturing method and tft substrate Download PDFInfo
- Publication number
- US20170040462A1 US20170040462A1 US14/778,090 US201514778090A US2017040462A1 US 20170040462 A1 US20170040462 A1 US 20170040462A1 US 201514778090 A US201514778090 A US 201514778090A US 2017040462 A1 US2017040462 A1 US 2017040462A1
- Authority
- US
- United States
- Prior art keywords
- contact zone
- layer
- drain
- terminal
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 71
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 238000009413 insulation Methods 0.000 claims abstract description 43
- 239000007924 injection Substances 0.000 claims abstract description 25
- 238000002347 injection Methods 0.000 claims abstract description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 12
- 239000010410 layer Substances 0.000 claims description 348
- 229920002120 photoresistant polymer Polymers 0.000 claims description 32
- 239000011229 interlayer Substances 0.000 claims description 30
- 238000002161 passivation Methods 0.000 claims description 27
- 238000000151 deposition Methods 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 21
- 230000008569 process Effects 0.000 claims description 21
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 11
- 239000010409 thin film Substances 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 10
- 239000011248 coating agent Substances 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 9
- 229910052796 boron Inorganic materials 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 8
- 238000011161 development Methods 0.000 claims description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 238000004380 ashing Methods 0.000 claims description 5
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 3
- 238000002425 crystallisation Methods 0.000 claims description 3
- 230000008025 crystallization Effects 0.000 claims description 3
- 229910001882 dioxygen Inorganic materials 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- 238000005224 laser annealing Methods 0.000 claims description 3
- 239000007790 solid phase Substances 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 35
- 239000002800 charge carrier Substances 0.000 abstract description 9
- 239000003031 high energy carrier Substances 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 230000005012 migration Effects 0.000 abstract description 3
- 238000013508 migration Methods 0.000 abstract description 3
- 150000002500 ions Chemical class 0.000 description 25
- -1 phosphorous ion Chemical class 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- 239000010936 titanium Substances 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 239000002131 composite material Substances 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 239000000243 solution Substances 0.000 description 4
- 229920001621 AMOLED Polymers 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
Definitions
- the present invention relates to the field of display technology, and in particular to a thin-film-transistor (TFT) substrate manufacturing method and a TFT substrate.
- TFT thin-film-transistor
- TFTs Thin-film transistors
- LCDs liquid crystal displays
- AMOLEDs active matrix organic light-emitting diodes
- the TFTs have various structures and there are various materials that are used to make the corresponding ones of the TFT structures.
- Low temperature poly-silicon (LTPS) material is one of the preferred materials.
- the regular arrangement of atoms of LTPS makes the mobility of charge carriers high.
- driving liquid crystal molecules to rotate can be achieved with a thin-film transistor having a smaller size.
- Hot carrier effect is an important mechanism of failure of metal oxide semiconductor (MOS) devices and with the size of the MOS devices being increasingly reduced, the hot carrier injection effect becomes increasingly severe.
- MOS metal oxide semiconductor
- PMOS P-type metal oxide semiconductor
- the electrons are collected by a substrate to form a substrate current; and most of the holes generated by the collision flow to the drain terminal, while a fraction of the holes are acted upon by a longitudinal electric field to inject into the gate terminal and form a gate current. This phenomenon is referred to as “hot carrier injection”.
- the hot carriers may cause breaking of energy bonds at the silicon substrate and silicon oxide gate oxide interface and generate an interface state between the silicon substrate and the silicon oxide gate oxide interface, leading to deterioration of device performance, such as threshold voltage, transconductance and linear zone/saturation zone currents, and eventually resulting in failure of the MOS device.
- the failure of the MOS device generally occurs at the drain terminal first. This is because the charge carriers are accelerated by the electric field in the entire channel and when getting to the drain terminal, the energy of the charge carriers reaches the maximum level. Consequently, the hot carrier injection phenomenon is more severe at the drain terminal. Thus, a hot spot of researches of those working in this field would be to alleviate the damage of a semiconductor device caused by hot carrier injection.
- the charge carrier mobility is around 20-100 times of that of amorphous silicon (a-Si) TFTs and they are readily susceptible to hot carrier injection phenomenon.
- the charge carriers when moving in an intense electric field (>4E10 ⁇ 4V/cm), may acquire an amount of energy from the electric field that is greater than an amount of energy lost by interaction with the crystal lattice so that the speed of the charge carriers may get higher and higher, eventually resulting in the occurrence of hot carrier injection.
- solutions that are commonly adopted are to apply ion injection to form a lightly doped transition zone, such as lightly doped drain (LDD) and gate overlapped lightly doped drain (GOLDD).
- LDD lightly doped drain
- GOLDD gate overlapped lightly doped drain
- An object of the present invention is to provide a thin-film transistor (TFT) substrate manufacturing method, which applies etching to source and drain contact zones of an active layer to have heights thereof lower than a height of a channel zone in the middle and configures the source and drain contact zones in a stepwise form so that due to the formation of the steps in the drain contact zone, the peak intensity of the lateral electric field (Vds electric field) around the drain contact zone and the intensity of a longitudinal electric field (Vgs electric field) of the drain contact zone are both reduced, making a pinch-off point shifted toward an edge of the drain contact zone, reducing drifting of threshold voltage, and improving TFT reliability.
- TFT thin-film transistor
- Another object of the present invention is to provide a TFT substrate, which alleviates the hot carrier effect, reducing drifting of threshold voltage Vth, and improve reliability of the thin-film transistor.
- upper surfaces of the first source contact zone and the first drain contact zone become horizontal surfaces or slope surfaces that are lower than an upper surface of the first channel zone so that the upper surfaces of the first source contact zone and the first drain contact zone each form a step with respect to the upper surface of the first channel zone;
- step (4) Injection of N-type ion to the first source contact zone and the first drain contact zone is conducted in step (4) and injection of P-type ion to the second source contact zone and the second drain contact zone is conducted in step (6);
- step (4) injection of P-type ion to the first source contact zone and the first drain contact zone is conducted in step (4) and injection of N-type ion to the second source contact zone and the second drain contact zone is conducted in step (6).
- the present invention also provides a TFT substrate, which comprises: a substrate, a buffer layer formed on the substrate, a first active layer and a second active layer formed on the buffer layer, a gate insulation layer formed on the first active layer and the second active layer, a first gate terminal and a second gate terminal formed on the gate insulation layer and respectively corresponding to the first active layer and the second active layer, an interlayer dielectric layer formed on the first gate terminal and the second gate terminal, a first source terminal, a first drain terminal, a second source terminal, and a second drain terminal formed on the interlayer dielectric layer, a planarization layer formed on the first source terminal, the first drain terminal, the second source terminal, and the second drain terminal, a passivation layer formed on the planarization layer, and a pixel electrode formed on the passivation layer;
- first active layer and the second active layer are both low temperature poly-silicon layers
- the second active layer comprises a second channel zone located in a middle portion thereof and exactly corresponding to the second gate terminal and a second source contact zone and a second drain contact zone respectively located on opposite sides of the second channel zone.
- Impurity for doping of the N-type heavily-doped zones comprises phosphorous ion and impurity for doping of the P-type heavily-doped zones comprises boron ion.
- the interlayer dielectric layer and the gate insulation layer comprise, formed therein, first vias respectively corresponding to the first source contact zone and the first drain contact zone and second vias respectively corresponding to the second source contact zone and the second drain contact zone, wherein the first source terminal and the first drain terminal are respectively connected through the first vias to the first source contact zone and the first drain contact zone and the second source terminal and the second drain terminal are respectively connected through the second vias to the second source contact zone and the second drain contact zone; and
- the present invention further provides a TFT substrate, which comprises: a substrate, a buffer layer formed on the substrate, a first active layer and a second active layer formed on the buffer layer, a gate insulation layer formed on the first active layer and the second active layer, a first gate terminal and a second gate terminal formed on the gate insulation layer and respectively corresponding to the first active layer and the second active layer, an interlayer dielectric layer formed on the first gate terminal and the second gate terminal, a first source terminal, a first drain terminal, a second source terminal, and a second drain terminal formed on the interlayer dielectric layer, a planarization layer formed on the first source terminal, the first drain terminal, the second source terminal, and the second drain terminal, a passivation layer formed on the planarization layer, and a pixel electrode formed on the passivation layer;
- first active layer and the second active layer are both low temperature poly-silicon layers
- the second active layer comprises a second channel zone located in a middle portion thereof and exactly corresponding to the second gate terminal and a second source contact zone and a second drain contact zone respectively located on opposite sides of the second channel zone;
- first source contact zone and the first drain contact zone have upper surfaces that are horizontal surfaces or slope surfaces that are lower than an upper surface of the first channel zone so that the upper surfaces of the first source contact zone and the first drain contact zone each form a step with respect to the upper surface of the first channel zone,
- the upper surfaces of the first source contact zone and the first drain contact zone each comprise a plurality of steps having heights reduced stepwise in a direction from the first channel zone to the outside, the steps having step surfaces that are horizontal surfaces or slope surfaces;
- first source contact zone and the first drain contact zone are N-type heavily-doped zones and the second source contact zone and the second drain contact zone are P-type heavily-doped zones
- the first source contact zone and the first drain contact zone are P-type heavily-doped zones and the second source contact zone and the second drain contact zones are N-type heavily-doped zones;
- interlayer dielectric layer and the gate insulation layer comprise, formed therein, first vias respectively corresponding to the first source contact zone and the first drain contact zone and second vias respectively corresponding to the second source contact zone and the second drain contact zone, wherein the first source terminal and the first drain terminal are respectively connected through the first vias to the first source contact zone and the first drain contact zone and the second source terminal and the second drain terminal are respectively connected through the second vias to the second source contact zone and the second drain contact zone, and
- planarization layer and the passivation layer comprise a third via formed therein and corresponding to the second drain terminal and the pixel electrode is connected through the third via to the second drain terminal.
- the efficacy of the present invention is that the present invention provides a TFT substrate manufacturing method, which applies etching to source and drain contact zones of an active layer to have heights thereof lower than a height of a channel zone in the middle and configures the source and drain contact zones in a stepwise form so that charge carriers are affected by an electric field (Vds electric field) that is deviated in a direction away from a poly-silicon/gate insulation layer interface and the migration path thereof is caused to shift away from the poly-silicon/gate insulation layer interface thereby reducing the injection of high energy carriers into the gate insulation layer.
- Vds electric field an electric field
- the peak intensity of the lateral electric field (Vds electric field) around the drain contact zone and the intensity of a longitudinal electric field (Vgs electric field) of the drain contact zone are both reduced, making a pinch-off point shifted toward an edge of the drain contact zone, reducing drifting of threshold voltage, and improving TFT reliability.
- a TFT substrate according to the present invention is structured to have the heights of source and drain contact zones of an active layer lower than a height of a channel zone in the middle and to configure the source and drain contact zones in a stepwise form so that the peak intensity of a lateral electric field (Vds electric field) around the drain contact zone and the intensity of a longitudinal electric field (Vgs electric field) of the drain contact zone are both reduced, making a pinch-off point shifted toward an edge of the drain contact zone, reducing drifting of threshold voltage, and improving TFT reliability.
- Vds electric field a lateral electric field
- Vgs electric field longitudinal electric field
- FIG. 1 is a schematic view illustrating a first step of a thin-film transistor (TFT) substrate manufacturing method according to the present invention
- FIG. 2 is a schematic view illustrating a second step of the TFT substrate manufacturing method according to the present invention.
- FIG. 3 is a schematic view illustrating a third step of the TFT substrate manufacturing method according to the present invention.
- FIG. 4 is a schematic view illustrating a fourth step of the TFT substrate manufacturing method according to the present invention.
- FIG. 5 is a schematic view illustrating a fifth step of the TFT substrate manufacturing method according to the present invention.
- FIG. 6 is a schematic view illustrating a sixth step of the TFT substrate manufacturing method according to the present invention.
- FIG. 7 is a schematic view illustrating a seventh step of the TFT substrate manufacturing method according to the present invention.
- FIG. 8 is a schematic view illustrating an eighth step of the TFT substrate manufacturing method according to the present invention.
- FIG. 9 is a schematic view illustrating a ninth step of the TFT substrate manufacturing method according to the present invention.
- FIG. 10 is a schematic view illustrating a tenth step of the TFT substrate manufacturing method according to the present invention and is also a schematic view illustrating a structure of a TFT substrate according to the present invention.
- the present invention provides a thin-film transistor (TFT) substrate manufacturing method, which comprises the following steps:
- Step 1 as shown in FIG. 1 , providing a substrate 1 and sequentially depositing a buffer layer 2 and an amorphous silicon layer 21 on the substrate 1 .
- the buffer layer 2 can be a silicon oxide (SiO x ) layer, a silicon nitride (SiN x ) layer, or a stacked combination of a silicon oxide layer and a silicon nitride layer.
- Step 2 as shown in FIG. 2 , subjecting the amorphous silicon layer 21 to excimer laser annealing (ELA) or solid phase crystallization (SPC) to convert the amorphous silicon layer into a low temperature poly-silicon layer and applying a photolithographic process to pattern the low temperature poly-silicon layer to form a first active layer 31 and a second active layer 32 that are spaced from each other.
- ELA excimer laser annealing
- SPC solid phase crystallization
- Step 3 as shown in FIG. 3 , coating a photoresist layer 30 on the first active layer 31 , the second active layer 32 , and the substrate 1 , subjecting the photoresist layer 30 to exposure and development to expose two end portions of the first active layer 31 , using the photoresist layer 30 as a shielding layer to subject the two end portions of the first active layer 31 to injection of N-type or P-type ion so as to form a first source contact zone 311 and a first drain contact zone 312 respectively at the two end portions of the first active layer 31 ; and defining a zone between the first source contact zone 311 and the first drain contact zone 312 as a first channel zone 313 .
- the N-type ion can be pentavalent ion, such as phosphorous ion
- the P-type ion can be trivalent ion, such as boron ion.
- Step 4 as shown in FIG. 4 , subjecting the photoresist layer 30 to ashing and partly etching off the first source contact zone 311 and the first drain contact zone 312 of the first active layer 31 in such a way that heights of the first source contact zone 311 and the first drain contact zone 312 are both less than a height of the first channel zone 313 .
- upper surfaces of the first source contact zone 311 and the first drain contact zone 312 become horizontal surfaces (as shown in FIG. 4 ) or slope surfaces that are lower than an upper surface of the first channel zone 313 .
- the upper surfaces of the first source contact zone 311 and the first drain contact zone 312 each form a step with respect to the upper surface of the first channel zone 313 .
- the step surface shows a height difference of 10-1000 ⁇ from the upper surface of and the first channel zone 313 ;
- the upper surfaces of the first source contact zone 311 and the first drain contact zone 312 each comprise a plurality of steps of which the heights are reduced stepwise in a direction from the first channel zone 313 to the outside. These steps have step surfaces that are horizontal surfaces or slope surfaces and the height difference between two adjacent step surfaces is 10-1000 ⁇ .
- the ashing treatment of the photoresist layer 30 and the etching operation of first source contact zone 311 and the first drain contact zone 312 can be carried out simultaneously.
- oxygen is applied to ash the photoresist layer 55 and, in the oxygen gas, an etchant gas that is active to poly-silicon is mixed to etch the first source contact zone 311 and the first drain contact zone 312 .
- the ashing treatment of the photoresist layer 30 and the etching operation of first source contact zone 311 and the first drain contact zone 312 can be carried out separately in two stages. For example, oxygen is first applied to ash the photoresist layer 30 and then, other measures, such as a photolithographic process, are conducted to etch the first source contact zone 311 and the first drain contact zone 312 .
- Step 5 as shown in FIG. 5 , peeling off the photoresist layer 30 , depositing a gate insulation layer 4 on the first active layer 31 , the second active layer 32 , and the substrate 1 , depositing a first metal layer on the gate insulation layer 4 , applying a photolithographic process to pattern the first metal layer in order to form a first gate terminal 51 and a second gate terminal 52 respectively located above and corresponding to the first active layer 31 and the second active layer 32 .
- the gate insulation layer 4 can be a silicon oxide layer, a silicon nitride layer, or a stacked combination of a silicon oxide layer and a silicon nitride layer.
- the first metal layer can be a composite layer structure comprising an aluminum layer interposed between two molybdenum layers (Mo/Al/Mo), or alternatively, a composite layer structure comprising an aluminum layer interposed between two titanium layers (Ti/Al/Ti).
- Step 6 as shown in FIG. 6 , coating a photoresist layer 50 on the first gate terminal 51 and the second gate terminal 52 and subjecting the photoresist layer 50 to exposure and development to expose the second gate terminal 52 and a portion of the gate insulation layer 4 corresponding to the second active layer 32 ; using the second gate terminal 52 as a shielding layer to subject two end portions of the second active layer 32 to injection of P-type or N-type ion to form a second source contact zone 321 and a second drain contact zone 322 respectively at the two ends of the second active layer 32 ; defining a zone between the second source contact zone 321 and the second drain contact zone 322 as a second channel zone 323 .
- the N-type ion can be pentavalent ion, such as phosphorous ion
- the P-type ion can be trivalent ion, such as boron ion.
- N-type ion is injected to the second source contact zone 321 and the second drain contact zone 322 in Step 6 .
- Step 7 peeling off the photoresist layer 50 , depositing an interlayer dielectric layer 6 on the first gate terminal 51 and the second gate terminal 52 , and the gate insulation layer 4 , applying a photolithographic process to pattern the interlayer dielectric layer 6 and the gate insulation layer 4 to form, in the interlayer dielectric layer 6 and the gate insulation layer 4 , first vias 61 respectively corresponding to the first source contact zone 311 and the first drain contact zone 312 and second vias 62 respectively corresponding to the second source contact zone 321 and the second drain contact zone 322 .
- Step 8 depositing a second metal layer on the interlayer dielectric layer 6 and applying a photolithographic process to pattern the second metal layer so as to form a first source terminal 71 , a first drain terminal 72 , a second source terminal 73 , and a second drain terminal 74 , wherein the first source terminal 71 and the first drain terminal 72 are respectively connected through the first vias 61 to the first source contact zone 311 and the first drain contact zone 312 and the second source terminal 73 and the second drain terminal 74 are respectively connected through the second vias 62 to the second source contact zone 321 and the second drain contact zone 322 .
- the second metal layer can be a composite layer structure comprising an aluminum layer interposed between two molybdenum layers (Mo/Al/Mo), or alternatively a composite layer structure comprising an aluminum layer interposed between two titanium layers (Ti/Al/Ti).
- Step 9 as shown in FIG. 9 , coating a planarization layer 8 on the first source terminal 71 , the first drain terminal 72 , the second source terminal 73 , the second drain terminal 74 , and the interlayer dielectric layer 6 and depositing a passivation layer 9 on the planarization layer 8 and applying a photolithographic process to pattern the planarization layer 8 and the passivation layer 9 to form a third via 91 in the planarization layer 8 and the passivation layer 9 to correspond to the second drain terminal 74 .
- Step 10 depositing a transparent conductive semiconductor layer on the passivation layer 9 and applying a photolithographic process to pattern the transparent conductive semiconductor layer to form a pixel electrode 10 , wherein the pixel electrode 10 is connected through the third via 91 to the second drain terminal 74 thereby completing the manufacture of a TFT substrate.
- the transparent conductive semiconductor layer is formed of a material of ITO (Indium Tin Oxide).
- the present invention also provides a TFT substrate, which comprises: a substrate 1 , a buffer layer 2 formed on the substrate 1 , a first active layer 31 and a second active layer 32 formed on the buffer layer 2 , a gate insulation layer 4 formed on the first active layer 31 and the second active layer 32 , a first gate terminal 51 and a second gate terminal 52 formed on the gate insulation layer 4 and respectively corresponding to the first active layer 31 and the second active layer 32 , an interlayer dielectric layer 6 formed on the first gate terminal 51 and the second gate terminal 52 , a first source terminal 71 , a first drain terminal 72 , a second source terminal 73 , and a second drain terminal 74 formed on the interlayer dielectric layer 6 , a planarization layer 8 formed on the first source terminal 71 , the first drain terminal 72 , the second source terminal 73 , and the second drain terminal 74 , a passivation layer 9 formed on the planarization layer 8
- the first active layer 31 and the second active layer 32 are both low temperature poly-silicon layers.
- the first active layer 31 comprises a first channel zone 313 located in a middle thereof and a first source contact zone 311 and a first drain contact zone 312 respectively located on opposite sides of the first channel zone 313 .
- the first source contact zone 311 and the first drain contact zone 312 have heights that are less than a height of the first channel zone 313 .
- the first source contact zone 311 and the first drain contact zone 312 have upper surfaces that are horizontal surfaces (as shown in FIG. 10 ) or slope surfaces that are lower than an upper surface of the first channel zone 313 .
- the upper surfaces of the first source contact zone 311 and the first drain contact zone 312 each form a step with respect to the upper surface of the first channel zone 313 .
- the step surface shows a height difference of 10-1000 ⁇ from the upper surface of and the first channel zone 313 ;
- the upper surfaces of the first source contact zone 311 and the first drain contact zone 312 each comprise a plurality of steps of which the heights are reduced stepwise in a direction from the first channel zone 313 to the outside. These steps have step surfaces that are horizontal surfaces or slope surfaces and the height difference between two adjacent step surfaces is 10-1000 ⁇ .
- the second active layer 32 comprises a second channel zone 323 located in a middle portion thereof and exactly corresponding to the second gate terminal 52 and a second source contact zone 321 and a second drain contact zone 322 respectively located on opposite sides of the second channel zone 323 .
- first source contact zone 311 and the first drain contact zone 312 are N-type heavily-doped zones and the second source contact zone 321 and the second drain contact zone 322 are P-type heavily-doped zones;
- the first source contact zone 311 and the first drain contact zone 312 are P-type heavily-doped zones and the second source contact zone 321 and the second drain contact zone 322 are N-type heavily-doped zones.
- the impurity that is used for doping in the N-type heavily-doped zones can be pentavalent ion, such as phosphorous ion, and the impurity that is used for doping in the P-type heavily-doped zones can be trivalent ion, such as boron ion.
- the interlayer dielectric layer 6 and the gate insulation layer 4 comprise, formed therein, first vias 61 respectively corresponding to the first source contact zone 311 and the first drain contact zone 312 and second vias 62 respectively corresponding to the second source contact zone 321 and the second drain contact zone 322 , wherein the first source terminal 71 and the first drain terminal 72 are respectively connected through the first vias 61 to the first source contact zone 311 and the first drain contact zone 312 and the second source terminal 73 and the second drain terminal 74 are respectively connected through the second vias 62 to the second source contact zone 321 and the second drain contact zone 322 .
- planarization layer 8 and the passivation layer 9 comprise a third via 91 formed therein and corresponding to the second drain terminal 74 .
- the pixel electrode 10 is connected through the third via 91 to the second drain terminal 74 .
- the buffer layer 2 can be a silicon oxide (SiO x ) layer, a silicon nitride (SiN x ) layer, or a stacked combination of a silicon oxide layer and a silicon nitride layer.
- the first gate terminal 51 , the second gate terminal 52 , the first source terminal 71 , the first drain terminal 72 , the second source terminal 73 , and the second drain terminal 74 can each be a composite layer structure comprising an aluminum layer interposed between two molybdenum layers (Mo/Al/Mo) or a composite layer structure comprising an aluminum layer interposed between two titanium layers (Ti/Al/Ti).
- the pixel electrode 10 is formed of a material of ITO (Indium Tin Oxide).
- the present invention provides a TFT substrate manufacturing method, which applies etching to source and drain contact zones of an active layer to have heights thereof lower than a height of a channel zone in the middle and configures the source and drain contact zones in a stepwise form so that charge carriers are affected by an electric field (Vds electric field) that is deviated in a direction away from a poly-silicon/gate insulation layer interface and the migration path thereof is caused to shift away from the poly-silicon/gate insulation layer interface thereby reducing the injection of high energy carriers into the gate insulation layer.
- Vds electric field an electric field
- the peak intensity of the lateral electric field (Vds electric field) around the drain contact zone and the intensity of a longitudinal electric field (Vgs electric field) of the drain contact zone are both reduced, making a pinch-off point shifted toward an edge of the drain contact zone, reducing drifting of threshold voltage, and improving TFT reliability.
- a TFT substrate according to the present invention is structured to have the heights of source and drain contact zones of an active layer lower than a height of a channel zone in the middle and to configure the source and drain contact zones in a stepwise form so that the peak intensity of a lateral electric field (Vds electric field) around the drain contact zone and the intensity of a longitudinal electric field (Vgs electric field) of the drain contact zone are both reduced, making a pinch-off point shifted toward an edge of the drain contact zone, reducing drifting of threshold voltage, and improving TFT reliability.
- Vds electric field a lateral electric field
- Vgs electric field longitudinal electric field
Abstract
Description
- The present invention relates to the field of display technology, and in particular to a thin-film-transistor (TFT) substrate manufacturing method and a TFT substrate.
- Thin-film transistors (TFTs) are currently the primary driving device of liquid crystal displays (LCDs) and active matrix organic light-emitting diodes (AMOLEDs) and are directly related to the development of high performance flat panel display devices. The TFTs have various structures and there are various materials that are used to make the corresponding ones of the TFT structures. Low temperature poly-silicon (LTPS) material is one of the preferred materials. The regular arrangement of atoms of LTPS makes the mobility of charge carriers high. For the liquid crystal displays that are driven by voltage, due to the relatively high mobility that a poly-silicon thin-film transistor may have, driving liquid crystal molecules to rotate can be achieved with a thin-film transistor having a smaller size. This greatly reduces the space occupied by the thin-film transistor and thus increases the light transmitting area and provides increased brightness and resolution. For AMOLEDs that are driven by current, a LTPS TFT may better suit the need for driving current. Hot carrier effect is an important mechanism of failure of metal oxide semiconductor (MOS) devices and with the size of the MOS devices being increasingly reduced, the hot carrier injection effect becomes increasingly severe. Taking P-type metal oxide semiconductor (PMOS) device as an example, holes existing in the channel are acted upon by an intense lateral electric field established between the drain and source terminals to get accelerated and become high energy carriers. The high energy carriers collide the crystal lattice of silicon and generate electron-hole pairs through ionization. The electrons are collected by a substrate to form a substrate current; and most of the holes generated by the collision flow to the drain terminal, while a fraction of the holes are acted upon by a longitudinal electric field to inject into the gate terminal and form a gate current. This phenomenon is referred to as “hot carrier injection”.
- The hot carriers may cause breaking of energy bonds at the silicon substrate and silicon oxide gate oxide interface and generate an interface state between the silicon substrate and the silicon oxide gate oxide interface, leading to deterioration of device performance, such as threshold voltage, transconductance and linear zone/saturation zone currents, and eventually resulting in failure of the MOS device. The failure of the MOS device generally occurs at the drain terminal first. This is because the charge carriers are accelerated by the electric field in the entire channel and when getting to the drain terminal, the energy of the charge carriers reaches the maximum level. Consequently, the hot carrier injection phenomenon is more severe at the drain terminal. Thus, a hot spot of researches of those working in this field would be to alleviate the damage of a semiconductor device caused by hot carrier injection.
- For LTPS TFTs, the charge carrier mobility is around 20-100 times of that of amorphous silicon (a-Si) TFTs and they are readily susceptible to hot carrier injection phenomenon. The charge carriers, when moving in an intense electric field (>4E10̂4V/cm), may acquire an amount of energy from the electric field that is greater than an amount of energy lost by interaction with the crystal lattice so that the speed of the charge carriers may get higher and higher, eventually resulting in the occurrence of hot carrier injection. To alleviate the damage caused by hot carrier injection, solutions that are commonly adopted are to apply ion injection to form a lightly doped transition zone, such as lightly doped drain (LDD) and gate overlapped lightly doped drain (GOLDD). These solutions, however, are complicated and are readily susceptible to doping deviation to result in failure.
- An object of the present invention is to provide a thin-film transistor (TFT) substrate manufacturing method, which applies etching to source and drain contact zones of an active layer to have heights thereof lower than a height of a channel zone in the middle and configures the source and drain contact zones in a stepwise form so that due to the formation of the steps in the drain contact zone, the peak intensity of the lateral electric field (Vds electric field) around the drain contact zone and the intensity of a longitudinal electric field (Vgs electric field) of the drain contact zone are both reduced, making a pinch-off point shifted toward an edge of the drain contact zone, reducing drifting of threshold voltage, and improving TFT reliability.
- Another object of the present invention is to provide a TFT substrate, which alleviates the hot carrier effect, reducing drifting of threshold voltage Vth, and improve reliability of the thin-film transistor.
- To achieve the above objects, the present invention provides a TFT substrate manufacturing method, which comprises the following steps:
- (1) providing a substrate and sequentially depositing a buffer layer and an amorphous silicon layer on the substrate;
- (2) subjecting the amorphous silicon layer to excimer laser annealing or solid phase crystallization to convert the amorphous silicon layer into a low temperature poly-silicon layer and applying a photolithographic process to pattern the low temperature poly-silicon layer to form a first active layer and a second active layer that are spaced from each other;
- (3) coating a photoresist layer on the first active layer, the second active layer, and the substrate, subjecting the photoresist layer to exposure and development to expose two end portions of the first active layer, using the photoresist layer as a shielding layer to subject the two end portions of the first active layer to injection of N-type or P-type ion so as to form a first source contact zone and a first drain contact zone respectively at the two end portions of the first active layer; and defining a zone between the first source contact zone and the first drain contact zone as a first channel zone;
- (4) subjecting the photoresist layer to ashing and partly etching off the first source contact zone and the first drain contact zone of the first active layer in such a way that heights of the first source contact zone and the first drain contact zone are both less than a height of the first channel zone;
- (5) peeling off the photoresist layer, depositing a gate insulation layer on the first active layer, the second active layer, and the substrate, depositing a first metal layer on the gate insulation layer, applying a photolithographic process to pattern the first metal layer in order to form a first gate terminal and a second gate terminal respectively located above and corresponding to the first active layer and the second active layer;
- (6) coating a photoresist layer on the first gate terminal and the second gate terminal and subjecting the photoresist layer to exposure and development to expose the second gate terminal and a portion of the gate insulation layer corresponding to the second active layer; using the second gate terminal as a shielding layer to subject two end portions of the second active layer to injection of P-type or N-type ion to form a second source contact zone and a second drain contact zone respectively at the two ends of the second active layer; defining a zone between the second source contact zone and the second drain contact zone as a second channel zone;
- (7) peeling off the photoresist layer, depositing an interlayer dielectric layer on the first gate terminal and the second gate terminal, and the gate insulation layer, applying a photolithographic process to pattern the interlayer dielectric layer and the gate insulation layer to form, in the interlayer dielectric layer and the gate insulation layer, first vias respectively corresponding to the first source contact zone and the first drain contact zone and second vias respectively corresponding to the second source contact zone and the second drain contact zone;
- (8) depositing a second metal layer on the interlayer dielectric layer and applying a photolithographic process to pattern the second metal layer so as to form a first source terminal, a first drain terminal, a second source terminal, and a second drain terminal, wherein the first source terminal and the first drain terminal are respectively connected through the first vias to the first source contact zone and the first drain contact zone and the second source terminal and the second drain terminal are respectively connected through the second vias to the second source contact zone and the second drain contact zone;
- (9) coating a planarization layer on the first source terminal, the first drain terminal, the second source terminal, the second drain terminal, and the interlayer dielectric layer and depositing a passivation layer on the planarization layer and applying a photolithographic process to pattern the planarization layer and the passivation layer to form a third via in the planarization layer and the passivation layer to correspond to the second drain terminal; and
- (10) depositing a transparent conductive semiconductor layer on the passivation layer and applying a photolithographic process to pattern the transparent conductive semiconductor layer to form a pixel electrode, wherein the pixel electrode is connected through the third via to the second drain terminal thereby completing the manufacture of a TFT substrate.
- Through the etching conducted in step (4), upper surfaces of the first source contact zone and the first drain contact zone become horizontal surfaces or slope surfaces that are lower than an upper surface of the first channel zone so that the upper surfaces of the first source contact zone and the first drain contact zone each form a step with respect to the upper surface of the first channel zone;
- or alternatively, the upper surfaces of the first source contact zone and the first drain contact zone each comprise a plurality of steps having heights reduced stepwise in a direction from the first channel zone to the outside, the steps having step surfaces that are horizontal surfaces or slope surfaces.
- In step (4), oxygen is applied to ash the photoresist layer and, in the oxygen gas, an etchant gas that is active to poly-silicon is mixed to etch the first source contact zone and the first drain contact zone;
- or alternatively, oxygen is first applied to ash the photoresist layer and then, a photolithographic process is conducted to etch the first source contact zone and the first drain contact zone.
- Injection of N-type ion to the first source contact zone and the first drain contact zone is conducted in step (4) and injection of P-type ion to the second source contact zone and the second drain contact zone is conducted in step (6);
- or injection of P-type ion to the first source contact zone and the first drain contact zone is conducted in step (4) and injection of N-type ion to the second source contact zone and the second drain contact zone is conducted in step (6).
- The N-type ion is phosphorous ion and the P-type ion is boron ion.
- The present invention also provides a TFT substrate, which comprises: a substrate, a buffer layer formed on the substrate, a first active layer and a second active layer formed on the buffer layer, a gate insulation layer formed on the first active layer and the second active layer, a first gate terminal and a second gate terminal formed on the gate insulation layer and respectively corresponding to the first active layer and the second active layer, an interlayer dielectric layer formed on the first gate terminal and the second gate terminal, a first source terminal, a first drain terminal, a second source terminal, and a second drain terminal formed on the interlayer dielectric layer, a planarization layer formed on the first source terminal, the first drain terminal, the second source terminal, and the second drain terminal, a passivation layer formed on the planarization layer, and a pixel electrode formed on the passivation layer;
- wherein the first active layer and the second active layer are both low temperature poly-silicon layers;
- the first active layer comprises a first channel zone located in a middle thereof and a first source contact zone and a first drain contact zone respectively located on opposite sides of the first channel zone, the first source contact zone and the first drain contact zone having heights that are less than a height of the first channel zone; and
- the second active layer comprises a second channel zone located in a middle portion thereof and exactly corresponding to the second gate terminal and a second source contact zone and a second drain contact zone respectively located on opposite sides of the second channel zone.
- The first source contact zone and the first drain contact zone have upper surfaces that are horizontal surfaces or slope surfaces that are lower than an upper surface of the first channel zone so that the upper surfaces of the first source contact zone and the first drain contact zone each form a step with respect to the upper surface of the first channel zone;
- or alternatively, the upper surfaces of the first source contact zone and the first drain contact zone each comprise a plurality of steps having heights reduced stepwise in a direction from the first channel zone to the outside, the steps having step surfaces that are horizontal surfaces or slope surfaces.
- The first source contact zone and the first drain contact zone are N-type heavily-doped zones and the second source contact zone and the second drain contact zone are P-type heavily-doped zones;
- or alternatively, the first source contact zone and the first drain contact zone are P-type heavily-doped zones and the second source contact zone and the second drain contact zones are N-type heavily-doped zones.
- Impurity for doping of the N-type heavily-doped zones comprises phosphorous ion and impurity for doping of the P-type heavily-doped zones comprises boron ion.
- The interlayer dielectric layer and the gate insulation layer comprise, formed therein, first vias respectively corresponding to the first source contact zone and the first drain contact zone and second vias respectively corresponding to the second source contact zone and the second drain contact zone, wherein the first source terminal and the first drain terminal are respectively connected through the first vias to the first source contact zone and the first drain contact zone and the second source terminal and the second drain terminal are respectively connected through the second vias to the second source contact zone and the second drain contact zone; and
- the planarization layer and the passivation layer comprise a third via formed therein and corresponding to the second drain terminal and the pixel electrode is connected through the third via to the second drain terminal.
- The present invention further provides a TFT substrate, which comprises: a substrate, a buffer layer formed on the substrate, a first active layer and a second active layer formed on the buffer layer, a gate insulation layer formed on the first active layer and the second active layer, a first gate terminal and a second gate terminal formed on the gate insulation layer and respectively corresponding to the first active layer and the second active layer, an interlayer dielectric layer formed on the first gate terminal and the second gate terminal, a first source terminal, a first drain terminal, a second source terminal, and a second drain terminal formed on the interlayer dielectric layer, a planarization layer formed on the first source terminal, the first drain terminal, the second source terminal, and the second drain terminal, a passivation layer formed on the planarization layer, and a pixel electrode formed on the passivation layer;
- wherein the first active layer and the second active layer are both low temperature poly-silicon layers,
- the first active layer comprises a first channel zone located in a middle thereof and a first source contact zone and a first drain contact zone respectively located on opposite sides of the first channel zone, the first source contact zone and the first drain contact zone having heights that are less than a height of the first channel zone, and
- the second active layer comprises a second channel zone located in a middle portion thereof and exactly corresponding to the second gate terminal and a second source contact zone and a second drain contact zone respectively located on opposite sides of the second channel zone;
- wherein the first source contact zone and the first drain contact zone have upper surfaces that are horizontal surfaces or slope surfaces that are lower than an upper surface of the first channel zone so that the upper surfaces of the first source contact zone and the first drain contact zone each form a step with respect to the upper surface of the first channel zone,
- or alternatively, the upper surfaces of the first source contact zone and the first drain contact zone each comprise a plurality of steps having heights reduced stepwise in a direction from the first channel zone to the outside, the steps having step surfaces that are horizontal surfaces or slope surfaces;
- wherein the first source contact zone and the first drain contact zone are N-type heavily-doped zones and the second source contact zone and the second drain contact zone are P-type heavily-doped zones,
- or alternatively, the first source contact zone and the first drain contact zone are P-type heavily-doped zones and the second source contact zone and the second drain contact zones are N-type heavily-doped zones; and
- wherein the interlayer dielectric layer and the gate insulation layer comprise, formed therein, first vias respectively corresponding to the first source contact zone and the first drain contact zone and second vias respectively corresponding to the second source contact zone and the second drain contact zone, wherein the first source terminal and the first drain terminal are respectively connected through the first vias to the first source contact zone and the first drain contact zone and the second source terminal and the second drain terminal are respectively connected through the second vias to the second source contact zone and the second drain contact zone, and
- the planarization layer and the passivation layer comprise a third via formed therein and corresponding to the second drain terminal and the pixel electrode is connected through the third via to the second drain terminal.
- The efficacy of the present invention is that the present invention provides a TFT substrate manufacturing method, which applies etching to source and drain contact zones of an active layer to have heights thereof lower than a height of a channel zone in the middle and configures the source and drain contact zones in a stepwise form so that charge carriers are affected by an electric field (Vds electric field) that is deviated in a direction away from a poly-silicon/gate insulation layer interface and the migration path thereof is caused to shift away from the poly-silicon/gate insulation layer interface thereby reducing the injection of high energy carriers into the gate insulation layer. Further, due to the formation of the steps in the drain contact zone, the peak intensity of the lateral electric field (Vds electric field) around the drain contact zone and the intensity of a longitudinal electric field (Vgs electric field) of the drain contact zone are both reduced, making a pinch-off point shifted toward an edge of the drain contact zone, reducing drifting of threshold voltage, and improving TFT reliability. A TFT substrate according to the present invention is structured to have the heights of source and drain contact zones of an active layer lower than a height of a channel zone in the middle and to configure the source and drain contact zones in a stepwise form so that the peak intensity of a lateral electric field (Vds electric field) around the drain contact zone and the intensity of a longitudinal electric field (Vgs electric field) of the drain contact zone are both reduced, making a pinch-off point shifted toward an edge of the drain contact zone, reducing drifting of threshold voltage, and improving TFT reliability.
- The features and technical contents of the present invention will be apparent from the following detailed description of the present invention and the attached drawing; however, these drawings are provided for reference and illustration and are not intended to limit the scope of the present invention. In the drawing:
-
FIG. 1 is a schematic view illustrating a first step of a thin-film transistor (TFT) substrate manufacturing method according to the present invention; -
FIG. 2 is a schematic view illustrating a second step of the TFT substrate manufacturing method according to the present invention; -
FIG. 3 is a schematic view illustrating a third step of the TFT substrate manufacturing method according to the present invention; -
FIG. 4 is a schematic view illustrating a fourth step of the TFT substrate manufacturing method according to the present invention; -
FIG. 5 is a schematic view illustrating a fifth step of the TFT substrate manufacturing method according to the present invention; -
FIG. 6 is a schematic view illustrating a sixth step of the TFT substrate manufacturing method according to the present invention; -
FIG. 7 is a schematic view illustrating a seventh step of the TFT substrate manufacturing method according to the present invention; -
FIG. 8 is a schematic view illustrating an eighth step of the TFT substrate manufacturing method according to the present invention; -
FIG. 9 is a schematic view illustrating a ninth step of the TFT substrate manufacturing method according to the present invention; -
FIG. 10 is a schematic view illustrating a tenth step of the TFT substrate manufacturing method according to the present invention and is also a schematic view illustrating a structure of a TFT substrate according to the present invention. - To further expound the technical solution adopted in the present invention and the advantages thereof, a detailed description is given to a preferred embodiment of the present invention and the attached drawings.
- Referring to
FIGS. 1-10 , firstly, the present invention provides a thin-film transistor (TFT) substrate manufacturing method, which comprises the following steps: - Step 1: as shown in
FIG. 1 , providing asubstrate 1 and sequentially depositing abuffer layer 2 and anamorphous silicon layer 21 on thesubstrate 1. - Specifically, the
buffer layer 2 can be a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, or a stacked combination of a silicon oxide layer and a silicon nitride layer. - Step 2: as shown in
FIG. 2 , subjecting theamorphous silicon layer 21 to excimer laser annealing (ELA) or solid phase crystallization (SPC) to convert the amorphous silicon layer into a low temperature poly-silicon layer and applying a photolithographic process to pattern the low temperature poly-silicon layer to form a firstactive layer 31 and a secondactive layer 32 that are spaced from each other. - Step 3: as shown in
FIG. 3 , coating aphotoresist layer 30 on the firstactive layer 31, the secondactive layer 32, and thesubstrate 1, subjecting thephotoresist layer 30 to exposure and development to expose two end portions of the firstactive layer 31, using thephotoresist layer 30 as a shielding layer to subject the two end portions of the firstactive layer 31 to injection of N-type or P-type ion so as to form a firstsource contact zone 311 and a firstdrain contact zone 312 respectively at the two end portions of the firstactive layer 31; and defining a zone between the firstsource contact zone 311 and the firstdrain contact zone 312 as afirst channel zone 313. - Specifically, the N-type ion can be pentavalent ion, such as phosphorous ion, and the P-type ion can be trivalent ion, such as boron ion.
- Step 4: as shown in
FIG. 4 , subjecting thephotoresist layer 30 to ashing and partly etching off the firstsource contact zone 311 and the firstdrain contact zone 312 of the firstactive layer 31 in such a way that heights of the firstsource contact zone 311 and the firstdrain contact zone 312 are both less than a height of thefirst channel zone 313. - Specifically, through the etching operation of
Step 4, upper surfaces of the firstsource contact zone 311 and the firstdrain contact zone 312 become horizontal surfaces (as shown inFIG. 4 ) or slope surfaces that are lower than an upper surface of thefirst channel zone 313. In other words, the upper surfaces of the firstsource contact zone 311 and the firstdrain contact zone 312 each form a step with respect to the upper surface of thefirst channel zone 313. The step surface shows a height difference of 10-1000 Å from the upper surface of and thefirst channel zone 313; - or alternatively, the upper surfaces of the first
source contact zone 311 and the firstdrain contact zone 312 each comprise a plurality of steps of which the heights are reduced stepwise in a direction from thefirst channel zone 313 to the outside. These steps have step surfaces that are horizontal surfaces or slope surfaces and the height difference between two adjacent step surfaces is 10-1000 Å. - Specifically, the ashing treatment of the
photoresist layer 30 and the etching operation of firstsource contact zone 311 and the firstdrain contact zone 312 can be carried out simultaneously. For example, oxygen is applied to ash the photoresist layer 55 and, in the oxygen gas, an etchant gas that is active to poly-silicon is mixed to etch the firstsource contact zone 311 and the firstdrain contact zone 312. - Specifically, the ashing treatment of the
photoresist layer 30 and the etching operation of firstsource contact zone 311 and the firstdrain contact zone 312 can be carried out separately in two stages. For example, oxygen is first applied to ash thephotoresist layer 30 and then, other measures, such as a photolithographic process, are conducted to etch the firstsource contact zone 311 and the firstdrain contact zone 312. - Step 5: as shown in
FIG. 5 , peeling off thephotoresist layer 30, depositing agate insulation layer 4 on the firstactive layer 31, the secondactive layer 32, and thesubstrate 1, depositing a first metal layer on thegate insulation layer 4, applying a photolithographic process to pattern the first metal layer in order to form afirst gate terminal 51 and asecond gate terminal 52 respectively located above and corresponding to the firstactive layer 31 and the secondactive layer 32. - Specifically, the
gate insulation layer 4 can be a silicon oxide layer, a silicon nitride layer, or a stacked combination of a silicon oxide layer and a silicon nitride layer. - Specifically, the first metal layer can be a composite layer structure comprising an aluminum layer interposed between two molybdenum layers (Mo/Al/Mo), or alternatively, a composite layer structure comprising an aluminum layer interposed between two titanium layers (Ti/Al/Ti).
- Step 6: as shown in
FIG. 6 , coating aphotoresist layer 50 on thefirst gate terminal 51 and thesecond gate terminal 52 and subjecting thephotoresist layer 50 to exposure and development to expose thesecond gate terminal 52 and a portion of thegate insulation layer 4 corresponding to the secondactive layer 32; using thesecond gate terminal 52 as a shielding layer to subject two end portions of the secondactive layer 32 to injection of P-type or N-type ion to form a secondsource contact zone 321 and a seconddrain contact zone 322 respectively at the two ends of the secondactive layer 32; defining a zone between the secondsource contact zone 321 and the seconddrain contact zone 322 as asecond channel zone 323. - Specifically, the N-type ion can be pentavalent ion, such as phosphorous ion, and the P-type ion can be trivalent ion, such as boron ion.
- Specifically, when N-type ion is injected into the first
source contact zone 311 and the firstdrain contact zone 312 inStep 4, P-type ion is injected to the secondsource contact zone 321 and the seconddrain contact zone 322 inStep 6; - when P-type ion is injected to the first
source contact zone 311 and the firstdrain contact zone 312 inStep 4, N-type ion is injected to the secondsource contact zone 321 and the seconddrain contact zone 322 inStep 6. - Step 7: as shown in
FIG. 7 , peeling off thephotoresist layer 50, depositing aninterlayer dielectric layer 6 on thefirst gate terminal 51 and thesecond gate terminal 52, and thegate insulation layer 4, applying a photolithographic process to pattern theinterlayer dielectric layer 6 and thegate insulation layer 4 to form, in theinterlayer dielectric layer 6 and thegate insulation layer 4,first vias 61 respectively corresponding to the firstsource contact zone 311 and the firstdrain contact zone 312 andsecond vias 62 respectively corresponding to the secondsource contact zone 321 and the seconddrain contact zone 322. - Step 8: as shown in
FIG. 8 , depositing a second metal layer on theinterlayer dielectric layer 6 and applying a photolithographic process to pattern the second metal layer so as to form afirst source terminal 71, afirst drain terminal 72, asecond source terminal 73, and asecond drain terminal 74, wherein thefirst source terminal 71 and thefirst drain terminal 72 are respectively connected through thefirst vias 61 to the firstsource contact zone 311 and the firstdrain contact zone 312 and thesecond source terminal 73 and thesecond drain terminal 74 are respectively connected through thesecond vias 62 to the secondsource contact zone 321 and the seconddrain contact zone 322. - Specifically, the second metal layer can be a composite layer structure comprising an aluminum layer interposed between two molybdenum layers (Mo/Al/Mo), or alternatively a composite layer structure comprising an aluminum layer interposed between two titanium layers (Ti/Al/Ti).
- Step 9: as shown in
FIG. 9 , coating aplanarization layer 8 on thefirst source terminal 71, thefirst drain terminal 72, thesecond source terminal 73, thesecond drain terminal 74, and theinterlayer dielectric layer 6 and depositing a passivation layer 9 on theplanarization layer 8 and applying a photolithographic process to pattern theplanarization layer 8 and the passivation layer 9 to form a third via 91 in theplanarization layer 8 and the passivation layer 9 to correspond to thesecond drain terminal 74. - Step 10: as shown in
FIG. 10 , depositing a transparent conductive semiconductor layer on the passivation layer 9 and applying a photolithographic process to pattern the transparent conductive semiconductor layer to form apixel electrode 10, wherein thepixel electrode 10 is connected through the third via 91 to thesecond drain terminal 74 thereby completing the manufacture of a TFT substrate. - Specifically, the transparent conductive semiconductor layer is formed of a material of ITO (Indium Tin Oxide).
- Referring to
FIG. 10 , based on the TFT substrate manufacturing method described above, the present invention also provides a TFT substrate, which comprises: asubstrate 1, abuffer layer 2 formed on thesubstrate 1, a firstactive layer 31 and a secondactive layer 32 formed on thebuffer layer 2, agate insulation layer 4 formed on the firstactive layer 31 and the secondactive layer 32, afirst gate terminal 51 and asecond gate terminal 52 formed on thegate insulation layer 4 and respectively corresponding to the firstactive layer 31 and the secondactive layer 32, aninterlayer dielectric layer 6 formed on thefirst gate terminal 51 and thesecond gate terminal 52, afirst source terminal 71, afirst drain terminal 72, asecond source terminal 73, and asecond drain terminal 74 formed on theinterlayer dielectric layer 6, aplanarization layer 8 formed on thefirst source terminal 71, thefirst drain terminal 72, thesecond source terminal 73, and thesecond drain terminal 74, a passivation layer 9 formed on theplanarization layer 8, and apixel electrode 10 formed on the passivation layer 9. - Specifically, the first
active layer 31 and the secondactive layer 32 are both low temperature poly-silicon layers. - Specifically, the first
active layer 31 comprises afirst channel zone 313 located in a middle thereof and a firstsource contact zone 311 and a firstdrain contact zone 312 respectively located on opposite sides of thefirst channel zone 313. The firstsource contact zone 311 and the firstdrain contact zone 312 have heights that are less than a height of thefirst channel zone 313. - Specifically, the first
source contact zone 311 and the firstdrain contact zone 312 have upper surfaces that are horizontal surfaces (as shown inFIG. 10 ) or slope surfaces that are lower than an upper surface of thefirst channel zone 313. In other words, the upper surfaces of the firstsource contact zone 311 and the firstdrain contact zone 312 each form a step with respect to the upper surface of thefirst channel zone 313. The step surface shows a height difference of 10-1000 Å from the upper surface of and thefirst channel zone 313; - or alternatively, the upper surfaces of the first
source contact zone 311 and the firstdrain contact zone 312 each comprise a plurality of steps of which the heights are reduced stepwise in a direction from thefirst channel zone 313 to the outside. These steps have step surfaces that are horizontal surfaces or slope surfaces and the height difference between two adjacent step surfaces is 10-1000 Å. - Specifically, the second
active layer 32 comprises asecond channel zone 323 located in a middle portion thereof and exactly corresponding to thesecond gate terminal 52 and a secondsource contact zone 321 and a seconddrain contact zone 322 respectively located on opposite sides of thesecond channel zone 323. - Specifically, the first
source contact zone 311 and the firstdrain contact zone 312 are N-type heavily-doped zones and the secondsource contact zone 321 and the seconddrain contact zone 322 are P-type heavily-doped zones; - or alternatively, the first
source contact zone 311 and the firstdrain contact zone 312 are P-type heavily-doped zones and the secondsource contact zone 321 and the seconddrain contact zone 322 are N-type heavily-doped zones. - The impurity that is used for doping in the N-type heavily-doped zones can be pentavalent ion, such as phosphorous ion, and the impurity that is used for doping in the P-type heavily-doped zones can be trivalent ion, such as boron ion.
- Specifically, the
interlayer dielectric layer 6 and thegate insulation layer 4 comprise, formed therein,first vias 61 respectively corresponding to the firstsource contact zone 311 and the firstdrain contact zone 312 andsecond vias 62 respectively corresponding to the secondsource contact zone 321 and the seconddrain contact zone 322, wherein thefirst source terminal 71 and thefirst drain terminal 72 are respectively connected through thefirst vias 61 to the firstsource contact zone 311 and the firstdrain contact zone 312 and thesecond source terminal 73 and thesecond drain terminal 74 are respectively connected through thesecond vias 62 to the secondsource contact zone 321 and the seconddrain contact zone 322. - Specifically, the
planarization layer 8 and the passivation layer 9 comprise a third via 91 formed therein and corresponding to thesecond drain terminal 74. Thepixel electrode 10 is connected through the third via 91 to thesecond drain terminal 74. - Specifically, the
buffer layer 2 can be a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, or a stacked combination of a silicon oxide layer and a silicon nitride layer. - The
first gate terminal 51, thesecond gate terminal 52, thefirst source terminal 71, thefirst drain terminal 72, thesecond source terminal 73, and thesecond drain terminal 74 can each be a composite layer structure comprising an aluminum layer interposed between two molybdenum layers (Mo/Al/Mo) or a composite layer structure comprising an aluminum layer interposed between two titanium layers (Ti/Al/Ti). - Specifically, the
pixel electrode 10 is formed of a material of ITO (Indium Tin Oxide). - In summary, the present invention provides a TFT substrate manufacturing method, which applies etching to source and drain contact zones of an active layer to have heights thereof lower than a height of a channel zone in the middle and configures the source and drain contact zones in a stepwise form so that charge carriers are affected by an electric field (Vds electric field) that is deviated in a direction away from a poly-silicon/gate insulation layer interface and the migration path thereof is caused to shift away from the poly-silicon/gate insulation layer interface thereby reducing the injection of high energy carriers into the gate insulation layer. Further, due to the formation of the steps in the drain contact zone, the peak intensity of the lateral electric field (Vds electric field) around the drain contact zone and the intensity of a longitudinal electric field (Vgs electric field) of the drain contact zone are both reduced, making a pinch-off point shifted toward an edge of the drain contact zone, reducing drifting of threshold voltage, and improving TFT reliability. A TFT substrate according to the present invention is structured to have the heights of source and drain contact zones of an active layer lower than a height of a channel zone in the middle and to configure the source and drain contact zones in a stepwise form so that the peak intensity of a lateral electric field (Vds electric field) around the drain contact zone and the intensity of a longitudinal electric field (Vgs electric field) of the drain contact zone are both reduced, making a pinch-off point shifted toward an edge of the drain contact zone, reducing drifting of threshold voltage, and improving TFT reliability.
- Based on the description given above, those having ordinary skills of the art may easily contemplate various changes and modifications of the technical solution and technical ideas of the present invention and all these changes and modifications are considered within the protection scope of right for the present invention.
Claims (12)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510471923.XA CN105097841B (en) | 2015-08-04 | 2015-08-04 | The production method and TFT substrate of TFT substrate |
CN201510471923.X | 2015-08-04 | ||
PCT/CN2015/087912 WO2017020362A1 (en) | 2015-08-04 | 2015-08-24 | Tft substrate and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
US20170040462A1 true US20170040462A1 (en) | 2017-02-09 |
US9570618B1 US9570618B1 (en) | 2017-02-14 |
Family
ID=54577906
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/778,090 Active US9570618B1 (en) | 2015-08-04 | 2015-08-24 | TFT substrate manufacturing method and TFT substrate |
Country Status (3)
Country | Link |
---|---|
US (1) | US9570618B1 (en) |
CN (1) | CN105097841B (en) |
WO (1) | WO2017020362A1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20190019825A1 (en) * | 2017-07-11 | 2019-01-17 | Canon Kabushiki Kaisha | Semiconductor apparatus and equipment |
CN111370465A (en) * | 2018-12-06 | 2020-07-03 | 三星显示有限公司 | Thin film transistor, display device including the same, and method of manufacturing the same |
US10957713B2 (en) * | 2018-04-19 | 2021-03-23 | Wuhan China Star Optoelectronics Technology Co., Ltd. | LTPS TFT substrate and manufacturing method thereof |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105552084A (en) * | 2015-12-14 | 2016-05-04 | 昆山工研院新型平板显示技术中心有限公司 | Thin film transistor and preparation method thereof, array substrate and display device |
CN105489618B (en) | 2016-01-22 | 2019-04-26 | 深圳市华星光电技术有限公司 | The preparation method of thin-film transistor array base-plate and thin-film transistor array base-plate |
CN106094366B (en) * | 2016-08-23 | 2019-02-01 | 深圳市华星光电技术有限公司 | The production method and IPS type array substrate of IPS type array substrate |
US10559696B2 (en) | 2017-10-11 | 2020-02-11 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Hybrid CMOS device and manufacturing method thereof |
CN107768309B (en) * | 2017-10-11 | 2019-12-10 | 深圳市华星光电半导体显示技术有限公司 | hybrid CMOS device and manufacturing method thereof |
CN108565247B (en) * | 2018-04-19 | 2020-09-29 | 武汉华星光电技术有限公司 | Manufacturing method of LTPS TFT substrate and LTPS TFT substrate |
CN110620119A (en) * | 2019-08-26 | 2019-12-27 | 武汉华星光电技术有限公司 | Array substrate and preparation method thereof |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060091397A1 (en) * | 2004-11-04 | 2006-05-04 | Kengo Akimoto | Display device and method for manufacturing the same |
JP4957942B2 (en) * | 2005-08-05 | 2012-06-20 | Nltテクノロジー株式会社 | Manufacturing method of semiconductor device provided with thin film transistor |
JP2008021719A (en) * | 2006-07-11 | 2008-01-31 | Toshiba Matsushita Display Technology Co Ltd | Thin-film transistor device and manufacturing method thereof |
CN100505221C (en) * | 2007-03-28 | 2009-06-24 | 友达光电股份有限公司 | Semiconductor structure of liquid crystal display and producing method thereof |
CN103201843B (en) * | 2010-11-04 | 2016-06-29 | 夏普株式会社 | The manufacture method of semiconductor device, display device and semiconductor device and display device |
KR101877448B1 (en) * | 2011-06-30 | 2018-07-12 | 엘지디스플레이 주식회사 | Array substrate for fringe field switching mode liquid crystal display device and method of fabricating the same |
CN102299104A (en) * | 2011-09-20 | 2011-12-28 | 深圳市华星光电技术有限公司 | Manufacturing method of thin film transistor (TFT) array substrate and TFT array substrate |
CN104465509B (en) * | 2013-09-18 | 2017-08-04 | 昆山国显光电有限公司 | A kind of OLED display device array base palte and preparation method thereof |
CN103700709B (en) * | 2013-12-27 | 2016-10-05 | 京东方科技集团股份有限公司 | A kind of thin film transistor (TFT) and preparation method thereof, array base palte and display |
KR102295611B1 (en) * | 2013-12-27 | 2021-08-30 | 엘지디스플레이 주식회사 | Manufacturing method of thin film transistor array substrate |
KR102188690B1 (en) * | 2014-01-20 | 2020-12-09 | 삼성디스플레이 주식회사 | Thin film transistor, method of manufacturing the thin film transistor and flat panel display device havint the thin film transistor |
TWM483036U (en) * | 2014-03-06 | 2014-08-01 | li-xing You | Filter system of censer |
CN104465702B (en) * | 2014-11-03 | 2019-12-10 | 深圳市华星光电技术有限公司 | Manufacturing method of AMOLED (active matrix/organic light emitting diode) backboard |
CN104600028B (en) * | 2014-12-24 | 2017-09-01 | 深圳市华星光电技术有限公司 | The preparation method and its structure of low temperature polycrystalline silicon TFT substrate |
CN104617104B (en) * | 2015-01-08 | 2017-06-13 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display device |
-
2015
- 2015-08-04 CN CN201510471923.XA patent/CN105097841B/en active Active
- 2015-08-24 US US14/778,090 patent/US9570618B1/en active Active
- 2015-08-24 WO PCT/CN2015/087912 patent/WO2017020362A1/en active Application Filing
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20190019825A1 (en) * | 2017-07-11 | 2019-01-17 | Canon Kabushiki Kaisha | Semiconductor apparatus and equipment |
US10475829B2 (en) * | 2017-07-11 | 2019-11-12 | Canon Kabushiki Kaisha | Semiconductor apparatus and equipment |
US10957713B2 (en) * | 2018-04-19 | 2021-03-23 | Wuhan China Star Optoelectronics Technology Co., Ltd. | LTPS TFT substrate and manufacturing method thereof |
CN111370465A (en) * | 2018-12-06 | 2020-07-03 | 三星显示有限公司 | Thin film transistor, display device including the same, and method of manufacturing the same |
US11063155B2 (en) * | 2018-12-06 | 2021-07-13 | Samsung Display Co., Ltd. | Display device including thin film transistor with active layer portions having different thicknesses |
US20210313474A1 (en) * | 2018-12-06 | 2021-10-07 | Samsung Display Co., Ltd. | Thin film transistor, display device including the thin film transistor, and method of manufacturing the thin film transistor and the display device |
US11563126B2 (en) * | 2018-12-06 | 2023-01-24 | Samsung Display Co., Ltd. | Method of manufacturing thin film transistor and display device including polishing capping layer coplanar with active layer |
Also Published As
Publication number | Publication date |
---|---|
US9570618B1 (en) | 2017-02-14 |
CN105097841A (en) | 2015-11-25 |
CN105097841B (en) | 2018-11-23 |
WO2017020362A1 (en) | 2017-02-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9570618B1 (en) | TFT substrate manufacturing method and TFT substrate | |
KR101944644B1 (en) | Amoled back plate manufacturing method | |
US7915689B2 (en) | Thin film transistor, display device including the same and manufacturing method thereof | |
US20170047352A1 (en) | Polysilicon thin film transistor and manufacturing method thereof, array substrate | |
TW201721720A (en) | TFT array substrate, display panel, display device and method for making the TFT array substrate | |
JPWO2002095834A1 (en) | Thin film transistor, active matrix display device, and manufacturing method thereof | |
US9698177B1 (en) | Method for manufacturing N-type TFT | |
WO2017161626A1 (en) | Manufacturing method for tft substrate and manufactured tft substrate | |
KR20140148296A (en) | Thin film transistor | |
CN102405527A (en) | Thin film semiconductor device for display device, and method for manufacturing the thin film semiconductor device | |
CN109037343B (en) | Double-layer channel thin film transistor, preparation method thereof and display panel | |
US11869976B2 (en) | Thin film transistor and manufacturing method therefor, array substrate, and display device | |
US10121883B2 (en) | Manufacturing method of top gate thin-film transistor | |
KR101600475B1 (en) | Thin film transistor and active matrix organic light emitting diode assembly and method for manufacturing the same | |
US8258024B2 (en) | Display device and method of manufacturing the same | |
US7763889B2 (en) | Thin film transistor, method of fabricating the same, and a display device including the thin film transistor | |
US20130077012A1 (en) | Semiconductor device and method for manufacturing the same, and liquid crystal display device | |
US20040065924A1 (en) | Ldd structure of thin film transistor and process for producing same | |
US10629746B2 (en) | Array substrate and manufacturing method thereof | |
US9793302B1 (en) | Active device | |
US20210193694A9 (en) | Array substrate and display panel comprising barrier as doping mask overlapping gate electrode | |
US20230155031A1 (en) | Oxide thin film transistor, display panel and preparation method thereof | |
KR20200121478A (en) | Thin-Film Transistor Having A Dual Source Layer and A Fabrication Method Of The Same | |
CN114203726A (en) | Display panel and preparation method thereof | |
KR20060070861A (en) | Method for fabricating thin film transistor of liquid crystal display |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO. Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LU, MACAI;REEL/FRAME:036596/0095 Effective date: 20150914 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |