JP2008021719A - Thin-film transistor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an array substrate for controlling the threshold voltage of a p-type thin-film transistor easily. <P>SOLUTION: A metal material has a resistance value smaller than that of a metal material used for a gate electrode 27 for p-types, and is used for a gate electrode 25 for n-types and gate wiring 26. An aluminum-based material is used for the gate electrode 25 for n-types and the gate wiring 26, and molybdenum- and tungsten-based materials are used for the gate electrode 27 for p-types. An aluminum-based low-resistance material having a relatively small resistance value can be used for the gate wiring 26. The aluminum-based material needs not to be used for the gate electrode 27 for p-types. The threshold voltage of the p-type thin-film transistor 6 cannot fluctuate easily. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a thin film transistor device having an N-type thin film transistor and a P-type thin film transistor and a method for manufacturing the same.

  Conventionally, an array substrate as a thin film transistor device of this type is arranged to face a counter substrate, and a liquid crystal layer is interposed between the array substrate and the counter substrate to constitute a liquid crystal display device. The array substrate includes a plurality of pixels provided in a matrix on a glass substrate, and each of the plurality of pixels includes a glass substrate in which a P-type thin film transistor and an N-type thin film transistor are respectively used as switching elements. They are stacked on top of each other.

  The N-type thin film transistor and the P-type thin film transistor are each provided with a semiconductor layer stacked on a glass substrate and made of polysilicon (p-Si), and these semiconductor layers are provided on both sides of the channel region. And a drain region are provided.

Further, a gate electrode is stacked via a gate insulating film so as to face the channel region of the semiconductor layer of each of the N-type thin film transistor and the P-type thin film transistor. These gate electrodes are electrically connected to the gate wiring stacked on these gate electrodes. The gate electrode of each of the N-type thin film transistor and the P-type thin film transistor is formed of a material such as molybdenum-tungsten (MoW). Further, since it is preferable to use aluminum (Al) for the gate wiring of each of these N-type thin film transistors and P-type thin film transistors, it is preferable to use titanium (Ti) / aluminum-copper (AlCu) / titanium from the lower layer. A structure formed in a (Ti) three-layer structure is known (see, for example, Patent Document 1).
JP 2005-64337 A

  As described above, in the liquid crystal display device, for the purpose of reducing the resistance value of the gate electrode, these gate wirings are made of titanium (Ti) / aluminum-copper (AlCu) / titanium (Ti) 3 containing aluminum. It is formed in a layer structure.

  For this reason, the resistance value of these gate wirings can be lowered and the resistance value between these gate wirings and the gate electrode of the thin film transistor can be reduced. In the P-type thin film transistor, a titanium layer is laminated on the aluminum layer of the gate wiring. Since the titanium material in the titanium layer is a hydrogen storage alloy, hydrogen in the semiconductor layer is reduced in the titanium material, and defects such as dangling bonds are generated in the semiconductor layer. The resistance value between the channel region of the semiconductor layer of these P-type thin film transistors and the gate electrode may be too low.

  For this reason, there is a possibility that the threshold voltage between the channel region of the semiconductor layer of these P-type thin film transistors and the gate electrode may become unstable, so that the threshold voltage of these P-type thin film transistors is not easily controlled. ing.

  The present invention has been made in view of the above points, and provides a thin film transistor device and a method of manufacturing the same that can easily control the threshold voltage of a P-type thin film transistor while maintaining the low resistance of the first gate electrode of the N-type thin film transistor. The purpose is to provide.

  The present invention relates to a first active portion having a channel region and a source region and a drain region connected to the channel region and made of polycrystalline silicon, and spaced apart from the channel region of the first active portion. An N-type thin film transistor having a first gate electrode positioned; a channel region; a second active portion made of polycrystalline silicon having a source region and a drain region connected to the channel region; and And a P-type thin film transistor provided with a second gate electrode which is positioned opposite to the channel region of the active portion and has a resistance value higher than the resistance value of the first gate electrode.

  According to the present invention, the resistance value of the second gate electrode of the P-type thin film transistor is made higher than the resistance value of the first gate electrode of the N-type thin film transistor, so that the low resistance of the first gate electrode is maintained. Since the threshold voltage between the channel region of the second active portion of the P-type thin film transistor and the second gate electrode can be prevented from becoming unstable, the threshold voltage of the P-type thin film transistor can be easily controlled.

  The configuration of the first embodiment of the semiconductor device of the present invention will be described below with reference to FIGS.

  In FIG. 1, reference numeral 1 denotes a liquid crystal display device 1 as a semiconductor device. The liquid crystal display device 1 is a thin film transistor type flat display device and includes an array substrate 2 having a substantially rectangular flat plate shape. The array substrate 2 has a glass substrate 3 which is a light-transmitting substrate as a substantially transparent rectangular flat plate-like insulating substrate. An undercoat layer 4 made of silicon nitride (SiN), silicon oxide (SiO), or the like is laminated on the surface which is one main surface of the glass substrate 3.

  On the undercoat layer 4, a plurality of N-channel (N-ch) N-type thin film transistors (TFTs) 5, which are N-type switching elements for liquid crystal display, and P-type switching for liquid crystal display are provided. A plurality of P-channel (P-ch) P-type thin film transistors 6 which are elements are formed in a matrix.

  Here, each of the N-type thin film transistor 5 and the P-type thin film transistor 6 is provided as a single pixel component in a plurality of pixels 8 provided in a matrix on the glass substrate 3 of the array substrate 2. The plurality of pixels 8 are provided in each region partitioned by scanning lines and signal lines (not shown) wired in a lattice pattern on the glass substrate 3 of the array substrate 2.

  Each of the N-type thin film transistor 5 and the P-type thin film transistor 6 provided in each pixel 8 includes polysilicon layers 11 and 12 as polycrystalline semiconductor layers formed on the undercoat layer 4. . As shown in FIG. 2, these polysilicon layers 11 and 12 are formed in an elongated rectangular shape in plan view, and polysilicon (Poly-Si) formed by laser annealing of amorphous silicon as an amorphous semiconductor. It is composed of.

Here, the polysilicon layer 11 of the N-type thin film transistor 5 is a first active portion as an N-type semiconductor, and a channel region 13 is provided in the central portion of the polysilicon layer 11. Then, on both sides of the channel region 13, each of the source region 14 and drain region 15 is a N ⁺ polysilicon (N ⁺ poly-Si) layer serving as the N ⁺ region is provided opposite. Furthermore, between the source region 14 and drain region 15 and channel region 13, as a low concentration impurity regions N ^- polysilicon (N ^- poly-Si) LDD is layer (Lightly Doped Drain) regions 16 and 17 Is provided.

On the other hand, the polysilicon layer 12 of the P-type thin film transistor 6 is a second active portion as a P-type semiconductor, and a channel region 21 is provided at the center of the polysilicon layer 12. And this on both sides of the channel region 21 is provided in each face of the P ⁺ polysilicon source region 22 and drain region 23 is a (P ⁺ poly-Si) layer serving as a P ⁺ region.

  Further, on the polysilicon layers 11 and 12 of the N-type thin film transistor 5 and the P-type thin film transistor 6, respectively, a gate insulating film 24 made of insulating silicon oxide (SiO) or silicon nitride (SiN) is provided. These polysilicon layers 11 and 12 are laminated and formed to cover the undercoat layer 4 provided. That is, the gate insulating film 24 is provided so as to cover the surface of the undercoat layer 4 located between the polysilicon layers 11 and 12 in each pixel 8.

  An N-type gate electrode 25 as a first gate electrode is laminated on the gate insulating film 24 facing the channel region 13 of the polysilicon layer 11 of the N-type thin film transistor 5. The N-type gate electrode 25 is formed in an elongated strip shape in plan view having a longitudinal direction perpendicular to the longitudinal direction of the polysilicon layer 11, and one end side 25a in the longitudinal direction of the N-type gate electrode 25 is It is provided on the channel region 13 of the polysilicon layer 11 so as to oppose it. That is, the N-type gate electrode 25 is provided at a position where one end side 25a of the N-type gate electrode 25 faces the channel region 13 of the N-type thin film transistor 5 through the gate insulating film 24. It is made of an aluminum (Al) metal having a relatively small resistance value.

  Specifically, the N-type gate electrode 25 has a so-called Ti / Al / Ti layer in which an aluminum (Al) layer is laminated on a titanium (Ti) layer and a titanium (Ti) layer is laminated on the aluminum layer. A three-layer structure, a laminated structure of an aluminum layer and a titanium nitride (TiN) layer, a single layer of an aluminum layer, or the like.

  Further, the other end side 25b of the N-type gate electrode 25 is one end portion of the gate wiring 26 which is a lead-out wiring as a wiring portion for electrically connecting the N-type gate electrodes 25 of the N-type thin film transistors 5 in parallel. Are integrally and electrically connected to each other. The gate wiring 26 is formed by extending the other end side 25b of the N-type gate electrode 25 integrally and extending it in direct electrical and mechanical contact. It is formed in an elongated band shape in plan view having a longitudinal direction perpendicular to the direction. Further, the gate wiring 26 is an inter-gate electrode wiring having a width dimension equal to the width dimension of the N-type gate electrode 25, and one end side 26 a in the longitudinal direction of the gate wiring 26 is connected to the N-type gate electrode 25. Are connected integrally to the other end 25b in the longitudinal direction.

  Further, the gate wiring 26 is electrically connected to the scanning line, and is integrally provided at the same time in the same process using the same material as the N-type gate electrode 25 of each N-type thin film transistor 5. That is, the gate wiring 26 is formed to have a thickness dimension equal to the thickness dimension of the N-type gate electrode 25, and is laminated on the undercoat layer 4 which is the same layer as the N-type gate electrode 25. Is provided.

  On the other hand, a P-type gate electrode 27 as a second gate electrode is stacked on the gate insulating film 24 facing the channel region 21 of the polysilicon layer 12 of the P-type thin film transistor 6. The P-type gate electrode 27 is formed in an elongated band shape in plan view having a longitudinal direction perpendicular to the longitudinal direction of the polysilicon layer 12, and one end side 27a in the longitudinal direction of the P-type gate electrode 27 is It is provided on the channel region 21 of the polysilicon layer 12 so as to oppose it.

  That is, the P-type gate electrode 27 is provided at a position where one end side 27a of the P-type gate electrode 27 is opposed to the channel region 21 of the P-type thin film transistor 6 through the gate insulating film 24. For example, it is made of molybdenum (Mo) or tungsten (W) -based metal having a relatively higher resistance value than that of aluminum-based metal, such as molybdenum-tungsten (MoW) alloy. That is, the P-type gate electrode 27 is made of a material different from the material constituting the N-type gate electrode 25 and the gate wiring 26, and has a resistance larger than the resistance values of the N-type gate electrode 25 and the gate wiring 26. Has a value.

  Further, as shown in FIG. 2, the P-type gate electrode 27 has the other end 27b of the P-type gate electrode 27 widened in a square shape in plan view, which becomes a thick joint as a connection portion. Is formed. Specifically, the other end 27b of the P-type gate electrode 27 is formed in a square shape in plan view in which the length of one side is larger than the width of the one end 27a of the P-type gate electrode 27.

  Further, a gate wiring 26 is stacked on the other end side 27b of the P-type gate electrode 27, and the other end side 26b of the gate wiring 26 is electrically connected to the other end side 27b of the P-type gate electrode 27. Has been. The P-type gate electrode 27 is laminated on the gate insulating film 24 in the form of an elongated strip having the same width as each of the N-type gate electrode 25 and the gate wiring 26.

  On the N-type gate electrode 25, the gate wiring 26 and the P-type gate electrode 27, the gate insulating film 24 between the N-type gate electrode 25, the gate wiring 26 and the P-type gate electrode 27 is covered. As described above, for example, an interlayer insulating film 33 as an insulating sidewall layer made of silicon oxide (SiO) or silicon nitride (SiN) is laminated and provided. The interlayer insulating film 33 and the gate insulating film 24 are provided with a plurality of contact holes 34, 35, 36, and 37 which are through holes as conductive portions penetrating the interlayer insulating film 33 and the gate insulating film 24, respectively. An opening is provided.

  Here, each of the contact holes 34 and 35 is provided on both sides of the N-type gate electrode 25 of the N-type thin film transistor 5, and above the source region 14 and the drain region 15 of the polysilicon layer 11 of the N-type thin film transistor 5. Is provided. The contact hole 34 is opened to communicate with the source region 14 of the polysilicon layer 11 of the N-type thin film transistor 5, and the contact hole 35 is communicated to the drain region 15 of the polysilicon layer 11 of the N-type thin film transistor 5. Open.

  Further, each of the contact holes 36 and 37 is provided on both sides of the P-type gate electrode 27 of the P-type thin film transistor 6, and on the source region 22 and the drain region 23 of the polysilicon layer 12 of the P-type thin film transistor 6. Is provided. The contact hole 36 is opened to communicate with the source region 22 of the P-type thin film transistor 6, and the contact hole 37 is opened to communicate with the drain region 23 of the P-type thin film transistor 6.

  On the contact hole 34 communicating with the source region 14 of the N-type thin film transistor 5, a source electrode 41 which is a signal line as a conductive layer is provided by being laminated. The source electrode 41 is electrically connected to the source region 14 of the N-type thin film transistor 5 through the contact hole 34 to be conductive. In addition, a drain electrode 42 which is a signal line as a conductive layer is provided in a stacked manner in the contact hole 35 communicating with the drain region 15 of the N-type thin film transistor 5. The drain electrode 42 is electrically connected to the drain region 15 of the N-type thin film transistor 5 through the contact hole 35 to be conductive.

  Further, in the contact hole 36 communicating with the source region 22 of the P-type thin film transistor 6, a source electrode 43 which is a signal line as a conductive layer is provided by being laminated. The source electrode 43 is electrically connected to the source region 22 of the P-type thin film transistor 6 through the contact hole 36 to be conductive. In addition, a drain electrode 44 which is a signal line as a conductive layer is provided in a stacked manner in the contact hole 37 communicating with the drain region 23 of the P-type thin film transistor 6. The drain electrode 44 is electrically connected to the drain region 23 of the P-type thin film transistor 6 through the contact hole 37 to be conductive.

  On the other hand, on the source electrodes 41 and 43 and the drain electrodes 42 and 44 of the N-type thin film transistor 5 and the P-type thin film transistor 6, an interlayer insulating film 33 located between the source electrodes 41 and 43 and the drain electrodes 42 and 44, respectively. A passivation film 51 as an insulating protective film is laminated and formed so as to cover the top.

  On the passivation film 51, a pixel electrode (not shown) is laminated as a transparent electrode made of, for example, ITO (Indium Tin Oxide). The pixel electrode is electrically connected to the drain electrodes 42 and 44 of the N-type thin film transistor 5 or the P-type thin film transistor 6 through a contact hole (not shown) to be conductive. That is, the pixel electrode is controlled by either the N-type thin film transistor 5 or the P-type thin film transistor 6. Further, an alignment film 54 is laminated on the pixel electrode so as to cover the passivation film 51 between the pixel electrodes.

  On the other hand, an opposing substrate 61 having a rectangular flat plate shape is disposed facing the array substrate 2. The counter substrate 61 includes a glass substrate 62 that is a translucent substrate as a substantially transparent rectangular flat plate-like insulating substrate. A counter electrode 63 is provided on substantially the entire surface of one main surface of the glass substrate 62 facing the array substrate 2. Further, an alignment film 64 is laminated and formed on substantially the entire surface of the counter electrode 63.

  The array substrate 2 and the counter substrate 61 are overlapped with a predetermined interval in a state in which the alignment film 54 of the array substrate 2 and the alignment film 64 of the counter substrate 61 are opposed to each other. It is pasted through. Here, a gap between the alignment film 54 of the array substrate 2 and the alignment film 64 of the counter substrate 61 becomes a liquid crystal sealing region 65, and a liquid crystal element 66 is injected into the liquid crystal sealing region 65 and sealed. Thus, the liquid crystal display device 1 is configured by being provided with a liquid crystal layer 67 interposed as a light modulation layer.

  Next, a method for manufacturing the array substrate according to the first embodiment will be described.

  First, as shown in FIG. 3, an undercoat layer 4 is formed by laminating silicon nitride (SiN) or silicon oxide (SiO) on the entire surface of the glass substrate 3.

  Then, an amorphous silicon film (not shown), which is amorphous silicon as an amorphous semiconductor, is formed on the undercoat layer 4 by, for example, a CVD (Chemical Vapor Deposition) method. Thereafter, the amorphous silicon film is irradiated with an excimer laser beam and crystallized by laser annealing to form a polysilicon film 71 as a polycrystalline semiconductor layer.

  Next, the polysilicon film 71 is formed into an island shape by photolithography to form a polysilicon layer 11 constituting the N-type thin film transistor 5 and a polysilicon layer 12 constituting the P-type thin film transistor 6.

  Thereafter, a gate insulating film 24 is formed on the polysilicon layers 11 and 12 so as to cover the undercoat layer 4 located between the polysilicon layers 11 and 12 by, for example, PE (Plasma Enhanced) -CVD. Form a film.

  Next, for example, molybdenum (Mo) or tungsten (W) is formed on the entire surface of the gate insulating film 24 to form a high resistance metal layer 72 which is a high resistance conductive film. At this time, the high resistance metal layer 72 may be molybdenum-tungsten (MoW), molybdenum-tantalum (MoTa), or the like.

  Further, a first resist mask 73 is formed on the portion of the high-resistance metal layer 72 that becomes the P-type gate electrode 27, and then a first photolithography process is performed using the first resist mask 73 as a mask to form a P-type. A gate for the thin film transistor 6 is processed to form a P-type gate electrode 27.

  Thereafter, as shown in FIG. 4, after removing the first resist mask 73 from the P-type gate electrode 27, the N-type thin film transistor 5 is formed on the gate insulating film 24 as shown in FIG. A second resist mask 74 covering the polysilicon layer 11 is formed.

In this state, using the second resist mask 74 and the P-type gate electrode 27 as masks, the portion that becomes the source region 22 and the drain region 23 of the polysilicon layer 12 constituting the P-type thin film transistor 6 is formed, for example, in the P-type The source region 22 and the drain region 23 are formed by ion doping and injecting a high concentration of diborane (B ₂ H ₅ ), which is a dopant, to form a high dose.

  Next, after the second resist mask 74 is removed from the gate insulating film 24, as shown in FIG. 6, the entire surface of the gate insulating film 24 is covered with the P-type gate electrode on the gate insulating film 24. For example, a three-layer structure of Ti / Al / Ti is formed as an aluminum material to form a low-resistance metal layer 75 that is a low-resistance conductive film. At this time, the low-resistance metal layer 75 may be a laminated structure of an aluminum layer and a titanium nitride (TiN) layer, a single layer of an aluminum layer, or the like.

  Further, a third resist mask 76 is formed on the low-resistance metal layer 75 so as to cover each of a portion to be the N-type gate electrode 25 and a portion to be the gate wiring 26 constituting the N-type thin film transistor 5.

  In this state, a third photolithography process is performed using the third resist mask 76 as a mask, and the N-type thin film transistor 5 side is gate-processed to form an N-type gate electrode 25 as shown in FIG. The gate wiring 26 is formed by wiring processing.

  Next, the third resist mask 76 is removed from the N-type gate electrode 25 and the gate wiring 26.

In this state, using the N-type gate electrode 25 as a mask, at least a portion of the polysilicon layer 11 constituting the N-type thin film transistor 5 to be the source region 14, the drain region 15 and the LDD regions 16 and 17 is coated with an N-type dopant. A certain amount of phosphine (PH ₃ ) is ion-doped at a low concentration and implanted to reduce the dose.

  Next, as shown in FIG. 8, on the gate insulating film 24, on the portions of the polysilicon layer 11 of the N-type thin film transistor 5 on the channel region 13 and the LDD regions 16 and 17, and the polysilicon layer of the P-type thin film transistor 6. A fourth resist mask 77 is formed so as to cover each of the entire surface 12.

In this state, a fourth photolithography process is performed using the fourth resist mask 77 as a mask, and phosphine (PH ₃ ) is added to each of the portions of the polysilicon layer 11 of the N-type thin film transistor 5 which will become the source region 14 and the drain region 15. The source region 14 and the drain region 15 are formed by ion doping at a high concentration and implantation to form a high dose.

  At this time, regions which are inside the source region 14 and the drain region 15 of the polysilicon layer 11 of the N-type thin film transistor 5 and are low dosed by the N-type dopant become LDD regions 16 and 17, respectively. A portion of the silicon layer 11 located between the LDD regions 16 and 17 that is not dosed becomes the channel region 13.

  Thereafter, after removing the fourth resist mask 77 from the gate insulating film 24, for example, a silicon oxide is formed on the gate insulating film 24 as shown in FIG. An interlayer insulating film 33 is formed to cover each of the N-type gate electrode 25, the gate wiring 26 and the P-type gate electrode 27.

  Next, in a photolithography process, contact holes 34 and 35 communicating with the source region 14 and the drain region 15 of the N-type thin film transistor 5 and the P-type thin film transistor 6 through the interlayer insulating film 33 and the gate insulating film 24, respectively. , 36, 37 are formed.

  Thereafter, on this interlayer insulating film 33, for example, a laminated film of molybdenum (Mo) and aluminum (Al) is covered with a conductive layer serving as a signal line so as to cover each of the contact holes 34, 35, 36, and 37. After forming a film by sputtering, etching is performed by a photolithography process to form source electrodes 41 and 43 and drain electrodes 42 and 44 of N-type thin film transistor 5 and P-type thin film transistor 6, respectively.

  Further, as shown in FIG. 10, for example, a silicon nitride film is formed on the entire surface of the interlayer insulating film 33 by PE-CVD to cover the source electrodes 41 and 43 and the drain electrodes 42 and 44, respectively. A passivation film 51 is formed.

  Subsequently, in the photolithography process, the passivation film 51 is etched to form a contact hole (not shown) that conducts to one of the drain electrodes 42 and 44 of the N-type thin film transistor 5 and the P-type thin film transistor 6.

  Thereafter, after forming a transparent conductive film in the contact hole by sputtering, the transparent conductive film is patterned into the shape of the pixel 8 by a photolithography process and an etching process to form a pixel electrode.

  Further, an alignment film 54 covering these pixel electrodes is laminated on the entire surface of the passivation film 51 provided with these pixel electrodes to form the array substrate 2.

  Here, in a conventional device such as the array substrate 2 in which the N-type thin film transistor 5 and the P-type thin film transistor 6 are formed on the glass substrate 3, the gate wiring 26 wired on the glass substrate 3 of the array substrate 2 is provided. The N-type gate electrode 25 and the P-type gate electrode 27 are formed in the same layer.

  Therefore, it is inherently preferable to use an aluminum-based material having a low resistance value for the gate wiring 26 for the purpose of reducing the wiring resistance. When an aluminum (Al) -based material such as a Ti / Al / Ti laminated structure is used as a material constituting the gate wiring 26, each of the N-type gate electrode 25 and the P-type gate electrode 27 is also used. The gate wiring 26 is made of an aluminum-based material.

  At this time, when the P-type gate electrode 27 is made of an aluminum-based material, the threshold voltage (Vth) of the P-type thin film transistor 6 is experimentally reduced to the minus (−) side, for example, from −1V to −2V. There is a risk of a large shift, and the switching timing of the P-type thin film transistor 6 may be delayed.

  That is, for example, when a Ti / Al / Ti laminated structure is used as the P-type gate electrode 27, titanium (Ti) in the titanium layer laminated under the aluminum layer of the P-type gate electrode 27 is used. ) Since the material is a hydrogen (H) storage alloy, it is considered that hydrogen in the polysilicon layer 12 may be reduced.

  From this, the behavior of the hydrogen is affected at the portion of the polysilicon layer 12 where the hydrogen is reduced, and the atoms at the portion where the hydrogen is reduced lose the covalent bond partner and are not involved in the bond. Defects such as so-called dangling bonds, which are bonds occupied by electrons, may occur. As a result, the threshold voltage of the P-type thin film transistor 6 becomes unstable, so that it is not easy to control the threshold voltage of the P-type thin film transistor 6.

  Therefore, as in the first embodiment, the metal materials constituting the N-type gate electrode 25 of the N-type thin film transistor 5, the gate wiring 26, and the P-type gate electrode 27 of the P-type thin film transistor 6 are different. The configuration was As its configuration, a metal material having a resistance value smaller than that of the metal material used for the P-type gate electrode 27 is used for the N-type gate electrode 25 and the gate wiring 26.

  Specifically, at least an aluminum-based material such as a three-layer structure of Ti / Ai / Ti or a laminated structure of Al / TiN is used for the N-type gate electrode 25 and the gate wiring 26, and the P-type gate electrode For example, a material having a resistance greater than that of the aluminum-based material other than the aluminum-based material such as molybdenum (Mo), tungsten (W), or tantalum (Ta) is used.

  As a result, for the purpose of reducing the routing resistance of the gate wiring 26 and the N-type gate electrode 25, an aluminum-based low resistance material having a relatively small resistance value is used as the gate wiring 26 and the N-type gate electrode 25. However, it is not necessary to use an aluminum-based material for the P-type gate electrode 27.

  Therefore, the threshold voltage of the P-type thin film transistor 6 can be made difficult to vary while maintaining the low resistance of the N-type gate electrode 25 and maintaining the stability of the threshold voltage of the N-type thin film transistor 5, so that the threshold voltage is stabilized. The array substrate 2 having the P-type thin film transistor 6 can be manufactured.

  Further, by using the same material as the gate wiring 26 as the N-type gate electrode 25 of the N-type thin film transistor 5 whose threshold voltage is less likely to fluctuate than the P-type thin film transistor 6 experimentally, the low resistance of the gate wiring 26 itself is reduced. The N-type gate electrode 25 and the gate wiring 26 can be integrally formed at the same time in the same process using the same material.

  For this reason, the operation and the process of connecting the N-type gate electrode 25 and the gate wiring 26 in electrical and mechanical contact are unnecessary, and the N-type gate electrode 25 and the P-type gate electrode 27 are connected to each other. Connection points of the gate wiring 26 to be connected can be reduced. Therefore, the array substrate 2 having the N-type thin film transistor 5 and the P-type thin film transistor 6 with stable threshold voltages can be manufactured without significantly increasing the photolithography process necessary for manufacturing the array substrate 2.

  That is, as in the comparative example shown in FIG. 17, molybdenum (Mo) or tungsten (W) materials are used as the N-type gate electrode 25 and the P-type gate electrode 27, and the gate wiring 26 is made of aluminum (Al). In the case of using a material, in order to facilitate the alignment in the photolithography process, the connection portion between the gate wiring 26 and the N-type gate electrode 25 and the P-type gate electrode 27 is made into a thick joint portion. There is a need.

  For this reason, since it is necessary to form a large number of thick joints in each of the gate wiring 26, the N-type gate electrode 25 and the P-type gate electrode 27, the gate wiring 26, the N-type gate electrode 25 and P It is difficult to pack a circuit constituted by the mold gate electrode 27 on the glass substrate 3.

  Further, the other end 27b of the P-type gate electrode 27 was widened in a square shape in plan view having a side dimension larger than the width dimension of the one end side 27a of the P-type gate electrode 27. As a result, electrical and mechanical connection between the other end side 26b of the gate wiring 26 directly stacked on the other end side 27b of the P-type gate electrode 27 and the other end side 27b of the P-type gate electrode 27 is performed. More reliable contact. Therefore, the direct electrical and mechanical connection between the other end side 27b of the P-type gate electrode 27 and the other end side 26b of the gate wiring 26 can be ensured. The conductivity between the end side 27b and the other end side 26b of the gate wiring 26 can be made more reliable.

  Next, a method for manufacturing the array substrate according to the second embodiment of the present invention will be described.

  In the second embodiment, the N-type thin film transistor 5 is formed before the P-type thin film transistor 6, contrary to the first embodiment in which the P-type thin film transistor 6 is formed before the N-type thin film transistor 5. It is.

  First, as shown in FIG. 11, an undercoat layer 4 is formed on a glass substrate 3, and island-like polysilicon layers 11, 12 are formed on the undercoat layer 4, and these polysilicon layers 11, 12 are formed. On the portion of the polysilicon layer 11 of the N-type thin film transistor 5 and the LDD regions 16 and 17 on the gate insulating film 24 laminated thereon, and on the entire polysilicon layer 12 of the P-type thin film transistor 6 respectively. Then, a first resist mask 73 is formed.

  In this state, a first photolithography process is performed using the first resist mask 73 as a mask, and an N-type dopant is applied at a high dose to each of the portions of the polysilicon layer 11 of the N-type thin film transistor 5 which will become the source region 14 and the drain region 15. Thus, the source region 14 and the drain region 15 are formed.

  At this time, when a pixel capacitor (Cs) (not shown) having a so-called MIM (Metal-Insulator-Metal) structure is formed adjacent to the N-type thin film transistor 5 and the P-type thin film transistor 6, At the same time, the polysilicon layer of the pixel capacitance is also heavily dosed with N-type dopants.

  Next, a three-layer structure of, for example, Ti / Al / Ti is formed as an aluminum material on the entire surface of the gate insulating film 24 to form a low resistance metal layer 75 as a first conductive film.

  Thereafter, as shown in FIG. 12, a second resist mask 74 is formed on the low-resistance metal layer 75 so as to cover each of the portion that becomes the N-type gate electrode 25 and the portion that becomes the gate wiring 26.

  In this state, a second photolithography process is performed using the second resist mask 74 as a mask, and the N-type thin film transistor 5 side is processed to form an N-type gate electrode 25 as shown in FIG. The gate wiring 26 is formed by wiring processing.

  Next, the second resist mask 74 is removed from the N-type gate electrode 25 and the gate wiring 26.

  Further, as shown in FIG. 14, for example, molybdenum (Mo) or tungsten (W) is formed on the entire surface of the gate insulating film 24 to form a high resistance metal layer 72 as a second conductive film. Then, a third resist mask 76 is formed on the portion of the high resistance metal layer 72 that becomes the P-type gate electrode 27.

  In this state, a third photolithography process is performed using the third resist mask 76 as a mask, and as shown in FIG. 15, the side to be the P-type thin film transistor 6 is gate-processed to form a P-type gate electrode 27.

  Next, using the N-type gate electrode 25 as a mask, an N-type dopant is low dosed at least in the polysilicon layer 11 constituting the N-type thin film transistor 5 to become the source region 14, the drain region 15 and the LDD regions 16, 17. Thus, LDD regions 16 and 17 of the polysilicon layer 11 of the N-type thin film transistor 5 are formed.

  Thereafter, as shown in FIG. 16, a fourth resist mask 77 covering the entire polysilicon layer 11 of the N-type thin film transistor 5 is formed on the gate insulating film 24.

  In this state, using the fourth resist mask 77 and the P-type gate electrode 27 as a mask, a P-type dopant is highly dosed to the portions of the polysilicon layer 12 of the P-type thin film transistor 6 that will become the source region 22 and the drain region 23. Thus, the source region 22 and the drain region 23 are formed, respectively.

  Further, after removing the fourth resist mask 77 from the gate insulating film 24, an interlayer insulating film 33 is formed on the gate insulating film 24 as shown in FIG. Contact holes 34, 35, 36, and 37 are formed in the film 24.

  Then, the source electrodes 41 and 43 and the drain electrodes 42 and 44 of the N-type thin film transistor 5 and the P-type thin film transistor 6 are formed in the contact holes 34, 35, 36, and 37, respectively, and then the passivation is formed on the entire surface of the interlayer insulating film 33. A film 51 is formed.

  Next, after forming a contact hole in the passivation film 51 and then forming a pixel electrode in the contact hole, an alignment film 54 is laminated on the entire surface of the passivation film 51 provided with the pixel electrode to form an array substrate. 2.

  As described above, according to the second embodiment, even if the N-type thin film transistor 5 is formed before the P-type thin film transistor 6, an aluminum-based material is used for the N-type gate electrode 25 and the gate wiring 26. A material having a resistance value larger than that of an aluminum-based material can be used for the P-type gate electrode 27.

  Therefore, an aluminum-based low-resistance material having a relatively small resistance value can be used for the gate wiring 26, and an aluminum-based material can be omitted for the P-type gate electrode 27. Since the same material as that of the wiring 26 can be used, the same effect as that of the first embodiment can be obtained.

  In each of the above embodiments, the high-resistance metal layer 72 can be composed of an alloy containing molybdenum (Mo), that is, either molybdenum-tungsten (MoW) or molybdenum-tantalum (MoTa). Further, as the low resistance metal layer 75, an alloy containing aluminum (Al), that is, at least one of aluminum (Al) and aluminum-copper (AlCu), molybdenum (Mo), titanium (Ti) and titanium nitride ( It can also be constituted by a laminated film with at least one of TiN).

  Further, not the N-type gate electrode 25 on the array substrate 2 but the other end side 27b of the P-type gate electrode 27 on the array substrate 2 is integrally extended and extended to form a gate wiring 26. Even if the other end side 26b of the wiring 26 is electrically and mechanically brought into linear contact with the other end side 25b of the N-type gate electrode 25, the gate wiring 26, the N-type gate electrode 25, and the P-type gate electrode can be used. Connection points with 27 can be reduced.

  Further, R (Red), G (Green), and B (Blue) color filter layers corresponding to the three primary colors of light are applied to each pixel 8 on the array substrate 2 on the array substrate 2 or the counter substrate 61 of the liquid crystal display device 1. The liquid crystal display device 1 can be formed so as to correspond to the liquid crystal display device 1 capable of color display.

  Further, the liquid crystal display device 1 using the N-type thin film transistor 5 and the P-type thin film transistor 6 as a switching element has been described. For example, other than the liquid crystal display device 1 using the N-type thin film transistor 5 and the P-type thin film transistor 6, for example, electroluminescence (EL ) Even a flat display device such as a display device or other various semiconductor devices can be used correspondingly.

1 is an explanatory cross-sectional view illustrating a first embodiment of a thin film transistor device of the present invention. It is a top view which shows a part of thin-film transistor apparatus same as the above. It is explanatory sectional drawing which shows the state in which the electroconductive film and 1st resist mask of the thin-film transistor device same as the above were formed. It is explanatory sectional drawing which shows the state in which the 2nd gate electrode of the thin-film transistor device same as the above was formed. It is explanatory sectional drawing which shows the state which doped the 2nd active part of a thin-film transistor device same as the above. It is explanatory sectional drawing which shows the state which formed the 1st electrically conductive film and the 3rd resist mask in the thin-film transistor apparatus same as the above. It is explanatory sectional drawing which shows the state which carries out low dose of the 1st active part of a thin-film transistor device same as the above. It is explanatory sectional drawing which shows the state which carries out the high dose of the 1st active part of a thin-film transistor device same as the above. It is explanatory sectional drawing which shows the state which formed the 1st active part and 2nd active part of the thin-film transistor device same as the above. It is explanatory sectional drawing which shows the state in which the same thin-film transistor device was formed. It is explanatory sectional drawing which shows the state which carries out the high dose of the 1st active part of the thin-film transistor device of the 2nd Embodiment of this invention. It is explanatory sectional drawing which shows the state which formed the electroconductive film and 2nd resist mask of a thin-film transistor apparatus same as the above. It is explanatory sectional drawing which shows the state which formed the 1st gate electrode and wiring part of the thin-film transistor device same as the above. It is explanatory sectional drawing which shows the state in which the 2nd conductive film and 3rd resist mask of the thin-film transistor device same as the above were formed. It is explanatory sectional drawing which shows the state which carries out low dose of the 1st active part of a thin-film transistor device same as the above. It is explanatory sectional drawing which shows the state which doped the 2nd active part of a thin-film transistor device same as the above. It is a top view which shows a part of thin-film transistor apparatus of a comparative example.

Explanation of symbols

2 Array substrate as thin film transistor device 5 N type thin film transistor 6 P type thin film transistor
11 Polysilicon layer as the first active part
12 Polysilicon layer as second active part
13 channel region
14 Source area
15 Drain region
21 Channel region as second active part
22 Source area
23 Drain region
25 N-type gate electrode as first gate electrode
27 P-type gate electrode as second gate electrode
72 High resistance metal layer as second conductive film as conductive film
75 Low resistance metal layer as the first conductive film as the conductive film

Claims (6)

A first active portion having a channel region and a source region and a drain region connected to the channel region and made of polycrystalline silicon, and a first active portion that is positioned facing and spaced apart from the channel region of the first active portion An N-type thin film transistor provided with a gate electrode;
A second active portion having a channel region and a source region and a drain region connected to the channel region, and made of polycrystalline silicon; and the second active portion located opposite to the channel region of the second active portion. A thin film transistor device comprising: a P-type thin film transistor including a second gate electrode having a resistance value higher than a resistance value of one gate electrode. The thin film transistor device according to claim 1, wherein the first gate electrode and the second gate electrode are provided in electrical and physical contact. The thin film transistor device according to claim 1, wherein the first gate electrode is made of a material containing aluminum (Al). The thin film transistor device according to any one of claims 1 to 3, wherein the second gate electrode is formed of a material containing at least one of molybdenum (Mo) and tungsten (W). A first active portion having a channel region and a source region and a drain region connected to the channel region and made of polycrystalline silicon, and a first active portion that is positioned facing and spaced apart from the channel region of the first active portion An N-type thin film transistor provided with a gate electrode;
A second active portion having a channel region and a source region and a drain region connected to the channel region, and made of polycrystalline silicon; and the second active portion located opposite to the channel region of the second active portion. A method of manufacturing a thin film transistor device including a P-type thin film transistor including a second gate electrode having a resistance value higher than the resistance value of one gate electrode,
Providing the first active part and the second active part;
Forming a conductive film on at least the channel region of the second active portion to provide the second gate electrode;
A first conductive film having a resistance value lower than that of the conductive film is formed on at least the channel region of the first active portion by being in electrical and physical contact with the second gate electrode. An electrode is provided. A method of manufacturing a thin film transistor device. A first active portion having a channel region and a source region and a drain region connected to the channel region and made of polycrystalline silicon, and a first active portion that is positioned facing and spaced apart from the channel region of the first active portion An N-type thin film transistor provided with a gate electrode;
A second active portion having a channel region and a source region and a drain region connected to the channel region, and made of polycrystalline silicon; and the second active portion located opposite to the channel region of the second active portion. A method of manufacturing a thin film transistor device including a P-type thin film transistor including a second gate electrode having a resistance value higher than the resistance value of one gate electrode,
Providing the first active part and the second active part;
Forming a conductive film on at least the channel region of the first active portion to provide the first gate electrode;
A second conductive film having a higher resistance value than the conductive film is formed on at least the channel region of the second active portion in electrical and physical contact with the first gate electrode to form the second gate electrode. A method of manufacturing a thin film transistor device, comprising: providing a thin film transistor device.

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