WO2016204207A1 - 配線パターンの製造方法、トランジスタの製造方法、及び転写用部材 - Google Patents
配線パターンの製造方法、トランジスタの製造方法、及び転写用部材 Download PDFInfo
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- WO2016204207A1 WO2016204207A1 PCT/JP2016/067870 JP2016067870W WO2016204207A1 WO 2016204207 A1 WO2016204207 A1 WO 2016204207A1 JP 2016067870 W JP2016067870 W JP 2016067870W WO 2016204207 A1 WO2016204207 A1 WO 2016204207A1
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- layer
- manufacturing
- wiring pattern
- resist layer
- metal layer
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 37
- 238000012546 transfer Methods 0.000 title claims description 14
- 238000000034 method Methods 0.000 claims abstract description 82
- 229910052751 metal Inorganic materials 0.000 claims abstract description 78
- 239000002184 metal Substances 0.000 claims abstract description 78
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000000059 patterning Methods 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 12
- 229920005989 resin Polymers 0.000 claims description 71
- 239000011347 resin Substances 0.000 claims description 71
- 239000004065 semiconductor Substances 0.000 claims description 51
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 238000004544 sputter deposition Methods 0.000 claims description 12
- 239000010949 copper Substances 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 239000010409 thin film Substances 0.000 abstract description 10
- 239000010410 layer Substances 0.000 description 206
- 239000010408 film Substances 0.000 description 31
- 230000001681 protective effect Effects 0.000 description 20
- 238000010438 heat treatment Methods 0.000 description 9
- 239000000243 solution Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 229920000139 polyethylene terephthalate Polymers 0.000 description 8
- 239000005020 polyethylene terephthalate Substances 0.000 description 8
- 238000010030 laminating Methods 0.000 description 7
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 6
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 description 6
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 6
- 238000011161 development Methods 0.000 description 6
- 238000003475 lamination Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229920001187 thermosetting polymer Polymers 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- -1 polyethylene terephthalate Polymers 0.000 description 3
- 229910000029 sodium carbonate Inorganic materials 0.000 description 3
- 229920000178 Acrylic resin Polymers 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- JHIVVAPYMSGYDF-UHFFFAOYSA-N cyclohexanone Chemical compound O=C1CCCCC1 JHIVVAPYMSGYDF-UHFFFAOYSA-N 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000007429 general method Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 2
- 238000007641 inkjet printing Methods 0.000 description 2
- 238000001659 ion-beam spectroscopy Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000011112 polyethylene naphthalate Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910005191 Ga 2 O 3 Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 235000010724 Wisteria floribunda Nutrition 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000003618 dip coating Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000005038 ethylene vinyl acetate Substances 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- QOSATHPSBFQAML-UHFFFAOYSA-N hydrogen peroxide;hydrate Chemical compound O.OO QOSATHPSBFQAML-UHFFFAOYSA-N 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000003980 solgel method Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229920005992 thermoplastic resin Polymers 0.000 description 1
- 238000009941 weaving Methods 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
- H01L21/447—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428 involving the application of pressure, e.g. thermo-compression bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
- H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/4763—Deposition of non-insulating, e.g. conductive -, resistive -, layers on insulating layers; After-treatment of these layers
- H01L21/47635—After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
- H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
- H01L21/441—Deposition of conductive or insulating materials for electrodes
- H01L21/445—Deposition of conductive or insulating materials for electrodes from a liquid, e.g. electrolytic deposition
Definitions
- the present invention relates to a wiring pattern manufacturing method, a transistor manufacturing method, and a transfer member.
- the present invention claims the priority of Japanese Patent Application No. 2015-121905 filed on June 17, 2015. For designated countries where weaving by reference is allowed, the contents described in the application are as follows: Is incorporated into this application by reference.
- An oxide semiconductor film having visible light transparency and electrical conductivity is used as a transparent electrode for flat panel displays, thin film solar cells, and the like.
- a layer including a metal that becomes wiring is formed on the substrate, a resist layer is overlaid on the metal layer, and a wiring pattern is formed by a photoresist method. The method is known.
- Patent Document 1 discloses that “a method of manufacturing a thin film transistor, in which a pair of conductive layers is formed on the transfer-type protrusions in which protrusions are formed according to the arrangement pattern of the thin film transistors.
- a gate insulating film forming step for forming a gate insulating film and a transfer step for transferring the gate insulating film, the semiconductor film, and the conductive layer onto a wiring previously formed on the substrate by a printing method.
- a technique related to the manufacturing method is disclosed.
- a wiring pattern manufacturing method includes a first member having a resist layer and a metal layer formed on the resist layer.
- the laminate forming step according to an aspect of the present invention may be characterized in that the first member and the second member are brought into contact with each other through a resin layer.
- the resin layer according to an aspect of the present invention may be provided on the second member.
- the resin layer according to an aspect of the present invention may be a photocurable resin.
- the wiring pattern manufacturing method according to an aspect of the present invention may further include a resin layer curing step of curing the resin layer after the laminate forming step.
- the laminate forming step according to an aspect of the present invention may be characterized in that the laminate is obtained by pressure-bonding the first member and the second member.
- the first member according to an aspect of the present invention may include a semiconductor layer formed on the metal layer.
- the semiconductor layer according to an aspect of the present invention may be formed by a sputtering method.
- the resist layer may be patterned by selectively exposing the resist layer by light irradiation and removing either the exposed part or the unexposed part. May be a feature.
- the resist layer according to an aspect of the present invention may be a dry film resist.
- the metal layer according to an aspect of the present invention may be formed of copper.
- a method for manufacturing a transistor according to an aspect of the present invention is characterized by using any one of the above-described wiring pattern manufacturing methods.
- a method for manufacturing a transistor according to an aspect of the present invention includes a first member having a resist layer, a metal layer formed on the resist layer, and a semiconductor layer formed on the metal layer; A laminate forming step of obtaining a laminate by bringing a gate electrode and a second member formed with a gate insulating layer into contact with each other, a resist layer patterning step of patterning the resist layer, and the metal layer selectively And an electrode forming step of obtaining a source electrode and a drain electrode by removing the electrode.
- the transfer member according to an aspect of the present invention includes a resist layer and a metal layer formed on the resist layer.
- the transfer member according to an aspect of the present invention may further include a semiconductor layer selectively formed on the metal layer.
- the semiconductor layer according to an aspect of the present invention may be formed by a sputtering method.
- the resist layer according to an aspect of the present invention may be a dry film resist.
- FIG. 1 is a process diagram for explaining an example of an outline of a wiring pattern manufacturing method according to the present embodiment.
- a first stacked body including a resist layer and a second stacked body including a substrate are formed, and the third stacked body is formed using the first stacked body and the second stacked body.
- the first stacked body is formed by the following steps S11 to S13, and the second stacked body is formed by steps S21 to S22.
- the third stacked body is formed in step S31. The order of forming the first stacked body and the second stacked body does not matter.
- a resist layer is formed.
- the resist layer is formed, for example, by applying a resist material on a protective sheet, but a dry film resist (hereinafter referred to as “DFR”) in which a resist layer is formed in advance on the protective sheet may be used.
- a protective sheet materials, such as a polyethylene terephthalate (PET), a polyimide, a polyethylene naphthalate (PEN), can be used.
- step S12 a metal layer is formed on the resist layer.
- the details of the lamination method will be described later.
- step S13 a semiconductor layer is formed on the metal layer. Through the above steps, the first stacked body is formed.
- step S21 a metal layer is formed on the substrate.
- step S22 an adhesive and insulating layer is formed on the metal layer formed in step S21.
- the adhesion / insulation layer is formed of an insulating resin.
- a resin layer a resin that is cured in response to environmental changes, such as a photocurable resin or a thermosetting resin, is used. By curing the resin layer, the adhesion with a component in contact with the resin layer is improved. Through the above steps, the second stacked body is formed.
- step S31 the first laminated body and the second laminated body are overlaid, and a laminating process (pressurizing process) is performed using a laminator.
- a laminating process pressurizing process
- the third laminated body in which the first laminated body and the second laminated body are overlapped is pressure-bonded.
- this step the first stacked body and the second stacked body are aligned, and the adhesion is improved.
- this step is not limited to the laminating process as long as the first laminated body and the second laminated body are laminated and bonded in a predetermined stacking order.
- this step may be omitted when the bonding surface between the first laminated body and the second laminated body has sufficient adhesion.
- step S32 the resin layer is cured.
- the environment is changed according to the material used for the resin layer, and the resin layer is cured.
- the resin layer curing step is executed.
- step S33 a second laminating process is performed.
- This process is a process for improving the adhesion of each layer, but may be omitted in this embodiment.
- step S34 the resist layer is exposed. At the time of exposure, a predetermined portion of the resist is exposed by using a photomask showing a wiring shape.
- step S35 development is performed.
- the third laminated body obtained in step S34 is immersed in a developing solution, and the resist layer other than necessary portions is removed.
- a resist layer patterning step is executed by the processes in steps S34 and S35.
- step S36 etching is performed.
- the metal layer in the portion where the resist is removed is removed by immersing the third laminate in a predetermined solution. Thereby, a predetermined wiring pattern is obtained in the third laminate. An etching process is performed by this process.
- step S37 the resist layer is peeled off. By removing the resist layer, the wiring pattern formed in step S36 is exposed. Thereafter, the processing according to the present embodiment is terminated.
- FIG. 2 is a diagram illustrating an example of a process for forming the first laminate.
- 2A corresponds to step S11 described above
- FIG. 2B corresponds to step S12
- FIG. 2C corresponds to step S13.
- a resist layer 12 is formed on the protective sheet 11 in the resist layer forming step shown in FIG.
- the resist layer 12 is formed by applying a photosensitive resist to the protective sheet 11.
- the resist material to be used is not particularly limited, and a conventionally known material can be used.
- the resist layer 12 is formed by a commonly used coating method such as spin coating, dip coating, or spraying. Moreover, the formation method of the resist layer 12 is not limited to application
- a metal layer 13 is formed on the resist layer 12.
- a metal such as Cu, Al, Ti, Cr, Au, or Fe, or a multilayer film thereof can be used.
- a deposition method such as a vapor deposition method, a plating method, a printing method, a laminate of Cu foil or Al foil, a sputtering method, or an ion beam sputtering method is used. Note that the metal layer 13 is used later as a source electrode and a drain electrode of a transistor.
- the semiconductor layer 14 is selectively formed with respect to the metal layer 13.
- a semiconductor material such as a-IGZO, ZnO, Ga 2 O 3 , In 2 O 3 can be used.
- the method for forming the semiconductor layer 14 is not limited, a low-temperature and high-performance semiconductor film can be obtained by film formation by sputtering. Note that, when the sputtering method is used, plasma is generated, but the generated plasma and light generated by the plasma are blocked by the metal layer 13 and do not reach the resist layer 12, so that the resist layer 12 is damaged by the plasma. Can be prevented.
- the patterning method of the semiconductor layer 14 is not limited, for example, a normal lithography process using a photoresist can be used. By removing the unnecessary portion of the semiconductor layer 14, the semiconductor layer 14 selectively formed with respect to the metal layer 13 can be obtained. Moreover, you may obtain the semiconductor layer 14 selective with respect to the metal layer 13 using inkjet printing.
- FIG. 3 is a diagram illustrating an example of a formation process of the second stacked body.
- 3A, FIG. 3B, and FIG. 3C correspond to step S21 described above, and FIG. 3D corresponds to step S22.
- FIG. 3A shows the substrate 21.
- the substrate 21 includes a resin substrate such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyimide, or a semiconductor substrate such as silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), or silicon dioxide.
- a resin substrate such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyimide, or a semiconductor substrate such as silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), or silicon dioxide.
- An oxide substrate such as (SiO 2 ), sapphire, or zinc oxide (ZnO) can be used.
- FIG. 3B is a diagram showing a state in which the metal layer 22 is formed on the substrate 21.
- a metal such as Al, Cu, Ti, Cr, Au, Fe, or a multilayer film thereof can be used.
- the same method as the formation of the metal layer 13 can be used.
- FIG. 3C is a diagram showing a state in which the metal layer 22 is selectively removed. Since the metal layer 22 later becomes the gate electrode of the transistor, it is selectively removed according to the design. As a selective removal method, the unnecessary portion of the metal layer 22 may be removed by, for example, a normal lithography process using a photoresist. Alternatively, the selective metal layer 22 may be obtained by inkjet printing or the like.
- the resin layer 23 is formed so as to overlap the substrate 21 and the metal layer 22 selectively formed with respect to the substrate 21.
- Photocurable resins such as epoxy resins and acrylic resins, thermosetting resins such as epoxy resins and acrylic resins, or thermoplastic resins such as ethylene vinyl acetate (EVA) can be used.
- EVA ethylene vinyl acetate
- a two-component mixed resin or a moisture curable resin may be used.
- a method for forming the resin layer 23 a general film forming method is used. Note that the resin layer 23 is used later as a gate insulating film of a transistor.
- FIG. 4 is a diagram illustrating an example of a third laminate forming process and a resin layer curing process.
- 4A corresponds to step S31 described above
- FIG. 4B corresponds to step S32
- FIG. 4C corresponds to step S33.
- the laminating step 1 shown in FIG. 4 (a) the first laminated body and the second laminated body are overlaid and pressure-bonded by a laminator.
- the semiconductor layer 14 and the resin layer 23 are overlaid so as to contact each other.
- This step can be performed under conditions where the resin layer 23 is not cured.
- This step is performed at room temperature, for example.
- heating may be performed during the laminating process. The heating is desirably performed at a temperature at which the photocurable resin does not undergo modification such as aggregation. For example, when SU-8 is used for the resin layer 23, it is desirable that the temperature be 95 ° C. or lower.
- the resin layer 23 is cured.
- a thermosetting resin as the resin layer 23 and heating at the time of laminating, the laminate 1 is obtained. You may perform a process and a resin layer hardening process in parallel.
- the resin layer 23 is cured in the resin layer curing step shown in FIG.
- the resin layer 23 is a photocurable resin
- the resin layer 23 is cured by irradiating light from a light source ⁇ installed on the substrate 21 side.
- the resin layer 23 is a thermosetting resin
- the resin layer 23 is cured by heating the third laminate.
- the third laminate obtained by curing the resin layer 23 is pressure-bonded while being heated.
- a laminator is used for heating and pressure bonding. This step improves the adhesion of each layer. Heating is performed at a temperature lower than the softening point of the substrate 21.
- FIG. 5 is a diagram showing an example of a resist layer patterning step and an etching step.
- 5A corresponds to step S34 shown in FIG. 1
- FIG. 5B corresponds to step S35
- FIG. 5C corresponds to step S36
- step S5 (d) corresponds to step S37.
- the resist layer 12 is exposed.
- the resist layer 12 is irradiated with UV light from the light source ⁇ using a photomask (not shown), and the resist layer 12 is selectively exposed to perform patterning.
- the resist layer 12 may be a negative type in which a portion exposed during development remains, or a positive type in which a portion not exposed during development remains.
- the protective sheet 11 is removed and the resist layer 12 is selectively removed.
- the protective sheet 11 may be removed by a method of peeling the protective sheet 11 by physically applying a force, or by using a predetermined solution in which the protective sheet 11 is dissolved.
- a resist layer 12 having a source electrode and drain electrode pattern is formed on the metal layer 13.
- the removal of the protective sheet 11 may be performed before the resist layer 12 is exposed in the exposure step. In that case, after removing the protective sheet 11 by the same method as described above, the resist layer 12 is selectively exposed. Thereafter, a developing process for selectively removing the resist layer 12 is performed.
- the metal layer 13 is selectively removed. Etching is performed by a general method using a predetermined solution or gas. By this step, a selective metal film corresponding to the patterning shape of the resist layer 12 can be obtained.
- the resist layer 12 is stripped in the resist stripping process shown in FIG.
- the resist layer 12 is peeled by a general method such as using a predetermined solution.
- the first stacked body including the resist layer 12, the metal layer 13, and the semiconductor layer 14 and the second stacked body including the substrate 21, the metal layer 22, and the resin layer 23 are used.
- a third laminated body is formed, and the third laminated body is patterned to obtain a desired wiring pattern.
- a laminated body is obtained by sequentially stacking components on a substrate.
- a vacuum apparatus may be required for film formation. If the process used is performed between other processes, there is a problem that process management becomes complicated.
- the thin film which gave the wiring pattern more efficiently can be obtained by forming the 1st laminated body and the 2nd laminated body separately.
- a film forming method such as a sol-gel method, an electroless deposition method, or an electrolytic deposition method is often used. According to these film formation methods, a semiconductor film having high crystallinity can be obtained by growing the semiconductor film at a high temperature by heating the stacked body. However, it is difficult to obtain an oxide semiconductor film with high crystallinity at a low temperature (about 100 ° C. to 200 ° C.) at which a resin substrate such as PET can withstand.
- the formation process of the semiconductor layer 14 does not affect the substrate 21. Therefore, the semiconductor layer 14 with better performance can be obtained without affecting the substrate 21. Therefore, according to the present embodiment, a thin film with a wiring pattern can be obtained more efficiently.
- a transistor in the third stacked body obtained by this embodiment, can be obtained by using the metal layer 13 as a source electrode and a drain electrode, the resin layer 23 as a gate insulating layer, and the metal layer 22 as a gate electrode. it can.
- DFR (manufactured by Hitachi Chemical: RD-1225) is used as the protective sheet 11 and the resist layer 12 in the first laminate.
- a protective resin 11 is coated with a photosensitive resin of 25 ⁇ m.
- Cu particles were attached to the DFR using ion beam sputtering to form a metal layer 13 that is a metal film. Thereby, the metal layer 13 having high adhesion and flatness was obtained.
- a-IGZO was deposited on the metal layer 13 by sputtering to form a semiconductor layer 14.
- the metal film has the role of a light shielding film, the exposure of the DFR was at a level that can be ignored.
- the semiconductor layer 14 having high mobility at a low temperature could be obtained.
- a PET substrate 21 was prepared.
- a Cu film was formed on the substrate 21 by vapor deposition. Thereafter, the metal layer 22 was patterned using a photoresist and etched to obtain a metal layer 22 having a gate electrode wiring structure.
- a solution prepared by dissolving 20 wt% of SU-8 (manufactured by Nippon Kayaku: SU-8 3005) in cyclohexanone was prepared.
- This SU-8 is an epoxy negative photosensitive resin that is cured by i-line. This was formed at 1000 rpm by spin coating on the substrate 21 on which the metal layer 22 was formed, and dried at 90 ° C. for 10 minutes.
- the first and second laminates are stacked so that the semiconductor layer 14 and the resin layer 23 are in contact with each other to form a third laminate, and a laminator (manufactured by Fuji Plastics: LPD3224). ) was used without heating.
- the third laminate was irradiated with i rays under an irradiation condition of 200 mJ / cm 2 to expose SU-8 used for the resin layer 23. It should be noted that i-rays were irradiated from the substrate 21 side so that the metal layer 13 did not interfere with the exposure when the resin layer 23 was exposed.
- the third laminate was inserted into the same laminator as described above, and was subjected to pressure bonding while heating at 120 ° C.
- the third laminated body after the press bonding was heated under a condition of 105 ° C. for 1 hour using an oven.
- a mask in the shape of a source electrode and a drain electrode was prepared, the mask was placed on the protective sheet 11, and the third semiconductor was irradiated with i rays from the protective sheet 11 side.
- the protective sheet 11 was peeled off.
- the third laminate was immersed in an aqueous solution of sodium carbonate in which 1 wt% sodium carbonate was dissolved in water, and the resist layer 12 in a portion not exposed to light was dissolved.
- etching process acetic acid, hydrogen peroxide solution, and water are prepared, and the metal layer 13 is etched using an etching solution in which acetic acid: hydrogen peroxide solution: water is mixed at a ratio of 1: 1: 20. went.
- etching solution in which acetic acid: hydrogen peroxide solution: water is mixed at a ratio of 1: 1: 20. went.
- the exposed resist layer 12 was stripped.
- a sodium hydroxide solution in which 1 wt% sodium hydroxide was dissolved in water was used.
- FIG. 6 is a diagram showing the semiconductor characteristics of the third laminate obtained by the example. As shown in this figure, it was found that the third stacked body has semiconductor characteristics (characteristics in which a drain current flows in accordance with the gate bias voltage).
- the metal layer 22 was formed using PET for the substrate 21 and Cu for the metal layer 22. Thereafter, in the bonding and insulating layer forming step, an aluminum oxide thin film having a thickness of 200 nm was prepared as an insulator used for the resin layer 23 instead of the resin, and was laminated on the metal layer 22 to form a second laminate. Thereafter, the semiconductor layer 14 included in the first laminate and the aluminum oxide thin film were brought into contact with each other to form a third laminate. However, since aluminum oxide is an inorganic material, the above-described lamination 1 step and the curing step are performed. There wasn't.
- the third laminate was heated to 120 ° C., which is the limit temperature of PET. Then, when the exposure process, the image development process, the etching process, and the resist peeling process were performed, the semiconductor layer 14 and the aluminum oxide thin film did not adhere
- Example 2 As in Example 1, DFR was used as the protective sheet 11 and the resist layer 12. Next, as a metal layer forming step in the first laminate, a Cu metal layer 13 was formed by sputtering the DFR. At that time, sputtering was performed with a sufficient distance between the target Cu and DFR so that plasma damage did not affect the resist layer 12.
- Example 2 a semiconductor layer forming step was performed in the same manner as in Example 1 to form a first stacked body. Further, a second laminated body is formed in the same manner as in Example 1, and a third laminated body is formed in the same manner as in Example 1 using the first laminated body and the second laminated body. A curing step, two lamination steps, and an exposure step were performed.
- the protective sheet 11 was peeled off in the same manner as in Example 1, and the third laminate was immersed in an aqueous sodium carbonate solution, but the resist layer 12 did not dissolve and could not be patterned. . It is considered that plasma by the sputtering method sensitized the resist layer 12 and the resist layer 12 was cured. According to this comparative example, it was found that it is not suitable to use a method in which the resist layer 12 is exposed to form the metal layer 13.
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Abstract
Description
エポキシ系樹脂、アクリル系樹脂等の光硬化性樹脂、エポキシ系樹脂、アクリル系樹脂等の熱硬化性樹脂、又はエチレン酢酸ビニル(EVA)等の熱可塑性樹脂を用いることができる。これらの樹脂の他に、2液混合型や水分硬化型の樹脂を用いてもよい。樹脂層23の形成方法には一般的な成膜方法を用いる。なお、樹脂層23は後にトランジスタのゲート絶縁膜として用いられる。
本実施例では、第1の積層体における保護シート11及びレジスト層12として、DFR(日立化成製:RD-1225)を用いる。本DFRは、保護シート11上に25μmの感光性樹脂が被覆されている。次に、第1の積層体における金属層形成工程として、DFRに対してイオンビームスパッタを用いてCu粒子を付着させ、金属膜である金属層13を成膜した。これにより、高い密着性と平坦性とを有する金属層13が得られた。
第2の積層体の金属層形成工程において、基板21にPETを用い、金属層22にCuを使用して金属層22を形成した。その後、接着兼絶縁層形成工程において、樹脂層23に用いる絶縁体として樹脂に代わって200nmの酸化アルミニウム薄膜を準備し、金属層22に対して積層して第2の積層体を形成した。その後、第1の積層体が有する半導体層14と酸化アルミニウム薄膜とを接触させて第3の積層体を形成したが、酸化アルミニウムは無機材料であるため、上述のラミネート1工程と硬化工程は行わなかった。
実施例1と同様に、保護シート11及びレジスト層12としてDFRを用いた。次に、第1の積層体における金属層形成工程として、DFRに対してスパッタ法を用いてCuの金属層13を成膜した。その際、プラズマによるダメージがレジスト層12に影響を与えないよう、ターゲットであるCuとDFRとの距離を充分に離してスパッタを行った。
Claims (17)
- レジスト層と前記レジスト層上に形成された金属層とを有する第1の部材と、基板を含む第2の部材とを接触させて積層体を形成する積層体形成工程と、
前記レジスト層をパターニングするレジスト層パターニング工程と、
前記金属層を選択的に除去するエッチング工程と、
を備えることを特徴とする配線パターンの製造方法。 - 請求項1に記載の配線パターンの製造方法であって、
前記積層体形成工程は、樹脂層を介して前記第1の部材と前記第2の部材とを接触させることを特徴とする配線パターンの製造方法。 - 請求項2に記載の配線パターンの製造方法であって、
前記樹脂層は前記第2の部材に設けられていることを特徴とする配線パターンの製造方法。 - 請求項2又は3に記載の配線パターンの製造方法であって、
前記樹脂層は光硬化性樹脂であることを特徴とする配線パターンの製造方法。 - 請求項2から4のいずれか一項に記載の配線パターンの製造方法であって、
前記積層体形成工程の後、前記樹脂層を硬化させる樹脂層硬化工程を備えることを特徴とする配線パターンの製造方法。 - 請求項1から5のいずれか一項に記載の配線パターンの製造方法であって、
前記積層体形成工程は、前記第1の部材と前記第2の部材とを圧着することにより前記積層体を得ることを特徴とする配線パターンの製造方法。 - 請求項1から6のいずれか一項に記載の配線パターンの製造方法であって、
前記第1の部材は、前記金属層上に形成された半導体層を有することを特徴とする配線パターンの製造方法。 - 請求項7に記載の配線パターンの製造方法であって、
前記半導体層は、スパッタリング法により形成されていることを特徴とする配線パターンの製造方法。 - 請求項1から8のいずれか一項に記載の配線パターンの製造方法であって、
前記レジスト層パターニング工程は、光照射により前記レジスト層を選択的に露光し、露光された部分又は露光されていない部分のいずれか一方を除去することによりパターニングすることを特徴とする配線パターンの製造方法。 - 請求項1から9のいずれか一項に記載の配線パターンの製造方法であって、
前記レジスト層は、ドライフィルムレジストであることを特徴とする配線パターンの製造方法。 - 請求項1から10のいずれか一項に記載の配線パターンの製造方法であって、
前記金属層は銅で形成されていることを特徴とする配線パターンの製造方法。 - 請求項1から11のいずれか一項に記載の配線パターンの製造方法を用いることを特徴とするトランジスタの製造方法。
- レジスト層と前記レジスト層上に形成された金属層と前記金属層上に形成された半導体層とを有する第1の部材と、基板上にゲート電極とゲート絶縁層とが形成された第2の部材と、を接触させて積層体を得る積層体形成工程と、
前記レジスト層をパターニングするレジスト層パターニング工程と、
前記金属層を選択的に除去してソース電極とドレイン電極を得る電極形成工程と、
を備えることを特徴とするトランジスタの製造方法。 - レジスト層と、
前記レジスト層上に形成された金属層と、
を有することを特徴とする転写用部材。 - 請求項14に記載の転写用部材であって、
前記金属層上に、選択的に形成された半導体層を更に有することを特徴とする転写用部材。 - 請求項15に記載の転写用部材であって、
前記半導体層は、スパッタリング法により形成されていることを特徴とする転写用部材。 - 請求項14から請求項16のいずれか一項に記載の転写用部材であって、
前記レジスト層は、ドライフィルムレジストであることを特徴とする転写用部材。
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0547701A (ja) * | 1991-08-13 | 1993-02-26 | Dainippon Printing Co Ltd | 微細パターンの形成方法 |
JPH0682825A (ja) * | 1992-09-02 | 1994-03-25 | Dainippon Printing Co Ltd | 微細パターンの転写方法 |
JP2006073794A (ja) * | 2004-09-02 | 2006-03-16 | Victor Co Of Japan Ltd | 電界効果トランジスタ及びその製造方法 |
JP2007115805A (ja) * | 2005-10-19 | 2007-05-10 | Sony Corp | 半導体装置の製造方法 |
JP2009130327A (ja) * | 2007-11-28 | 2009-06-11 | Seiko Epson Corp | 半導体装置の製造方法、電子機器の製造方法、半導体装置および電子機器 |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5146904B2 (ja) * | 1971-09-30 | 1976-12-11 | ||
JPS5752711Y2 (ja) | 1977-09-05 | 1982-11-16 | ||
JPS6038891B2 (ja) | 1977-09-17 | 1985-09-03 | シチズン時計株式会社 | 超小型水晶振動子の製造方法 |
US4831429A (en) * | 1985-06-27 | 1989-05-16 | Sanyo Electric Co., Ltd. | Transparent photo detector device |
JP2002151517A (ja) * | 2000-11-08 | 2002-05-24 | Tokyo Electron Ltd | 半導体デバイスの製造方法及び半導体デバイス |
US6707115B2 (en) * | 2001-04-16 | 2004-03-16 | Airip Corporation | Transistor with minimal hot electron injection |
CN101024315A (zh) * | 2001-07-06 | 2007-08-29 | 钟渊化学工业株式会社 | 层压体及其制造方法 |
US7036209B1 (en) * | 2002-07-01 | 2006-05-02 | Seagate Technology Llc | Method of simultaneously forming magnetic transition patterns of a dual side recording medium |
JP2004259374A (ja) * | 2003-02-26 | 2004-09-16 | Tdk Corp | 情報記録ディスクのメタルマスタの製造方法及びメタルマスタ |
TW594339B (en) * | 2003-03-12 | 2004-06-21 | Ind Tech Res Inst | Liquid crystal display manufacture method |
JP2007030212A (ja) * | 2005-07-22 | 2007-02-08 | Ricoh Co Ltd | プラスチック成形用スタンパの製造方法 |
JP2007073696A (ja) * | 2005-09-06 | 2007-03-22 | Meisho Kiko Kk | パターン形成方法、パターン形成装置およびパターン形成ずみフィルム |
KR100636597B1 (ko) * | 2005-12-07 | 2006-10-23 | 한국전자통신연구원 | 티형 게이트의 제조 방법 |
KR20070071180A (ko) * | 2005-12-29 | 2007-07-04 | 엘지.필립스 엘시디 주식회사 | 유기박막트랜지스터 및 그 제조방법 |
US7969005B2 (en) * | 2007-04-27 | 2011-06-28 | Sanyo Electric Co., Ltd. | Packaging board, rewiring, roughened conductor for semiconductor module of a portable device, and manufacturing method therefor |
JP2009132142A (ja) * | 2007-10-31 | 2009-06-18 | Jsr Corp | 金属パターン形成用転写フィルムおよび金属パターン形成方法 |
CN101459087B (zh) * | 2007-12-13 | 2011-03-23 | 中芯国际集成电路制造(上海)有限公司 | 再分布金属线及再分布凸点的制作方法 |
WO2011058611A1 (ja) | 2009-11-13 | 2011-05-19 | 株式会社島津製作所 | 薄膜トランジスタの製造方法 |
JP5751055B2 (ja) * | 2010-11-30 | 2015-07-22 | Jnc株式会社 | 光ナノインプリント用硬化性組成物および硬化性組成物から得られた硬化膜 |
KR101691157B1 (ko) * | 2010-12-15 | 2017-01-02 | 삼성전자주식회사 | 나노임프린트용 스탬프 제조방법 |
KR101761943B1 (ko) * | 2012-09-20 | 2017-07-26 | 삼성전기주식회사 | 인쇄회로기판의 제조에 있어서의 시드층의 제거방법 및 그를 이용하여 제조된 인쇄회로기판 |
CN104299913B (zh) * | 2014-07-29 | 2017-09-05 | 深圳市华星光电技术有限公司 | 薄膜晶体管的制造方法 |
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0547701A (ja) * | 1991-08-13 | 1993-02-26 | Dainippon Printing Co Ltd | 微細パターンの形成方法 |
JPH0682825A (ja) * | 1992-09-02 | 1994-03-25 | Dainippon Printing Co Ltd | 微細パターンの転写方法 |
JP2006073794A (ja) * | 2004-09-02 | 2006-03-16 | Victor Co Of Japan Ltd | 電界効果トランジスタ及びその製造方法 |
JP2007115805A (ja) * | 2005-10-19 | 2007-05-10 | Sony Corp | 半導体装置の製造方法 |
JP2009130327A (ja) * | 2007-11-28 | 2009-06-11 | Seiko Epson Corp | 半導体装置の製造方法、電子機器の製造方法、半導体装置および電子機器 |
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JP6856020B2 (ja) | 2021-04-07 |
US20180108539A1 (en) | 2018-04-19 |
KR20180018512A (ko) | 2018-02-21 |
JPWO2016204207A1 (ja) | 2018-04-05 |
TWI628699B (zh) | 2018-07-01 |
TW201712733A (zh) | 2017-04-01 |
US10438814B2 (en) | 2019-10-08 |
CN107615452B (zh) | 2021-06-22 |
KR102665506B1 (ko) | 2024-05-10 |
CN107615452A (zh) | 2018-01-19 |
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