WO2016161679A1 - 一种goa电路及液晶显示器 - Google Patents

一种goa电路及液晶显示器 Download PDF

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Publication number
WO2016161679A1
WO2016161679A1 PCT/CN2015/077999 CN2015077999W WO2016161679A1 WO 2016161679 A1 WO2016161679 A1 WO 2016161679A1 CN 2015077999 W CN2015077999 W CN 2015077999W WO 2016161679 A1 WO2016161679 A1 WO 2016161679A1
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Prior art keywords
transistor
gate
source
circuit
pull
Prior art date
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Ceased
Application number
PCT/CN2015/077999
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English (en)
French (fr)
Inventor
肖军城
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Wuhan China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd, Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to GB1708785.9A priority Critical patent/GB2548274B/en
Priority to JP2017551664A priority patent/JP6518785B2/ja
Priority to US14/761,102 priority patent/US9558704B2/en
Priority to RU2017134463A priority patent/RU2669520C1/ru
Priority to DE112015005415.4T priority patent/DE112015005415T5/de
Priority to KR1020177023828A priority patent/KR102019577B1/ko
Publication of WO2016161679A1 publication Critical patent/WO2016161679A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to a GOA circuit and a liquid crystal display.
  • Gate Driver On Array is a technology that uses the existing thin film transistor liquid crystal display Array process to make the Gate scan drive signal circuit on the Array substrate to realize the drive mode of Gate progressive scan.
  • the existing GOA circuit is mainly composed of a pull-up part and a pull-up control circuit (Pull-up control). Part), transfer part (Key Pull-down Part), pull-down maintenance circuit (Pull-down Holding) Part), and the capacitor responsible for potential lift (Boost Part) composition.
  • the pull-up circuit is mainly responsible for outputting the input clock signal (Clock) to the Gate terminal as the driving signal of the display device;
  • the pull-up control circuit is responsible for controlling the opening of the pull-up circuit, generally the signal function transmitted by the superior GOA circuit;
  • the circuit is responsible for lowering the Gate to a low level at the first time after the Gate output is completed, that is, turning off the Gate signal;
  • the pull-down holding circuit is responsible for the Gate output signal and the Gate signal of the pull-up circuit (generally called Q point). Keep in the off state (ie set negative potential), usually there are two pull-down sustain circuits alternately; capacitance (Boost Part) is responsible for the secondary rise of the Q point potential, thus ensuring the normal output of the G(N) of the pull-up circuit.
  • Boost Part capacitance
  • such a design includes a pull-and-hold circuit for each stage, and is alternately operated by two parts, which consumes a large amount of power and is not environmentally friendly.
  • the technical problem to be solved by the present invention is to provide a GOA circuit and a liquid crystal display, which can reduce the power consumption of the GOA circuit in the liquid crystal display.
  • a technical solution adopted by the present invention is to provide a GOA circuit
  • the GOA circuit includes a plurality of GOA units, and each GOA unit sequentially pairs the Nth horizontal scanning line G(N) and the display area of the display area.
  • the N+1 level horizontal scanning line G(N+1) is charged, and the GOA unit includes an N-stage pull-up control circuit, an N+1-stage pull-up control circuit, an N-stage pull-up circuit, an N+1-stage pull-up circuit, and an N-stage.
  • the pull-down sustain circuit maintains the potential of the Nth gate signal point Q(N) and the Nth horizontal scanning line G(N) to a low potential after the Nth horizontal scanning line G(N) is charged, The N+1th horizontal scanning line G(N+1) is maintained after charging
  • the N-stage pull-up circuit and the pull-down sustain circuit are respectively connected to the Nth-level gate signal point Q(N) and the N-th horizontal scan line G(N)
  • the N-stage pull-up control circuit and the N-stage pull-down circuit are connected to the Nth-level gate signal point Q(N);
  • the N+1-stage pull-up circuit and the pull-down sustain circuit are respectively connected to the N+1th-level gate signal point Q ( N+1) is connected to the N+1th horizontal scanning line G(N+1), the N+1 stage pull-up control circuit, the N+1 stage pull-down circuit and the N+1th level gate signal point Q (N+ 1) connection;
  • the pull-down sustain circuit maintains the potential of the Nth gate signal point Q(N
  • the drain is connected to the N+1th gate signal point Q(N+1), the source is connected to the first DC low voltage VSS1, and the tenth transistor T10 is connected to the gate.
  • Two common points P(N), the drain is connected to the N+1th horizontal scanning line G(N+1), the source is connected to the first DC low voltage VSS1, and the eleventh transistor T11 is connected to the gate and the drain a second clock signal LC2; a twelfth transistor T12 having a gate connected to the source of the eleventh transistor T11, a drain connected to the second clock signal LC2, and a source connected to the second common point P(N); the thirteenth transistor T13, the gate is connected to the first clock signal LC1, the drain is connected to the second clock signal LC2, the source is connected to the second common point P(N), and the fourteenth transistor T14 is connected to the second common point of the gate and the drain.
  • a fifteenth transistor T15 having a gate connected to an Nth-order gate signal point Q(N), a drain connected to a source of the eleventh transistor (T11) and a source of the fourteenth transistor T14, Source connected to the first DC low Voltage VSS1;
  • the sixteenth transistor T16 has a gate connected to the N+1th gate signal point Q(N+1), a drain connected to the source of the eleventh transistor T11, and a source connected to the first DC low voltage VSS1;
  • the seventeenth transistor T17 whose gate is connected to the second common point P(N), the drain is connected to the Nth gate signal point Q(N), and the source is connected to the first DC low voltage VSS1;
  • the transistor T18 has a gate connected to the second common point P(N), a drain connected to the Nth horizontal scanning line G(N), a source connected to the first DC low voltage VSS1, and a 19th transistor T19 whose gate Connected to the first common point (K(N)), the drain is connected to the
  • the drain is connected to the Nth horizontal scanning line G(N), and the source is connected to the first DC low voltage VSS1;
  • the GOA unit further includes a reset circuit; the reset circuit is connected to the Nth stage gate
  • the pole signal point Q(N), the N+1th gate signal point Q(N+1), and the first DC low voltage VSS1 are used to pull down the Nth gate signal point Q after receiving the reset signal (N) and the potential of the N+1th gate signal point Q(N+1) to Low potential.
  • the GOA circuit includes a plurality of GOA units, and each GOA unit sequentially pairs the Nth horizontal scanning line G(N) of the display area and The N+1th horizontal scanning line G(N+1) is charged, and the GOA unit includes an N-stage pull-up control circuit, an N+1-stage pull-up control circuit, an N-stage pull-up circuit, an N+1-stage pull-up circuit, and a N Stage pull-down circuit, N+1 stage pull-down circuit and pull-down sustain circuit; wherein, the N-stage pull-up circuit and the pull-down sustain circuit are respectively combined with the Nth-level gate signal point Q(N) and the N-th horizontal scanning line G(N) Connection, N-stage pull-up control circuit, N-stage pull-down circuit is connected with Nth-level gate signal point Q(N); N+1-stage pull-up circuit and pull-down sustain circuit respectively and N+1th-level gate signal point Q (N+1)
  • the pull-down sustaining circuit includes: a first transistor T1 having a gate and a drain connected to the first clock signal LC1; a second transistor T2 having a gate connected to the source of the first transistor T1 and a drain connected to the first clock signal LC1
  • the source is connected to the first common point K(N);
  • the third transistor T3 has a gate connected to the second clock signal LC2, a drain connected to the first clock signal LC1, and a source connected to the first common point K(N);
  • the four transistor T4 has a gate and a drain connected to the first common point K(N), a fifth transistor T5 whose gate is connected to the Nth gate signal point Q(N), and a drain connected to the source of the first transistor T1
  • the source of the pole and the fourth transistor T4 is connected to the first DC low voltage VSS1;
  • the sixth transistor T6 has a gate connected to the N+1th gate signal point Q(N+1), and the drain connection is a source of the transistor T1, the source is
  • a fourteenth transistor T14 having a gate and a drain connected to a second common point P(N); a fifteenth transistor T15 having a gate connected to the Nth gate signal point Q(N), and a drain connection a source of the eleven transistor (T11) and a source of the fourteenth transistor T14, the source is connected to the first DC low voltage VSS1; and the thirteenth transistor T16 has a gate connected to the N+1th gate signal point Q (N+1) The drain is connected to the source of the eleventh transistor T11, the source is connected to the first DC low voltage VSS1, and the seventeenth transistor T17 has a gate connected to the second common point P(N) and a drain connected to the Nth gate.
  • the source is connected to the first DC low voltage VSS1;
  • the eighteenth transistor T18 has a gate connected to the second common point P(N), and the drain is connected to the Nth horizontal scanning line G(N)
  • the source is connected to the first DC low voltage VSS1;
  • the nineteenth transistor T19 has a gate connected to the first common point (K(N)), and a drain connected to the Nth gate signal point Q(N), the source Connecting the first DC low voltage VSS1;
  • the twentieth transistor T20 has a gate connected to the first common point K(N), a drain connected to the Nth horizontal scanning line G(N), and a source connected to the first DC low Voltage VSS1.
  • the pull-down maintaining circuit further includes: a twenty-second transistor T22 whose gate is connected to the N+1th-level gate signal point Q(N+1), and the drain and the source are respectively connected to the first common point K(N) And the second common point P(N).
  • the GOA unit further includes an Nth stage downlink transmission circuit and an N+1th stage downlink transmission circuit; the Nth stage downlink transmission circuit is connected to the Nth stage gate signal point Q(N) for the The pass control circuit provides an N-stage down signal ST(N); the N+1th stage down circuit is connected to the N+1th level gate signal point Q(N+1) for the N+2 of the lower level GOA unit
  • the level down control circuit provides an N+1 level down signal ST(N+1).
  • the pull-down maintaining circuit further includes: a twenty-third transistor T23 having a gate connected to the N+1th horizontal scanning line G(N+1), a drain connected to the first common point K(N), and a source connection a DC low voltage VSS1; a twenty-fourth transistor T24 having a gate connected to the Nth horizontal scanning line G(N), a drain connected to the second common point P(N), and a source connected to the first DC low voltage VSS1.
  • the gate of the twenty-third transistor T23 is connected to the N+1 stage down signal ST(N+1); the gate of the twenty fourth transistor T24 is connected to the N stage down signal ST(N).
  • the source of the seventh transistor T7, the source of the ninth transistor T9, the source of the seventeenth transistor T17, and the source of the nineteenth transistor T19 are connected to the second DC low voltage VSS2.
  • the pull-down maintaining circuit further includes: a twenty-fifth transistor T25 having a gate connected to the first common point K(N), a drain connected to the N+1-level downlink signal ST(N+1), and a source connected to the second DC low voltage VSS2; the twenty-sixth transistor T26 has its gate connected to the second common point P(N), the drain connected to the N+1 stage down signal ST(N+1), and the source connected to the second DC low voltage VSS2; twenty-seventh transistor T27, whose gate is connected to the second common point P(N), the drain is connected to the N-stage down signal ST(N), the source is connected to the second DC low voltage VSS2; the twenty-eighth transistor T28, whose gate is connected to the first common point K(N), the drain is connected to the N-stage down signal ST(N), and the source is connected to the second DC low voltage VSS2.
  • the GOA unit further includes a reset circuit; the reset circuit is connected to the Nth gate signal point Q(N), the N+1th gate signal point Q(N+1), and the first DC low voltage VSS1, For pulling down the potential of the Nth stage gate signal point Q(N) and the N+1th stage gate signal point Q(N+1) to a low level after receiving the reset signal.
  • a liquid crystal display including a GOA circuit, the GOA circuit including a plurality of GOA units, each of the GOA units sequentially facing the Nth stage of the display area
  • the horizontal scanning line G(N) and the N+1th horizontal scanning line G(N+1) are charged, and the GOA unit includes an N-stage pull-up control circuit, an N+1-stage pull-up control circuit, an N-stage pull-up circuit, and a N +1-stage pull-up circuit, N-stage pull-down circuit, N+1-stage pull-down circuit and pull-down sustain circuit; wherein, the N-stage pull-up circuit and the pull-down sustain circuit respectively and the Nth-level gate signal point Q(N) and the Nth Level horizontal scanning line G(N) connection, N-stage pull-up control circuit, N-stage pull-down circuit connected to Nth-level gate signal point Q(N); N+1-stage pull-up circuit and pull-down sustain circuit respectively and Nth +1 level
  • the present invention combines two adjacent GOA units to share the same pull-down maintaining circuit with the two-stage GOA unit.
  • the pull-down maintaining circuit is in the first stage GOA. After the circuit is charged, the first stage GOA circuit is maintained to a low potential, and the second stage GOA circuit is maintained to a low level after the second stage GOA circuit is charged. In this way, the power consumption of half of the pull-down sustain circuit in the entire display can be reduced, thereby reducing power consumption.
  • 1 is a schematic structural diagram of connection of respective GOA units in the first embodiment of the GOA circuit of the present invention
  • FIG. 2 is a schematic circuit diagram of a GOA unit in a first embodiment of the GOA circuit of the present invention
  • FIG. 3 is a schematic diagram showing a specific circuit connection of a GOA unit in a second embodiment of the GOA circuit of the present invention
  • FIG. 4 is a schematic diagram showing waveforms of respective signals in a specific circuit of a GOA unit in a second embodiment of the GOA circuit of the present invention
  • FIG. 5 is a schematic diagram showing a specific circuit connection of a GOA unit in a third embodiment of the GOA circuit of the present invention.
  • FIG. 6 is a schematic diagram showing a specific circuit connection of a GOA unit in a fourth embodiment of the GOA circuit of the present invention.
  • FIG. 7 is a schematic diagram showing a specific circuit connection of a GOA unit in a fifth embodiment of the GOA circuit of the present invention.
  • FIG. 8 is a schematic diagram showing a specific circuit connection of a GOA unit in a sixth embodiment of the GOA circuit of the present invention.
  • FIG. 9 is a schematic diagram showing a specific circuit connection of a GOA unit in a seventh embodiment of the GOA circuit of the present invention.
  • Figure 10 is a waveform diagram showing signals in a specific circuit of a GOA unit in a seventh embodiment of the GOA circuit of the present invention.
  • a schematic diagram of a structure of a connection of each GOA unit in a first embodiment of a GOA circuit according to the present invention includes a plurality of GOA units, each of which sequentially charges adjacent two horizontal scanning lines of the display area.
  • the GOA unit for charging the Nth horizontal scanning line G(N) and the N+1th horizontal scanning line G(N+1):
  • the GOA unit includes an N-stage pull-up control circuit 101, an N+1-stage pull-up control circuit 102, an N-stage pull-up circuit 201, an N+1-stage pull-up circuit 202, and an N-stage pull-down circuit.
  • 301, N+1 stage pull-down circuit 302 and pull-down sustain circuit 400 is an N-stage pull-up control circuit 101, an N+1-stage pull-up control circuit 102, an N-stage pull-up circuit 201, an N+1-stage pull-up circuit 202, and an N-stage pull-down circuit.
  • the N-stage pull-up circuit 201 and the pull-down sustain circuit 400 are respectively connected to the Nth-level gate signal point Q(N) and the N-th horizontal scanning line G(N), and the N-stage pull-up control circuit 101 and the N-stage pull-down Circuit 301 is coupled to the Nth stage gate signal point Q (N.
  • the N+1 stage pull-up circuit 202 and the pull-down maintenance 400 circuit are respectively connected to the N+1th-level gate signal point Q(N+1) and the N+1-th horizontal scanning line G(N+1), N+1.
  • the stage pull-up control circuit 102 and the N+1 stage pull-down circuit 302 are connected to the N+1th stage gate signal point Q(N+1).
  • the pull-down maintaining circuit 400 maintains the potential of the Nth-level gate signal point Q(N) and the N-th horizontal scanning line G(N) to a low potential after charging of the N-th horizontal scanning line G(N), at the N+th After the 1-level horizontal scanning line G(N+1) is charged, the potential of the N+1th gate signal point Q(N+1) and the Nth horizontal scanning line G(N+1) is maintained to a low potential.
  • the N-stage pull-up control circuit 101 raises the potential value of the Nth-level gate signal point Q(N) after receiving the G(N-1) signal of the previous-stage GOA unit and controls the N-stage pull-up.
  • the circuit 201 is turned on, receives the N-level clock signal CK(N) to charge the N-th horizontal scanning line G(N), and after the charging is completed, the N-stage pull-down circuit 301 pulls down the potential of the N-th gate signal point Q(N).
  • the N-stage pull-up circuit 201 is turned off, and the pull-down sustain circuit 400 pulls down and maintains the potential of the Nth-level gate signal point Q(N) and the N-th horizontal scanning line G(N) to a low level and remains low.
  • the scanning signal G(N) outputted by the Nth horizontal scanning line G(N) is used as an input signal of the N+1 stage pull-up control circuit in the N+1 stage circuit, and the working principle of the N+1 stage circuit and the N stage circuit Similarly, only the control signals of the pull-up control circuit and the pull-down circuit are different.
  • the pull-down maintaining module 400 simultaneously pulls down the potential of the two-stage circuit under the control of the first clock signal LC1 and the second clock signal LC2. Go low and maintain low potential.
  • the two-stage GOA units share the same pull-down maintaining circuit by coupling adjacent two-stage GOA units, and the pull-down maintaining circuit maintains the first level after the first-stage GOA circuit is charged.
  • the GOA circuit is low to maintain the second stage GOA circuit to a low potential after the second stage GOA circuit is charged. In this way, the power consumption of half of the pull-down sustain circuit in the entire display can be reduced, thereby reducing power consumption.
  • the GOA unit includes an N-stage pull-up control circuit 101, an N+1-stage pull-up control circuit 102, and an N-stage pull-up circuit.
  • the pull-down sustain circuit 400 includes: a first transistor T1 having a gate and a drain connected thereto a clock signal LC1; a second transistor T2 having a gate connected to the source of the first transistor T1, a drain connected to the first clock signal LC1, a source connected to the first common point K(N), and a third transistor T3 having a gate
  • the pole is connected to the second clock signal LC2, the drain is connected to the first clock signal LC1, the source is connected to the first common point K(N), and the fourth transistor T4 is connected to the first common point K(N);
  • the fifth transistor T5 has a gate connected to the Nth gate signal point Q(N), a drain connected to the source of the first transistor T1 and a source of the fourth transistor T4, and a source connected to the first DC low voltage VSS1 a sixth transistor T6
  • a ninth transistor T9 having a gate connected to a second common point P(N), a drain connected to an N+1th gate signal point Q(N+1), and a source connected first DC low voltage VSS1;
  • tenth transistor T10 whose gate is connected to the second common point P(N), the drain is connected to the N+1th horizontal scanning line G(N+1), and the source is connected to the first DC low a voltage VSS1;
  • an eleventh transistor T11 having a gate and a drain connected to the second clock signal LC2;
  • a twelfth transistor T12 having a gate connected to the source of the eleventh transistor T11 and a drain connected to the second clock signal LC2,
  • the source is connected to the second common point P(N);
  • the thirteenth transistor T13 has a gate connected to the first clock signal LC1, a drain connected to the second clock signal LC2, and a source connected to the second common point P(N);
  • Fourteen transistor T14 its gate and The drain is connected to the second common point
  • the source is connected to the first DC low voltage VSS1; the seventh transistor T17 has a gate connected to the second common point P(N), and the drain is connected to the Nth gate signal point Q(N), the source The first DC low voltage VSS1 is connected to the pole; the eighteenth transistor T18 has a gate connected to the second common point (P(N)), a drain connected to the Nth horizontal scanning line G(N), and the source is connected to the first The DC low voltage VSS1; the nineteenth transistor T19 has a gate connected to the first common point K(N), a drain connected to the Nth gate signal point Q(N), and a source connected to the first DC low voltage VSS1 The twentieth transistor T20 has a gate connected to the first common point K(N), a drain connected to the Nth horizontal scanning line G(N), and a source connected to the first DC low voltage VSS1.
  • FIG. 4 is a schematic diagram of waveforms of signals in a specific circuit of a GOA unit in a second embodiment of the GOA circuit of the present invention.
  • the waveform is divided into 1-8 working intervals by dashed lines:
  • the first action interval: G(N-1) is a low level
  • the N-stage pull-up control circuit 101 is turned off
  • the Q(N) point is at a low level
  • the N-stage pull-up circuit 201 is turned off. Due to the effects of LC1 and LC2,
  • the P(N) point is high level, T12 is turned on, and G(N) is kept low, then the N+1 stage pull-up control circuit 102 is turned off, and the Q(N+1) point is low level, N+
  • the 1-stage pull-up circuit 202 is turned off. Due to the action of LC1 and LC2, the P(N) point is at a high level, T10 is turned on, and G(N+1) is outputted at a low level;
  • Q(N) is high level, T21, T5 and T15 are turned on, that is, P(N) and K(N) are simultaneously low. Level, G(N+1) continues to remain low;
  • the third action interval: G(N-1) is a low level, the N-stage pull-up control circuit 101 is turned off, the Q(N) point is slightly lowered, and other key points are substantially unchanged;
  • the fourth action interval due to the bootstrap action of the first capacitor Cb1 in the N-stage pull-up circuit 201, the potential of the Q(N) point is raised to a higher level, and the N-stage pull-up circuit 201 is still turned on. At this time, the N-level clock is turned on. The signal CK(N) becomes high and G(N) is charged;
  • the fifth action interval the N-level clock signal CK(N) becomes a low potential, and the G(N) charging is completed, causing the N+1-stage pull-up control circuit 102 to be turned off, and the other key points are substantially unchanged;
  • the sixth action interval due to the bootstrap action of the second capacitor Cb2 in the N+1 stage pull-up circuit 202, the potential of the Q(N+1) point is raised to a higher level, and the N+1 stage pull-up circuit 202 is still turned on. At this time, the N+1-level clock signal CK(N+1) becomes a high potential, and G(N+1) is charged;
  • G(N+1) becomes high, the first pull-down circuit 301 is turned on, and the voltage of Q(N) is pulled down, T21, T5 and T15 are turned off, but due to Q(N+1) action, and changes of LC1 and LC2 , causing P(N) and K(N) to remain low.
  • the seventh action interval the N+1-level clock signal CK(N+1) becomes a low potential, and the G(N+1) charging is completed, and the other key points are substantially unchanged.
  • FIG. 5 a schematic diagram of a specific circuit connection of a GOA unit in a third embodiment of a GOA circuit according to the present invention. the difference between the GOA unit and the second embodiment is:
  • the pull-down maintaining circuit 400 further includes: a twenty-second transistor T22 whose gate is connected to the N+1th-level gate signal point Q(N+1), and the drain and the source are respectively connected to the first common point K(N) and The second common point P(N).
  • the pull-down maintaining circuit 400 Since the pull-down maintaining circuit 400 has to pull down and maintain the two-stage circuit at the same time, the combination of T22 and T21 ensures the normal output of the two-stage circuit, making the circuit more secure and more stable.
  • FIG. 6 is a schematic diagram of a specific circuit connection of a GOA unit in a fourth embodiment of a GOA circuit according to the present invention. the difference between the GOA unit and the third embodiment is:
  • the GOA unit further includes an Nth stage downlink transmission circuit 501 and an N+1th stage downlink transmission circuit 502.
  • the Nth stage downlink transmission circuit 501 is connected to the Nth stage gate signal point Q(N) for the N+1th stage.
  • the downlink control circuit provides an N-stage downlink signal ST(N); the N+1th downlink transmission circuit 502 is connected to the N+1th-level gate signal point Q(N+1) for the Nth of the lower-level GOA unit.
  • the +2 level down control circuit provides the N+1 level down signal ST(N+1).
  • control signals of the N-stage pull-up control circuit 101 and the N+1-stage pull-up control circuit 102 are replaced with ST(N-1) and ST(N), respectively, that is, the N-stage pull-up control circuit 101
  • the gates of the TFT transistors in the N+1 stage pull-up control circuit 102 are connected to ST(N-1) and ST(N), respectively.
  • FIG. 7 a specific circuit connection diagram of a GOA unit in a fifth embodiment of a GOA circuit according to the present invention.
  • the difference between the GOA unit and the fourth embodiment is:
  • the pull-down sustain circuit further includes: a twenty-third transistor T23 whose gate is connected to the N+1th horizontal scanning line G(N+1), the drain is connected to the first common point K(N), and the source is connected to the first straight
  • the low voltage VSS1 is connected;
  • the twenty fourth transistor T24 has a gate connected to the Nth horizontal scanning line G(N), a drain connected to the second common point P(N), and a source connected to the first DC low voltage VSS1.
  • two TFT transistors are newly added, mainly to enhance the pull-down of P(N) and K(N) during the action period, because the pull-down during the output is important, and if the pull-down is not good, it will directly lead to Display Error.
  • the gate signal of the N-stage pull-down circuit can be changed to ST(N+1), the gate signal of the N+1-stage pull-down circuit is changed to ST(N+2), and the gate signal of T23 is changed to ST(N +1), the gate signal of T24 is changed to ST(N), which prevents leakage of the transistor.
  • FIG. 8 a specific circuit connection diagram of a GOA unit in a sixth embodiment of a GOA circuit according to the present invention.
  • the difference between the GOA unit and the fifth embodiment is as follows:
  • the source of the seventh transistor T7, the source of the ninth transistor T9, the source of the seventeenth transistor T17, and the source of the nineteenth transistor T19 are connected to the second DC low voltage VSS2.
  • FIG. 9 is a schematic diagram of a specific circuit connection of a GOA unit in a seventh embodiment of a GOA circuit according to the present invention.
  • the difference between the GOA unit and the sixth embodiment is that the pull-down maintaining circuit further includes:
  • the gate is connected to the first common point K (N), the drain is connected to the N+1 stage down signal ST (N + 1), the source is connected to the second DC low voltage VSS2;
  • the twenty-sixth transistor T26 has a gate connected to the second common point P(N), a drain connected to the N+1 stage down signal ST(N+1), and a source connected to the second DC low voltage VSS2;
  • the twenty-seventh transistor T27 has a gate connected to the second common point P(N), a drain connected to the N-stage down signal ST(N), and a source connected to the second DC low voltage VSS2;
  • the twenty-eighth transistor T28 has a gate connected to the first common point K(N), a drain connected to the N-stage down signal ST(N), and a source connected to the second DC low voltage VSS2.
  • the gate signal of the N-stage pull-down circuit can be changed to ST(N+2), and the gate signal of the N+1-stage pull-down circuit is changed to ST(N+3), which is beneficial to the formation of the Q(N) point.
  • the embossed waveform is
  • FIG. 10 is a schematic diagram of waveforms of signals in a specific circuit of a GOA unit in a seventh embodiment of the GOA circuit of the present invention. This waveform is similar to Figure 4 except that the conjugate waveforms of Q(N) and Q(N+1) are more complete.
  • TFTs in the above embodiments are all exemplified by NTFTs, and may be replaced by PTFTs in actual operation, and the control potentials of the gates are interchanged, and the timing of the potentials is not changed.

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Abstract

一种GOA电路及液晶显示器，该GOA电路包括多个GOA单元，每个GOA单元依次对显示区域的第N级水平扫描线G(N)及第N+1级水平扫描线G(N+1)充电；GOA单元包括N级上拉控制电路(101)、N+1级上拉控制电路(102)、N级上拉电路(201)、N+1级上拉电路(202)、N级下拉电路(301)、N+1级下拉电路(302)及下拉维持电路(400)；下拉维持电路(400)在第N级水平扫描线G(N)充电后维持第N级栅极信号点Q(N)及第N级水平扫描线G(N)的电位至低电位，在第N+1级水平扫描线G(N+1)充电后维持第N+1级栅极信号点Q(N+1)及第N+1级水平扫描线G(N+1)的电位至低电位。通过上述方式，能够使两级GOA单元共用同一个下拉维持电路(400)，降低功耗。

Description

一种GOA电路及液晶显示器
【技术领域】
本发明涉及液晶显示领域，特别是涉及一种GOA电路及液晶显示器。
【背景技术】
Gate Driver On Array，简称GOA，也就是利用现有薄膜晶体管液晶显示器Array制程，将Gate行扫描驱动信号电路制作在Array基板上，实现对Gate逐行扫描的驱动方式的一项技术。
现有的GOA电路主要由上拉电路(Pull-up part)，上拉控制电路(Pull-up control part),下传电路(Transfer Part，下拉电路(Key Pull-down Part)，下拉维持电路(Pull-down Holding Part)，以及负责电位抬升的电容(Boost Part)组成。上拉电路主要负责将输入的时钟讯号(Clock)输出至Gate端，作为显示装置的驱动讯号；上拉控制电路负责控制上拉电路的打开，一般是由上级GOA电路传递来的讯号作用；下拉电路负责在Gate输出完后的第一时间将Gate拉低为低电位，即关闭Gate讯号；下拉保持电路则负责将Gate输出讯号和上拉电路的Gate讯号(通常称为Q点) 保持在关闭状态(即设定的负电位)，通常有两个下拉维持电路交替作用；电容(Boost Part)则负责Q点电位的二次抬升，这样确保上拉电路的G(N)正常输出。
但是这样的设计由于每级都包括一下拉维持电路，并由两部分交替作用，功耗较大，不利于环保。
【发明内容】
本发明主要解决的技术问题是提供一种GOA电路及液晶显示器，能够降低液晶显示器中GOA电路的功耗。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种GOA电路，GOA电路包括多个GOA单元，每个GOA单元依次对显示区域的第N级水平扫描线G(N)及第N+1级水平扫描线G(N+1)充电，GOA单元包括N级上拉控制电路、N+1级上拉控制电路、N级上拉电路、N+1级上拉电路、N级下拉电路、N+1级下拉电路及下拉维持电路；其中，N级上拉电路及下拉维持电路分别与第N级栅极信号点Q(N)和第N级水平扫描线G(N)连接，N级上拉控制电路、N级下拉电路与第N级栅极信号点Q(N)连接；N+1级上拉电路及下拉维持电路分别与第N+1级栅极信号点Q(N+1)和第N+1级水平扫描线G(N+1)连接，N+1级上拉控制电路、N+1级下拉电路与第N+1级栅极信号点Q(N+1)连接；下拉维持电路在第N级水平扫描线G(N)充电后维持第N级栅极信号点Q(N)及第N级水平扫描线G(N)的电位至低电位，在第N+1级水平扫描线G(N+1)充电后维持第N+1级栅极信号点Q(N+1)及第N级水平扫描线G(N+1)的电位至低电位；其中，下拉维持电路包括：第一晶体管T1，其栅极和漏极连接第一时钟信号LC1；第二晶体管T2，其栅极连接第一晶体管T1的源极，漏极连接第一时钟信号LC1，源极连接第一公共点K(N)；第三晶体管T3，其栅极连接第二时钟信号LC2，漏极连接第一时钟信号LC1，源极连接第一公共点K(N)；第四晶体管T4，其栅极和漏极连接第一公共点K(N)；第五晶体管T5，其栅极连接第N级栅极信号点Q(N)，漏极连接第一晶体管T1的源极和第四晶体管T4的源极，源极连接第一直流低电压VSS1；第六晶体管T6，其栅极连接第N+1级栅极信号点Q(N+1)，漏极连接第一晶体管T1的源极，源极连接第一直流低电压VSS1；第七晶体管T7，其栅极连接第一公共点K(N)，漏极连接第N+1级栅极信号点Q(N+1)，源极连接第一直流低电压VSS1；第八晶体管T8，其栅极连接第一公共点K(N)，漏极连接第N+1级水平扫描线G(N+1)，源极连接第一直流低电压VSS1；第九晶体管T9，其栅极连接第二公共点P(N)，漏极连接第N+1级栅极信号点Q(N+1)，源极连接第一直流低电压VSS1；第十晶体管T10，其栅极连接第二公共点P(N)，漏极连接第N+1级水平扫描线G(N+1)，源极连接第一直流低电压VSS1；第十一晶体管T11，其栅极和漏极连接第二时钟信号LC2；第十二晶体管T12，其栅极连接第十一晶体管T11的源极，漏极连接第二时钟信号LC2，源极连接第二公共点P(N)；第十三晶体管T13，其栅极连接第一时钟信号LC1，漏极连接第二时钟信号LC2，源极连接第二公共点P(N)；第十四晶体管T14，其栅极和漏极连接第二公共点P(N)；第十五晶体管T15，其栅极连接第N级栅极信号点Q(N)，漏极连接第十一晶体管(T11)的源极和第十四晶体管T14的源极，源极连接第一直流低电压VSS1；第十六晶体管T16，其栅极连接第N+1级栅极信号点Q(N+1)，漏极连接第十一晶体管T11的源极，源极连接第一直流低电压VSS1；第十七晶体管T17，其栅极连接第二公共点P(N)，漏极连接第N级栅极信号点Q(N)，源极连接第一直流低电压VSS1；第十八晶体管T18，其栅极连接第二公共点P(N)，漏极连接第N级水平扫描线G(N)，源极连接第一直流低电压VSS1；第十九晶体管T19，其栅极连接第一公共点(K(N))，漏极连接第N级栅极信号点Q(N)，源极连接第一直流低电压VSS1；第二十晶体管T20，其栅极连接第一公共点K(N)，漏极连接第N级水平扫描线G(N)，源极连接第一直流低电压VSS1；其中，GOA单元还包括重置电路；重置电路连接第N级栅极信号点Q(N)、第N+1级栅极信号点Q(N+1)及第一直流低电压VSS1，用于在接收到重置信号后下拉第N级栅极信号点Q(N)及第N+1级栅极信号点Q(N+1)的电位至低电位。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种GOA电路，GOA电路包括多个GOA单元，每个GOA单元依次对显示区域的第N级水平扫描线G(N)及第N+1级水平扫描线G(N+1)充电，GOA单元包括N级上拉控制电路、N+1级上拉控制电路、N级上拉电路、N+1级上拉电路、N级下拉电路、N+1级下拉电路及下拉维持电路；其中，N级上拉电路及下拉维持电路分别与第N级栅极信号点Q(N)和第N级水平扫描线G(N)连接，N级上拉控制电路、N级下拉电路与第N级栅极信号点Q(N)连接；N+1级上拉电路及下拉维持电路分别与第N+1级栅极信号点Q(N+1)和第N+1级水平扫描线G(N+1)连接，N+1级上拉控制电路、N+1级下拉电路与第N+1级栅极信号点Q(N+1)连接；下拉维持电路在第N级水平扫描线G(N)充电后维持第N级栅极信号点Q(N)及第N级水平扫描线G(N)的电位至低电位，在第N+1级水平扫描线G(N+1)充电后维持第N+1级栅极信号点Q(N+1)及第N级水平扫描线G(N+1)的电位至低电位。
其中，下拉维持电路包括：第一晶体管T1，其栅极和漏极连接第一时钟信号LC1；第二晶体管T2，其栅极连接第一晶体管T1的源极，漏极连接第一时钟信号LC1，源极连接第一公共点K(N)；第三晶体管T3，其栅极连接第二时钟信号LC2，漏极连接第一时钟信号LC1，源极连接第一公共点K(N)；第四晶体管T4，其栅极和漏极连接第一公共点K(N)；第五晶体管T5，其栅极连接第N级栅极信号点Q(N)，漏极连接第一晶体管T1的源极和第四晶体管T4的源极，源极连接第一直流低电压VSS1；第六晶体管T6，其栅极连接第N+1级栅极信号点Q(N+1)，漏极连接第一晶体管T1的源极，源极连接第一直流低电压VSS1；第七晶体管T7，其栅极连接第一公共点K(N)，漏极连接第N+1级栅极信号点Q(N+1)，源极连接第一直流低电压VSS1；第八晶体管T8，其栅极连接第一公共点K(N)，漏极连接第N+1级水平扫描线G(N+1)，源极连接第一直流低电压VSS1；第九晶体管T9，其栅极连接第二公共点P(N)，漏极连接第N+1级栅极信号点Q(N+1)，源极连接第一直流低电压VSS1；第十晶体管T10，其栅极连接第二公共点P(N)，漏极连接第N+1级水平扫描线G(N+1)，源极连接第一直流低电压VSS1；第十一晶体管T11，其栅极和漏极连接第二时钟信号LC2；第十二晶体管T12，其栅极连接第十一晶体管T11的源极，漏极连接第二时钟信号LC2，源极连接第二公共点P(N)；第十三晶体管T13，其栅极连接第一时钟信号LC1，漏极连接第二时钟信号LC2，源极连接第二公共点P(N)；第十四晶体管T14，其栅极和漏极连接第二公共点P(N)；第十五晶体管T15，其栅极连接第N级栅极信号点Q(N)，漏极连接第十一晶体管(T11)的源极和第十四晶体管T14的源极，源极连接第一直流低电压VSS1；第十六晶体管T16，其栅极连接第N+1级栅极信号点Q(N+1)，漏极连接第十一晶体管T11的源极，源极连接第一直流低电压VSS1；第十七晶体管T17，其栅极连接第二公共点P(N)，漏极连接第N级栅极信号点Q(N)，源极连接第一直流低电压VSS1；第十八晶体管T18，其栅极连接第二公共点P(N)，漏极连接第N级水平扫描线G(N)，源极连接第一直流低电压VSS1；第十九晶体管T19，其栅极连接第一公共点(K(N))，漏极连接第N级栅极信号点Q(N)，源极连接第一直流低电压VSS1；第二十晶体管T20，其栅极连接第一公共点K(N)，漏极连接第N级水平扫描线G(N)，源极连接第一直流低电压VSS1。
其中，下拉维持电路还包括：第二十二晶体管T22，其栅极连接第N+1级栅极信号点Q(N+1)，漏极和源极分别连接第一公共点K(N)和第二公共点P(N)。
其中，GOA单元还包括第N级下传电路及第N+1级下传电路；第N级下传电路连接第N级栅极信号点Q(N)，用于给第N+1级下传控制电路提供N级下传信号ST(N)；第N+1级下传电路连接第N+1级栅极信号点Q(N+1)，用于给下级GOA单元的第N+2级下传控制电路提供N+1级下传信号ST(N+1)。
其中，下拉维持电路还包括：第二十三晶体管T23，其栅极连接第N+1级水平扫描线G(N+1)，漏极连接第一公共点K(N)，源极连接第一直流低电压VSS1；第二十四晶体管T24，其栅极连接第N级水平扫描线G(N)，漏极连接第二公共点P(N)，源极连接第一直流低电压VSS1。
其中，第二十三晶体管T23的栅极连接N+1级下传信号ST(N+1)；第二十四晶体管T24的栅极连接N级下传信号ST(N)。
其中，第七晶体管T7的源极、第九晶体管T9的源极、第十七晶体管T17的源极及第十九晶体管T19的源极连接第二直流低电压VSS2。
其中，下拉维持电路还包括：第二十五晶体管T25，其栅极连接第一公共点K(N)，漏极连接N+1级下传信号ST(N+1)，源极连接第二直流低电压VSS2；第二十六晶体管T26，其栅极连接第二公共点P(N)，漏极连接N+1级下传信号ST(N+1)，源极连接第二直流低电压VSS2；第二十七晶体管T27，其栅极连接第二公共点P(N)，漏极连接N级下传信号ST(N)，源极连接第二直流低电压VSS2；第二十八晶体管T28，其栅极连接第一公共点K(N)，漏极连接N级下传信号ST(N)，源极连接第二直流低电压VSS2。
其中，GOA单元还包括重置电路；重置电路连接第N级栅极信号点Q(N)、第N+1级栅极信号点Q(N+1)及第一直流低电压VSS1，用于在接收到重置信号后下拉第N级栅极信号点Q(N)及第N+1级栅极信号点Q(N+1)的电位至低电位。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种液晶显示器，该液晶显示器包括GOA电路，该GOA电路包括多个GOA单元，每个GOA单元依次对显示区域的第N级水平扫描线G(N)及第N+1级水平扫描线G(N+1)充电，GOA单元包括N级上拉控制电路、N+1级上拉控制电路、N级上拉电路、N+1级上拉电路、N级下拉电路、N+1级下拉电路及下拉维持电路；其中，N级上拉电路及下拉维持电路分别与第N级栅极信号点Q(N)和第N级水平扫描线G(N)连接，N级上拉控制电路、N级下拉电路与第N级栅极信号点Q(N)连接；N+1级上拉电路及下拉维持电路分别与第N+1级栅极信号点Q(N+1)和第N+1级水平扫描线G(N+1)连接，N+1级上拉控制电路、N+1级下拉电路与第N+1级栅极信号点Q(N+1)连接；下拉维持电路在第N级水平扫描线G(N)充电后维持第N级栅极信号点Q(N)及第N级水平扫描线G(N)的电位至低电位，在第N+1级水平扫描线G(N+1)充电后维持第N+1级栅极信号点Q(N+1)及第N级水平扫描线G(N+1)的电位至低电位。
本发明的有益效果是：区别于现有技术的情况，本发明通过将相邻的两级GOA单元进行耦合，使两级GOA单元共用同一个下拉维持电路，该下拉维持电路在第一级GOA电路充电完后维持第一级GOA电路至低电位，在第二级GOA电路充电完后维持第二级GOA电路至低电位。采用这样的方式，能够减少整个显示器中一半的下拉维持电路的耗电量，从而降低能耗。
【附图说明】
图1是本发明GOA电路第一实施方式中各个GOA单元连接的结构示意图；
图2是本发明GOA电路第一实施方式中GOA单元的电路连接示意图；
图3是本发明GOA电路第二实施方式中GOA单元的具体电路连接示意图；
图4是本发明GOA电路第二实施方式中GOA单元的具体电路中各信号的波形示意图；
图5是本发明GOA电路第三实施方式中GOA单元的具体电路连接示意图；
图6是本发明GOA电路第四实施方式中GOA单元的具体电路连接示意图；
图7是本发明GOA电路第五实施方式中GOA单元的具体电路连接示意图；
图8是本发明GOA电路第六实施方式中GOA单元的具体电路连接示意图；
图9是本发明GOA电路第七实施方式中GOA单元的具体电路连接示意图；
图10是本发明GOA电路第七实施方式中GOA单元的具体电路中各信号的波形示意图。
【具体实施方式】
参阅图1，本发明一种GOA电路第一实施方式中各个GOA单元连接的结构示意图，该GOA电路包括多个GOA单元，每个GOA单元依次对显示区域的相邻两级水平扫描线充电。
下面以给第N级水平扫描线G(N)及第N+1级水平扫描线G(N+1)充电的GOA单元为例：参阅图2，本发明一种GOA电路第一实施方式中一个GOA单元中的电路连接示意图，GOA单元包括N级上拉控制电路101、N+1级上拉控制电路102、N级上拉电路201、N+1级上拉电路202、N级下拉电路301、N+1级下拉电路302及下拉维持电路400。
其中，N级上拉电路201及下拉维持电路400分别与第N级栅极信号点Q(N)和第N级水平扫描线G(N)连接，N级上拉控制电路101、N级下拉电路301与第N级栅极信号点Q(N连接。
N+1级上拉电路202及下拉维持400电路分别与第N+1级栅极信号点Q(N+1)和第N+1级水平扫描线G(N+1)连接，N+1级上拉控制电路102、N+1级下拉电路302与第N+1级栅极信号点Q(N+1)连接。
下拉维持电路400在第N级水平扫描线G(N)充电后维持第N级栅极信号点Q(N)及第N级水平扫描线G(N)的电位至低电位，在第N+1级水平扫描线G(N+1)充电后维持第N+1级栅极信号点Q(N+1)及第N级水平扫描线G(N+1)的电位至低电位。
具体地，N级上拉控制电路101在接收上一级GOA单元的G(N-1)信号后抬高第N级栅极信号点Q(N)的电位值高电位并控制N级上拉电路201打开，接收N级时钟信号CK(N)从而对第N级水平扫描线G(N)充电，充电完成后，N级下拉电路301下拉第N级栅极信号点Q(N)的电位至低电位，同时关闭N级上拉电路201，下拉维持电路400下拉并维持第N级栅极信号点Q(N)和第N级水平扫描线G(N)的电位至低电位并维持低电位；
第N级水平扫描线G(N)输出的扫描信号G(N)又作为N+1级电路中N+1级上拉控制电路的输入信号，N+1级电路与N级电路的工作原理相同，仅仅是上拉控制电路和下拉电路的控制信号不同，在两级电路的工作期间，下拉维持模块400在第一时钟信号LC1和第二时钟信号LC2的控制下同时下拉两级电路的电位至低电位并维持低电位。
区别于现有技术，本实施方式通过将相邻的两级GOA单元进行耦合，使两级GOA单元共用同一个下拉维持电路，该下拉维持电路在第一级GOA电路充电完后维持第一级GOA电路至低电位，在第二级GOA电路充电完后维持第二级GOA电路至低电位。采用这样的方式，能够减少整个显示器中一半的下拉维持电路的耗电量，从而降低能耗。
参阅图3，本发明一种GOA电路第二实施方式中GOA单元的具体电路连接示意图，该GOA单元包括N级上拉控制电路101、N+1级上拉控制电路102、N级上拉电路201、N+1级上拉电路202、N级下拉电路301、N+1级下拉电路302及下拉维持电路400，其中下拉维持电路400包括：第一晶体管T1，其栅极和漏极连接第一时钟信号LC1；第二晶体管T2，其栅极连接第一晶体管T1的源极，漏极连接第一时钟信号LC1，源极连接第一公共点K(N)；第三晶体管T3，其栅极连接第二时钟信号LC2，漏极连接第一时钟信号LC1，源极连接第一公共点K(N)；第四晶体管T4，其栅极和漏极连接第一公共点K(N)；第五晶体管T5，其栅极连接第N级栅极信号点Q(N)，漏极连接第一晶体管T1的源极和第四晶体管T4的源极，源极连接第一直流低电压VSS1；第六晶体管T6，其栅极连接第N+1级栅极信号点Q(N+1)，漏极连接第一晶体管T1的源极，源极连接第一直流低电压VSS1；第七晶体管T7，其栅极连接第一公共点K(N)，漏极连接第N+1级栅极信号点Q(N+1)，源极连接第一直流低电压VSS1；第八晶体管T8，其栅极连接第一公共点K(N)，漏极连接第N+1级水平扫描线G(N+1)，源极连接第一直流低电压VSS1；第九晶体管T9，其栅极连接第二公共点P(N)，漏极连接第N+1级栅极信号点Q(N+1)，源极连接第一直流低电压VSS1；第十晶体管T10，其栅极连接第二公共点P(N)，漏极连接第N+1级水平扫描线G(N+1)，源极连接第一直流低电压VSS1；第十一晶体管T11，其栅极和漏极连接第二时钟信号LC2；第十二晶体管T12，其栅极连接第十一晶体管T11的源极，漏极连接第二时钟信号LC2，源极连接第二公共点P(N)；第十三晶体管T13，其栅极连接第一时钟信号LC1，漏极连接第二时钟信号LC2，源极连接第二公共点P(N)；第十四晶体管T14，其栅极和漏极连接第二公共点P(N)；第十五晶体管T15，其栅极连接第N级栅极信号点Q(N)，漏极连接第十一晶体管T11的源极和第十四晶体管T14的源极，源极连接第一直流低电压VSS1；第十六晶体管T16，其栅极连接第N+1级栅极信号点Q(N+1)，漏极连接第十一晶体管T11的源极，源极连接第一直流低电压VSS1；第十七晶体管T17，其栅极连接第二公共点P(N)，漏极连接第N级栅极信号点Q(N)，源极连接第一直流低电压VSS1；第十八晶体管T18，其栅极连接第二公共点(P(N))，漏极连接第N级水平扫描线G(N)，源极连接第一直流低电压VSS1；第十九晶体管T19，其栅极连接第一公共点K(N)，漏极连接第N级栅极信号点Q(N)，源极连接第一直流低电压VSS1；第二十晶体管T20，其栅极连接第一公共点K(N)，漏极连接第N级水平扫描线G(N)，源极连接第一直流低电压VSS1。
同时参阅图4，本发明一种GOA电路第二实施方式中GOA单元的具体电路中各信号的波形示意图。图4中用虚线将波形图划分为1-8个工作区间：
第1作用区间：G(N-1)为低电平，N级上拉控制电路101关闭，Q(N)点为低电平，N级上拉电路201关闭，由于LC1和LC2的作用，P(N)点为高电平，T12导通，维持G(N)为低电平，则N+1级上拉控制电路102关闭，Q(N+1)点为低电平，N+1级上拉电路202关闭，由于LC1和LC2的作用，P(N)点为高电平，T10导通，G(N+1)输出低电平；
第2作用区间：G(N-1)为高电平，N级上拉控制电路101开启，Q(N)点为高电平，N级上拉电路102开启，但由于CK(N)仍为低电平，因此G(N)仍然输出低电平，另外，由于Q(N)为高电平，导致T21、T5及T15导通，即P(N)和K(N)同时为低电平，G(N+1)继续保持低电平；
第3作用区间：G(N-1)为低电平，N级上拉控制电路101关闭，Q(N)点略微降低，其他关键点大致不变；
第4作用区间：由于N级上拉电路201中第一电容Cb1的自举作用，将Q(N)点的电位抬升到更高，N级上拉电路201依然开启，此时，N级时钟信号CK(N)变为高电位，G(N)充电；
由于G(N)变高，N+1级上拉控制电路102开启，Q(N+1)变为高电位，N+1级上拉电路202打开，但此时N+1级时钟信号为低，G(N+1)仍然为低；
第5作用区间：N级时钟信号CK(N)变为低电位，G(N)充电完毕，导致N+1级上拉控制电路102关闭，其他关键点大致不变；
第6作用区间：由于N+1级上拉电路202中第二电容Cb2的自举作用，将Q(N+1)点的电位抬升到更高，N+1级上拉电路202依然开启，此时，N+1级时钟信号CK(N+1)变为高电位，G(N+1)充电；
G(N+1)变为高电位，第一下拉电路301开启，下拉Q(N)的电压，T21、T5及T15关闭，但由于Q(N+1)作用，及LC1和LC2的变化，导致P(N)及K(N)仍然为低。
第7作用区间：N+1级时钟信号CK(N+1)变为低电位，G(N+1)充电完毕，其他关键点大致不变。
参阅图5，本发明一种GOA电路第三实施方式中GOA单元的具体电路连接示意图；该GOA单元与上述第二实施方式的区别在于：
下拉维持电路400还包括：第二十二晶体管T22，其栅极连接第N+1级栅极信号点Q(N+1)，漏极和源极分别连接第一公共点K(N)和第二公共点P(N)。
由于下拉维持电路400要同时下拉并维持两级电路，采用T22与T21共同作用保证两级电路的正常输出，使电路更加保险，更加稳定。
参阅图6，本发明一种GOA电路第四实施方式中GOA单元的具体电路连接示意图；该GOA单元与上述第三实施方式的区别在于：
GOA单元还包括第N级下传电路501及第N+1级下传电路502；第N级下传电路501连接第N级栅极信号点Q(N)，用于给第N+1级下传控制电路提供N级下传信号ST(N)；第N+1级下传电路502连接第N+1级栅极信号点Q(N+1)，用于给下级GOA单元的第N+2级下传控制电路提供N+1级下传信号ST(N+1)。
在该实施方式中，将N级上拉控制电路101和N+1级上拉控制电路102的控制信号分别更换为ST(N-1)及ST(N)，即N级上拉控制电路101和N+1级上拉控制电路102中的TFT晶体管的栅极分别连接ST(N-1)及ST(N)。
参阅图7，本发明一种GOA电路第五实施方式中GOA单元的具体电路连接示意图；该GOA单元与上述第四实施方式的区别在于：
下拉维持电路还包括：第二十三晶体管T23，其栅极连接第N+1级水平扫描线G(N+1)，漏极连接第一公共点K(N)，源极连接第一直流低电压VSS1；第二十四晶体管T24，其栅极连接第N级水平扫描线G(N)，漏极连接第二公共点P(N)，源极连接第一直流低电压VSS1。
本实施方式中新增加两个TFT晶体管，主要是为了增强在作用期间的对P(N)和K(N)的强化下拉，因为输出期间的下拉很重要，如果下拉不好，将会直接导致显示异常。
另外，可以将N级下拉电路的栅极信号改为ST(N+1)，N+1级下拉电路的栅极信号改为ST(N+2)，T23的栅极信号改为ST(N+1)，T24的栅极信号改为ST(N)，这样防止晶体管的漏电。
参阅图8，本发明一种GOA电路第六实施方式中GOA单元的具体电路连接示意图；该GOA单元与上述第五实施方式的区别在于：
第七晶体管T7的源极、第九晶体管T9的源极、第十七晶体管T17的源极及第十九晶体管T19的源极连接第二直流低电压VSS2。
参阅图9，本发明一种GOA电路第七实施方式中GOA单元的具体电路连接示意图；该GOA单元与上述第六实施方式的区别在于：下拉维持电路还包括：
第二十五晶体管T25，其栅极连接第一公共点K(N)，漏极连接N+1级下传信号ST(N+1)，源极连接第二直流低电压VSS2；
第二十六晶体管T26，其栅极连接第二公共点P(N)，漏极连接N+1级下传信号ST(N+1)，源极连接第二直流低电压VSS2；
第二十七晶体管T27，其栅极连接第二公共点P(N)，漏极连接N级下传信号ST(N)，源极连接第二直流低电压VSS2；
第二十八晶体管T28，其栅极连接第一公共点K(N)，漏极连接N级下传信号ST(N)，源极连接第二直流低电压VSS2。
另外，可以将N级下拉电路的栅极信号改为ST(N+2)，N+1级下拉电路的栅极信号改为ST(N+3)，有利于Q(N)点形成较好的凸字波形。
同时参阅图10，本发明一种GOA电路第七实施方式中GOA单元的具体电路中各信号的波形示意图。该波形图与图4类似，区别在于Q(N)和Q(N+1)的凸字波形更加的完整。
以上各个实施方式中的TFT均以NTFT为例，在实际操作中也可以替换为PTFT，其栅极的控制电位高低互换，电位的时序不发生改变。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (18)

  1. 一种GOA电路，用于液晶显示，其中，所述GOA电路包括多个GOA单元，每个所述GOA单元依次对显示区域的第N级水平扫描线(G(N))及第N+1级水平扫描线(G(N+1))充电，所述GOA单元包括N级上拉控制电路、N+1级上拉控制电路、N级上拉电路、N+1级上拉电路、N级下拉电路、N+1级下拉电路及下拉维持电路；
    其中，所述N级上拉电路及下拉维持电路分别与第N级栅极信号点(Q(N))和所述第N级水平扫描线(G(N))连接，所述N级上拉控制电路、N级下拉电路与所述第N级栅极信号点(Q(N))连接；
    所述N+1级上拉电路及下拉维持电路分别与第N+1级栅极信号点(Q(N+1))和所述第N+1级水平扫描线(G(N+1))连接，所述N+1级上拉控制电路、N+1级下拉电路与所述第N+1级栅极信号点(Q(N+1))连接；
    所述下拉维持电路在所述第N级水平扫描线(G(N))充电后维持所述第N级栅极信号点(Q(N))及所述第N级水平扫描线(G(N))的电位至低电位，在所述第N+1级水平扫描线(G(N+1))充电后维持所述第N+1级栅极信号点(Q(N+1))及所述第N级水平扫描线(G(N+1))的电位至低电位；
    其中，所述下拉维持电路包括：
    第一晶体管(T1)，其栅极和漏极连接第一时钟信号(LC1)；
    第二晶体管(T2)，其栅极连接所述第一晶体管(T1)的源极，漏极连接所述第一时钟信号(LC1)，源极连接第一公共点(K(N))；
    第三晶体管(T3)，其栅极连接第二时钟信号(LC2)，漏极连接所述第一时钟信号(LC1)，源极连接所述第一公共点(K(N))；
    第四晶体管(T4)，其栅极和漏极连接所述第一公共点(K(N))；
    第五晶体管(T5)，其栅极连接所述第N级栅极信号点(Q(N))，漏极连接所述第一晶体管(T1)的源极和所述第四晶体管(T4)的源极，源极连接第一直流低电压(VSS1)；
    第六晶体管(T6)，其栅极连接所述第N+1级栅极信号点(Q(N+1))，漏极连接所述第一晶体管(T1)的源极，源极连接所述第一直流低电压(VSS1)；
    第七晶体管(T7)，其栅极连接所述第一公共点(K(N))，漏极连接所述第N+1级栅极信号点(Q(N+1))，源极连接所述第一直流低电压(VSS1)；
    第八晶体管(T8)，其栅极连接所述第一公共点(K(N))，漏极连接所述第N+1级水平扫描线(G(N+1))，源极连接所述第一直流低电压(VSS1)；
    第九晶体管(T9)，其栅极连接第二公共点(P(N))，漏极连接所述第N+1级栅极信号点(Q(N+1))，源极连接所述第一直流低电压(VSS1)；
    第十晶体管(T10)，其栅极连接所述第二公共点(P(N))，漏极连接所述第N+1级水平扫描线(G(N+1))，源极连接所述第一直流低电压(VSS1)；
    第十一晶体管(T11)，其栅极和漏极连接所述第二时钟信号(LC2)；
    第十二晶体管(T12)，其栅极连接所述第十一晶体管(T11)的源极，漏极连接所述第二时钟信号(LC2)，源极连接第二公共点(P(N))；
    第十三晶体管(T13)，其栅极连接第一时钟信号(LC1)，漏极连接所述第二时钟信号(LC2)，源极连接所述第二公共点(P(N))；
    第十四晶体管(T14)，其栅极和漏极连接所述第二公共点(P(N))；
    第十五晶体管(T15)，其栅极连接所述第N级栅极信号点(Q(N))，漏极连接所述第十一晶体管(T11)的源极和所述第十四晶体管(T14)的源极，源极连接第一直流低电压(VSS1)；
    第十六晶体管(T16)，其栅极连接所述第N+1级栅极信号点(Q(N+1))，漏极连接所述第十一晶体管(T11)的源极，源极连接所述第一直流低电压(VSS1)；
    第十七晶体管(T17)，其栅极连接所述第二公共点(P(N))，漏极连接所述第N级栅极信号点(Q(N))，源极连接所述第一直流低电压(VSS1)；
    第十八晶体管(T18)，其栅极连接所述第二公共点(P(N))，漏极连接所述第N级水平扫描线(G(N))，源极连接所述第一直流低电压(VSS1)；
    第十九晶体管(T19)，其栅极连接第一公共点(K(N))，漏极连接所述第N级栅极信号点(Q(N))，源极连接所述第一直流低电压(VSS1)；
    第二十晶体管(T20)，其栅极连接所述第一公共点(K(N))，漏极连接所述第N级水平扫描线(G(N))，源极连接所述第一直流低电压(VSS1)；
    所述GOA单元还包括重置电路；所述重置电路连接所述第N级栅极信号点(Q(N))、第N+1级栅极信号点(Q(N+1))及第一直流低电压(VSS1)，用于在接收到重置信号后下拉所述第N级栅极信号点(Q(N))及第N+1级栅极信号点(Q(N+1))的电位至低电位。
  2. 根据权利要求1所述的GOA电路，其中，所述下拉维持电路还包括：
    第二十二晶体管(T22)，其栅极连接所述第N+1级栅极信号点(Q(N+1))，漏极和源极分别连接所述第一公共点(K(N))和所述第二公共点(P(N))。
  3. 根据权利要求2所述的GOA电路，其中，所述GOA单元还包括第N级下传电路及第N+1级下传电路；
    所述第N级下传电路连接所述第N级栅极信号点(Q(N))，用于给所述第N+1级下传控制电路提供N级下传信号(ST(N))；
    所述第N+1级下传电路连接所述第N+1级栅极信号点(Q(N+1))，用于给下级GOA单元的第N+2级下传控制电路提供N+1级下传信号(ST(N+1))。
  4. 根据权利要求3所述的GOA电路，其中，所述下拉维持电路还包括：
    第二十三晶体管(T23)，其栅极连接所述第N+1级水平扫描线(G(N+1))，漏极连接所述第一公共点(K(N))，源极连接所述第一直流低电压(VSS1)；
    第二十四晶体管(T24)，其栅极连接所述第N级水平扫描线(G(N))，漏极连接所述第二公共点(P(N))，源极连接所述第一直流低电压(VSS1)。
  5. 根据权利要求4所述的GOA电路，其中，所述第二十三晶体管(T23)的栅极连接所述N+1级下传信号(ST(N+1))；所述第二十四晶体管(T24)的栅极连接所述N级下传信号(ST(N))。
  6. 根据权利要求5所述的GOA电路，其中，所述第七晶体管(T7)的源极、第九晶体管(T9)的源极、第十七晶体管(T17)的源极及第十九晶体管(T19)的源极连接第二直流低电压(VSS2)。
  7. 根据权利要求6所述的移位寄存器，其中，所述下拉维持电路还包括：
    第二十五晶体管(T25)，其栅极连接所述第一公共点(K(N))，漏极连接所述N+1级下传信号(ST(N+1))，源极连接所述第二直流低电压(VSS2)；
    第二十六晶体管(T26)，其栅极连接所述第二公共点(P(N))，漏极连接所述N+1级下传信号(ST(N+1))，源极连接所述第二直流低电压(VSS2)；
    第二十七晶体管(T27)，其栅极连接所述第二公共点(P(N))，漏极连接所述N级下传信号(ST(N))，源极连接所述第二直流低电压(VSS2)；
    第二十八晶体管(T28)，其栅极连接所述第一公共点(K(N))，漏极连接所述N级下传信号(ST(N))，源极连接所述第二直流低电压(VSS2)。
  8. 一种GOA电路，用于液晶显示，其中，所述GOA电路包括多个GOA单元，每个所述GOA单元依次对显示区域的第N级水平扫描线(G(N))及第N+1级水平扫描线(G(N+1))充电，所述GOA单元包括N级上拉控制电路、N+1级上拉控制电路、N级上拉电路、N+1级上拉电路、N级下拉电路、N+1级下拉电路及下拉维持电路；
    其中，所述N级上拉电路及下拉维持电路分别与第N级栅极信号点(Q(N))和所述第N级水平扫描线(G(N))连接，所述N级上拉控制电路、N级下拉电路与所述第N级栅极信号点(Q(N))连接；
    所述N+1级上拉电路及下拉维持电路分别与第N+1级栅极信号点(Q(N+1))和所述第N+1级水平扫描线(G(N+1))连接，所述N+1级上拉控制电路、N+1级下拉电路与所述第N+1级栅极信号点(Q(N+1))连接；
    所述下拉维持电路在所述第N级水平扫描线(G(N))充电后维持所述第N级栅极信号点(Q(N))及所述第N级水平扫描线(G(N))的电位至低电位，在所述第N+1级水平扫描线(G(N+1))充电后维持所述第N+1级栅极信号点(Q(N+1))及所述第N级水平扫描线(G(N+1))的电位至低电位。
  9. 根据权利要求8所述的GOA电路，其中，所述下拉维持电路包括：
    第一晶体管(T1)，其栅极和漏极连接第一时钟信号(LC1)；
    第二晶体管(T2)，其栅极连接所述第一晶体管(T1)的源极，漏极连接所述第一时钟信号(LC1)，源极连接第一公共点(K(N))；
    第三晶体管(T3)，其栅极连接第二时钟信号(LC2)，漏极连接所述第一时钟信号(LC1)，源极连接所述第一公共点(K(N))；
    第四晶体管(T4)，其栅极和漏极连接所述第一公共点(K(N))；
    第五晶体管(T5)，其栅极连接所述第N级栅极信号点(Q(N))，漏极连接所述第一晶体管(T1)的源极和所述第四晶体管(T4)的源极，源极连接第一直流低电压(VSS1)；
    第六晶体管(T6)，其栅极连接所述第N+1级栅极信号点(Q(N+1))，漏极连接所述第一晶体管(T1)的源极，源极连接所述第一直流低电压(VSS1)；
    第七晶体管(T7)，其栅极连接所述第一公共点(K(N))，漏极连接所述第N+1级栅极信号点(Q(N+1))，源极连接所述第一直流低电压(VSS1)；
    第八晶体管(T8)，其栅极连接所述第一公共点(K(N))，漏极连接所述第N+1级水平扫描线(G(N+1))，源极连接所述第一直流低电压(VSS1)；
    第九晶体管(T9)，其栅极连接第二公共点(P(N))，漏极连接所述第N+1级栅极信号点(Q(N+1))，源极连接所述第一直流低电压(VSS1)；
    第十晶体管(T10)，其栅极连接所述第二公共点(P(N))，漏极连接所述第N+1级水平扫描线(G(N+1))，源极连接所述第一直流低电压(VSS1)；
    第十一晶体管(T11)，其栅极和漏极连接所述第二时钟信号(LC2)；
    第十二晶体管(T12)，其栅极连接所述第十一晶体管(T11)的源极，漏极连接所述第二时钟信号(LC2)，源极连接第二公共点(P(N))；
    第十三晶体管(T13)，其栅极连接第一时钟信号(LC1)，漏极连接所述第二时钟信号(LC2)，源极连接所述第二公共点(P(N))；
    第十四晶体管(T14)，其栅极和漏极连接所述第二公共点(P(N))；
    第十五晶体管(T15)，其栅极连接所述第N级栅极信号点(Q(N))，漏极连接所述第十一晶体管(T11)的源极和所述第十四晶体管(T14)的源极，源极连接第一直流低电压(VSS1)；
    第十六晶体管(T16)，其栅极连接所述第N+1级栅极信号点(Q(N+1))，漏极连接所述第十一晶体管(T11)的源极，源极连接所述第一直流低电压(VSS1)；
    第十七晶体管(T17)，其栅极连接所述第二公共点(P(N))，漏极连接所述第N级栅极信号点(Q(N))，源极连接所述第一直流低电压(VSS1)；
    第十八晶体管(T18)，其栅极连接所述第二公共点(P(N))，漏极连接所述第N级水平扫描线(G(N))，源极连接所述第一直流低电压(VSS1)；
    第十九晶体管(T19)，其栅极连接第一公共点(K(N))，漏极连接所述第N级栅极信号点(Q(N))，源极连接所述第一直流低电压(VSS1)；
    第二十晶体管(T20)，其栅极连接所述第一公共点(K(N))，漏极连接所述第N级水平扫描线(G(N))，源极连接所述第一直流低电压(VSS1)。
  10. 根据权利要求9所述的GOA电路，其中，所述下拉维持电路还包括：第二十二晶体管(T22)，其栅极连接所述第N+1级栅极信号点(Q(N+1))，漏极和源极分别连接所述第一公共点(K(N))和所述第二公共点(P(N))。
  11. 根据权利要求10所述的GOA电路，其中，所述GOA单元还包括第N级下传电路及第N+1级下传电路；
    所述第N级下传电路连接所述第N级栅极信号点(Q(N))，用于给所述第N+1级下传控制电路提供N级下传信号(ST(N))；
    所述第N+1级下传电路连接所述第N+1级栅极信号点(Q(N+1))，用于给下级GOA单元的第N+2级下传控制电路提供N+1级下传信号(ST(N+1))。
  12. 根据权利要求11所述的GOA电路，其中，所述下拉维持电路还包括：
    第二十三晶体管(T23)，其栅极连接所述第N+1级水平扫描线(G(N+1))，漏极连接所述第一公共点(K(N))，源极连接所述第一直流低电压(VSS1)；
    第二十四晶体管(T24)，其栅极连接所述第N级水平扫描线(G(N))，漏极连接所述第二公共点(P(N))，源极连接所述第一直流低电压(VSS1)。
  13. 根据权利要求12所述的GOA电路，其中，
    所述第二十三晶体管(T23)的栅极连接所述N+1级下传信号(ST(N+1))；
    所述第二十四晶体管(T24)的栅极连接所述N级下传信号(ST(N))。
  14. 根据权利要求13所述的GOA电路，其中，
    所述第七晶体管(T7)的源极、第九晶体管(T9)的源极、第十七晶体管(T17)的源极及第十九晶体管(T19)的源极连接第二直流低电压(VSS2)。
  15. 根据权利要求14所述的移位寄存器，其中，所述下拉维持电路还包括：
    第二十五晶体管(T25)，其栅极连接所述第一公共点(K(N))，漏极连接所述N+1级下传信号(ST(N+1))，源极连接所述第二直流低电压(VSS2)；
    第二十六晶体管(T26)，其栅极连接所述第二公共点(P(N))，漏极连接所述N+1级下传信号(ST(N+1))，源极连接所述第二直流低电压(VSS2)；
    第二十七晶体管(T27)，其栅极连接所述第二公共点(P(N))，漏极连接所述N级下传信号(ST(N))，源极连接所述第二直流低电压(VSS2)；
    第二十八晶体管(T28)，其栅极连接所述第一公共点(K(N))，漏极连接所述N级下传信号(ST(N))，源极连接所述第二直流低电压(VSS2)。
  16. 根据权利要求8所述的GOA电路，其中，所述GOA单元还包括重置电路；
    所述重置电路连接所述第N级栅极信号点(Q(N))、第N+1级栅极信号点(Q(N+1))及第一直流低电压(VSS1)，用于在接收到重置信号后下拉所述第N级栅极信号点(Q(N))及第N+1级栅极信号点(Q(N+1))的电位至低电位。
  17. 一种液晶显示器，其中，所述液晶显示器包括GOA电路，所述GOA电路包括多个GOA单元，每个所述GOA单元依次对显示区域的第N级水平扫描线(G(N))及第N+1级水平扫描线(G(N+1))充电，所述GOA单元包括N级上拉控制电路、N+1级上拉控制电路、N级上拉电路、N+1级上拉电路、N级下拉电路、N+1级下拉电路及下拉维持电路；
    其中，所述N级上拉电路及下拉维持电路分别与第N级栅极信号点(Q(N))和所述第N级水平扫描线(G(N))连接，所述N级上拉控制电路、N级下拉电路与所述第N级栅极信号点(Q(N))连接；
    所述N+1级上拉电路及下拉维持电路分别与第N+1级栅极信号点(Q(N+1))和所述第N+1级水平扫描线(G(N+1))连接，所述N+1级上拉控制电路、N+1级下拉电路与所述第N+1级栅极信号点(Q(N+1))连接；
    所述下拉维持电路在所述第N级水平扫描线(G(N))充电后维持所述第N级栅极信号点(Q(N))及所述第N级水平扫描线(G(N))的电位至低电位，在所述第N+1级水平扫描线(G(N+1))充电后维持所述第N+1级栅极信号点(Q(N+1))及所述第N级水平扫描线(G(N+1))的电位至低电位。
  18. 根据权利要求17所述的GOA电路，其中，所述下拉维持电路包括：
    第一晶体管(T1)，其栅极和漏极连接第一时钟信号(LC1)；
    第二晶体管(T2)，其栅极连接所述第一晶体管(T1)的源极，漏极连接所述第一时钟信号(LC1)，源极连接第一公共点(K(N))；
    第三晶体管(T3)，其栅极连接第二时钟信号(LC2)，漏极连接所述第一时钟信号(LC1)，源极连接所述第一公共点(K(N))；
    第四晶体管(T4)，其栅极和漏极连接所述第一公共点(K(N))；
    第五晶体管(T5)，其栅极连接所述第N级栅极信号点(Q(N))，漏极连接所述第一晶体管(T1)的源极和所述第四晶体管(T4)的源极，源极连接第一直流低电压(VSS1)；
    第六晶体管(T6)，其栅极连接所述第N+1级栅极信号点(Q(N+1))，漏极连接所述第一晶体管(T1)的源极，源极连接所述第一直流低电压(VSS1)；
    第七晶体管(T7)，其栅极连接所述第一公共点(K(N))，漏极连接所述第N+1级栅极信号点(Q(N+1))，源极连接所述第一直流低电压(VSS1)；
    第八晶体管(T8)，其栅极连接所述第一公共点(K(N))，漏极连接所述第N+1级水平扫描线(G(N+1))，源极连接所述第一直流低电压(VSS1)；
    第九晶体管(T9)，其栅极连接第二公共点(P(N))，漏极连接所述第N+1级栅极信号点(Q(N+1))，源极连接所述第一直流低电压(VSS1)；
    第十晶体管(T10)，其栅极连接所述第二公共点(P(N))，漏极连接所述第N+1级水平扫描线(G(N+1))，源极连接所述第一直流低电压(VSS1)；
    第十一晶体管(T11)，其栅极和漏极连接所述第二时钟信号(LC2)；
    第十二晶体管(T12)，其栅极连接所述第十一晶体管(T11)的源极，漏极连接所述第二时钟信号(LC2)，源极连接第二公共点(P(N))；
    第十三晶体管(T13)，其栅极连接第一时钟信号(LC1)，漏极连接所述第二时钟信号(LC2)，源极连接所述第二公共点(P(N))；
    第十四晶体管(T14)，其栅极和漏极连接所述第二公共点(P(N))；
    第十五晶体管(T15)，其栅极连接所述第N级栅极信号点(Q(N))，漏极连接所述第十一晶体管(T11)的源极和所述第十四晶体管(T14)的源极，源极连接第一直流低电压(VSS1)；
    第十六晶体管(T16)，其栅极连接所述第N+1级栅极信号点(Q(N+1))，漏极连接所述第十一晶体管(T11)的源极，源极连接所述第一直流低电压(VSS1)；
    第十七晶体管(T17)，其栅极连接所述第二公共点(P(N))，漏极连接所述第N级栅极信号点(Q(N))，源极连接所述第一直流低电压(VSS1)；
    第十八晶体管(T18)，其栅极连接所述第二公共点(P(N))，漏极连接所述第N级水平扫描线(G(N))，源极连接所述第一直流低电压(VSS1)；
    第十九晶体管(T19)，其栅极连接第一公共点(K(N))，漏极连接所述第N级栅极信号点(Q(N))，源极连接所述第一直流低电压(VSS1)；
    第二十晶体管(T20)，其栅极连接所述第一公共点(K(N))，漏极连接所述第N级水平扫描线(G(N))，源极连接所述第一直流低电压(VSS1)。
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