WO2015096245A1 - 自修复型栅极驱动电路 - Google Patents

自修复型栅极驱动电路 Download PDF

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Publication number
WO2015096245A1
WO2015096245A1 PCT/CN2014/070950 CN2014070950W WO2015096245A1 WO 2015096245 A1 WO2015096245 A1 WO 2015096245A1 CN 2014070950 W CN2014070950 W CN 2014070950W WO 2015096245 A1 WO2015096245 A1 WO 2015096245A1
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WIPO (PCT)
Prior art keywords
circuit
point
gate
pull
thin film
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PCT/CN2014/070950
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English (en)
French (fr)
Inventor
戴超
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US14/348,680 priority Critical patent/US9257083B2/en
Priority to KR1020167014126A priority patent/KR101818385B1/ko
Priority to GB1607190.4A priority patent/GB2534520B/en
Priority to JP2016541109A priority patent/JP6216071B2/ja
Publication of WO2015096245A1 publication Critical patent/WO2015096245A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared

Definitions

  • the present invention relates to the field of liquid crystal technology, and in particular, to a self-healing type bridge driving circuit. Background technique
  • Gate Driver On Array which uses the existing thin film transistor liquid crystal display array (Array) process to make the gate drive scan signal circuit on the array base. Extremely progressive scan drive.
  • the existing GOA circuit usually includes a plurality of cascaded GOA units, and each level of the GOA unit corresponds to driving a level one horizontal scanning line.
  • the main structure of the GOA unit includes a pull-up part, a pull-up control part, a transfer part, a key pull-down part, and Pull-down Holding Part and the Boast capacitor responsible for the potential rise.
  • the pull-up circuit is mainly responsible for outputting the clock signal (Ck) ck as a gate signal;
  • the pull-up control circuit is responsible for controlling the turn-on time of the pull-up circuit, and is generally connected to the downlink signal or the Gate signal transmitted from the GOA circuit of the previous stage;
  • the pull-down sustain circuit is responsible for maintaining the Gate output signal and the Gate signal of the pull-up circuit (commonly referred to as the Q point) in the off state (ie, Negative potential), usually two pull-down sustain modules alternate;
  • the bootstrap capacitor (C boast) is responsible for the secondary rise of the Q point, which is beneficial to the G ( N ) output of the pull-up circuit.
  • the pull-down sustaining portion of the GOA circuit is most susceptible to long-term stress (Stress), which causes some critically functioning thin film transistors (TFTs) to fail, thus increasing the risk of failure of the GOA circuit, and
  • Stress long-term stress
  • TFTs thin film transistors
  • the actual GOA circuit has a large delay capacity (RC) load, which will seriously affect the delay of the Gate waveform. Therefore, how to reduce the gate delay in the GO A circuit is also a common concern.
  • the pull-down sustain circuit is in the output of the Gate waveform. The quality of the off state during use will directly affect the delay of the Gate waveform (Delay). Summary of the invention
  • the present invention provides a self-healing type gate driving circuit including a plurality of cascaded GOA units, and controlling an Nth horizontal scanning line of a display area according to an Nth stage GOA unit control, the Nth stage
  • the GOA unit includes a pull-up control circuit, a pull-up circuit, a downlink circuit, a pull-down circuit, a bootstrap capacitor, a first pull-down sustain circuit, a second pull-down sustain circuit, and a bridge circuit;
  • the pull-up circuit, the pull-down circuit, the first The pull-down sustaining circuit, the second pull-down maintaining circuit and the bootstrap capacitor are respectively connected to the shed_pole signal point and the Nth horizontal scanning line, and the pull-up control circuit and the lower transmission circuit are respectively connected to the gate signal point, a bridge circuit is connected between the first pull-down maintaining circuit and the second pull-down maintaining circuit and is connected to the gate signal point;
  • the bridge circuit includes a first thin film transistor having a gate connected to the gate signal point, and a drain and a source connected to the first circuit point and the second circuit point, respectively;
  • the first pull-down maintaining circuit includes:
  • a second thin film transistor having a gate inputting a second clock signal, a drain and a source respectively inputting a first clock signal and connecting the second circuit point;
  • a third thin film transistor having a gate connected to a third circuit point, and a drain and a source respectively inputting a first clock signal and connecting the second circuit point;
  • a fourth thin film transistor having a gate inputting a first clock signal, a drain and a source respectively inputting a first clock signal and connecting the third circuit point;
  • a fifth thin film transistor having a tree pole connected to the second circuit point, and a drain and a source respectively connected to the second circuit point and the third circuit point;
  • a sixth thin film transistor having a cabinet connected to the gate signal point, and a drain and a source respectively connected to the second circuit point and an input DC low voltage;
  • a seventh thin film transistor having a gate connected to the second circuit point, and a drain and a source respectively inputting the DC low voltage and connecting the second level horizontal scan line;
  • An eighth thin film transistor having a gate connected to the second circuit point, wherein the drain and the source respectively input the DC low voltage and connect the gate signal point;
  • the second pull-down maintaining circuit includes:
  • a ninth thin film transistor having a gate inputting the first clock signal, a drain and a source respectively inputting the second clock signal and connecting the first circuit point;
  • a tenth thin film transistor having a gate connected to a fourth circuit point, and a drain and a source respectively inputting the second clock signal and connecting the first circuit point;
  • An eleventh thin film transistor having a gate inputting the second clock signal, a drain and a source respectively inputting the second clock signal and connecting the fourth circuit point;
  • a drain is connected to the first circuit point, and a drain and a source are respectively connected to the first circuit point and the fourth circuit point;
  • a thirteenth thin film transistor having a gate connected to the gate signal point, a drain and a source respectively connected to the fourth circuit point and inputting the DC low voltage;
  • a fourteenth thin film transistor having a gate connected to the first circuit point, and a drain and a source respectively inputting the DC low voltage and connecting the 13th stage 7
  • a fifteenth thin film transistor having a gate connected to the first circuit point, and a drain and a source respectively inputting the DC low voltage and connecting the gate signal point;
  • the low potential of the first clock signal and the second clock signal is less than the DC low voltage and the frequency is lower than a clock signal input to the pull-up circuit, and the first circuit point and the second circuit point are alternately placed High potential.
  • the pull-up control circuit comprises a sixteenth thin film transistor, wherein the shed-pole input is a downlink signal from the N-1th stage GOA unit, and the drain and the source are respectively connected to the N-1th horizontal scanning line and the ⁇ Extreme signal point.
  • the pull-up circuit includes a seventeenth thin film transistor having a gate connected to the gate signal point, and a drain and a source respectively inputting the clock signal and connecting the nth horizontal scan line.
  • the down circuit includes an eighteenth thin film transistor, the bridge is connected to the ⁇ -pole signal point, and the drain and the source respectively input the clock signal and output the downlink signal.
  • the pull-down circuit comprises: a nineteenth thin film transistor, the cabinet is connected to the second horizontal scanning line, the drain and the source are respectively connected to the second horizontal scanning line and the DC low voltage is input;
  • the thin film transistor has a gate connected to the ninth horizontal scan line, and a drain and a source respectively connected to the gate signal point and input the DC low voltage.
  • the duty cycle of the clock signal is 50%.
  • the first clock signal is input to the cascaded plurality of GOA units through a common metal line.
  • the second clock signal is input to the cascaded plurality of GOA units through a common metal line.
  • the DC low voltage is input to the cascaded plurality of GOA units through a common metal line.
  • the start signal is input into the pull-up control circuit of the first-stage GOA unit to And the pull-down circuit of the last stage GOA unit.
  • the present invention also provides a self-healing type drain driving circuit, comprising a plurality of cascaded GOA units, and controlling the Nth horizontal scanning line of the display area according to the Nth stage GOA unit control, the Nth stage GOA unit including the pull-up Control circuit, pull-up circuit, down-transmission circuit, pull-down circuit, bootstrap capacitor, first pull-down sustain circuit, second pull-down sustain circuit, and bridge circuit; the pull-up circuit, pull-down circuit, first pull-down sustain circuit, a second pull-down maintaining circuit and a bootstrap capacitor are respectively connected to the tree-pole signal point and the N-th horizontal scanning line, wherein the pull-up control circuit and the downlink circuit are respectively connected to the gate signal point, and the bridge circuit is connected to the first a pull-down maintaining circuit and a second pull-down maintaining circuit and connecting the cabinet signal point;
  • the bridge circuit includes a first thin film transistor having a gate connected to the gate signal point, and a drain and a source connected to the first circuit point and the second circuit point, respectively;
  • the first pull-down maintaining circuit includes:
  • a second thin film transistor having a gate inputting a second clock signal, a drain and a source respectively inputting a first clock signal and connecting the second circuit point;
  • a third thin film transistor having a gate connected to a third circuit point, and a drain and a source respectively inputting a first clock signal and connecting the second circuit point;
  • a fourth thin film transistor having a gate inputting a first clock signal, a drain and a source respectively inputting a first clock signal and connecting the third circuit point;
  • the cabinet is connected to the second circuit point, and the drain and the source are respectively connected to the second circuit point and the third circuit point;
  • a sixth thin film transistor having a gate connected to the gate signal point, a drain and a source respectively connected to the second circuit point and an input DC low voltage;
  • a seventh thin film transistor having a gate connected to the second circuit point, and a drain and a source respectively inputting the DC low voltage and connecting the nth horizontal scan line;
  • An eighth thin film transistor having a gate connected to the second circuit point, wherein the drain and the source respectively input the DC low voltage and connect the gate signal point;
  • the second pull-down maintaining circuit includes:
  • a ninth thin film transistor having a gate inputting the first clock signal, a drain and a source respectively inputting the second clock signal and connecting the first circuit point;
  • a tenth thin film transistor having a gate connected to a fourth circuit point, and a drain and a source respectively inputting the second clock signal and connecting the first circuit point;
  • An eleventh thin film transistor having a gate inputting the second clock signal, a drain and a source respectively inputting the second clock signal and connecting the fourth circuit point;
  • a twelfth thin film transistor having a gate connected to the first circuit point, and a drain and a source respectively connected The first circuit point and the fourth circuit point;
  • a thirteenth thin film transistor having a gate connected to the gate signal point, a drain and a source respectively connected to the fourth circuit point and inputting the DC low voltage;
  • a fourteenth thin film transistor having a gate connected to the first circuit point, and a drain and a source respectively inputting the DC low voltage and connecting the 13th horizontal scanning line;
  • a fifteenth thin film transistor having a gate connected to the first circuit point, and a drain and a source respectively inputting the DC low voltage and connecting the gate signal point;
  • the low potential of the first clock signal and the second clock signal is less than the DC low voltage and the frequency is lower than a clock signal input to the pull-up circuit, and the first circuit point and the second circuit point are alternately placed High potential
  • the pull-up control circuit comprises a sixteenth thin film transistor, wherein the shed-pole input is a downlink signal from the N-1th stage GOA unit, and the drain and the source are respectively connected to the N-1th horizontal scanning line and the ⁇ Pole signal point
  • the pull-up circuit includes a seventeenth thin film transistor having a gate connected to the drain signal point, and a drain and a source respectively inputting the clock signal and connecting the nth horizontal scan line;
  • the down-circuit circuit includes an eighteenth thin film transistor, the bridge is connected to the ⁇ -pole signal point, and the drain and the source respectively input the clock signal and output the downlink signal;
  • the pull-down circuit comprises: a nineteenth thin film transistor, wherein the drain is connected to the N+i level horizontal scan line, the drain and the source are respectively connected to the Nth horizontal scan line and the DC low voltage is input; a thin film transistor having a gate connected to the Nth level 1 horizontal scanning line, a drain and a source respectively connected to the gate signal point and inputting the DC low voltage;
  • the duty cycle of the clock signal is 50%.
  • the first clock signal is input to the cascaded plurality of GO A units through a common metal line.
  • the second clock signal is routed through the common metal wires into the cascaded plurality of GOA units.
  • the DC low voltage is input to the cascaded plurality of GOA units through a common metal line.
  • the start signal is input to the pull-up control circuit of the first stage GOA unit and the pull-down circuit of the last stage GOA unit.
  • the self-repairing gate driving circuit of the present invention can reduce the risk of failure of the pull-down sustaining circuit due to long-term operation of the process or the GOA circuit, and realize the self-repairing function of the circuit; Affects, ensures good Gate waveform output; improves the yield of GOA panel output and the long-term reliability of GQA circuit operation.
  • FIG. 1 is a circuit diagram of an embodiment of a self-healing type cabinet driving circuit of the present invention
  • Figure 2 is a waveform diagram of various input and output signals of the self-healing type ⁇ ⁇ pole driving circuit shown in the figure;
  • FIG. 3 is a schematic diagram of a circuit structure and inter-stage connection of a self-repairing gate driving circuit applied to a liquid crystal display panel according to the present invention
  • FIG. 4 is a schematic diagram of automatic repair of a self-repairing tree-pole driving circuit in a short-circuit state according to the present invention
  • Fig. 5 is a schematic view showing the automatic repair of the self-repairing gate drive circuit of the present invention in an open state. Specific. The way of travel.
  • the self-healing type gate driving circuit of the present invention comprises a plurality of cascaded GOA units, and the Nth horizontal scanning line G(N) of the display area is charged according to the Nth stage GOA unit control, and the Nth stage GOA unit includes a pull-up Control circuit 100, pull-up circuit 200, downlink circuit 300, pull-down circuit 400, bootstrap capacitor 500, first pull-down sustain circuit 600, second pull-down sustain circuit 700, and bridge circuit 800; pull-up circuit 200, pull-down The circuit 400 first-pull-up maintaining circuit 600, the second pull-down maintaining circuit 700, and the bootstrap capacitor 500 are respectively connected to the gate signal point Q (N) and the N-th horizontal scanning line G (N), and the pull-up control circuit 100 And the downlink circuit 300 is respectively connected to the gate signal point Q (N), the bridge circuit 800 is connected between the first pull-down maintaining circuit 600 and the second pull-down
  • the pull-up control circuit loo includes a thin film transistor ⁇ whose gate input is from the ⁇ -1 stage
  • the GOA unit's down signal ST(N 1), the drain and the source are connected to the Nth horizontal scanning line G (N-1 ) and the gate signal point Q (N), respectively.
  • the pull-up circuit 200 includes a thin film transistor T21 having a gate connected to the gate signal point Q (N), a drain and a source inputting a clock signal CK and a n-th horizontal scanning line G (N), respectively.
  • the down circuit 300 includes a thin film transistor T22 whose pole is connected to the gate signal point Q (N), and the drain and source respectively input the clock signal CK and the output down signal ST(N).
  • the pull-down circuit 400 includes: a thin film transistor T31 whose gate is connected to the N+1th horizontal scanning line G (N+1), and the drain and the source are respectively connected to the Nth horizontal scanning line G (N) and the input DC is low. Voltage VSS; thin film transistor T41, whose gate is connected to the first fl-fl level water
  • the flat scan line G (N+l) has a drain and a source connected to the gate signal point Q ( ⁇ ) and an input DC low voltage VSS, respectively.
  • the bridge circuit 800 includes a thin film transistor T55 having a gate connected to the gate signal point Q (N) and a drain and a source connected to the first circuit point K (N) and the second circuit point P (N), respectively.
  • the first pull-down maintaining circuit 600 includes: a thin film transistor T54 having a gate inputting a second clock signal LC2, a drain and a source respectively inputting a first clock signal LC1 and a second circuit point P(N); a thin film transistor T53, The drain is connected to the third circuit point S ( ⁇ ), the drain and the source respectively input the first clock signal LC1 and the second circuit point ⁇ ( ⁇ ); the thin film transistor T51, the gate of which inputs the first clock signal LC1, The drain and the source respectively input the first clock signal LC1 and the third circuit point S (N); the thin film transistor T56 has a gate connected to the second circuit point P (N ), and the drain and the source are respectively connected to the second a circuit point P (N ) and a third circuit point S (N); a thin film transistor T52 having a cabinet connected to the gate signal point Q ( ⁇ ), the drain and the source being respectively connected to the second circuit point ⁇ ( ⁇ ) and Input DC low voltage VSS; thin film transistor ⁇ 32,
  • the second pull-down maintaining circuit 700 includes: a thin film transistor ⁇ 64, the cabinet input of the first clock signal LC1, the drain and the source respectively input the second clock signal LC2 and the first circuit point ⁇ ( ⁇ ); the thin film transistor ⁇ 63, The gate is connected to the fourth circuit point ⁇ ( ⁇ ), the drain and the source are respectively input to the second clock signal LC2 and connected to the first circuit point ⁇ .
  • the thin film transistor T61 the gate input is the second The clock signal LC2, the drain and the source are respectively input to the second clock signal LC2 and connected to the fourth circuit point ⁇ ( ⁇ ); the thin film transistor ⁇ 66, the gate of which is connected to the first circuit point ⁇ ( ⁇ ), the drain and the source respectively Connecting a first circuit point ⁇ ( ⁇ ) and a fourth circuit point ⁇ ( ⁇ ); a thin film transistor ⁇ 62 having a gate connected to the pole signal point Q ( ⁇ ), a drain and a source respectively connected to the fourth circuit point ⁇ ( ⁇ ) and input DC low voltage VSS; thin film transistor ⁇ 33, its ⁇ -pole is connected to the first circuit point ⁇ ( ⁇ ), the drain and source are respectively input DC low voltage VSS and connected to the second level horizontal scanning line G ( ⁇ ); thin film transistor ⁇ 43, its cabinet connection Circuit point ⁇ ( ⁇ ), the drain and source electrodes are respectively input DC low voltage VSS and the connection point of the gate signal Q ( ⁇ ).
  • the low potentials of the first clock signal LC1 and the second clock signal LC2 are less than the DC low voltage VSS and the frequency is lower than the clock signal CK input to the pull-up circuit 200, and the first circuit is turned on ( ⁇ ) and The two circuit points ⁇ ( ⁇ ) alternately at high potential.
  • the bridge circuit 800 is mainly responsible for adjusting the two ends P(N) by bridging the TFT T55. And the potential of K(N), T55 Gate is connected to Q(N), Drain (drain) and Source (source) are connected to P(N) and K(N) respectively, and the gate of T55 is turned on during the action so that P(N) The potential of K(N) is close, and since the low potential of LC1 and LC2 is lower than VSS, the potential of p(N) and K(N) can be adjusted to be less than VSS during the action period. T32 of the (N) point, ⁇ 33, and ⁇ 42 of the pull-down Q point, and Vgs ⁇ 0 of ⁇ 43, can better prevent the G(N) point and the Q point leakage during the action period;
  • the first pull-down maintaining circuit 600 and the second pull-down maintaining circuit 700 adopt a symmetric design, and mainly realize the following functions: First, the first pull-down maintaining circuit 600 (the second pull-down maintaining circuit 700) is a large resistance off during the active period. In the state, the second pull-down maintaining circuit 700 (the first pull-down maintaining circuit 600) is an open state of the small resistor, and the bridge circuit 800 is in an open state of the small resistor, so that P(N) and K(N) are in a low potential state to ensure Q.
  • the G54 of the T54 is connected to the LC2, the Drain is connected to the LCI, the Source is connected to the P(N), the G64 of the T64 is connected to the LCI, the Drain is connected to the LC2, and the Source is connected to the L(N).
  • the two TFTs are called the Balance TFT. Adjust the resistance voltage division effect and the rapid discharge effect when the signal is switched; the Gate of T52 is connected to Q(N), Drain is connected to S(N), Source is connected to VSS, Gate of T62 is connected to Q(N), Drain is connected to T(N), Source is connected to VSS, so the main function of the two TFTs is to ensure that S(N) and ⁇ ( ⁇ ) are pulled down during the action.
  • the pull-down sustain circuit part introduces two TFTs T56 and T56 designed from the self-repairing diode (Diode), in which the Gate and Drain terminals of P56 are connected to P(N), and the source is terminated by S(N). ), T66's Gate and Drain are terminated by K(N;), and Source is terminated by T(N).
  • This design can prevent the risk of circuit failure caused by the failure of Bridge TFT T55.
  • the specific failure analysis will be carried out for the short circuit and open circuit of T55 in the circuit.
  • Figure 1 and subsequent Figure 2 primarily explain the normal operation of the circuit.
  • the invention uses the three-stage voltage division principle of the first pull-down maintaining circuit 600, the second pull-down maintaining circuit 700, and the bridge circuit 800 to design a new pull-down sustaining circuit portion of the GOA, which increases the high temperature stability of the pull-down maintaining circuit. Reliability and long-term operation reliability, and make full use of the role of low-frequency signals to achieve the switching of P(N) and K(N) and to pull P() and K(N) to lower potential during the action. Minimize the leakage of Q point and Gate. At the same time, one of P(N) and K(N) during low-activity period is close to the low potential of LC 1 and LC2.
  • T32/T42 or T33/T43 can be in the negative stress state (Stress) recovery state for half of the time, by adjusting the low frequency signal.
  • the low potential can control the potential of the negative stress, which can effectively reduce the failure of the pull-down maintenance circuit.
  • T56 and T66 The two self-repairing TFTs T56 and T66 introduced by the self-repairing circuit during normal operation do not affect the function of the circuit, and the normal conduction and reverse leakage of the Diode-designed TFT itself will not affect the operation of the circuit.
  • 3 ⁇ 4 can realize the mutual linkage of P(N)/K(N) and S(N)/T(N), and can quickly P(N)/K(N), S(N)/ during the action.
  • T() pulls to the low-potential shutdown state, which is beneficial to the output of Q(N) and G(N).
  • FIG. 2 it is a waveform diagram of various input and output signals of the self-repairing gate driving circuit shown in FIG. 1.
  • FIG. 1 is a GOA circuit of a group of clock control signals, and the duty ratio (Duty Ratio) is adopted. ) is a 50/50 high-frequency signal.
  • the clock signal of different duty ratio can be set to drive the GOA circuit according to the needs, or it can be displayed according to the liquid crystal display.
  • the STV signal is the start signal of the GOA circuit, so the STV signal is responsible for starting the first stage GOA circuit, and the start signal of the subsequent stage GOA circuit is the signal of the ST (N-1) of the downstream circuit part of the previous stage circuit.
  • the GOA driver circuit can be turned on step by step to realize the line scan driving;
  • CK and XCK are a set of high-frequency clock signals with the same high and low potential and opposite phase.
  • the pulse width, period and high and low potential of the clock signal mainly depend on the design of the Gate waveform of the liquid crystal display panel, so it is not necessarily used in practical liquid crystal display applications. It is a 50/50 Duty Ratio signal as shown in the figure, and sometimes a different number of clock signals are used to withstand the load required by different designs according to the design of the panel;
  • the G(N-1) signal is the output signal of the upper level Gate, and the ST(N-1) signal of the upper level GOA circuit is responsible for turning on the Nth stage GOA circuit, that is, the pull-up as shown in FIG. T11 of control circuit 100;
  • the waveform of the Q() node has two potential rises mainly for better opening of the upload circuit part, which is beneficial to the output of the Gate waveform, and Q(N) is also responsible for turning off the pull-down sustain circuit pair Q during the action of the Gate waveform output.
  • Q(N) and G(N) that is, S(N) and P(N) are simultaneously pulled to a low potential as shown in Fig. 2, and the negative potential during this period directly determines the Q() point.
  • the output waveform of Gate
  • G(N) is the Gate waveform generated by the GOA circuit of this level, which is consistent with the pulse width of the spatio-temporal control signal
  • ST(N) is the signal generated by the downlink part T22
  • G(N) is responsible for turning on the next level of GOA. Circuit
  • LC1 and LC2 are two sets of low-frequency clock signals that work alternately. They are mainly responsible for controlling the pull-down sustain circuit. On the one hand, the three-stage resistor divider principle is used to complete the replacement of P(N) and K(N). In this design, the positive and negative signals of this group of low-frequency clock signals are fully utilized.
  • the signals shown in Figure 2 are the signals when LC1 is high and LC2 is low.
  • LC1 and LC2 can be frequencies. Signals with the same opposite phase, if LC1 is low and LC2 is high, the opposite is true, S(N) and P(N) are at low potential, and T(N) and K.(N) are at high potential;
  • VSS is a DC negative voltage source.
  • the main purpose is to provide a stable shutdown state during Q-point and Gate non-output.
  • FIG. 3 it is a schematic diagram of a circuit structure and inter-stage connection of a self-repairing gate driving circuit of the present invention applied to a liquid crystal display panel.
  • the STV signal is connected to the first stage GO A unit, ⁇ 1 is responsible for opening the first stage circuit, and is also connected to the last stage Dummy level.
  • the T3 and T41 of the GO A are responsible for clearing the dummy before the start of a frame. (Dummy) level of charge at points Q and G;
  • the whole GOA driver circuit is divided into three parts, the first part is the start part of the initial stage, the second part is the normal transfer part of the intermediate stage, responsible for generating the Gate signal opened by this, and the third part is the dummy element of the last two stages (Dummy Level, responsible for pulling down the last two levels of Gate and dummy (Dummy level Gate does not accept any in-plane display area load;
  • the CK signal is connected to the pull-up portion T2 of the base-level GOA circuit and the ⁇ 22 of the downstream portion, and the XCK signal is connected to the pull-up portion T21 of the even-numbered GOA circuit and the ⁇ 22 of the downstream portion, each of which needs to be connected to the LC1.
  • the signals generated by LC2, VSS, G(N), and ST(N) are responsible for turning on the next level of the GOA circuit, which in turn loops to turn on the output that implements the Gate waveform.
  • FIG. 4 it is a schematic diagram of the automatic repair of the self-repairing gate driving circuit in the short-circuit state of the present invention, which is a circuit diagram after the short circuit (Short) of the bridge TFT T55 in the figure is assumed.
  • the pull-down sustain circuit part is divided into the circuit of the two-stage resistor divider by the original three-stage resistor divider.
  • the potentials of P(N) and K(N) are the same, and no longer follow the LC1 and LC2. Switching changes, the non-active period is always at a high potential, and this high potential depends on the size relationship of the TFTs for voltage division on both sides of P(N)/K(N);
  • T53 is turned off, which ensures that P(N)/K(N) is pulled low to low potential (close to LC2 Low potential) does not affect the normal output of the Q(N) and G(N) points; and because of the addition of two Diode designs, the TFTs T56 and T66 ensure that P(N)/K(N) does not occur.
  • High potential because when P(N)/K( ) is too high, T56 and T66 will be automatically turned on, and P(N)/K(N) at high potential will be pulled to and S(N)/ T (N) is about the same potential level.
  • the risk of the T55 short circuit can be effectively reduced, and the GOA circuit can still operate normally after the TFT functioning in the pull-down sustaining circuit is disabled.
  • FIG. 5 it is an automatic state of the self-repairing gate driving circuit in the open state of the present invention. Fixing and repairing the schematic intent map, is: false..
  • Set the schematic diagram intent of the electrical circuit after the bridge in the diagram ii is connected to the TTFFTT TT5555 breaking circuit ((OOppeenn)) Figure. .
  • the first one of the electrical circuit paths shown in FIG. 11 maintains the holding circuit 660000, and the second and second lower pull-down maintains the holding circuit 770000, and the bridge is bridged.
  • the electric circuit circuit 880000 is configured to form a three-three-segment type electric resistance resistor sub-pressure, and the lower pull-down dimension maintains the holding circuit, for example, if the TT5555 breaks the road, this new kind of self-new
  • the first pull-down of the self-repairing and repairing circuit circuit maintains the power circuit 660000, and the second and second pull-downs maintain the power circuit 770000.
  • the two-two-segment type electric resistance resistor sub-sub-circuit circuit for sub-dividing and pressing, can ensure that the normal normal working work of maintaining the holding circuit is ensured;
  • the potentials due to PP((NN)) and KK((NN)) are dependent on SS(()) and TT((NN)).
  • the electric potential is used to control the TT5533 and TT6633, and their electrical potential relationship is sufficient to satisfy the PP((NN)) ⁇ SS((NN)). .,, KK((NN)) ⁇ TT((NN)),, in this case, the DDiiooddee TTFFTT TT5566 and TT6666 from the self-repairing design are in the closed state. State; but but Dangdang
  • TT5555 When the road is broken, if there is no DDiiooddee TTFFTT TT5566 and TT6666 added to the self-repair, then PP((NN)) and KK..((NN )) will be in a suspended state, and his electric potential will be higher and higher during the period of use of the GGaattee output, no It is impossible to ensure that the TT4433//TT4422//TT3333//TT3322 is closed, and the output is affected by the influence of QQ ((NN)) and GG ((NN)). . In the self-repairing and repairing circuit shown in Figure 11, if TT5555 is disconnected, it will become the GGOOAA electric as shown in Figure 55. The circuit path, PP((NN)) and quasi-standard) is connected to SS((NN)) and TT((NN)) through the DDiiooddee connection, so that it is no longer no longer In a suspended state
  • the 1155 state especially especially when the GDAattee output is used during the period of use, when SS((NN)) and TT((NN)) are pulled down to low and low
  • the time-potential relationship is sufficient to satisfy the PP((NN))>>SS((NN)), KK((NN))>>TT((NN)), that Then the TT5566 and ⁇ 6666 of the design of the two-pole body are in the open state, and the self-automatic will pull the PP(()) and the ⁇ (( ⁇ )).
  • Low to low and low potential it is guaranteed that the energy can be closed and closed 4433// ⁇ 4422// ⁇ 3333// ⁇ 3322.
  • the 2200 state state and does not affect the positive normal operation of the circuit circuit, it is only after ⁇ 5555 OOppeenn or due to long time operation After TT5555, the value of the voltage is increased by the voltage increase and the increase is not very good.
  • the control potential of the PP ((NN)) and KK ((NN)) potential potential, this time PP ( NN))>>SS((NN)) ,, ⁇ (( ⁇ ))>> ⁇ (( ⁇ )) , , ⁇ 5566 and ⁇ 6666 are only in the open state to adjust the thrift (( ⁇ )) and ⁇ (( ⁇ )),, or alternatively, the compensation for the electric potential control system after the long time period is performed. .
  • GGaattee shuts off the non-non-active period PP ((NN)) and KK ((NN)) can be enough to be at a certain high and high potential, GGOOAA Circuit path
  • 3300 normal normal output and output function can not be affected by severe and severe impact, which can not only reduce the low-cost failure, Fengfeng insurance, but also It is also possible to increase the rate of good GGOOAA by a certain degree. .
  • the present invention is based on the design of a new and new three-three-stage segment-type partial pressure pressing principle to lower the maintenance of the holding circuit.
  • the needle is proposed for the risk of failure of the bridge-type TTFFTT for the manufacturing process and the actual operation of the electrical circuit. 1.
  • two Diode-designed TFTs are introduced for self-repair.
  • the main function is that if the bridge TFT works normally, it will not affect the basic operation of the original circuit, if the bridge TFT is in
  • the self-repairing TFT can function when a short circuit or an open circuit (especially an open circuit), that is, the potential of P(N)/K.(N) is adjusted by the potential of S(N)/T(N), so that the action period P(N)/K(N) can pull down and the non-active period P()/K(N) can work normally, so that it will not affect the output of the Gate waveform;
  • the self-healing Diode TFT introduced can realize the interaction between S(N)ZT(N) and P(N)/K(N) when the GOA is working normally, and there is no need to worry about the leakage of the TFT itself designed by Diode. Problem, because the leakage can be achieved by S(N)/TN) to adjust P(N)/K(N), which can make the P(N)/K(N) function better during the off state and reduce the delay of the Gate waveform output. ( Delay ) ;
  • the threshold voltage Vth of the TFTs connected to the Q point pulled down by the P(N)ZK( ) pull-down of the pull-down sustain circuit part is increased.
  • the new self-healing Diode TFT can compensate for the effect of the stress on the pull-down sustain circuit, thus keeping it working properly without affecting the Gate waveform output.
  • the self-repairing gate driving circuit of the invention can reduce the failure of the pull-down sustaining circuit due to the long-time operation of the process or the GOA circuit, and realize the self-repair function of the circuit; reduce the delay of the pull-down maintaining circuit to the output waveform of the Gate. Effect, ensuring good Gate waveform output; improving yield of GOA panel output and long-term reliability of GOA circuit operation.

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Abstract

一种自修复型栅极驱动电路，包括级联的多个GOA单元，第N级GOA单元包括上拉控制电路（100）、上拉电路（200）、下传电路（300）、下拉电路（400）、自举电容（500）、第一下拉维持电路（600）、第二下拉维持电路（700）及桥接电路（800）。该桥接电路（800）包括第一薄膜晶体管（T55），其栅极连接栅极信号点（Q（N）），漏极和源极分别连接第一电路点（K（N））和第二电路点（P（N））。工作时，该第一电路点和该第二电路点交替处于高电位。该驱动电路可降低由于制程或GOA电路长时间操作的原因造成的下拉维持电路的失效风险，实现电路自修复功能。

Description

本发明涉及液晶技术领域， 尤其涉及一种自修复型橋极驱动电路。 背景技术
阵列基板行驱动 （ Gate Driver On Array, 简称 GOA ) , 也就是利用现 有薄膜晶体管液晶显示器阵列 （Array ) 制程将橱极（Gate ) 行扫描驱动信 号电路制作在阵列基 £上， 实现对棚 ·极逐行扫描的驱动方式。
现有的 GOA电路， 通常包括级联的多个 GOA单元， 每一级 GOA单 元对应驱动一级水平扫描线。 GOA单元的主要结构包括上拉电路（Pull- up part ) , 上拉控制电 .路 ( Pull-up control part ) , 下传电 ( Transfer Part ) , 下拉电.路 ( Key Pull-down Part ) 和下拉维持电¾> ( Pull-down Holding Part ) ， 以及负责电位抬升的自举（ Boast ) 电容。
上拉电路主要负责将时钟信号 （Ck)ck )输出为柵极信号； 上拉控制电 路负责控制上拉电路的打开时间， 一般连接前面级 GOA 电路传递过来的 下传信号或者 Gate 信号； 下拉电路负责在第一时间将 Gate 拉低为低电 位， 即关闭 Gate信号； 下拉维持电路则负责将 Gate输出信号和上拉电路 的 Gate 信号 （通常称为 Q 点） 维持 （Holding ) 在关闭状态 （即负电 位） ， 通常有两个下拉维持模块交替作用； 自举电容（C boast )则负责 Q 点的二次抬升， 这样有利于上拉电路的 G ( N )输出。
1、 在实际应用中发现 GOA电路的下拉维持部分最容易受到长时间的 应力 （Stress )作用使得一些起关键作用的薄膜晶体管 （TFT ) 失效， 这样 就增加了 GOA电路的失效风险， 而且由于目前设计的 GOA电路不具备修 复功能使得发生这种风险的几率大大提高；
2、 GOA制程中由于电路级数多、 TFT数量大等原因， 很容易发生一 些 TFT短路或者断路的风险， 尤其是下拉维持电路部分如果发生此类现象 的话会使得下拉维持电路一直处于打开或者关闭状态， 从 影响 Gate波形 的输出， 再加上 GOA 电路的修复难度较高， 这样会严重影响液晶面板产 出的良率；
3、 实际 GOA 电路由于有很大的阻容 （RC ) 负载会产生严重影响 Gate波形的延迟现象， 因此如何降低 GO A电路中楣-极延迟（ Gate Delay ) 也是目前普遍比较关注的一个问题， 而下拉维持电路在 Gate波形输出的作 用期间的关闭状态的好坏会直接影响到 Gate波形的延迟（Delay ) 。 发明内容
因此， 本发明的目的在于提供一种自修复型柵极驱动电路， 降低由于 制程或 GOA 电路长时间操作的原因造成的下拉维持电路的失效風险， 实 现电路自修复功能。
为实现上述目的， 本发明提供了一种自修复型栅极驱动电路， 包括级 联的多个 GOA单元， 按照第 N级 GOA单元控制对显示区域第 N级水平 扫描线充电， 该第 N级 GOA单元包括上拉控制电路， 上拉电路， 下传电 路， 下拉电路， 自举电容， 第一下拉维持电路， 第二下拉维持电路， 及桥 接电路； 该上拉电路、 下拉电路、 第一下拉维持电路、 第二下拉维持电路 及自举电容分别与棚 _极信号点和该第 N级水平扫描线连接， 该上拉控制电 路和下传电路分别与该栅极信号点连接， 该桥接电路连接于该第一下拉维 持电路和第二下拉维持电路之间并且连接该栅极信号点；
该桥接电路包括第一薄膜晶体管， 其栅极连接该栅极信号点， 漏极和 源极分别连接第一电路点和第二电路点；
该第一下拉维持电路包括：
第二薄膜晶体管， 其栅极输入第二时钟信号， 漏极和源极分别输入第 一时钟信号和连接该第二电路点;
第三薄膜晶体管， 其柵极连接第三电路点， 漏极和源极分别输入第一 时钟信号和连接该第二电路点；
第四薄膜晶体管， 其柵极输入第一时钟信号， 漏极和源极分别输入第 一时钟信号和连接该第三电路点；
第五薄膜晶体管， 其树极连接该第二电路点， 漏极和源极分别连接该 第二电路点和该第三电路点;
第六薄膜晶体管， 其橱极连接该栅极信号点， 漏极和源极分别连接该 第二电路点和输入直流低电压；
第七薄膜晶体管， 其柵极连接该第二电路点， 漏极和源极分别输入该 直流低电压和连接该第 II级水平扫描线；
第八薄膜晶体管， 其栅极连接该第二电路点， 漏极和源极分别输入该 直流低电压和连接该柵极信号点；
该第二下拉维持电路包括：
第九薄膜晶体管， 其柵极输入该第一时钟信号， 漏极和源极分别输入 该第二时钟信号和连接该第一电路点； 第十薄膜晶体管， 其栅极连接第四电路点， 漏极和源极分别输入该第 二时钟信号和连接该第一电路点；
第十一薄膜晶体管， 其柵极输入该第二时钟信号， 漏极和源极分别输 入该第二时钟信号和连接该第四电路点；
第十二薄膜晶体管， 其楣 -极连接该第一电路点， 漏极和源极分别连接 该第一电路点和该第四电路点；
第十三薄膜晶体管， 其栅极连接该栅极信号点， 漏极和源极分别连接 该第四电路点和输入该直流低电压；
第十四薄膜晶体管， 其栅极连接该第一电路点， 漏极和源极分别输入 该直流低电压和连接该第 13级 7
第十五薄膜晶体管， 其栅极连接该第一电路点， 漏极和源极分别输入 该直流低电压和连接该栅极信号点；
工作时， 该第一时钟信号和该第二时钟信号的低电位小于该直流低电 压且频率低于输入该上拉电路的时钟信号， 并且使该第一电路点和该第二 电路点交替处于高电位。
其中， 该上拉控制电路包括第十六薄膜晶体管， 其棚-极输入来自第 N- 1 级 GOA单元的下传信号， 漏极和源极分别连接第 N- 1 级水平扫描线和 该槲极信号点。
其中， 该上拉电路包括第十七薄膜晶体管， 其柵极连接该柵极信号 点， 漏极和源极分别输入该时钟信号和连接该第 n级水平扫描线。
其中， 该下传电路包括第十八薄膜晶体管， 其橋极连接该楣-极信号 点， 漏极和源极分别输入该时钟信号和输出下传信号。
其中， 该下拉电路包括： 第十九薄膜晶体管， 其櫥极连接第 Ν·Η级水 平扫描线， 漏极和源极分别连接该第 Ν 级水平扫描线和输入该直流低电 压； 第二十薄膜晶体管， 其柵极连接该第 Ν十 1级水平扫描线， 漏极和源极 分别连接该栅极信号点和输入该直流低电压。
其中， 该时钟信号的占空比为 50%。
其中， 该第一时钟信号通过公共的金属线输入所述级联的多个 GOA 单元。
其中， 该第二时钟信号通过公共的金属线输入所述级联的多个 GOA 单元。
其中， 该直流低电压通过公共的金属线输入所述級联的多个 GOA单 元。
其中， 工作时， 启动信号输入第一级 GOA单元的上拉控制电路中以 及.最后一级 GOA单元的下拉电路中。
本发明还提供一种自修复型槲极驱动电路， 包括级联的多个 GOA 单 元， 按照第 N级 GOA单元控制对显示区域第 N级水平扫描线充电， 该第 N级 GOA单元包括上拉控制电路， 上拉电路， 下传电路， 下拉电路， 自 举电容， 第一下拉维持电路， 第二下拉维持电路， 及桥接电路； 该上拉电 路， 下拉电路、 第一下拉维持电路、 第二下拉维持电路及自举电容分别与 树极信号点和该第 N級水平扫描线连接， 该上拉控制电路和下传电路分别 与该栅极信号点连接， 该桥接电路连接于该第一下拉维持电路和第二下拉 维持电路之间并且连接该櫥极信号点；
该桥接电路包括第一薄膜晶体管， 其柵极连接该柵极信号点， 漏极和 源极分别连接第一电路点和第二电路点；
该第一下拉维持电路包括：
第二薄膜晶体管， 其栅极输入第二时钟信号， 漏极和源极分别输入第 一时钟信号和连接该第二电路点；
第三薄膜晶体管， 其柵极连接第三电路点， 漏极和源极分别输入第一 时钟信号和连接该第二电路点；
第四薄膜晶体管， 其柵极输入第一时钟信号， 漏极和源极分别输入第 一时钟信号和连接该第三电路点；
第五薄膜晶体管， 其橱极连接该第二电路点， 漏极和源极分别连接该 第二电路点和该第三电路点;
第六薄膜晶体管， 其柵极连接该柵极信号点， 漏极和源极分别连接该 第二电路点和输入直流低电压；
第七薄膜晶体管， 其柵极连接该第二电路点， 漏极和源极分别输入该 直流低电压和连接该第 n级水平扫描线;
第八薄膜晶体管， 其柵极连接该第二电路点， 漏极和源极分别输入该 直流低电压和连接该柵极信号点；
该第二下拉维持电路包括：
第九薄膜晶体管， 其柵极输入该第一时钟信号， 漏极和源极分别输入 该第二时钟信号和连接该第一电路点；
第十薄膜晶体管， 其栅极连接第四电路点， 漏极和源极分别输入该第 二时钟信号和连接该第一电路点;
第十一薄膜晶体管， 其柵极输入该第二时钟信号， 漏极和源极分别输 入该第二时钟信号和连接该第四电路点；
第十二薄膜晶体管， 其柵极连接该第一电路点， 漏极和源极分别连接 该第一电路点和该第四电路点；
第十三薄膜晶体管， 其栅极连接该栅极信号点， 漏极和源极分别连接 该第四电路点和输入该直流低电压；
第十四薄膜晶体管， 其栅极连接该第一电路点， 漏极和源极分别输入 该直流低电压和连接该第 13级水平扫描线;
第十五薄膜晶体管， 其柵极连接该第一电路点， 漏极和源极分别输入 该直流低电压和连接该櫥极信号点；
工作时， 该第一时钟信号和该第二时钟信号的低电位小于该直流低电 压且频率低于输入该上拉电路的时钟信号， 并且使该第一电路点和该第二 电路点交替处于高电位；
其中， 该上拉控制电路包括第十六薄膜晶体管， 其棚-极输入来自第 N- 1 级 GOA单元的下传信号， 漏极和源极分别连接第 N- 1 级水平扫描线和 该槲极信号点；
其中， 该上拉电路包括第十七薄膜晶体管， 其栅极连接该槲极信号 点， 漏极和源极分别输入该时钟信号和连接该第 n级水平扫描线；
其中， 该下传电路包括第十八薄膜晶体管， 其橋极连接该楣-极信号 点， 漏极和源极分别输入该时钟信号和输出下传信号；
其中， 该下拉电路包括： 第十九薄膜晶体管， 其櫪极连接第 N+i级水 平扫描线， 漏极和源极分别连接该第 N 级水平扫描线和输入该直流低电 压； 第二十薄膜晶体管， 其柵极连接该第 N十 1级水平扫描线， 漏极和源极 分别连接该栅极信号点和输入该直流低电压；
其中， 该时钟信号的占空比为 50%。
该第一时钟信号通过公共的金属线输入所述级联的多个 GO A单元。 该第二时钟信号通过公共的金属线 入所述级联的多个 GOA单元。 该直流低电压通过公共的金属线输入所述级联的多个 GOA单元。
工作时， 启动信号输入第一级 GOA 单元的上拉控制电路中以及最后 一级 GOA单元的下拉电路中。
综上， 本发明的自修复型柵极驱动电路可以降低由于制程或 GOA 电 路长时间操作的原因造成的下拉维持电路的失效风险， 实现电路自修复功 能； 降低下拉维持电路对 Gate输出波形延迟的影响， 确保良好的 Gate波 形输出； 提高 GOA面板产出的良率和 GQA电路操作的长时闾的信赖性。 附图说明
下面结合附图， 通过对本发明的具体实施方式详细描述， 将使本发明 的技术方案及其弛有益效果显而易见„
附图中，
图 1为本发明的自修复型櫥极驱动电路一实施例的电路图；
图 2为图 所示的自修复型楣 ·极驱动电路的各种输入和输出信号的波 形图；
图 3 为本发明的自修复型柵极驱动电路应用于液晶显示器面板中的电 路架构和级间连接示意图；
图 4为本发明的自修复型树极驱动电路在短路状态下的自动修复示意 图；
图 5 为本发明的自修复型柵极驱动电路在断路状态下的自动修复示意 图。 具体.实旅方式.
参见图 1， 其为本发明的自修复型栅极驱动电路一实施例的电路图。 本发明的自修复型柵极驱动电路包括级联的多个 GOA单元， 按照第 N级 GOA单元控制对显示区域第 N级水平扫描线 G (N) 充电， 该第 N 级 GOA单元包括上拉控制电路 100, 上拉电路 200, 下传电路 300, 下拉电 路 400， 自举电容 500, 第一下拉维持电路 600， 第二下拉维持电路 700, 及桥接电路 800; 该上拉电路 200、 下拉电路 400 第- 下拉维持电路 600、 第二下拉维持电路 700及自举电容 500分别与栅极信号点 Q (N)和 该第 N级水平扫描线 G (N)连接， 该上拉控制电路 100和下传电路 300 分别与该栅极信号点 Q (N)连接， 该桥接电路 800连接于该第一下拉维 持电路 600 和第二下拉维持电路 700 之间并且连接该栅极信号点 Q (N) 。 其中第一下拉维持电路 600, 第二下拉维持电路 700， 及桥接电路 800构成三段式电阻分压设.计。
上拉控制电路 loo 包括薄膜晶体管 τη， 其柵极输入来自第 Ν- 1 级
GOA单元的下传信号 ST(N 1), 漏极和源极分别连接第 N 级水平扫描线 G (N-1 )和该栅极信号点 Q (N) 。 上拉电路 200包括薄膜晶体管 T21, 其棚极连接该柵极信号点 Q (N) , 漏极和源极分别输入时钟信号 CK和 连接第 n级水平扫描线 G (N) 。 下传电路 300 包括薄膜晶体管 T22, 其 极极连接櫥极信号点 Q (N) , 漏极和源极分别输入时钟信号 CK 和输出 下传信号 ST(N)。 下拉电路 400 包括： 薄膜晶体管 T31, 其栅极连接第 N+1级水平扫描线 G ( N+1 ) ， 漏:极和源极分别连接第 N级水平扫描线 G (N)和输入直流低电压 VSS; 薄膜晶体管 T41, 其栅极连接第 Ν-fl级水 平扫描线 G (N+l ) , 漏极和源极分别连接该栅极信号点 Q (Ν)和输入 该直流低电压 VSS。
桥接电路 800 包括薄膜晶体管 T55, 其栅极连接栅极信号点 Q (N) , 漏极和源极分别连接第一电路点 K (N)和第二电路点 P (N) 。
第一下拉维持电路 600 包括： 薄膜晶体管 T54, 其柵极输入第二时钟 信号 LC2, 漏极和源极分别输入第一时钟信号 LC1 和连接第二电路点 P (N) ； 薄膜晶体管 T53， 其槲极连接第三电路点 S (Ν) , 漏极和源极分 别输入第一时钟信号 LC1 和连接第二电路点 Ρ (Ν) ； 薄膜晶体管 T51, 其栅极输入第一时钟信号 LC1， 漏极和源极分别输入第一时钟信号 LC1和 连接第三电路点 S (N) ； 薄膜晶体管 T56, 其柵极连接第二电路点 P (N ) ， 漏极和源极分别连接该第二电路点 P (N ) 和第三电路点 S (N) ； 薄膜晶体管 T52， 其櫥极连接该柵极信号点 Q (Ν) , 漏极和源极 分别连接第二电路点 Ρ (Ν)和输入直流低电压 VSS; 薄膜晶体管 Τ32， 其栅极连接第二电路点 Ρ (Ν) ， 漏极和源极分别输该直流低电压 VSS和 连.接第 Ώ级水平扫描线 G (Ν) ； 薄膜晶体管 Τ42, 其櫥极连接第二电路 点 Ρ ( Ν ) , 漏极和源极分别输入直流低电压 VSS 和连接柵极信号点 Q (Ν) 。
第二下拉维持电路 700 包括： 薄膜晶体管 Τ64, 其櫥极输入第一时钟 信号 LC1, 漏极和源极分别输入第二时钟信号 LC2和连接该第一电路点 Κ (Ή ) ； 薄膜晶体管 Τ63, 其栅极连.接第四电路点 Τ (Ν) , 漏极和源极分 别输入第二时钟信号 LC2 和连接该第一电路点 Κ. (Ν ) ； 薄膜晶体管 T61, 其柵极输入第二时钟信号 LC2, 漏极和源极分别输入第二时钟信号 LC2 和连接第四电路点 Τ (Ν) ； 薄膜晶体管 Τ66, 其柵极连接第一电路 点 Κ (Ν ) ， 漏极和源极分别连接第一电路点 Κ ( Ν ) 和第四电路点 Τ (Ή ) ； 薄膜晶体管 Τ62, 其柵极连接该极极信号点 Q (Ν) ， 漏极和源极 分别连.接第四电路点 Τ (Ν)和输入直流低电压 VSS; 薄膜晶体管 Τ33， 其楣-极连接第一电路点 Κ (Ν) ， 漏极和源极分别输入直流低电压 VSS和 连接第 II级水平扫描线 G (Ν) ； 薄膜晶体管 Τ43， 其櫥极连接第一电路 点 Κ (Ν) , 漏极和源极分别输入直流低电压 VSS和连接该栅极信号点 Q (Ν) 。
工作时， 第一时钟信号 LC1 和第二时钟信号 LC2 的低电位小于该直 流低电压 VSS且频率低于输入该上拉电路 200的时钟信号 CK, 并且使第 一电路点 Κ (Ν)和第二电路点 Ρ (Ν) 交替处于高电位。
桥接电路 800主要通过桥接 ( Bridge ) TFT T55来负责调节两端 P(N) 和 K(N)的电位， T55 Gate接 Q(N)， Drain (漏极）和 Source (源极）分别 接 P(N)和 K(N)， 作用期间 T55的 Gate打开使得 P(N)和 K(N)的电位相近 处于关闭状态, 且由于低频信号 LC1 和 LC2的低电位小于 VSS, 这样可 以调节作用期间 p(N)和 K(N)的电位小于 VSS , 从, ¾保证下拉 G(N)点的 T32、 Τ33和下拉 Q点的 Τ42、 Τ43的 Vgs<0, 能够更好的防止作用期间的 G(N)点和 Q点漏电；
第一下拉维持电路 600 和第二下拉维持电路 700 采用的是对称式设 计， 主要实现以下功能： 一是作用期间第一下拉维持电路 600 (第二下拉 维持电路 700 )是大电阻的关闭状态， 第二下拉维持电路 700 (第一下拉 维持电路 600 ) 就是小电阻的打开状态， 桥接电路 800处于小电阻的打开 状态， 使得 P(N)和 K(N)处于低电位状态确保 Q(N)点抬升和 Gate输出； 二 是非作用期间第一下拉维持电路 600和第二下拉维持电路 700均处于小电 阻的打开状态， 而桥接电路 800处于大电阻的关闭状态， 这样实现 P( )和 K(N)的高低电位和交替作用；
其中 T54的 Gate接 LC2， Drain接 LCI , Source接 P(N)， T64的 Gate 接 LCI , Drain 接 LC2 , Source 接 L(N) , 这两颗 TFT 称之为平衡 ( Balance ) TFT 主要起到调节电阻分压作用和信号切换时的迅速放电作 用； T52 的 Gate接 Q(N)， Drain接 S(N), Source接 VSS , T62 的 Gate接 Q(N), Drain接 T(N) , Source接 VSS， 这样两颗 TFT的主要作用是保证在 作用期间拉低 S(N)和 Τ(Ν)。
在该电路设计中下拉维持电路部分引入了两颗起自修复作用的二极体 ( Diode )设计的 TFT T56和 T56 , 其中 T56的 Gate和 Drain端接 P(N) , Source端接 S(N)， T66的 Gate和 Drain端接 K(N；)， Source端接 T(N)。 这 祥的设计可以防止 Bridge TFT T55失效引发的电路失效的风险， 后面将会 针对电路中 T55的短路和断路两种情况进行具体的失效分析。 附图 1和随 后的附图 2主要解释该电路正常操作的情况。
本发明釆用第一下拉维持电路 600， 第二下拉维持电路 700， 及桥接 电路 800的三段式分压原理设计了全新的 GOA的下拉维持电路部分， 这 样增加了下拉维持电路的高温稳定性和长时间操作的可靠性， 且充分利 用了低频信号的作用实现了 P(N)和 K(N)的切换以及使得作用期间 P( )和 K(N)拉到更低的电位确保作用最大限度的降低 Q点和 Gate的漏电， 同时 非作用期间 P(N)和 K(N)其中一个处于低电位时基本接近 LC 1和 LC2的低 电位， 由于 LC1 和 LC2的低电位小于 VSS， 那么 T32/T42或者 T33/T43 能够有一半的时间处于负压应力 （Stress )恢复状态， 通过调节低频信号的 低电位可以控制负压应力 ( Stress ) 的电位， 这样可以有效低降低下拉维持 电路的失效凤险„
该自修复电路在正常运作时引入的两颗自修复功能的 TFT T56和 T66 并不影响电路的功能， 而且 Diode设计的 TFT本身的正常导通和反向漏电 也不会影响电路的操作， 反 ,¾可以实现 P(N)/K(N)和 S(N)/T(N)的相互联 动， 能够在作用期间更快地将 P(N)/K(N)、 S(N)/T( )拉到低电位的关闭状 态， 有利于 Q(N)和 G(N)的输出„
参见图 2 , 其为图 1 所示的自修复型栅极驱动电路的各种输入和输出 信号的波形图； 其中示意的是一组时钟控制信号的 GOA 电路， 采用的占 空比 （Duty Ratio )为 50/50的高频信号， 在实际液晶显示器中可以根据需 要设定不同占空比的时钟信号进行 GOA 电路的驱动， 也可以根据液晶显
STV信号为 GOA 电路的启动信号， 所以 STV信号负责启动第一级 GOA电路， 而后面的级 GOA电.路的启动信号由前面一级电路的下传电路 部分的 ST(N-1)的信号负责产生， 这样就可以逐级打开 GOA驱动电路, 实 现行扫描驱动；
CK和 XCK为一组高低电位相同、 相位相反的高频时钟信号， 时钟信 号的脉沖宽度、 周期以及高低电位主要取决于液晶显示面板的 Gate波形的 设计需要， 因此在实际液晶显示器应用中不一定是如图所示的 Duty Ratio 为 50/50 的信号， 而且有时候根据面板设计的需要会采用不同数量的时钟 信号来承受不同设计需要的负载；
G(N-1)信号为上一级 Gate 的输出信号， 同时和上一级 GOA 电路的 ST(N-1)信号负责开启第 N级的 GOA电路， 也就是如图 1所示的上拉控制 电路 100的 T11 ;
Q( )节点的波形存在两次的电位抬升主要是为了更好的打开上传电路 部分， 有利于 Gate波形的输出， 而且 Q(N)还负责在 Gate波形输出的作用 期间关闭下拉维持电路对 Q(N)和 G(N)的影响， 也就是如图 2 所示的将 S(N)和 P(N)同时拉到一个低电位， 而这一期间的负电位直接决定了 Q( ) 点和 Gate的输出波形；
G(N)为本级 GOA电路产生的 Gate 波形, 与时空控制信号的脉冲宽度 一致， ST(N)则为下传部分 T22产生的信号， 和 G(N)—起负责开启下一级 GOA电路；
LC1和 LC2是两组交替工作的低频时钟信号， 主要负责控制下拉维持 电路部分， 一方面利用三段式电阻分压原理完成 P(N)和 K(N)的交替工 作， 在这祥的设计中充分发挥了这一组低频时钟信号的正负信号的作用， 图 2所示的信号是 LC1 为高电位、 LC2为低电位时的信号， LC1 和 LC2 可以为频率相同相位相反的信号， 如果 LC1为低电位、 LC2为高电位时则 刚好相反， S(N)和 P(N)处于低电位， T(N)和 K.(N)处于高电位；
VSS为直流负压源， 主-要作用是提供 Q点和 Gate非输出期间有一个 稳定的关闭状态。
参见图 3， 其为本发明的自修复型栅极驱动电路实际应用于液晶显示 器面板中的电路架构和級间连接示意图。 其中 STV信号除了连接到第一级 GO A 单元的 ΤΊ 1 负责打开第一级电路， 还连接到最后一级哑元 ( Dummy ) 级 GO A 的 T3 和 T41 负责在一帧画面开始前清除啞 t ( Dummy )级的 Q点和 G点的电荷；
整个 GOA驱动电路分为三部分， 第一部分是初始级的启动部分， 第 二部分是中间级的正常传递部分， 负责产生以此打开的 Gate信号， 第三部 分是最后两级的哑元 （Dummy ) 级， 负责拉低最后两级的 Gate 且哑元 ( Dummy 级的 Gate不接任何面内显示区域的负载；
CK信号连接到基数级 GOA电路的上拉部分 T2】和下传部分的 Τ22, XCK信号连接到偶数级 GOA电路的上拉部分 T21和下传部分的 Τ22, 每 一级都需要连接到 LC1、 LC2、 VSS , G(N)和 ST(N)产生的信号负责打开 下一级 GOA电路， 这样依次循环传递打开实现 Gate波形的输出。
参见图 4， 其为本发明的自修复型柵极驱动电路在短路状态下的自动 修复示意图， 是假设图 】 中的桥接 ( Bridge ) TFT T55短路（Short )之后 的电路示意图。 T55 短路之后下拉维持电路部分由原来的三段式电阻分压 变成二段式电阻分压的电路， 这时候 P(N)和 K(N)的电位相同， 不再随着 LC1、 LC2 的切换而变化， 非作用期间一直处于高电位， 这一高电位取决 于 P(N)/K(N)两边的分压用的 TFT的尺寸关系；
作用期间当 LC1 处于高电位时， 由于 S(N)依然能够被 T52下拉到低 电位使得 T53 处于关闭状态， 这样能够确保 P(N)/K(N)被拉低到低电位 (接近 LC2的低电位） ， 不会影响到 Q(N)点和 G(N)点的正常输出； 而且 由于增加了两个 Diode设计的 TFT T56和 T66能够确保 P(N)/K(N)不产生 过高的电位， 因为当 P(N)/K( )电位过高时， T56和 T66会自动处于打开 状态， 把处于高电位的 P(N)/K(N)拉到和 S(N)/T(N)差不多的电位水平。
通过这样的自修复设计能够有效地降低 T55短路带来的风险， 确保下 拉维持电路中起关键作用的 TFT失效后 GOA电路依然能够正常工作。
参见图 5， 其为本发明的自修复型柵极驱动电路在断路状态下的自动 修修复复示示意意图图，， 是是..假假..设设图图 ii中中的的桥桥接接 TTFFTT TT5555断断路路（（OOppeenn ))之之后后的的电电路路示示意意 图图。。 图图 11 所所示示的的电电路路中中第第一一下下拉拉维维持持电电路路 660000,, 第第二二下下拉拉维维持持电电路路 770000，， 及及桥桥接接电电路路 880000构构成成三三段段式式电电阻阻分分压压的的下下拉拉维维持持电电路路,, 如如果果 TT5555 断断路路，， 这这 种种新新的的自自修修复复电电路路的的第第一一下下拉拉维维持持电电路路 660000，， 第第二二下下拉拉维维持持电电路路 770000依依然然 55 可可以以构构成成独独立立的的二二段段式式电电阻阻分分压压的的子子电电路路，， 能能够够确确保保下下拉拉维维持持电电路路的的正正常常 工工作作；；
正正常常情情况况下下，， 由由于于 PP((NN))和和 KK((NN))的的电电位位是是依依靠靠 SS(( ))和和 TT((NN))的的电电位位来来控控 制制 TT5533和和 TT6633 来来得得到到的的，， 他他们们的的电电位位关关系系满满足足 PP((NN))<<SS((NN))..,, KK((NN))<<TT((NN)),, 这这种种情情况况下下自自修修复复设设计计的的 DDiiooddee TTFFTT TT5566和和 TT6666 处处于于关关闭闭状状态态;; 但但是是当当
1100 TT5555 断断路路时时候候，， 如如果果没没有有加加入入自自修修复复的的 DDiiooddee TTFFTT TT5566和和 TT6666,, 那那么么 PP((NN)) 和和 KK..((NN))就就会会处处于于悬悬空空状状态态，， 他他钔钔的的电电位位在在 GGaattee 输输出出的的作作用用期期间间会会比比较较 高高，， 无无法法确确保保关关闭闭 TT4433//TT4422//TT3333//TT3322,, 从从而而影影响响 QQ((NN))和和 GG((NN))输输出出。。 在在图图 11 所所示示的的自自修修复复电电路路中中，， 如如果果 TT5555 断断路路之之后后就就会会成成为为图图 55 所所示示的的 GGOOAA 电电 路路，， PP((NN))和和準準))通通过过 DDiiooddee连连接接到到 SS((NN))和和 TT((NN)),, 这这样样就就不不再再处处于于悬悬空空状状
1155 态态，， 尤尤其其是是当当 GGaattee输输出出的的作作用用期期间间，， 当当 SS((NN))和和 TT((NN))被被下下拉拉到到低低电电位位时时,, 这这时时电电位位关关系系满满足足 PP((NN))>>SS((NN))、、 KK((NN))>>TT((NN)),, 那那么么二二极极体体设设计计的的 TT5566、、 ΤΤ6666 就就处处于于打打开开状状态态，， 自自动动将将 PP(( ))和和 ΚΚ((ΝΝ))拉拉低低到到低低电电位位，， 确确保保能能够够关关闭闭 ΤΤ4433//ΤΤ4422//ΤΤ3333//ΤΤ3322。。
因因此此，， 如如上上所所述述，， 在在正正常常情情况况下下，， 自自修修复复功功能能的的 ΤΤ5566和和 ΤΤ6666处处于于关关闭闭
2200 状状态态，， 并并不不影影响响电电路路的的正正常常运运作作，， 它它只只在在 ΤΤ5555 OOppeenn或或者者由由于于长长时时间间操操作作 之之后后 TT5555 闹闹值值电电压压增增加加无无法法很很好好的的控控制制 PP((NN))和和 KK((NN))的的电电位位，， 这这时时 PP((NN))>>SS((NN)) ,, ΚΚ((ΝΝ))>>ΤΤ((ΝΝ)) ,, ΤΤ5566 和和 ΤΤ6666 才才处处于于打打开开状状态态来来调调节节 ΡΡ((ΝΝ))和和 ΚΚ((ΝΝ)),, 或或者者对对长长时时间间搡搡作作后后的的电电位位控控制制进进行行补补偿偿作作用用。。
这这样样的的设设计计不不仅仅确确保保 ΤΤ5555短短路路和和断断路路之之后后 GGOOAA电电路路能能够够正正常常工工作作，，
2255 而而且且由由于于自自修修复复设设计计 DDiiooddee TTFFTT 受受到到的的应应力力 (( SSttrreessss ))作作用用远远远远小小于于其其他他 TTFFTT，， 因因此此这这种种设设计计还还可可以以补补偿偿下下拉拉维维持持电电路路中中三三段段式式分分压压用用的的桥桥式式 TTFFTT TT5555 长长时时间间应应力力 (( SSttrreessss ))之之后后阈阈值值电电压压增增加加对对 PP((NN))和和 KK((NN))的的不不良良影影响响。。 只只要要能能够够确确保保 GGaattee 输输出出的的作作用用 PP(( ))和和 KK((NN))能能够够很很好好的的下下拉拉到到低低电电位位、、 GGaattee关关闭闭的的非非作作用用期期间间 PP((NN))和和 KK((NN))能能够够处处于于一一定定的的高高电电位位，， GGOOAA电电路路的的
3300 正正常常输输出出功功能能就就不不会会受受到到严严重重的的影影响响，， 这这样样既既能能够够降降低低失失效效凤凤险险，， 也也能能够够 一一定定程程度度上上提提高高 GGOOAA的的良良率率。。
综综上上所所述述，， 本本发发明明基基于于全全新新的的三三段段式式分分压压原原理理的的下下拉拉维维持持电电路路的的设设 计计，， 针针对对制制程程和和电电路路实实际际操操作作中中起起关关键键作作用用的的桥桥式式 TTFFTT的的失失效效风风险险提提出出了了
Figure imgf000013_0001
1、 在三段式分压原理的新电路架构中引入两颗 Diode设计的 TFT来 进行自修复， 主要作用是如果桥式 TFT正常工作不会影响到原电路的基本 运作， 如果桥式 TFT处于短路或者断路时 （尤其是断路） 时自修复的 TFT 可以发挥作用， 也就是通过 S(N)/T(N)的电位来调节 P(N)/K.(N)的电位， 使 得作用期间 P(N)/K(N)能够拉低、 非作用期间 P( )/K(N)能够正常工作， 这 样就不会影响 Gate波形的输出；
2、 引入的自修复的 Diode TFT 可以在 GOA 正常工作时可以实现 S(N)ZT(N)和 P(N)/K(N)的相互影响， 而且也不用担心 Diode设计的 TFT本 身的漏电问题， 因为漏电反而可以实现 S(N)/T N)来调节 P(N)/K(N)， 可以 使得 P(N)/K(N)作用期间关闭状态更好， 降低 Gate 波形输出的延迟 ( Delay ) ；
3、 从 GOA 电路长时间操作的应力 （Stress ) 失效风险来说， 下拉维 持电路部分的起关键作用的调节 P(N)ZK( )下拉的与 Q点相连的几颗 TFT 存在阈值电压 Vth增加的可能性， 那么新的自修复的 Diode TFT可以补偿 由于应力 （Stress )作用对下拉维持电路产生的影响， 从而保持其能够正常 工作而不影响 Gate波形输出。
因此， 本发明的自修复型栅极驱动电路可以降低由于制程或 GOA 电 路长时间操作的原因造成的下拉维持电路的失效凤险， 实现电路自修复功 能； 降低下拉维持电路对 Gate输出波形延迟的影响， 确保良好的 Gate波 形输出； 提高 GOA面板产出的良率和 GOA电路操作的长时间的信赖性。
以上所述， 对于本领域的普通技术人员来说， 可以根据本发明的技术 方案和技术构思作出其他各种相应的改变和变形， 而所有这些改变和变形 都应属于本发明后附的权利要求的保护范围。

Claims

权 利 要 求
1 . 一种自修复型柵极驱动电路， 包括级联的多个 GOA单元， 按照第 N级 GOA单元控制对显示区域第 N级水平扫描线充电， 该第 N级 GOA 单元包括上拉控制电路， 上拉电路， 下传电路， 下拉电路， 自举电容， 第 一下拉维持电路， 第二下拉维持电路， 及桥接电路； 该上拉电路、 下拉电 路、 第一下拉维持电路、 第二下拉维持电路及自举电容分别与櫥极信号点 和该第 N级水平扫描线连接， 该上拉控制电路和下传电路分别与该栅极信 号点连接， 该桥接电路连接于该第一下拉维持电路和第二下拉维持电路之 间并且连接该柵极信号点；
该桥接电路包括第一薄膜晶体管， 其棚 ·极连接该棚 ·极信号点， 漏极和 源极分别连接第一电路点和第二电路点；
该第一下拉维持电路包括：
第二薄膜晶体管， 其树极输入第二时钟信号， 漏极和源极分别输入第 一时钟信号和连接该第二电路点；
第三薄膜晶体管， 其栅极连接第三电路点， 漏极和源极分别输入第一 时钟信号和连接该第二电路点；
第四薄膜晶体管， 其栅极输入第一时钟信号， 漏极和源极分别输入第 一时钟信号和连接该第三电路点;
第五薄膜晶体管， 其柵极连接该第二电路点， 漏极和源极分别连接该 第二电路点和该第三电路点；
第六薄膜晶体管， 其柵极连接该柵极信号点， 漏极和源极分别连接该 第二电路点和输入直流低电压；
第七薄膜晶体管， 其树极连接该第二电路点， 漏极和源极分别输入该 直流低电压和连接该第 n级水平扫描线;
第八薄膜晶体管， 其栅极连接该第二电路点, 漏极和源极分别输入该 直流低电压和连接该柵极信号点；
该第二下拉维持电路包括：
第九薄膜晶体管， 其柵极输入该第一时钟信号， 漏极和源极分别输入 该第二时钟信号和连接该第一电路点；
第十薄膜晶体管， 其栅极连接第四电路点， 漏极和源极分别输入该第 二时钟信号和连接该第一电路点；
第十一薄膜晶体管， 其栅极输入该第二时钟信号， 漏极和源极分别输 入该第二时钟信号和连接该第四电路点； 第十二薄膜晶体管， 其槲极连接该第一电路点， 漏极和源极分别连接 该第一电路点和该第四电路点；
第十三薄膜晶体管， 其柵极连接该柵极信号点， 漏极和源极分别连接 该第四电路点和输入该直流低电压；
十四薄膜晶体管， 其楣-极连接该第一电路点 漏极和源极分别输入 该直流低电压和连接该第 n级水平扫描线；
第十五薄膜晶体管， 其栅极连接该第一电路点， 漏极和源极分别输入 该直流低电压和连.接该栅极信号点；
工作时， 该第一时钟信号和该第二时钟信号的低电位小于该直流低电 压且频率低于输入该上拉电路的时钟信号， 并且使该第一电路点和该第二 电路点交替处于高电位。
2、 如权利要求 1 所述的自修复型柵极驱动电路， 其中， 该上拉控制 电路包括第十六薄膜晶体管， 其栅极输入来自第 N- 1 级 GOA单元的下传 信号， 漏极和源极分别连接第 N-1级水平扫描线和该栅极信号点。
3、 如权利要求 1 所述的自修复型柵极驱动电路， 其中， 该上拉电路 包括第十七薄膜晶体管， 其栅极连接该栅极信号点， 漏极和源极分别输入 该时钟信号和连接该第 II级水平扫描线。
4、 如权利要求 1 所述的自修复型槲极驱动电路， 其中， 该下传电路 包括第十八薄膜晶体管， 其栅极连接该栅极信号点， 漏极和源极分别输入 该时钟信号和输出下传信号。
5、 如权利要求 1 所述的自修复型栅极驱动电路， 其中， 该下拉电路 包括： 第十九薄膜晶体管， 其柵极连接第 N 级水平扫描线， 漏极和源极 分别连接该第 N级水平扫描线和输入该直流低电压； 第二十薄膜晶体管， 其栅极.连接该第 N+1級水平扫描线， 漏极和源极分别连接该栅极信号点和 输入该直流低电压。
6、 如权利要求 1 所述的自修复型栅极驱动电路， 其中， 该时钟信号 的占空比为 50%。
7、 如权利要求 i 所述的自修复型柵极驱动电路， 其中， 该第一时钟 信号通过公共的金属线输入所述级联的多个 GOA单元。
8 , 如权利要求 1 所述的自修复型槲极驱动电路， 其中， 该第二时钟 信号通过公共的金属线输入所述级联的多个 GQA单元。
9、 如权利要求 1 所述的自修复型栅极驱动电路, 其中， 该直流低电 压通过公共的金属线输入所述级联的多个 GOA单元。
10 , 如权利要求 1 所述的自修复型柵极驱动电路， 其中， 工作时， 启 动信号输入第一級 GOA单元的上拉控制电路中以及.最后一级 GOA单元的 下拉电路中。
11、 一种自修复型柵极驱动电路， 包括级联的多个 GOA单元， 按照 第 N 级 GOA单元控制对显示区域第 N级水平扫描线充电， 该第 N级 GOA 单元包括上拉控制电路， 上拉电路， 下传电路， 下拉电路， 自举电 容， 第一下拉维持电路， 第二下拉维持电路， 及桥接电路； 该上拉电路、 下拉电路、 第一下拉维持电路、 第二下拉维持电路及自举电容分别与栅极 信号点和该第 N级水平扫描线连接， 该上拉控制电路和下传电路分别与该 *极信号点连接， 该桥接电路连接于该第一下拉维持电路和第二下拉维持 电路之间并且连接该柵极信号点；
该桥接电路包括第一薄膜晶体管， 其棚 ·极连接该棚 ·极信号点， 漏极和 源极分别连接第一电路点和第二电路点；
该第一下拉维持电路包括：
第二薄膜晶体管， 其树极输入第二时钟信号， 漏极和源极分别输入第 一时钟信号和连接该第二电路点；
第三薄膜晶体管， 其栅极连接第三电路点， 漏极和源极分别输入第一 时钟信号和连接该第二电路点；
第四薄膜晶体管， 其栅极输入第一时钟信号， 漏极和源极分别输入第 一时钟信号和连接该第三电路点;
第五薄膜晶体管， 其柵极连接该第二电路点， 漏极和源极分别连接该 第二电路点和该第三电路点；
第六薄膜晶体管， 其柵极连接该柵极信号点， 漏极和源极分别连接该 第二电路点和输入直流低电压；
第七薄膜晶体管， 其树极连接该第二电路点， 漏极和源极分别输入该 直流低电压和连接该第 n级水平扫描线;
第八薄膜晶体管， 其栅极连接该第二电路点, 漏极和源极分别输入该 直流低电压和连接该柵极信号点；
该第二下拉维持电路包括：
第九薄膜晶体管， 其柵极输入该第一时钟信号， 漏极和源极分别输入 该第二时钟信号和连接该第一电路点;
第十薄膜晶体管， 其橱极连接第四电路点， 漏极和源极分别输入该第 二时钟信号和连接该第一电路点；
一薄膜晶体管， 其栅极输入该第二时钟信号， 漏极和源极分别输
Figure imgf000017_0001
第十二薄膜晶体管， 其槲极连接该第一电路点， 漏极和源极分别连接 该第一电路点和该第四电路点；
第十三薄膜晶体管， 其柵极连接该柵极信号点， 漏极和源极分别连接 该第四电路点和输入该直流低电压；
十四薄膜晶体管， 其楣-极连接该第一电路点 漏极和源极分别输入 该直流低电压和连接该第 n级水平扫描线；
第十五薄膜晶体管， 其栅极连接该第一电路点， 漏极和源极分别输入 该直流低电压和连.接该栅极信号点；
工作时， 该第一时钟信号和该第二时钟信号的低电位小于该直流低电 压且频率低于输入该上拉电路的时钟信号， 并且使该第一电路点和该第二 电路点交替处于高电位；
其中， 该上拉控制电路包括第十六薄膜晶体管， 其栅极输入来自第 N- 1 级 GOA单元的下传信号， 漏极和源极分别连接第 N- i 级水平扫描线和 该栅极信号点；
其中， 该上拉电路包括第十七薄膜晶体管， 其 *极连接该栅极信号 点， 漏极和源极分别输入该时钟信号和连接该第 n级水平扫描线；
其中， 该下传电路包括第十八薄膜晶体管， 其柵极连接该柵极信号 点， 漏极和源极分别输入该时钟信号和输出下传信号；
其中， 该下拉电路包括： 第十九薄膜晶体管， 其柵极连接第 N+1级水 平扫描线， 漏极和源极分别连接该第 N 级水平扫描线和输入该直流低电 压； 第二十薄膜晶体管， 其栅极连接该第 N+ 级水平扫描线， 漏极和源极 分别连接该栅极信号点和输入该直流低电压；
其中， 该时钟信号的占空比为 50%。
12 , 如权利要求 11 所述的自修复型栅极驱动电路， 其中， 该第一时 钟信号通过公共的金属线输入所述级联的多个 GOA单元。
13 , 如权利要求 11 所述的自修复型柵极驱动电路， 其中， 该第二时 钟信号通过公共的金属线输入所述级联的多个 GOA单元。
14 , 如权利要求 11 所述的自修复型柵极驱动电路， 其中， 该直流低 电压通过公共的金属线输入所述级联的多个 GOA单元。
15、 如权利要求 11 所述的自修复型 *极驱动电路， 其中， 工作时， 启动信号输入第一级 GOA单元的上拉控制电路中以及最后一級 GOA单元 的下拉电路中。
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